ISL97678IRZ-TK [RENESAS]
8-Channel 45V 50mA LED Driver; QFN32; Temp Range: -40° to 85°C;
| 型号： | ISL97678IRZ-TK |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-Channel 45V 50mA LED Driver; QFN32; Temp Range: -40° to 85°C |
| 文件： | 总17页 (文件大小：1487K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL97678
8-Channel 45V, 50mA LED Driver
FN6998
Rev.3.00
Sep 8, 2017
The ISL97678 is an 8-channel PWM dimming LED driver for
LCD backlight applications. The ISL97678 is capable of driving
up to 96 pieces of 3.4V/50mA LEDs but larger numbers of
LEDs are possible if the LED forward voltage combined is less
than 45V. The ISL97678 has 8 channels of voltage controlled
current sources with typical currents matching to ±1%, which
compensate for the non-uniformity effect of forward voltages
variance in the LED strings. To minimize the voltage headroom
and power loss in the typical multi-string operation, the
ISL97678 features dynamic headroom control that monitors
the highest LED forward voltage string and uses its feedback
signal for output regulation.
Features
• 8 channels
• 4.75V ~ 26V input
• 45V maximum output
• Drive typically 96 LEDs (3.4V/50mA each)
• External PWM input up to 20kHz dimming
• Dimming range 0.4%~100% up to 30kHz
• Current matching ±0.7% typical
• Protections
- String open circuit and short circuit detections, OVP, and
OTP
The ISL97678 features PWM dimming up to 30kHz with
0.4%~100% duty cycle and maintains ±1% current matching
across all ranges. The PWM dimming frequency can be
adjusted between 100Hz and 30kHz. The boost switching
frequency can also be adjusted between 600kHz and 1.5MHz.
• Adjustable dimming frequency
• Adjustable switching frequency
• 32 Ld (5mmx5mm) QFN package
The ISL97678 features extensive protection functions that
include string open and short circuit detections, OVP, and OTP.
Applications
• Notebook displays WLED or RGB LED backlighting
The ISL97678 is available in the 32 Ld QFN 5mmx5mm and
operate from -40°C to +85°C with input voltage ranges from
4.75V to 26V.
• LCD monitor LED backlighting
Related Literature
• For a full list of related documents, visit our website
- ISL97678 product page
45V*, 50mA per String
96 (8x12) LEDs
VIN
4.75V~26V
CIN
10µH/3A
COUT
3x4.7µF/50V
10µF
VIN
EN
LX
OVP
PROCESSOR
PWM
ISL97678
RSET
CH1
CH2
RSET
LED
BACKLIGHT
FPWM
FSW
RFPWM
RFSW
CH8
AGND
PGND
FIGURE 1. TYPICAL APPLICATION CIRCUIT: TFT-LCD NOTEBOOK DISPLAY
FN6998 Rev.3.00
Sep 8, 2017
Page 1 of 17
ISL97678
Typical Application Circuit
45V*, 50mA per String
96 (8x12) LEDs
D1
L1
VIN* = 4.75V~26V
Optional fuse
COUT
CIN
10µH/3A
3x4.7µF/50V
20
21
10µF
VIN
EN
CUPPER
16
17
18
10
11
12
13
100pF
OVP
23
ISL97678
CLOWER
3.3nF
1µF
1µF
VDC
CH1 25
CH2
CH3
26
27
28
29
30
31
32
1
VLOGIC
FSW
50k
333k
FPWM
RSET
CH4
CH5
CH6
CH7
CH8
THERMAL
PAD
14.2k
3.3nF
14 COMP
15k
PWM
4
2
AGND
AGND
AGND
PGND
PGND
3
5
19
Note: V * ≥ 12V for 45V/50mA Applications
IN
6
7
8
9
15
22
FIGURE 2. ISL97678 TYPICAL APPLICATION DIAGRAM
FN6998 Rev.3.00
Sep 8, 2017
Page 2 of 17
ISL97678
Block Diagram
45V*, 50mA per String
96 (8x12) LEDs
VIN = 4.75V~26V
Optional fuse
CIN
10µH/3A
COUT
2x4.7µF/50V
VIN
LX
EN
10µF
O/P SHORT
OVP
VDC
OVP
REG1
ANALOG BIAS
VLOGIC
REG
LOGIC BIAS
FSW
FAULT
OSC &
RAMP
COMP
FSW
RFSW
FET
DRIVER
LOGIC
Imax
ILIMIT
PGND
Open Ckt, Short Ckt
Detection
FAULT CONTROL
COMP
GM
CH1
CH2
AMP
HIGHEST VF
STRING DETECT
VSET
1
2
+
-
+
-
CH8
REF
GEN
RSET
AGND
PWM
PWM DIMMING
CONTROLLER
8
+
-
FPWM
RFPWM
TEMP
SENSOR
FAULT
CONTROL
ISL97678
FIGURE 3. ISL97678 BLOCK DIAGRAM
Ordering Information
PART NUMBER
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
(Notes 1, 2)
PART MARKING
ISL9767 8IRZ
ISL97678IRZ
NOTES:
32 Ld 5x5 QFN
L32.5x5B
1. Add “-T” suffix for 6k unit or “-TK” for 1k unit tape and reel options. Refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see the product information page for ISL97678. For more information on MSL, see TB363.
FN6998 Rev.3.00
Sep 8, 2017
Page 3 of 17
ISL97678
Pin Configuration
ISL97678
(32 LD 5X5 QFN)
TOP VIEW
32 31 30 29 28 27 26 25
PGND
AGND
AGND
PWM
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
OVP
PGND
LX
EXPOSED THERMAL PAD
AGND
AGND
AGND
AGND
LX
PGND
VDC
EN
9
10 11
12 13 14 15 16
Pin Descriptions
(I = Input, O = Output, S = Supply)
PIN
NAME
PGND
AGND
TYPE
DESCRIPTION
1, 19, 22
S
S
Power Ground.
Analog Ground.
2, 3, 5, 6, 7,
8, 9, 15
4
PWM
VLOGIC
FSW
I
O
I
PWM Brightness Control.
Internal 2.5V Logic Bias Regulator. Need Decoupling Capacitor for Regulation.
10
11
When R
When R
is 100k, f
is 33k, f
SW
is 500kHz.
is 1.5MHz.
FSW
FSW
SW
12
FPWM
I
When R
When R
is 333k, FPWM is 200Hz.
is 3.3k, FPWM is 20kHz.
FPWM
FPWM
13
14
RSET
COMP
VIN
I
O
S
I
Resistor Connection for Setting LED Current.
Boost compensation.
16
Main Power.
17
EN
Enable
18
VDC
S
O
I
Internal 5V Analog Bias Regulator. Needs Decoupling Capacitor for Regulation.
Boost MOSFET Drain Terminal Switching Node.
Overvoltage Protection Input as well as Output Voltage FB Monitoring.
No Connect
20, 21
23
LX
OVP
24
NC
I/O
I
25 ~ 32
CH1 ~ CH8
LED Driver PWM Dimming Monitoring.
FN6998 Rev.3.00
Sep 8, 2017
Page 4 of 17
ISL97678
Absolute Maximum Ratings
Thermal Information
Voltage ratings are all with respect to AGND pin
Thermal Resistance (Typical)
32 Ld QFN (Notes 4, 5). . . . . . . . . . . . . . . . . 31
Thermal Characterization (Typical, Note 6)
(°C/W)
(°C/W)
3
JA
JC
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 27V
VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
VDC, PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V
COMP, RSET, FPWM, FSW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to min
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(VDC + 0.3V, 5.75V)
CH1 - CH8, LX, OVP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V
PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
PSI (°C/W)
JT
32 Ld QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.2
Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Power Dissipation
T
< +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2W
< +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8W
< +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3W
< +100°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8W
A
T
A
T
A
T
A
Recommended Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured with the component mounted on a high-effective thermal conductivity test board in free air. See TB379 for details.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. PSI is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die
JT
junction temperature can be estimated more accurately than the and thermal resistance ratings.
JA JC
5.
Electrical Specifications All specifications below are characterized at T = -40°C to +85°C; V = 12V, EN = 5V, R
= 36kΩ, unless
SET
A
IN
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
PARAMETER
GENERAL
DESCRIPTION
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNITS
V
V
Backlight Supply Voltage
4.75
26
IN
(Note 8)
I
VIN Shutdown Current
EN = 0
5
µA
V
VIN_SHDN
V
V
V
Output Voltage
45
3.3
OUT
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
2.9
4.8
2.3
V
UVLO
300
mV
UVLO_HYS
LINEAR REGULATOR
V
V
5V Analog Bias Regulator
VDC LDO Dropout Voltage
Active Current
V
> 6V
5
5.1
V
DC
IN
I
= 30mA
71
10
2.4
31
100
mV
mA
V
DC_DROP
VDC
VDC
EN = 5V, R = 33kΩ
> 6V
I
V
V
2.5V Logic Bias Regulator
V
2.5
LOGIC
IN
V
LDO Dropout Voltage
I = 30mA
VLOGIC
100
mV
LOGIC_DROP
LOGIC
BOOST SWITCHING REGULATOR
SS
Soft-Start
16
ms
A
SW
Boost FET Current Limit
Internal Boost Switch ON-Resistance
T
= +25°C to +85°C
3.0
4.7
ILimit
A
r
130
mΩ
V
DS(ON)
VFSW
f
Voltage
R
= 33kΩ
FSW
1.18
1.21
1.24
SW
FN6998 Rev.3.00
Sep 8, 2017
Page 5 of 17
ISL97678
Electrical Specifications All specifications below are characterized at T = -40°C to +85°C; V = 12V, EN = 5V, R
= 36kΩ, unless
SET
A
IN
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
Eff_peak
DESCRIPTION
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNITS
%
Peak Efficiency
V
= 24V, 96LEDs, 20mA
92.4
IN
each, L = 10µH with DCR
100mΩF = 600kHz,
SW
= +25°C
T
A
V
= 12V, 96 LEDs, 20mA
91.5
81.6
93.4
90.7
%
%
%
%
IN
each, L = 10µH with DCR
100mΩF = 600kHz,
SW
= +25°C
T
A
V
= 6V, 96 LEDs, 20mA
IN
each, L = 10µH with DCR
100mΩF = 600kHz,
SW
= +25°C
T
A
V
= 24V, 80 LEDs, 40mA
IN
each, L = 10µH with DCR
100mΩF =600kHz,
SW
= +25°C
T
A
V
= 12V, 80 LEDs, 40mA
IN
each, L = 10µH with DCR
100mΩF = 600kHz,
SW
= +25°C
T
A
D
D
Boost Maximum Duty Cycle
Boost Minimum Duty Cycle
Boost Switching Frequency
f
f
= 500kHz
= 500kHz
90
%
%
MAX
SW
SW
10
0.55
1.65
10
MIN
f
R
R
= 100kΩ
= 33kΩ
0.45
1.35
0.5
1.5
MHz
MHz
µA
SW
FSW
FSW
ILX_leakage
REFERENCE
Lx Leakage Current
VLX = 45V, EN= 0V
I
I
Channel-to-Channel Current Matching
Absolute Current Accuracy
I
= 20mA
-1.1
-1.5
-2
±0.7
+1.1
+1.5
+2
%
%
%
MATCH
LED
R
R
= 36kΩT = +25°C
ACC
SET
SET
A
= 36kΩ
T
= -40°C to +80°C
A
FAULT DETECTION
V
V
V
V
Channel Short Circuit Threshold
Over-Temperature Threshold
3.3
1.18
1.5
4.6
V
°C
°C
V
SC
150
5
temp
temp_acc
OVP
Over-Temperature Threshold Accuracy
Overvoltage Limit on OVP Pin
1.22
1.24
DIGITAL INTERFACE
V
V
Logic Input Low Voltage
Logic Input High Voltage
0.8
5.5
V
V
IL
IH
CURRENT SOURCES
V
V
V
Dominant Channel Current Source Headroom at
CH Pin
I
T
= 50mA
= +25°C
1.0
(Note 10)
V
mV
V
HEADROOM
HEADROOM_RANGE
RSET
LED
A
Dominant Channel Current Sink Headroom Range
at CHx Pin
I
T
= 50mA
= +25°C
90
LED
A
Voltage at RSET Pin
1.18
1.21
1.24
FN6998 Rev.3.00
Sep 8, 2017
Page 6 of 17
ISL97678
Electrical Specifications All specifications below are characterized at T = -40°C to +85°C; V = 12V, EN = 5V, R
= 36kΩ, unless
SET
A
IN
otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
PARAMETER
ILEDmax
DESCRIPTION
TEST CONDITIONS
(Note 7)
TYP
50
(Note 7)
UNITS
mA
Maximum LED Current per Channel
LED config = 8P10S with
VF = 3.4V and V = 11V
IN
PWM GENERATOR
FPWM
Generated PWM Frequency
R
R
= 330kΩ
= 3.3kΩ
180
18
200
20
220
22
Hz
kHz
%
FPWM
FPWM
Dimming Range
FPWMI
PWM Dimming Duty Cycle Limits (Note 9)
PWMI Input Frequency Range (Note 9)
VFPWM Voltage
f
30kHz
0.4
100
20k
1.25
PWM
200
1.18
Hz
V
VFPWM
R
= 3.3kΩ
1.21
FPWM
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. At maximum V of 26V, minimum V
IN OUT
is 28V. Minimum V can be lower at lower V
OUT IN
9. Limits established by characterization and are not production tested.
10. Varies within range specified by V
.
HEADROOM_RANGE
Typical Performance Curves
100
95
90
85
80
75
70
100
20mA
8P11S
SW
50mA
8P11S
SW
-40°C
f
= 600kHz
95
90
85
80
75
70
f
= 600kHz
0°C
0°C
-40°C
+85°C
+85°C
+25°C
+25°C
10
0
5
15
(V)
20
25
30
0
5
10
15
(V)
20
25
30
V
V
IN
IN
FIGURE 4. EFFICIENCY vs V vs TEMPERATURE AT 50mA
IN
FIGURE 5. EFFICIENCY vs V vs TEMPERATURE AT 20mA
IN
100
95
50mA
8P10S
95
90
85
80
75
70
65
60
55
50
45
40
35
30
94
93
92
91
90
89
88
87
86
85
84
8P11S
12V/50mA
24V
24V/50mA
12V
1k
0
10
20
I
30
(mA)
40
50
400
600
800
1.2k
1.4k
1.6k
SWITCHING FREQUENCY (Hz)
LED
FIGURE 7. EFFICIENCY vs SWITCHING FREQUENCY
FIGURE 6. EFFICIENCY vs I
LED
FN6998 Rev.3.00
Sep 8, 2017
Page 7 of 17
ISL97678
Typical Performance Curves(Continued)
1.0
0.8
1.0
20mA - 8P12S
50mA - 8P11S
50mA
8P11
0.8
0.6
0.6
0°C
12V/20mA
0.4
0.4
0.2
0.2
0.0
0.0
+25°C
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
+85°C
12V/50mA
-40°C
15
0
5
10
20
25
30
1
2
3
4
5
6
7
8
V
(V)
CHANNEL
IN
FIGURE 9. CURRENT MATCHING vs V vs TEMPERATURE
IN
FIGURE 8. CHANNEL-TO-CHANNEL CURRENT MATCHING EXAMPLE
2.0
2.0
20mA - 8P12S
20mA - 8P12S
1.8
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
50mA - 8P11S
50mA - 8P11S
12V/50mA
1.6
12V/50mA
1.4
24V/50mA
1.2
1.0
0.8
0.6
0.4
0.2
0.0
5V/20mA
12V/20mA
HEADROOM CONTROL CHANNEL
24V/20mA
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
1
2
3
4
5
6
7
8
CHANNEL
PWM DIMMING DUTY CYCLE (%)
FIGURE 10. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING
DUTY CYCLE
FIGURE 11. TYPICAL CHANNEL VOLTAGE EXAMPLE
1.00
1.0
20mA
50mA
0.95
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
8P11S
8P11S
+25°C
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
+85°C
+85°C
+25°C
0°C
20
0°C
0
5
10
15
(V)
25
30
0
5
10
15
(V)
20
25
30
V
V
IN
IN
FIGURE 13. V
vs V vs TEMPERATURE AT 20mA
IN
FIGURE 12. V
vs V vs TEMPERATURE AT 50mA
IN
HEADROOM
HEADROOM
FN6998 Rev.3.00
Sep 8, 2017
Page 8 of 17
ISL97678
Typical Performance Curves(Continued)
10
EN = HIGH
9
8
7
6
5
4
3
2
1
0
PWM DUTY CYCLE = 0%
LX (20V/DIV)
+85°C
V
(100mV/DIV)
O
-40°C
I
(20mA/DIV)
LED
0
5
10
15
(V)
20
25
30
V
IN
FIGURE 14. QUIESCENT CURRENT vs V vs TEMPERATURE WITH
IN
FIGURE 15. V
OUT
RIPPLE VOLTAGE
ENABLE
V
(20V/DIV)
V
(20V/DIV)
O
O
EN (5V/DIV)
EN (5V/DIV)
I
(1A/DIV)
IN
I
(1A/DIV)
IN
I
(50mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 17. IN-RUSH CURRENT AND LED CURRENT AT V = 26V
IN
FIGURE 16. IN-RUSH CURRENT and LED CURRENT AT V = 12V
IN
V
(10V/DIV)
IN
V
(10V/DIV)
IN
I
(500mA/DIV)
IN
I
(500mA/DIV)
IN
I
(50mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 19. LINE REGULATION WITH V CHANGES FROM 26V TO
IN
FIGURE 18. LINE REGULATION WITH V CHANGES FROM 12V TO
IN
12V
26V DISABLE PROFILE
FN6998 Rev.3.00
Sep 8, 2017
Page 9 of 17
ISL97678
Typical Performance Curves(Continued)
V
(1V/DIV)
O
V
(1V/DIV)
O
I
(20mA/DIV)
LED
I
(20mA/DIV)
LED
FIGURE 20. LOAD REGULATION WITH I
100% PWM DIMMING
CHANGES FROM 0.4% TO
FIGURE 21. LOAD REGULATION WITH I
0.4% PWM DIMMING
CHANGES FROM 100% TO
LED
LED
V
(1V/DIV)
V
(500mV/DIV)
O
O
I
(20mA/DIV)
LED
I
(20mA/DIV)
LED
FIGURE 23. LOAD REGULATION WITH I
0% PWM DIMMING
CHANGES FROM 100% to
FIGURE 22. LOAD REGULATION WITH I
100% PWM DIMMING
CHANGES FROM 0% TO
LED
LED
FPWM = 30KHz
100nSec/DIV
V
(20V/DIV)
O
PWM Input (1V/DIV)
EN (5V/DIV)
I
(1A/DIV)
IN
I
(20mA/DIV)
LED
I
(50mA/DIV)
LED
FIGURE 24. DISABLE PROFILE
FIGURE 25. MINIMUM 0.4% PWM DIMMING DUTY CYCLE
FN6998 Rev.3.00
Sep 8, 2017
Page 10 of 17
ISL97678
Because all LED strings are connected to the same output
voltage, the other CH pins will have a higher voltage, but the
regulated current source circuit on each channel ensures that
each channel has the same programmed current. The output
voltage regulates cycle-by-cycle and is always referenced to the
highest forward voltage string in the architecture.
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal
voltage needed to enable the LED string with the highest forward
voltage drop to run at the programmed current. The ISL97678
employs current mode control boost architecture, which has a
fast current sense loop and a slow voltage feedback loop. This
architecture achieves a fast transient response that is essential
for notebook backlight applications in which the power can be
several Li-ion cell batteries that instantly change to an AC/DC
adapter without rendering a noticeable visual nuisance. The
number of LEDs that can be driven by the ISL97678 depends on
the type of LED chosen in the application. The ISL97678 is
capable of boosting up to 45V and drive eight channels of LEDs
at a maximum of 45mA per channel.
OVP and V
Requirement
OUT
The Overvoltage Protection (OVP) pin sets the overvoltage trip
level and limits the V regulation range.
OUT
The ISL97678 OVP threshold is set by R
shown in Equation 1:
and R
LOWER
as
UPPER
V
= 1.21V R
+ R
R
LOWER
(EQ. 1)
OUT_OVP
UPPER
LOWER
V
can regulate only between 64% and 100% of the V
_
OUT
OUT OVP
such that:
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current
source circuit, as shown in Figure 26.
Allowable V
= 64% to 100% of V
_
OUT
OUT OVP
For example, if 10 LEDs are used with the worst case V
OUT
of
35V. If R
and R
are chosen such that the OVP level is
is allowed to operate between 25.6V
UPPER
LOWER
The LED peak current is set by translating the R
SET
current to the
set at 40V, then the V
OUT
and 40V. If the requirement is changed to a 6 LEDs 21V V
output with a scaling factor of 707.9/R . The sink terminals of
SET
OUT
the current source MOSFETs are designed to operate within a
range at about 500mV to optimize power loss versus accuracy
requirements. The sources of errors of the channel-to-channel
current matching come from the op amps offset, internal layout,
reference, and current source resistors. These parameters are
optimized for current matching and absolute current accuracy.
However, the absolute accuracy is additionally determined by the
application, then the OVP level must be reduced and users
should follow V = (64% ~100%) OVP requirement. Otherwise,
the headroom control will be disturbed such that the channel
voltage can be much higher than expected and sometimes it can
prevent the driver from operating properly.
OUT
The ratio of the OVP capacitors should be the inverse of the OVP
resistors. For example, if R = 33/1, then
/R
external R . A 0.1% tolerance resistor is recommended.
UPPER LOWER
SET
C
C
/C
UPPER LOWER
= 1/33 with C = 100pF and
UPPER
.
= 3.3nF.
LOWER
Dimming Controls
The ISL97678 provides two ways of controlling the LED current,
and therefore the brightness. They are:
1. DC current adjustment
2. PWM chopping of the LED current defined in Step 1.
There are various ways to achieve DC or PWM current control,
which will be described in the following.
+
-
+
REF
-
In any dimming controls, the EN pin must be high. EN is a high
voltage pin that can be applied with a digital signal or tied
directly to V for enable function.
IN
RSET
+
-
PWM DIMMING
MAXIMUM DC CURRENT SETTING
The initial brightness should be set by choosing an appropriate
value for R . This should be chosen to fix the maximum
FIGURE 26. SIMPLIFIED CURRENT SOURCE CIRCUIT
SET
possible LED current:
Dynamic Headroom Control
The ISL97678 features a proprietary Dynamic Headroom Control
circuit that detects the highest forward voltage string or
707.9
--------------
I
=
LEDmax
(EQ. 2)
R
SET
Alternatively, the R
can be replaced by a digital potentiometer
SET
for adjustable current.
effectively the lowest voltage from any of the CH pins. When this
lowest I voltage is lower than the short circuit threshold, V
,
IN SC
such voltage will be used as the feedback signal for the boost
regulator. The boost makes the output to the correct level such
that the lowest CH pin is at the target headroom voltage.
FN6998 Rev.3.00
Sep 8, 2017
Page 11 of 17
ISL97678
some LEDs, a zener diode, which is integrated into the device in
parallel with the now opened LED.
PWM CONTROL
The ISL97678 provides PWM dimming by PWM chopping of the
current in the LEDs for all eight channels. To achieve PWM
dimming, the user must apply a PWM signal at the PWM pin. The
PWM output follows the PWM input and the dimming frequency
For basic LEDs (which do not have built-in zener diodes), an open
circuit failure of an LED will only result in the loss of one channel
of LEDs without affecting other channels. Similarly, a short circuit
condition on a channel that results in that channel being turned
off does not affect other channels unless a similar fault is
occurring.
is set by R
. During the On periods, the LED current is defined
PWM
by the value of R , as described in Equation 1.
SET
PWM Dimming Frequency Adjustment
The dimming frequencies are set by an external resistor at the
FPWM pin as shown by Equation 3:
Due to the lag in boost response to any load change at its output,
certain transient events (such as significant step changes in LED
duty cycle) can transiently look like LED fault modes. The
ISL97678 uses feedback from the LEDs to determine when it is
in a stable operating region and prevents apparent faults during
these transient events from allowing any of the LED strings to
fault out. See Table 1 for more details.
7
6.6610
R
-----------------------
FPWM
(EQ. 3)
f
=
PWM
where f
PWM
is the desirable PWM dimming frequency and
range is from 100Hz to
R
is the setting resistor. f
FPWM
30kHz.
PWM
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each
channel and disables faulty channels which are detected above
the programmed short circuit threshold. When an LED becomes
shorted, the action taken is described in Table 1. The short circuit
threshold is 4V.
Switching Frequency
The boost switching frequency can be adjusted by a resistor as
shown in Equation 4:
10
510
R
-----------------------
(EQ. 4)
f
=
SW
FSW
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as
either an infinite resistance or a gradually increasing finite
resistance. The ISL97678 monitors the current in each channel
such that any string which reaches the intended output current is
considered “good”. If the current subsequently falls below the
target, the channel is considered an “open circuit”. Furthermore,
if the boost output of the ISL97678 reaches the OVP limit or if
the lower over-temperature threshold is reached, all channels
that are not “good” are immediately considered as “open circuit”.
Detection of an “open circuit” channel results in a time-out
before disabling of the affected channel.
where f
SW
the setting resistor.
is the desirable boost switching frequency and R is
FSW
5V and 2.3V Low Dropout Regulators
A 5V LDO regulator is present at the VDC pin to develop the
necessary low voltage supply, which is used by the chips internal
control circuitry. Because VDC is an LDO pin, it requires a bypass
capacitor of 1µF or more for the regulation. The VDC pin can be
used for a coarse regulator or reference but does not pull more
than a few mA from it.
Similarly, a 2.3V LDO regulator is present at the VLOGIC pin to
develop the necessary low voltage supply for the chip’s internal
logic control circuitry. A 1µF bypass capacitor or more is needed
for regulation. The VLOGIC pin can be used as a coarse regulator or
reference but does not pull more than a few mA from it.
Some users employ LEDs that have zener diode structure in
parallel with the LED for ESD enhancement, thus enabling open
circuit operation. When this type of LED goes open circuit, the
effect is as if the LED forward voltage has increased, but no light
will be emitted. Any affected string will not be disabled, unless the
failure results in the boost OVP limit being reached, allowing all
other LEDs in the string to remain functional. Care should be taken
in this case that the boost OVP limit and SCP limit are set properly,
so as to make sure that multiple failures on one string do not
cause all other good channels to be faulted out. This is due to the
increased forward voltage of the faulty channel making all other
channel look as if they have LED shorts. See Table 1 for details for
responses to fault conditions.
Soft-Start
The ISL97678 uses a digital soft-start in which the boost current
limit is stepped up in eight steps. The initial current limit level is
set to one ninth of the full current limit, with subsequent steps
increasing this by a ninth every 2ms. If no LEDs are conducting
during the interval since the last step (for example, if the LEDs
are running at a low duty cycle at a low PWM frequency) then the
step will be delayed until the LEDs are conducting. If the LEDs are
disabled and re-enabled again then soft-start will be restarted
when the LEDs are enabled.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps
the voltage at a safe level. The OVP threshold is set as shown in
Equation 5:
Fault Protection and Monitoring
The ISL97678 features extensive protection functions to cover all
the perceivable failure conditions. The failure mode of a LED can
be either open circuit or as a short. The behavior of an open
circuited LED can take the form of either infinite resistance or, for
OVP = 1.21V R
+ R
R
LOWER LOWER
(EQ. 5)
UPPER
These resistors should be large to minimize the power loss. For
example, a 1MkΩ R and 30kΩ R sets OVP to 41.2V.
UPPER
Large OVP resistors also allow C
LOWER
discharges slowly during the
OUT
FN6998 Rev.3.00
Sep 8, 2017
Page 12 of 17
ISL97678
PWM Off time. Parallel capacitors should be placed across the
regulation target will be treated as “open circuit” and disabled after
a time-out period. The intention of the lower threshold is to allow
bad channels to be isolated and disabled before they cause enough
power dissipation (as a result of other channels having large
voltages across them) to hit the upper temperature threshold.
OVP resistors such that R
/R
= C
/C
.
UPPER LOWER
LOWER UPPER
Using a C
value of at least 30pF is recommended. These
UPPER
capacitors reduce the AC impedance of the OVP node, which is
important when using high value resistors.
The upper threshold is set to +150°C. Each time this is reached,
the boost will stop switching and the output current sources will
be switched off and stay off until the control driver is power off
and re-enables it. For the extensive fault protection conditions,
please refer to Figure 27 and Table 1 for details.
Undervoltage Lockout
If the input voltage falls below the UVLO level of 2.8V, the device
will stop switching and be reset. Operation will restart only if the
device control interface re-enables it once the input voltage is
back in the normal operating range. Also all digital settings will
be reset to their default states.
Shutdown
When the EN pin is low the entire chip is shut down to give close
to zero shutdown current. The digital interfaces will not be active
during this time.
Over-Temperature Protection (OTP)
The ISL97678 includes two over-temperature thresholds. The lower
threshold is set to +130°C. When this threshold is reached, any
channel which is outputting current at a level significantly below the
VIN
VOUT
LX
FAULT
O/P
DRIVER
SHORT
OVP
FET
DRIVER
LOGIC
IMAX
ILIMIT
CH1
VSC
CH8
VSET/2
REG
THRM
SHDN
REF
T2
TEMP
SENSOR
OTP
T1
+
+
-
VSET
VSET
Q1
Q8
-
PWM1/OC1/SC1
PWM8/OC8/SC8
CONTROL
LOGIC
DC CURRENT
FIGURE 27. SIMPLIFIED FAULT PROTECTIONS
TABLE 1. PROTECTIONS TABLE
V
REGULATED
BY
OUT
CASE
1
FAILURE MODE
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION
CH2 through CH8 Normal
CH1 Short Circuit
Upper Over-Temperature CH1 ON and burns power
Protection limit (OTP) not
Highest VF of CH2
through CH8
triggered and VI
VSC
<
IN0
2
CH1 Short Circuit
Upper OTP triggered but CH1 goes off
VI < VSC
Same as CH1
Highest VF of CH2
through CH8
IN1
FN6998 Rev.3.00
Sep 8, 2017
Page 13 of 17
ISL97678
TABLE 1. PROTECTIONS TABLE (Continued)
FAILED CHANNEL ACTION
V
REGULATED
BY
OUT
CASE
FAILURE MODE
DETECTION MODE
GOOD CHANNELS ACTION
3
CH1 Short Circuit
Upper OTP not triggered CH1 disabled after 6 PWM cycles
but VI > VSC time-out.
If 3 channels are already shut
down, all channels will be shut
down. Otherwise CH2-8 will
remain as normal
Highest VF of CH2
through CH8
IN1
4
CH1 Open Circuit
with infinite
Upper OTP not triggered
and VI < VSC
V
will ramp to OVP. CH1 will
CH2 through CH8 Normal
Highest VF of CH2
through CH8
OUT
time-out after 6 PWM cycles and
IN1
resistance
switch off. V
will drop to normal
OUT
level.
5
6
7
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered CH1 remains ON and has highest
and VI < VSC VF, thus V increases
CH2 through CH8 ON, Q2 through VF of CH1
Q8 burn power
IN1
OUT
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP triggered but CH1 goes off
VI < VSC
Same as CH1
VF of CH1
IN1
CH1 LED Open
Circuit but has
paralleled Zener
Upper OTP not triggered CH1 OFF
but VI > VSC
CH2 through CH8 Normal
Highest VF of CH2
through CH8
IN1
Upper OTP not triggered CH1 remains ON and has highest
but VI > VSC VF, thus V increases.
V
increases then CH-X
VF of CH1
OUT
switches OFF. This is an
INx OUT
unwanted shut off and can be
prevented by setting OVP and/or
VSC at an appropriate level.
8
9
Channel-to-Channel Lower OTP triggered but Any channel at below the target current will fault out after 6 PWM
Highest VF of CH1
through CH8
VF too high
VI < VSC
cycles.
INx
Remaining channels driven with normal current.
Channel-to-Channel Upper OTP triggered but All channels switched off
Highest VF of CH1
through CH8
VF too high
VI < VSC
INx
10
11
Output LED string
voltage too high
V
> VOVP
Driven with normal current. Any channel that is below the target current Highest VF of CH1
OUT
will time-out after 6 PWM cycles.
through CH8
V
/LX shorted to
LX will not switch
OUT
GND
Components Selections
Input Capacitor
According to the inductor Voltage-Second Balance principle, the
change of inductor current during the switching regulator
On-time is equal to the change of inductor current during the
switching regulator Off-time. The voltage across an inductor is as
shown in Equation 6:
Switching regulators require input capacitors to deliver peak
charging current and to reduce the impedance of the input
supply. This reduces interaction between the regulator and input
supply, thereby improving system stability. The high switching
frequency of the loop causes almost all ripple current to flow in
the input capacitor, which must be rated accordingly.
(EQ. 6)
V
= L I t
L
L
A capacitor with low internal series resistance should be chosen
to minimize heating effects and improve system efficiency, such
as X5R or X7R ceramic capacitors, which offer small size and a
lower value of temperature and voltage coefficient compared to
other ceramic capacitors.
and I @ On = I @ Off, therefore:
L
L
(EQ. 7)
V – 0 L D t = V – V – V L 1 – D t
S
I
S
O
D
I
where D is the switching duty cycle defined by the turn-on time
It is recommended that an input capacitor of at least 10µF be
used. Ensure the voltage rating of the input capacitor is suitable
to handle the full supply range.
over the switching periods. V is Schottky diode forward voltage
D
that can be neglected for approximation.
Rearranging the terms without accounting for V gives the boost
D
ratio and duty cycle respectively as Equations 8 and 9:
(EQ. 8)
(EQ. 9)
V
V = 1 1 – D
I
O
D = V – V V
O
O
I
FN6998 Rev.3.00
Sep 8, 2017
Page 14 of 17
ISL97678
Inductor
The selection of the inductor should be based on its maximum
and saturation current (I ) characteristics, power dissipation
SAT
(DCR), EMI susceptibility (shielded vs unshielded), and size.
Inductor type and value influence many key parameters,
including ripple current, current limit, efficiency, transient
performance, and stability.
The inductor’s maximum current capability must be adequate
enough to handle the peak current at the worst case condition.
Additionally, if an inductor core is chosen with too low a current
rating, saturation in the core will cause the effective inductor
value to fall, leading to an increase in peak to average current
level, poor efficiency and overheating in the core. The series
resistance, DCR, within the inductor causes conduction loss and
heat dissipation. A shielded inductor is usually more suitable for
EMI susceptible applications, such as LED backlighting.
The peak current can be derived from the voltage across the
inductor during the Off-period, as expressed in Equation 10:
IL
= V I 85% V + 1 2V V – V L V f
O O I I O I O SW
peak
(EQ. 10)
The choice of 85% is an average term for the efficiency
approximation. The first term is the average current, which is
inversely proportional to the input voltage. The second term is
the inductor current change, which is inversely proportional to L
and f
as a result, for a given switching.
SW
FN6998 Rev.3.00
Sep 8, 2017
Page 15 of 17
ISL97678
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure
you have the latest revision.
DATE
REVISION
FN6998.3
CHANGE
9/8/2017
Added VHEADROOM_RANGE spec to the Electrical Specifications table.
Added Note 11.
In “Current Matching and Current Accuracy” on page 11, updated the second sentence in the second paragraph
for clarification.
Added Related Literature section.
Applied new header/footer.
3/22/2014
FN6998.2
Changed PWM dimming “0.8%~100% duty cycle” to “0.4%~100% duty cycle” on the front page.
Changed External PWM Input “25kHz” to “20kHz” in the Features section in order to be consistent with Electrical
Specifications.
Updated Application Circuit and Block Diagram drawings along with the resistor and capacitor names.
Moved the VFSW specification to the BOOST SWITCHING REGULAR section of the Electrical Specifications table.
Changed “/SHUT” to “EN” to be consistent with the Pin Descriptions table.
Changed “I ” to “R ” for the LED current setting resistor to be consistent across the datasheet.
SET SET
Changed “V ” to “V
” to be consistent with the RSET pin name.
ISET
RSET
” to be consistent across the datasheet.
” and “R ”, respectively in OVP and V
Changed “R
”
“R
OSC to FSW
Changed “R ” and “R ” to “R
Requirement section.
1
2
UPPER LOWER OUT
Added FIGURE 1. TYPICAL APPLICATION CIRCUIT: TFT-LCD NOTEBOOK DISPLAY.
Added FIGURE 25. MINIMUM 0.4% PWM DIMMING DUTY CYCLE.
Updated “Package Outline Drawing” on page 17 to the latest revision.
11/5/09
FN6998.1
FN6998.0
Changed VSC spec from “3.3min, 4.4max” to “3.3min, 4.6max”.
Initial release
10/26/09
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
For a listing of definitions and abbreviations of common terms used in our documents, visit www.intersil.com/glossary.
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Reliability reports are also available from our website at www.intersil.com/support.
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All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN6998 Rev.3.00
Sep 8, 2017
Page 16 of 17
ISL97678
For the most recent package outline drawing, see L32.5x5B.
Package Outline Drawing
L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 5/10
4X
3.5
0.50
5.00
28X
A
6
B
PIN #1 INDEX AREA
32
25
6
1
24
PIN 1
INDEX AREA
3 .30 ± 0 . 15
17
8
(4X)
0.15
9
16
0.10 M
C
A B
0.07
+
32X 0.40 ± 0.10
4
32X 0.23
- 0.05
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
0.10
C
C
0 . 90 ± 0.1
BASE PLANE
SEATING PLANE
0.08
C
( 4. 80 TYP )
(
( 28X 0 . 5 )
SIDE VIEW
3. 30 )
(32X 0 . 23 )
( 32X 0 . 60)
5
0 . 2 REF
C
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6998 Rev.3.00
Sep 8, 2017
Page 17 of 17
相关型号：
ISL97682IRTZ-T7
LED DISPLAY DRIVER, PQCC16, 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-220WEED, TQFN-16
RENESAS
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