ISL55033IRTZ-T7 [RENESAS]
Video Amplifier;
| 型号： | ISL55033IRTZ-T7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Video Amplifier 放大器 商用集成电路 |
| 文件： | 总13页 (文件大小：872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
400MHz Slew Rate Enhanced, Rail-to-Rail Output Gain
Block
ISL55033
Features
The ISL55033 is a triple rail-to-rail output gain block with a
-3dB bandwidth of 400MHz and slew rate of 2350V/µs into a
150 load. The ISL55033 has a fixed gain of +2. The inputs
are capable of sensing ground. The outputs are capable of
swinging to 0.45V to either rail through a 150Ω resistor
connected to V+/2.
• 400MHz -3dB bandwidth
• 2350V/µs typ slew rate, R = 150Ωto V+/2
L
• Single-supply operation from +3V to +5.5V
• Rail-to-rail output
• Input ground sensing
The ISL55033 is designed for general purpose video
applications. The part includes a fast-acting global
disable/power-down function.
• Fast 25ns disable time
• Pb-free (RoHS compliant)
Applications
• Video amplifiers
• Set-top boxes
The ISL55033 is available in a 12 Ld TQFN package. Operation
is specified over the -40°C to +85°C temperature range.
• Video distribution
Pin Configuration
ISL55033
(12 LD TQFN)
TOP VIEW
12
11
10
IN+_1
IN+_2
IN+_3
9
OUTPUT_1
OUTPUT_2
OUTPUT_3
1
8
7
2
3
EP
6
4
5
EACH CHANNEL
= +2
A
V
June 29, 2015
FN6346.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2008, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL55033
Pin Descriptions
EQUIVALENT
CIRCUIT
PIN NUMBER
PIN NAME
IN+_1
DESCRIPTION
1
2
3
4
5
Circuit 1
Circuit 1
Circuit 1
Circuit 4
Amplifier 1 noninverting input
Amplifier 2 noninverting input
Amplifier 3 noninverting input
IN+_2
IN+_3
GND_IN-(1, 2, 3)
GND_PWR
Common input for amplifiers 1, 2, 3 inverting inputs
Circuits 1, 2, 4, 5 Power supply ground. This is also the potential of the exposed metal pad on the package
bottom.
6
7
GND_OUTPUT
OUTPUT_3
OUTPUT_2
OUTPUT_1
V+_OUTPUT
EN
Circuit 3
Circuit 3
Circuit 3
Circuit 3
Circuit 3
Circuit 2
Output power supply ground
Amplifier 3 output
8
Amplifier 2 output
9
Amplifier 1 output
10
11
Output power supply
Enable pin with internal pull-down: Logic “1” selects the disabled state; Logic “0” selects the
enabled state
12
EP
V+
EP
Circuits 1, 2, 4 Positive power supply
Circuit 5 Package’s exposed thermal pad. Connect to GND_PWR.
V+
V+_OUTPUT
V+
IN+
EN
OUTPUT (1, 2, 3)
GND_OUTPUT
dV/dt
CLAMP
GND_PWR
GND_PWR
CIRCUIT 3
CIRCUIT 1
CIRCUIT 2
V+
DIE SUBSTRATE
~1MΩ
GND_IN-(1, 2, 3)
GND_PWR
500
THERMAL HEAT SINK PAD (EP)
CIRCUIT 5
500k
GND_PWR
CIRCUIT 4
Ordering Information
PART NUMBER
(Note 1, 2, 3)
PART
MARKING
TEMP RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL55033IRTZ
NOTES:
5033
-40 to +85
12 Ld TQFN
L12.3x3A
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL55033. For more information on MSL, please see tech brief TB363.
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ISL55033
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn-on Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs
EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA
Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V+) + 0.3V to GND - 0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
ESD Rating:
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV
Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300V
Charge Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kV
Thermal Resistance (Typical) . . . . . . . . . . . . .
12 Ld TQFN Package (Notes 4, 5) . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
(°C/W)
57
(°C/W)
10
JA
JC
Operating Conditions
Ambient Operating Temperature Range (T ) . . . . . . . . . . -40°C to +85°C
A
Maximum Operating Junction Temperature (T ). . . . . . . . . . . . . . . +125°C
J
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
4. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
Electrical Specifications V+ = V+_OUTPUT = 5V, T = +25°C, R = 1kΩ to V+/2, V = 0.1VDC, unless otherwise specified.
A
L
IN
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
INPUT CHARACTERISTICS
V
Output Offset Voltage
(Note 6)
-9
-1
-3
9
mV
µV/°C
µA
OS
TCV
Offset Voltage Temperature Coefficient Measured from -40°C to +85°C
OS
IB
Input Bias Current
Input Resistance
Input Capacitance
V
= 0V
-8.5
-6
IN
R
7
MΩ
IN
C
0.5
pF
IN
OUTPUT CHARACTERISTICS
A
Closed Loop Gain
V
= 0.5V to 4V, R = 150Ω
1.97
1.99
30
2.014
V/V
mΩ
V
CL
OUT
L
R
Output Resistance
A
= +2
OUT
OH
V
V
Positive Output Voltage Swing
R = 1kΩ to 2.5V
4.7
4.5
4.75
4.55
27
L
R = 150Ω to 2.5V
V
L
V
Negative Output Voltage Swing
R
R
R
R
= 1kΩ to 2.5V
50
mV
mV
mA
mA
OL
L
L
L
L
= 150Ω to 2.5V
130
200
I
I
(source)
Output Short-circuit Current
Output Short-circuit Current
= 10Ωto GND, V = 1.5V
IN
50
50
SC
(sink)
= 10Ωto + 2.5V, V = 0V
IN
SC
POWER SUPPLY
PSRR
Power Supply Rejection Ratio
Supply Current - Enabled
V+ = 3V to 5.5V, R = Open
65
83
dB
mA
µA
L
I
I
V
= 0.1V, R = Open
18.5
275
21.3
486
24.5
900
S-ON
IN
L
Supply Current - All Amplifiers Disabled R = Open
S-OFF
L
ENABLE
t
t
Enable Time
R
R
= 150ΩV = 0.5V
IN
250
25
0.8
2
ns
ns
V
EN
DS
L
L
Disable Time
= 150ΩV = 0.5V
IN
V
V
EN Pin Low Voltage for Power-up
EN Pin High Voltage for Shut-Down
EN Pin Input Current High
EN Pin Input Current Low
IL-ENB
IH-ENB
IH-ENB
IL-ENB
V
I
I
V
V
= 5V
= 0V
1
7
15
10
µA
µA
EN
EN
-10
2
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ISL55033
Electrical Specifications V+ = V+_OUTPUT = 5V, T = +25°C, R = 1kΩ to V+/2, V = 0.1VDC, unless otherwise specified. (Continued)
A
L
IN
MIN
MAX
PARAMETER
DESCRIPTION
TEST CONDITIONS
(Note 7)
TYP
400
(Note 7)
UNIT
MHz
AC PERFORMANCE
BW
-3dB Bandwidth
V
V
= 100mV R = 150Ω, C = 2pF,
P-P
OUT
L
L
= 1.0 VDC
IN
BW
±0.1dB Bandwidth
V
= 100mV R = 150Ω, C = 2pF
60
MHz
dB
OUT
OUT
P-P
L
L
Peak
Gain Peaking
V
= 100mV R = 150Ω,
1.5
P-P
L
C
= 3.2pF
L
dG
dP
Differential Gain
V
= 0.1V to 2.0V, V
= 100mV ,
P-P
0.012
0.11
35
%
°
IN
OUT
f = 3.58MHz, R = 150Ω
L
Differential Phase
e
Output Voltage Noise Density
Input Current Noise Density
Off-state Isolation
f = 10kHz
f = 10kHz
nV/Hz
pA/Hz
dB
N-OUT
i
2.9
N
ISO
V
= 0.8VDC + 1V , C = 2pF,
P-P
-80
IN
L
f
= 10MHz
R
= 150Ω
O
L
X-TALK
PSRR
Channel-to-channel Crosstalk,
= 10MHz
V
R
= 0.8VDC + 1V , C = 2pF,
= 150Ω
-65
-55
dB
dB
IN
L
P-P
L
f
O
Power Supply Rejection Ratio
= 10MHz
V
C
= 0.2VDC, V
= 1V
,
P-P
IN
SOURCE
f
= 2pF, R = 150Ω
O
L
L
TRANSIENT RESPONSE
SR Slew Rate 25% to 75%
t , t Large Rise Time, t 20% to 80%
R
= 150Ω, V
OUT
= 0.5V to 3.5V
2350
0.8
0.7
0.6
0.6
0.55
0.55
13
V/µs
ns
ns
ns
ns
ns
ns
%
L
V
V
V
= 3V R = 150ΩC = 2pF
P-P
r
f
r
OUT
L
L
Signal
Fall Time, t 80% to 20%
f
Rise Time, t 20% to 80%
= 2V R = 150ΩC = 2pF
P-P
r
OUT
OUT
L
L
Fall Time, t 80% to 20%
f
t , t , Small
Rise Time, t 20% to 80%
= 100mV R = 150ΩC = 2pF
P-P
r
f
r
L
L
Signal
Fall Time, t 80% to 20%
f
OS
Overshoot
100mV step
t
t
Propagation Delay
0.1% Settling Time
100mV step; R = 150Ω
1
ns
ns
PD
S
L
2V step
65
NOTES:
6. V is extrapolated from 2 output voltage measurements, with V = 62.5mV and V = 125mV, R = 1k.
OS IN IN
L
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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ISL55033
Typical Performance Curves
3
8
6
R
= 1k
L
C = 9.2pF
L
2
1
R
= 499
L
C
= 7.8pF
= 5.7pF
L
4
C
L
0
2
C
= 4.3pF
L
-1
-2
-3
-4
-5
-6
0
R
= 150
= 100
L
-2
-4
-6
-8
V+ = V+_OUT = 5V
R
C
= 3.2pF
L
L
A
C
= +2
= 2pF
= 100mV
(DC) = 0.1V
V+ = V+_OUT = 5V
V
L
A
R
V
V
= +2
= 150Ω
= 100mV
V
L
C
= 2.0pF
L
V
V
OUT
IN
P-P
OUT P-P
(DC) = 0.1V
1M
IN
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
10M
FREQUENCY (Hz)
100M
1G
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS C
FIGURE 1. GAIN vs FREQUENCY FOR VARIOUS R
LOAD
LOAD
1
0
4
2
0
-1
V
V
= 0.1V
= 0.5V
OUT
P-P
-2
-3
-4
-5
-6
-7
-8
-9
V
V
V
V
= 2.3V
= 2.2V
= 2.0V
= 1.0V
= 0.1V
IN(DC)
IN(DC)
IN(DC)
IN(DC)
OUT
P-P
-2
-4
V
= 1.0V
OUT
OUT
P-P
P-P
V
IN(DC)
V
= 1.5V
V+ = V+_OUT = 5V
AV = +2
V+ = V+_OUT = 5V
-6
A
R
C
= +2
= 150Ω
= 2pF
R
= 150Ω
V
L
L
L
C
= 2pF
-8
L
V
(DC) = 0.1V
IN
V
= 100mV
OUT
P-P
-10
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS DC INPUT VOLTAGES
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS V
OUT
7
6
0.2
0.1
0
ALL CHANNELS
5
-0.1
-0.2
-0.3
4
3
-0.4
V+ = V+_OUT = 5V
V+ = V+_OUT = 5V
A
= +2
= 150Ω
= 2pF
= 100mV
(DC) = 0.1V
A
= +2
V
L
L
-0.5
-0.6
-0.7
-0.8
V
2
1
0
R
C
V
R
C
V
= 150Ω
= 2pF
L
L
= 100mV
OUT
P-P
OUT
P-P
V
V
(DC) = 0.1V
IN
IN
1M
FREQUENCY (Hz)
100M
1G
10k
100k
1M
FREQUENCY (Hz)
10M
100M
10k
100k
10M
FIGURE 6. 0.1 dB GAIN FLATNESS
FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS
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ISL55033
Typical Performance Curves(Continued)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-20
V+ = V+_OUT = 5V
V+ = V+_OUT = 5V
A
= +2
V
A
R
C
= +2
= 150Ω
= 2pF
V
L
L
R
C
V
= 150Ω
= 2pF
L
L
-40
= 1V
SOURCE
P-P
V
= 0.8VDC+1V
IN
P-P
ALL INPUTS = +0.2V DC
ALL INPUTS = +0.8VDC
-60
-80
-100
-120
-140
100k
10M
100M
10k
1M
10k
100k
1M
FREQUENCY (Hz)
10M
100M
1G
FREQUENCY (Hz)
FIGURE 8. OFF-ISOLATION vs FREQUENCY
FIGURE 7. PSRR vs FREQUENCY
10000
1000
100
0
-10
-20
-30
-40
-50
-60
-70
-80
V+ = V+_OUT = 5V
A
R
C
= +2
= 150Ω
= 2pF
V
L
L
V
(DRIVEN CHANNEL)=2V
P-P
OUT
ALL INPUTS = +0.8V DC
10
1M
FREQUENCY (Hz)
100M
1G
10k
100k
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 10. OUTPUT VOLTAGE NOISE DENSITY vs FREQUENCY
FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs FREQUENCY
5.5
1000
1.8
5.0
DISABLE
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.5
1.2
0.9
0.6
0.3
0
V
100
10
1
OUT
V
= 5V
= +2
= 150Ω
= 2pF
+
A
V
R
C
V
L
L
= 0.5V
IN
ENABLE
EN
-0.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
1
10
100
1k
10k
100k
1M
10M
TIME (µs)
FREQUENCY (Hz)
FIGURE 11. INPUT CURRENT NOISE DENSITY vs FREQUENCY
FIGURE 12. ENABLE/DISABLE TIMING
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ISL55033
Typical Performance Curves(Continued)
0.62
0.60
0.58
0.56
0.54
0.52
0.50
0.48
3.0
2.5
2.0
1.5
1.0
0.5
0
V+ = V+_OUT = 5V
V+ = V+_OUT = 5V
A
= +2
V
A
R
C
= +2
= 150Ω
= 2.0pF
R
C
V
= 150Ω
= 2.0pF
V
L
L
L
L
= 100mV
OUT
P-P
V
= 2V
OUT
P-P
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 13. SMALL SIGNAL STEP RESPONSE
FIGURE 14. LARGE SIGNAL (2V ) STEP RESPONSE
P-P
4.0
0.014
0.012
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V+ = V+_OUT = 5V
0.010
A
R
C
= +2
= 150Ω
= 2pF
V
L
L
0.008
0.006
0.004
0.002
0
V+ = V+_OUT = 5V
F = 3.58MHz
= 100mV
A
= +2
V
V
OUT
P-P
R
C
= 150Ω
= 2.0pF
L
L
V
= 3V
OUT
P-P
-0.002
-0.004
-0.006
-0.008
-0.01
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
INPUT DC OFFSET (V)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 15. LARGE SIGNAL (3V ) STEP RESPONSE
P-P
FIGURE 16. DIFFERENTIAL GAIN
1000
100
10
0.1
0.05
0
V+ = V+_OUT = 5V
A
C
= +2
= 2.0pF
= 1.25V DC
V
L
V
V
IN
= 1V
SOURCE
P-P
V+ = V+_OUT = 5V
-0.05
A
R
C
= +2
= 150Ω
= 2pF
V
L
L
-0.10
-0.15
-0.20
-0.25
-0.3
F = 3.58MHz
= 100mV
V
OUT
P-P
1
0.1
100k
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
INPUT DC OFFSET (V)
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 18. Z
(ENABLED) vs FREQUENCY
FIGURE 17. DIFFERENTIAL PHASE
OUT
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ISL55033
Typical Performance Curves(Continued)
10000
1000
100
1M
100k
10k
1k
V+ = V+_OUT = 5V
A
= +2
= 2.0pF
= 1.25V DC
V+ = 5V
V
L
C
V
A
R
C
= +2
= 150Ω
= 3.0pF
V
L
L
IN
V
= 1V
SOURCE
P-P
100
10
V
V
= 1.25V DC
IN
= 1V
SOURCE
P-P
10
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 19. Z
(DISABLED) vs FREQUENCY
OUT
FIGURE 20. Z vs FREQUENCY
IN
24
20
16
12
8
4
R
= OPEN
L
0
1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0 5.4 5.8
SUPPLY VOLTAGE (V)
FIGURE 21. SUPPLY CURRENT vs SUPPLY VOLTAGE
720
670
7.25
MAX
MAX
7.20
7.15
7.10
7.05
7.00
6.95
6.90
6.85
6.80
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
= 1kΩ
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
620
570
520
470
420
370
R
L
R
= 1kΩ
L
MEDIAN
MEDIAN
MIN
MIN
20
-40 -20
0
20
40
60
80
100 120
-40 -20
0
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. DISABLED SUPPLY CURRENT vs TEMPERATURE
FIGURE 22. ENABLED SUPPLY CURRENT vs TEMPERATURE
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ISL55033
Typical Performance Curves(Continued)
7
4
3
MAX
MAX
6
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
5
2
4
R
= 1kΩ
R
= 150Ω
L
L
1
3
MEDIAN
2
0
MEDIAN
1
-1
-2
-3
-4
0
MIN
40
-1
-2
-3
MIN
20
-40 -20
0
40
60
80
100 120
-40 -20
0
20
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 24. OUTPUT OFFSET VOLTAGE V vs TEMPERATURE
OS
FIGURE 25. OUTPUT OFFSET VOLTAGE V vs TEMPERATURE
OS
-4.5
SAMPLE SIZE = 100
115
V+ = V+_OUT = 5V
SAMPLE SIZE = 100
V = 3V to 5.5V
MAX
-5.0
MAX
S
105
95
-5.5
MEDIAN
-6.0
85
MIN
MEDIAN
-6.5
-7.0
75
MIN
0
65
-40 -20
20
40
60
80
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 27. PSRR vs TEMPERATURE
FIGURE 26. I
BIAS
vs TEMPERATURE
160
4.61
4.60
4.59
4.58
4.57
4.56
4.55
4.54
4.53
4.52
4.51
4.50
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
= 150Ω
155
150
145
140
135
130
125
120
115
110
R
= 150Ω
R
L
L
MAX
MAX
MEDIAN
MEDIAN
MIN
MIN
-40 -20
0
20
40
60
80
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 28. V
OUT
HIGH vs TEMPERATURE
FIGURE 29. V
OUT
LOW vs TEMPERATURE
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ISL55033
Typical Performance Curves(Continued)
34
32
30
28
26
24
22
4.78
4.77
4.76
4.75
4.74
4.73
4.72
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
SAMPLE SIZE = 100
V+ = V+_OUT = 5V
R
= 1kΩ
L
MAX
R
= 1kΩ
L
MAX
MEDIAN
MIN
MEDIAN
MIN
-40 -20
0
20
40
60
80
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 31. V
OUT
LOW vs TEMPERATURE
FIGURE 30. V
OUT
HIGH vs TEMPERATURE
DECOUPLING CAPACITORS (0.1µF || 1nF FOR EACH PIN)
V+
EN
V+_OUT
GND_OUTPUT
IN+_1
IN+_2
IN+_3
OUT_1
OUT_2
R
1
2
OUT
R
1
IN
R
OUT
R
2
3
IN
OUT_3
R
3
OUT
R
IN
GND_IN-(1, 2, 3)
FIGURE 32. BASIC APPLICATION CIRCUIT
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ISL55033
amplifiers off. The output presents a relatively high impedance
Application Information
General
The ISL55033 single supply, fixed gain, triple amplifier is
intended for use in a variety of video and other high speed
applications. The device features a ground-sensing PNP input
stage and a bipolar rail-to-rail output stage. The three amplifiers
have an internally fixed gain of 2 and share a single enable pin as
shown in Figure 32.
(~2kΩ) to the output pin. Multiplexing several outputs together is
possible using the enable/disable function as long as the
application can tolerate the limited power-down output
impedance.
Limiting the Output Current
No output short-circuit current limit exists on these parts. All
applications need to limit the output current to less than 40mA.
Adequate thermal heat sinking of the parts is also required.
Ground Connections
PC Board Layout
The AC performance of this circuit depends greatly on the care
taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
For the best isolation performance and crosstalk rejection, all
GND pins must connect directly to the GND plane. In addition, the
electrically conductive thermal pad (EP) must also connect
directly to ground.
Power Considerations
• The use of low inductance components, such as chip resistors
and chip capacitors, is strongly recommended.
Separate V+ power supply and GND pins for the input and output
stages are provided to maximize PSRR. Providing separate
power pins provides a way to prevent high speed transient
currents in the output stage from bleeding into the sensitive
amplifier input and gain stages. To maximize crosstalk isolation,
each power supply pin should have its own decoupling capacitors
connected as close to the pin as possible as shown in Figure 32
(0.1µF in parallel with 1nF recommended).
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners. Use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
frequency performance may be degraded for traces greater
than one inch, unless controlled impedance (50Ωor75Ωstrip
lines or microstrips are used.
The ESD protection circuits use internal diodes from all pins to the
V+ and ground pins. In addition, a dV/dt-triggered clamp is
connected between the V+ and V- pins, as shown in Equivalent
Circuit 1 on page 2. The dV/dt triggered clamp imposes a
maximum supply turn-on slew rate of 1V/µs. Damaging currents
can flow for power supply slew rates in excess of 1V/µs, such as
during hot plugging. Under these conditions, additional methods
should be employed to ensure the maximum supply slew rate is
not exceeded.
• Match channel-to-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
• Maximize use of AC decoupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or PCB gaps under these lines). Avoid vias in the signal I/O
lines.
• Use proper value and location of termination resistors. Input
termination resistors should be as close to the input terminal as
possible and output termination resistors as close to the receiving
device as possible.
Single Supply Input/Output Considerations
For best performance, the input signal voltage range should be
maintained between 0.1V to 2.1V. These input limits correspond
to an output voltage range of 0.2V to 4.2V and define the limits
of linear operation. Figure 4 shows the frequency response
versus the input DC voltage level. Figures 16 and 17 show the
differential gain-phase performance over the input range of 0V to
2.4V operating into a 150Ω load. The 0.1V to 2.1V input levels
corresponds to a 0.2V to 4.2V output levels, which define the
minimum and maximum range of output linear operation.
• When testing, use good quality connectors and cables, matching
cable types and keeping cable lengths to a minimum.
• A minimum of two, high frequency, power supply decoupling
capacitors (1000pF, 0.1µF), on each V+ pin, are recommended as
close to the devices as possible. Avoid vias between the capacitor
and the device because vias add unwanted inductance. Larger
capacitors (e.g., electrolytics) can be farther away. When vias are
required in a layout, they should be routed as far away from the
device as possible.
Composite video with sync requires care to ensure that the
negative sync tip voltage (typically -300mV) is properly
level-shifted up into the ISL55033 input linear operating region
of +0.1V to 2.1V. The high input impedance enables AC coupling
using low values of coupling capacitance with relatively high
input voltage divider resistances.
EN and Power-down States
The EN pin is active low. An internal pull-down resistor ensures
the device will be active with no connection to the EN pin. The
power-down state is established within approximately 25ns, if a
logic high (>2V) is placed on the EN pin. In the power-down state,
supply current is reduced significantly by shutting the three
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ISL55033
pad. Maximum AC performance is achieved if the thermal pad
The QFN Package Requires Additional PCB
Layout Rules for the Thermal Pad
The thermal pad (EP) is electrically connected to power supply
ground (GND_PWR) through the high resistance IC substrate. Its
primary function is to provide heat sinking for the IC. However,
because of the connection to the power ground pins through the
substrate, the thermal pad must be tied to the power supply
ground to prevent unwanted current flow through the thermal
has good contact to the IC ground pins. Heat sinking
requirements can be satisfied using thermal vias directly
beneath the thermal pad to a heat dissipating layer of a square
at least 1” on a side. Fill the PCB pad under the EP with vias and
connect those vias to a substantial ground plane. Reference
TB379, section 3) on page 2 and Appendix A, or JEDEC JESD51-5,
for more information.
l
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN6346.1
CHANGE
June 29, 2015
-Pin Descriptions table on page 2, updated equivalent circuit as follows:
Pin number 4: from Circuit 1 to Circuit 4.
Pin number 5: from Circuit 4 to Circuits 1, 2, 4, 5 and added sentence to the description.
Pin number 6: from Circuit 4 to Circuit 3.
Pin number 10: from Circuit 4 to Circuit 3.
Pin number 12: from Circuit 4 to Circuits 1, 2, 4.
Added EP details to the table.
Updated Circuits 3 and 4 figure.
-Ordering information table on page 2: Removed ISL55033EVAL1Z.
- Ordering information table on page 2: Added MSL note.
-Thermal Information table on page 3, added “Theta jc” and reference “Note 5”.
-“Electrical Specification” table on page 3, test condition from V+ = 5V to V+_VOUT = 5V.
-Electrical Specification” table on page 3, under enable section changed “Parameter” name “VIH-ENB” to
“VIL-ENB” for the 0.8V typical value and changed “Parameter” name “VIL-ENB” to “VIH-ENB” for the 2V
typical value.
-“PC Board Layout” on page 11, changed reference from “0.01µF” cap to “0.1µF”, removed paragraph
referencing “NIC” pins.
-updated “The QFN Package Requires Additional PCB Layout Rules for the Thermal Pad” on page 12
paragraph.
- Added revision history and about Intersil verbiage.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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ISL55033
Package Outline Drawing
L12.3x3A
12 LEAD THIN QUAD FLAT NO LEAD PLASTIC PACKAGE
Rev 0, 09/07
3.00
0 . 5
BSC
A
6
B
12
10
PIN #1 INDEX AREA
6
PIN 1
INDEX AREA
9
7
1
3
0.10
M C A B
0.15
(4X)
4
0.25 +0.05 / -0.07
6
4
12X 0 . 4 ± 0 . 1
TOP VIEW
BOTTOM VIEW
SEE DETAIL "X"
C
0.10
C
0 . 75
BASE PLANE
SEATING PLANE
0.08
( 2 . 8 TYP )
C
SIDE VIEW
5
0 . 6
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
0 . 50
0 . 25
NOTES:
DETAIL "X"
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
TYPICAL RECOMMENDED LAND PATTERN
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
Tiebar shown (if present) is a non-functional feature.
5.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
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