ISL55036 [INTERSIL]
400MHz Slew Rate Enhanced Rail-to-Rail Output Gain Block; 400MHz的压摆率增强的轨至轨输出增益模块
| 型号： | ISL55036 |
| 厂家： | 
Intersil |
| 描述： | 400MHz Slew Rate Enhanced Rail-to-Rail Output Gain Block |
| 文件： | 总11页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL55036
®
Data Sheet
September 11, 2008
FN6640.1
400MHz Slew Rate Enhanced Rail-to-Rail
Output Gain Block
Features
• 400MHz -3dB Bandwidth
The ISL55036 is a hex, rail-to-rail output, fixed gain amplifier
(G = 4) with a -3dB bandwidth of 400MHz and slew rate of
2500V/µs into a 150Ω load. The ISL55036 features single
supply operation over a voltage range of 3VDC to 5.5VDC.
The inputs are capable of sensing ground with an output
swing of VCC - 0.3V into a 150Ω load tied to V+/2. The part
includes a fast-acting global disable/power-down circuit.
The ISL55036 is available in a 24 Ld TQFN package.
Operation is specified over the -40°C to +85°C temperature
range.
• 2500V/µs Typical Slew Rate, R = 150Ω
L
• Supplies from 3V to 5.5V
• Rail-to-Rail Output (R = 1k)
L
• Input Ground Sensing
• Fast 25ns Disable
• Low Cost
• Pb-Free (RoHS Compliant)
Applications
Ordering Information
• Video RGB Line Driver
• LCD Based Projectors Pixel Control
PART
MARKING
PACKAGE
(Pb-free)
PKG.
DWG. #
PART NUMBER
ISL55036IRTZ
55036 IRTZ
24 Ld TQFN
24 Ld TQFN
L24.4x5C
L24.4x5C
Pinout
ISL55036IRTZ-T13* 55036 IRTZ
ISL55036
24 LD TQFN
TOP VIEW
*Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
24 23 22 21 20
IN+_2
IN+_3
1
2
3
4
5
6
19
18
17
OUT_2
OUT_3
0.80
0.75
0.70
GND_OUT(1, 2, 3)
GND_PWR(1, 2, 3)
V+_OUT(4,5,6)
OUT_4
GND_IN(1, 2, 3)
EN(4, 5, 6)
V+(4, 5, 6)
IN+_4
DIE 1
16
15
14
13
V
= 5V
= +4
= 150Ω
= 3.0pF
+
0.65
0.60
0.55
0.50
0.45
A
V
R
C
V
L
L
= 250mV
P-P
OUT_5
OUT
DIE 2
10 11 12
IN+_5
7
8
9
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 1. SMALL SIGNAL STEP RESPONSE
A
EACH CHANNEL
V
EQUALS +4
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
ISL55036
Pin Descriptions
EQUIVALENT
CIRCUIT
24 LD TQFN
PIN NAME
DESCRIPTION
1
2
3
4
IN+_2
Circuit 1
Circuit 1
Circuit 4
Circuit 2
Amplifier 2 non-inverting input
Amplifier 3 non-inverting input
IN+_3
GND_IN(1, 2, 3)
EN(4, 5, 6)
Common reference input for Amplifiers 1, 2, 3
Enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects
the enabled state. Channels 4, 5, 6
5
V+(4, 5, 6)
Circuit 5
Circuit 1
Circuit 1
Circuit 1
Circuit 5
Circuit 5
Circuit 3
Circuit 3
Circuit 3
Circuit 3
Circuit 3
Circuit 4
Circuit 3
Circuit 3
Circuit 3
Circuit 3
Circuit 3
Circuit 2
Positive power supply for Channels 4, 5, 6.
Amplifier 4 non-inverting input
Amplifier 5 non-inverting input
Amplifier 6 non-inverting input
Common reference input for Amplifiers 4, 5, 6
Power supply ground for Channels 4, 5, 6.
Output power supply ground for Channels 4, 5, 6.
Amplifier 6 output
6
IN+_4
7
IN+_5
8
IN+_6
9
GND_IN(4, 5, 6)
GND_PWR(4, 5, 6)
GND_OUT(4, 5, 6)
OUT_ 6
10
11
12
13
14
15
16
17
18
19
20
21
22
OUT_ 5
Amplifier 5 output
OUT_4
Amplifier 4 output
V+_OUT(4, 5, 6)
GND_PWR(1, 2, 3)
GND_OUT(1, 2, 3)
OUT_3
Output power supply for Channels 4, 5, 6.
Power supply ground Channels 1, 2, 3.
Output power supply ground Channels 1, 2, 3.
Amplifier 3 output
OUT_2
Amplifier 2 output
OUT_1
Amplifier 1 output
V+_OUT(1, 2, 3)
EN(1, 2, 3)
Output power supply Channels 1, 2, 3.
Enable pin internal pull-down; Logic “1” selects the disabled state; Logic “0” selects
the enabled state. Channels 1, 2, 3
23
24
V+(1, 2, 3)
IN+_1
Circuit 4
Circuit 1
Circuit 6
Positive power supply for Channels 1, 2, 3.
Amplifier 1 non-inverting input
Thermal Pad
Thermal heat sink pad makes electrical contact the IC substrate and must be
connected to same ground potential as the ground pins.
V+_OUT(1, 2, 3)
V+
V+
V+_OUT(4, 5, 6)
21k
+
OUT(1, 2, 3)
OUT(4, 5, 6)
IN+
EN
dv/dt
CLAMP
1.2V
GND_PWR
-
GND_OUT(1, 2, 3)
GND_OUT(4, 5, 6)
GND_PWR
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
V+(1, 2, 3)
V+(4,5,6)
SUBSTRATE 1
GND_PWR (1,2,3)
SUBSTRATE 2
GND_IN-(1,2,3)
GND_IN-(4, 5, 6)
GND(4, 5, 6)
~1MΩ
~1MΩ
500
500
1.5k
1.5k
GND_PWR(1,2,3)
GND_PWR(4, 5, 6)
THERMAL HEAT SINK PAD
CIRCUIT 6
CIRCUIT 4
CIRCUIT 5
FN6640.1
September 11, 2008
2
ISL55036
Absolute Maximum Ratings (T = +25°C)
Thermal Information
A
Supply Voltage from V+ to GND . . . . . . . . . . . . . . . . . . . . . . . 5.75V
Supply Turn On Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . 1V/µs
EN Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4mA
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . V+ + 0.3V to GND - 0.3V
Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
ESD Rating:
Thermal Resistance (Typical, Note 1)
θ
(°C/W)
42
JA
24 Ld TQFN Package . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +125°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,000V
Machine Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300V
Operating Conditions
Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . .+125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are
at the specified temperature and are pulsed tests, therefore: T = T = T
A
J
C
1. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications V = 5V, T = +25°C, R = 1k to V /2, A = 4, V = 0.1VDC, Unless Otherwise Specified.
+
A
L
+
V
IN
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 3)
TYP
(Note 3)
UNIT
INPUT CHARACTERISTICS
TCV
IB
Offset Voltage Temperature Coefficient Measured from -40°C to +85°C
-3
-5.5
7
µV/°C
µA
OS
Input Bias Current
Input Resistance
Input Capacitance
V
= 0V
-10
-2.5
IN
R
C
MΩ
pF
IN
0.5
IN
OUTPUT CHARACTERISTICS
V
A
Output Offset Voltage
Closed Loop Gain
Note 2
-14
3.9
-2
4
10
mV
V/V
mΩ
V
OS
CL
R
= 1k, 150Ω, V
= 0.5V to 4V
OUT
4.1
L
R
Output Resistance
A
= +4
30
OUT
OP
V
V
Positive Output Voltage Swing
R = 1kΩ to 2.5V
4.86
4.65
27
L
R = 150Ω to 2.5V
V
L
V
Negative Output Voltage Swing
R
= 1kΩ to 2.5V
L
mV
mV
mA
mA
ON
R = 150Ω to 2.5V
140
95
L
I
I
(source)
Output Short Circuit Current
Output Short Circuit Current
R
R
= 10Ω to GND, V = 1.5V
IN
60
70
SC
SC
L
L
(sink)
= 10Ω to + 2.5V, V = 0V
IN
105
POWER SUPPLY
PSRR Power Supply Rejection Ratio @ 1kHz V+ = 5V; V
= 1V
;
P-P
78
dB
SOURCE
f = 1kHz sine wave
I
I
Supply Current - Enabled per Amplifier
R
= Open
L
6.0
0.5
7.2
1.1
8.5
2
mA
mA
S-ON
Supply Current - All Amplifiers Disabled R = Open
S-OFF
L
ENABLE
t
t
Enable Time
R
= 150Ω, V = 0.25V
L IN
250
25
0.8
2
ns
ns
V
EN
DS
Disable Time
R = 150Ω, V = 0.25V
IN
L
V
V
ENABLE Pin Voltage for Power-Up
ENABLE Pin Voltage for Shut-Down
IH-ENB
IL-ENB
V
FN6640.1
September 11, 2008
3
ISL55036
Electrical Specifications V = 5V, T = +25°C, R = 1k to V /2, A = 4, V = 0.1VDC, Unless Otherwise Specified. (Continued)
+
A
L
+
V
IN
MIN
MAX
PARAMETER
DESCRIPTION
CONDITIONS
(Note 3)
TYP
(Note 3)
UNIT
µA
I
I
ENABLE Pin Input Current High
ENABLE Pin Input for Current Low
V
V
= 5V
= 0V
1
5.5
20
4
IH-ENB
IL-ENB
EN
-4
µA
EN
AC PERFORMANCE
BW
BW
Peak
dG
-3dB Bandwidth
R = 150Ω, C = 3pF
400
40
MHz
MHz
dB
L
L
±0.1dB Bandwidth
Peaking
R = 150Ω, C = 3pF
L
L
R
= 150Ω, C = 3pF
1
L
L
Differential Gain
Differential Phase
Output Noise Voltage
Input Noise Current
Off-State Isolation
V
= 0.1V to 1.0V, V
= 100mV ,
P-P
0.06
0.01
50
%
IN
OUT
f = 3.58MHz, R = 150Ω
L
dP
°
e
f = 10kHz
f = 10kHz
nV/√Hz
pA/√Hz
dB
N-OUT
i
0.9
-100
N
ISO
V
= 0.6VDC + 1V , C = 3pF,
P-P
IN
R = 150Ω
L
f
= 10MHz
O
L
X-TALK
Die to Die Crosstalk
= 10MHz
V
= 0.6VDC + 1V , C = 3pF,
P-P
-85
-65
-55
dB
dB
dB
IN
R = 150Ω
L
f
O
L
Same Die Channel-to-Channel
Crosstalk, f = 10MHz
O
PSRR
Power Supply Rejection Ratio
V
= 1V , C = 3pF, R = 150Ω
P-P
SOURCE
L
L
f
= 10MHz
O
TRANSIENT RESPONSE
SR Slew Rate 25% to 75%
t , t Large Rise Time, t 20% to 80%
R
= 150Ω, V
= 0.5V to 4.5V
OUT
2500
1.4
1
V/µs
ns
ns
ns
ns
ns
ns
%
L
V
V
V
= 4V
, R = 150Ω, C = 3pF
L L
r
f
r
OUT
P-P
Signal
Fall Time, t 20% to 80%
f
Rise Time, t 20% to 80%
= 2V
, R = 150Ω, C = 3pF
0.8
0.7
0.75
0.7
5
r
OUT
OUT
P-P
L
L
Fall Time, t 20% to 80%
f
t , t , Small
Rise Time, t 20% to 80%
= 0.2V
, R = 150Ω, C = 3pF
P-P
r
f
r
L
L
Signal
Fall Time, t 20% to 80%
f
OS
Overshoot
200mV step
200mV step
2V step
t
t
t
Propagation Delay
0.6
12
ns
ns
ns
PD
S
1% Settling Time
ENABLE to Output Turn-on Delay Time;
V
= 1VDC, R = 150Ω, C = 3pF
250
EN
OUT
L
L
10% EN - 10% V
OUT
ENABLE to Output Turn-off Delay Time;
10% EN - 10% V
V
= 1VDC, R = 150Ω, C = 3pF
25
ns
OUT
L
L
OUT
NOTES:
2. V
is extrapolated from 2 output voltage measurements, with V = 62.5mV and V = 125mV, R = 1k.
IN IN
OS
L
3. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN6640.1
September 11, 2008
4
ISL55036
Typical Performance Curves
6
5
4
5
4
R
= 1k
L
C
= 11.2pF
L
3
R
= 499
L
2
3
C
= 7.7pF
L
1
-2
-1
0
0
-1
-2
-3
-4
-5
-6
-7
C
= 5.2pF
L
-1
-2
-3
-4
-5
V
= 5V
= +4
= 3pF
+
C
= 3.0pF
L
A
V
= 5V
= +4
V
+
R
= 150
C
V
A
L
L
V
= 100mV
R = 150Ω
OUT
P-P
L
R
= 100
L
V
= 100mV
1M
OUT
P-P
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
10M
FREQUENCY (Hz)
100M
1G
FIGURE 2. GAIN vs FREQUENCY FOR VARIOUS R
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS C
LOAD
LOAD
1
0
15
14
13
12
V
= 4V
P-P
OUT
-1
-2
-3
-4
-5
-6
-7
-8
-9
V
= 3V
P-P
OUT
V
= 100mV
P-P
OUT
ALL CHANNELS
11
V
= 1V
OUT
OUT
P-P
P-P
10
9
V
= 2V
V
= 5V
= +4
= 150Ω
= 3pF
8
7
6
5
+
V
= 5V
= +4
= 150Ω
= 3pF
A
+
V
A
R
C
V
V
L
L
R
C
L
L
= 100mV
100k
OUT
P-P
1M
FREQUENCY (Hz)
100M
1G
10k
10M
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 4. -3dB BANDWIDTH vs V
FIGURE 5. GAIN vs FREQUENCY - ALL CHANNELS
OUT
0
0.2
0.1
V
= 5V
= +4
= 150Ω
= 3pF
-10
-20
-30
-40
-50
-60
-70
-80
-90
+
A
V
0
R
C
V
L
L
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
= 1V
P- P
SOURCE
ALL INPUTS = +0.2V DC
V
= 5V
= +4
= 150Ω
= 3pF
= 100mV
100k
+
A
V
R
C
L
L
V
OUT
P-P
100k
FREQUENCY (Hz)
10M
100M
1k
10k
1M
1M
FREQUENCY (Hz)
100M
10k
10M
FIGURE 6. 0.1 dB GAIN FLATNESS
FIGURE 7. PSRR vs FREQUENCY
FN6640.1
September 11, 2008
5
ISL55036
Typical Performance Curves (Continued)
0
-20
0
V
= 5V
= +4
= 150Ω
= 3pF
+
V
= 5V
= +4
= 150Ω
= 3pF
A
+
V
A
R
C
V
-20
-40
V
L
L
R
C
V
L
L
(DRIVEN CHANNEL)=4V
P-P
OUT
-40
= 0.6VDC+1V
P-P
IN
ALL INPUTS = +0.6V DC
ALL INPUTS = +0.6VDC
-60
-60
CHANNELS ON SAME DIE
-80
-80
-100
-120
-100
-120
CHANNELS ON DIFFERENT DIE
1M
FREQUENCY (Hz)
100M
1G
10k
100k
10M
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
FIGURE 9. CHANNEL-TO-CHANNEL CROSSTALK vs
FREQUENCY
FIGURE 8. OFF ISOLATION vs FREQUENCY
100.0
10.0
1.0
10000
1000
100
10
0.1
1
1M
10
100
1k
10k
100k
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. INPUT REFERRED NOISE CURRENT vs
FREQUENCY
FIGURE 10. OUTPUT NOISE VOLTAGE vs FREQUENCY
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.8
1.5
1.2
0.9
0.6
0.3
0
0.80
0.75
0.70
DISABLE
V
OUT
V
= 5V
= +4
= 150Ω
= 3.0pF
+
0.65
0.60
0.55
0.50
0.45
A
V
R
C
V
L
L
V
= 5V
= +4
= 150Ω
= 3pF
+
A
= 250mV
P-P
V
OUT
R
C
V
L
L
= 0.25V
IN
ENABLE
-0.5
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
TIME (µs)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 12. ENABLE/DISABLE TIMING
FIGURE 13. SMALL SIGNAL STEP RESPONSE
FN6640.1
September 11, 2008
6
ISL55036
Typical Performance Curves (Continued)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.0
2.5
2.0
V
= 5V
= +4
= 150Ω
= 3.0pF
+
V
= 5V
= +4
= 150Ω
= 3.0pF
+
A
V
A
V
R
C
V
L
L
1.5
1.0
0.5
0
R
C
V
L
L
= 4V
P-P
OUT
= 2V
P-P
OUT
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
0
5
10 15 20 25 30 35 40 45 50
TIME (ns)
FIGURE 15. LARGE SIGNAL (4V ) STEP RESPONSE
P-P
FIGURE 14. SMALL SIGNAL (2V
) STEP RESPONSE
P-P
0.04
0.02
0
0.004
0.002
0
-0.02
-0.002
V
= 5V
= +4
= 150Ω
= 3pF
V
= 5V
= +4
= 150Ω
= 3pF
+
+
A
-0.04
-0.06
-0.08
-0.10
A
V
-0.004
-0.006
-0.008
-0.010
V
R
C
R
C
L
L
L
L
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
INPUT DC OFFSET (V)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
INPUT DC OFFSET (V)
FIGURE 17. DIFFERENTIAL PHASE
FIGURE 16. DIFFERENTIAL GAIN
100k
10k
1k
V
= 5V
= +4
= 150Ω
= 3.0pF
+
A
V
R
C
V
L
L
= 100mV
P-P
SOURCE
100
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 18. Z vs FREQUENCY
IN
FN6640.1
September 11, 2008
7
ISL55036
Typical Performance Curves (Continued)
100.00
10k
1k
V
= 5V
= +4
= 150Ω
= 3.0pF
+
A
V
R
C
L
L
10.00
1.00
0.10
0.01
V
= 100mV
P-P
SOURCE
100
10
V
= 5V
= +4
= 150Ω
= 3.0pF
+
A
V
R
C
V
L
L
= 100mV
P-P
SOURCE
100k
1M
10M
FREQUENCY (Hz)
100M
1G
100k
1M
10M
FREQUENCY (Hz)
100M
1G
FIGURE 19. Z
(ENABLED) vs FREQUENCY
OUT
FIGURE 20. Z
(DISABLED) vs FREQUENCY
OUT
7.8
1.21
n = 100
7.7
n = 100
MAX
MAX
1.16
1.11
1.06
1.01
0.96
7.6
7.5
7.4
7.3
7.2
7.1
7.0
MEDIAN
MIN
MEDIAN
MIN
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 21. ENABLED SUPPLY CURRENT vs
FIGURE 22. DISABLED SUPPLY CURRENT vs
TEMPERATURE, V = ±2.5V
S
TEMPERATURE, V = ±2.5V
S
6
-4.7
n = 100
n = 100
MAX
-4.9
MAX
4
2
-5.1
-5.3
-5.5
-5.7
-5.9
-6.1
-6.3
-6.5
-6.7
MEDIAN
MIN
0
MEDIAN
-2
-4
MIN
-6
-8
-40
-20
0
20
40
60
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
TEMPERATURE (°C)
FIGURE 23. OUTPUT OFFSET VOLTAGE V
vs
TEMPERATURE, V = ±2.5V, R = 1k
FIGURE 24. I
vs TEMPERATURE, V = ±2.5V
BIAS S
OS
S
L
FN6640.1
September 11, 2008
8
ISL55036
Typical Performance Curves (Continued)
120
MAX
115
n = 100
110
105
100
95
MEDIAN
MIN
90
85
80
-40
-20
0
20
40
60
80
TEMPERATURE (°C)
FIGURE 25. PSRR vs TEMPERATURE 4.5V TO 5.5V
clamp imposes a maximum supply turn-on slew rate of 1V/µs.
Application Information
Damaging currents can flow for power supply rates-of-rise in
excess of 1V/µs, such as during hot plugging. Under these
conditions, additional methods should be employed to ensure
the maximum rate of rise is not exceeded.
General
The ISL55036 single supply, fixed gain hex amplifier is well
suited for a variety of video applications. The device features
a PNP ground-sensing input stage and a bipolar rail-to-rail
output stage.
EN and Power-Down States
The EN pin is active low. An internal pull-down resistor
ensures the device will be active with no connection to the
EN pin. The power-down state is established within
approximately 25ns, if a logic high (>2V) is placed on the EN
pin. In the power-down state, supply current is reduced
significantly by shutting the three amplifiers off. The output
presents a relatively high impedance (~2kΩ) to the output
pin. Multiplexing several outputs together is possible using
the enable/disable function as long as the application can
tolerate the limited power-down output impedance.
The ISL55036 is designed for general purpose video,
communication, instrumentation, and industrial applications.
The 6 fixed gain amplifiers operate independently, however,
they are organized into 2 triple amplifier groups as shown in
Figure 26. Each group has its own set of power supply pins,
ground pins, enable-disable logic and input ground
reference pins.
Ground Connections
For the best isolation performance and crosstalk rejection,
all GND pins must connect directly to the GND plane. In
addition, the electrically conductive thermal pad should also
connect directly to ground.
Limiting the Output Current
No output short circuit current limit exists on these parts. All
applications need to limit the output current to less than 40mA.
Adequate thermal heat sinking of the parts is also required.
Power Considerations
Each triple amplifier group has its own power supply and
PC Board Layout
ground pins. There are dedicated V OUT and GND V
+
OUT
The AC performance of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
pins to power only the output stage. A separate set of power
and ground pins power the rest of each of the triple op amps
(V and PWR GND). Providing separate power pins
+
provides a way to prevent high speed transient currents in
the output stage from bleeding into the sensitive amplifier
input and gain stages. To maximize crosstalk isolation, each
power supply pin should have its own de-coupling capacitors
connected as close to the pin as possible (0.1µF in parallel
with 1nF recommended).
• The use of low inductance components, such as chip
resistors and chip capacitors, is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid
sharp corners. Use rounded corners when possible. Vias
in the signal lines add inductance at high frequency and
should be avoided. PCB traces greater than 1" begin to
exhibit transmission line characteristics with signal rise/fall
times of 1ns or less. High frequency performance may be
The ESD protection circuits use internal diodes from all pins to
the V and ground pins. In addition, a dv/dt-triggered clamp is
+
connected between the V and V pins, as shown in the
+
-
Equivalent Circuits 1 through 4 on page 2. The dv/dt triggered
FN6640.1
September 11, 2008
9
ISL55036
DECOUPLING
CAPACITORS
V+(1,2,3)
EN(1,2,3)
V+_OUT(1,2,3)
GND_OUT(4,5,6)
IN+_1
IN+_2
IN+_3
OUT_1
OUT_2
R
1
2
3
OUT
R
4
5
6
IN
R
OUT
R
IN
OUT_3
R
OUT
R
IN
DIE 1
GND_PWR(1,2,3)
V+ (4,5,6)
GND_IN(1,2,3)
DECOUPLING
CAPACITORS
V+_OUT(4,5,6)
GND_OUT(4,5,6)
IN+_4
IN+_5
OUT_4
OUT_5
OUT_6
R
4
5
6
OUT
R
4
5
6
IN
R
OUT
R
IN
IN+_6
R
OUT
R
IN
DIE 2
GND_PWR(4,5,6)
GND_IN(4,5,6)
EN(4,5,6)
FIGURE 26. BASIC APPLICATION CIRCUIT
degraded for traces greater than one inch, unless
controlled impedance (50Ω or 75Ω) strip lines or
microstrips are used.
can be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
• Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e. no
split planes or PCB gaps under these lines). Avoid vias in the
signal I/O lines.
The thermal pad is electrically connected to power supply
ground through the high resistance IC substrate. Its primary
function is to provide heat sinking for the IC. However,
because of the connection to the power ground pins through
the substrate, the thermal pad must be tied to the power
supply ground to prevent unwanted current flow through the
thermal pad. Maximum AC performance is achieved if the
thermal pad has good contact to the IC ground pins. Heat
sinking requirements can be satisfied using thermal vias
directly beneath the thermal pad to a heat dissipating layer
of a square at least 1” on a side.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing, use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• A minimum of 2 power supply decoupling capacitors are
recommended (1000pF, 0.01µF) as close to the devices as
possible. Avoid vias between the capacitor and the device
because vias add unwanted inductance. Larger capacitors
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6640.1
September 11, 2008
10
ISL55036
Package Outline Drawing
L24.4x5C
24 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 10/07
4.00
2.65
A
PIN 1
PIN #1 INDEX AREA
24X0.40
INDEX AREA
CHAMFER 0.40×0 X 45°
B
20
24
6
6
1
19
3.65
0.5x6=3.00 REF
7
13
12
8
0.10
0.23±0.05
0.10
4X
0.50
M
C A B
TOP VIEW
0.5x4=2.00 REF
BOTTOM VIEW
SEE DETAIL X''
0.10
C
C
0.75
SEATING PLANE
0.08
C
(24x0.25)
(20x0.50)
SIDE VIEW
(3.65)
(4.80 TYP)
5
0 . 20 REF
C
(24x0.60)
(2.65)
(3.80 TYP)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.28mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6640.1
September 11, 2008
11
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