ISL55100BIRZ [INTERSIL]
Quad 18V Pin Electronics Driver/Window Comparator; 四路18V引脚电子驱动器/窗口比较器
| 型号： | ISL55100BIRZ |
| 厂家： | 
Intersil |
| 描述： | Quad 18V Pin Electronics Driver/Window Comparator |
| 文件： | 总13页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL55100B
®
Data Sheet
March 17, 2006
FN6229.0
Quad 18V Pin Electronics Driver/Window
Comparator
Features
• Low Driver Output Resistance
- R Typical: 9.0Ω
The ISL55100B is a Quad pin driver and window comparator
fabricated in a wide voltage CMOS process. It is designed
specifically for Test During Burn In (TDBI) applications,
where cost, functional density, and power are all at a
premium.
OUT
• 18V I/O Range
• 50MHz Operation
• 4 Channel Driver/Receiver Pairs with Per Pin Flexibility
• Dual Level - Per Pin - Input Thresholds
• Differential or Single Ended Digital Inputs
• User Defined Comparator Output Levels
• Low Channel to Channel Timing Skew
• Small Footprint (72 Ld QFN)
This IC incorporates four channels of programmable drivers
and window comparators into a small 72 Ld QFN package.
Each channel has independent driver levels, data, and high
impedance control. Each receiver has dual comparators
which provide high and low threshold levels.
The ISL55100B uses differential mode digital inputs, and can
therefore mate directly with LVDS or CML outputs. Single
ended logic families are handled by connecting one of the
digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility). The comparator outputs are
single ended, and the output levels are user defined to mate
directly with any digital technology.
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Burn In ATE
• Wafer Level Flash Memory Test
• LCD Panel Test
• Low Cost ATE
The 18V driver output and receiver input ranges allow this
device to interface directly with TTL, ECL, CMOS (3V, 5V,
and 7V), LVCMOS, and custom level circuitry, as well as the
high voltage (Super Voltage) level required for many special
test modes for Flash Devices.
• Instrumentation
• Emulation
Functional Block Diagram
QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS
• Device Programmers
VH(0-3)
Ordering Information
DATA+(0-3)
DATA-(0-3)
DOUT(0-3)
VL(0-3)
+
-
TEMP.
PART
PART
RANGE
(°C)
PKG.
NUMBER
MARKING
PACKAGE DWG. #
DRVEN+(0-3)
DRVEN-(0-3)
+
-
ISL55100BIRZ ISL55100BIRZ -40 to +85 72 Ld QFN L72.10x10
(See Note)
(Pb-free)
Add “-T” suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
QUAD - DUAL LEVEL COMPARATOR - RECEIVERS
V
CC
COMP HIGH
QA(0-3)
CVA(0-3)
VINP(0-3)
COMP LOW
V
V
EE
CC
COMP HIGH
QB(0-3)
COMP LOW
CVB(0-3)
V
EE
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL55100B
Pinout
ISL55100B (QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
DATA+ 0
DATA- 0
QA 1
V
EXT
1
2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VH 0
DOUT 0
NC
3
QB 1
4
DRV EN+ 1
DRV EN- 1
VL 0
5
VH 1
6
DATA+ 1
DATA- 1
QA 2
DOUT 1
NC
7
8
VL 1
9
QB 2
DRV EN+ 2
DRV EN- 2
DATA+ 2
VH 2
DOUT 2
NC
10
11
12
13
14
VL 2
DATA- 2
VH 3
QA 3
QB 3
DOUT 3
NC
15
16
17
18
40
39
38
37
DRV EN+ 3
DRV EN- 3
VL 3
LOSWING
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FN6229.0
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March 17, 2006
ISL55100B
Pin Descriptions
PIN
FUNCTION
DATA+(0:3) Positive differential digital input that determines the driver output state when it is enabled.
DATA-(0:3) Negative differential digital input that determines the driver output state when it is enabled.
DRV EN+(0:3) Positive differential digital input that enables or disables the corresponding driver.
DRV EN-(0:3) Negative differential digital input that enables or disables the corresponding driver.
QA (0:3)
QB (0:3)
Comparator digital outputs. QA(X) is high when VINP(X) exceeds CVA(X).
Comparator digital outputs. QB(X) is high when VINP(X) exceeds CVB(X).
DOUT (0:3) Driver outputs.
VINP (0:3)
VH (0:3)
VL (0:3)
NC
Comparator inputs.
Unbuffered analog inputs that set each individual driver’s “high” voltage level.
Unbuffered analog inputs that set each individual driver’s “low” voltage level. VL must be a lower voltage than VH.
No internal connection.
CVA (0:3)
CVB (0:3)
COMP HI
COMP LO
Analog inputs that set the threshold for the corresponding channel’s A comparators.
Analog inputs that set the threshold for the corresponding channel’s B comparators.
Supply voltage, unbuffered input that sets the high output level of all comparators. Must be greater than COMP LO.
Supply voltage, unbuffered input that sets the low output level of all comparators. Must be less than COMP HI.
Positive power supply (5% tolerance).
V
CC
V
Negative power supply (5% tolerance).
EE
V
External 5.5VDC power supply (-0%+5% tolerance, referenced to V , NOT GND) for internal logic. Connect pin to V when
EE EE
EXT
not using an external supply.
LOSWING
Input that selects driver output configurations optimized to yield minimum overshoots for low level swings (VH < V +5V), or
EE
to select high
optimized for large output swings. Connect LOSWING to V to select low swing circuitry, or connect it to V
EE
CC
swing circuitry.
Truth Tables
RECEIVERS
DRIVERS
INPUT
OUTPUTS
INPUTS
OUTPUT
DOUT
Hi - Z
VH
VINP
QA
0
QB
0
DATA
DRV EN
+ > -
<CVA
<CVA
>CVA
>CVA
<CVB
X
+ > -
>CVB
<CVB
>CVB
0
1
+ < -
1
0
+ < -
+ < -
VL
1
1
X = DON’T CARE
FN6229.0
March 17, 2006
3
ISL55100B
Absolute Maximum Ratings
Thermal Information
Thermal Resistance (Typical, Note 1)
72 Ld QFN Package. . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150°C
Maximum Storage Temperature Range. . . . . . . . . . .-65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C
V
to V
EXT
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
EE
θ
JA
(°C/W)
23
θ
JC
(°C/W)
2.0
CC
EE
V
to V
Input Voltages
DATA, DRV EN, CVX, VH, VL, VINP, COMPX, LOSWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V
EE
+0.5V)
+0.5V)
CC
Output Voltages
DOUT . . . . . . . . . . . . . . . . . . . . . . . . (V -0.5V) to (V
EE
CC
QX . . . . . . . . . . . . . (COMP LOW -0.5V) to (COMP HIGH +0.5V)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured in free air with the component mounted on high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379 and Tech Brief TB389 for details. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review Power
Dissipation Considerations for more information.
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
TYP
MAX
18
UNITS
Device Power-(V
= V
V
not used
V
-V
12 (Note 5)
9 (Note 5)
5.5 (Note 5)
15
V
V
EXT
EXT
EE) EXT
= V +5.5V)
CC EE
Device Power-(V
V
-V
15
18
EE
CC EE
V
Optional External Logic Power
V
-V
5.75
6.0
V
EXT
EXT EE
Driver Output High Rail
Driver Output Low Rail
Comparator Output High Rail
Comparator Output Low Rail
Ambient Temperature
V
V
+1
EE
-
-
-
-
-
-
V
V
-0.5
CC
V
H
V
V
+0.5
EE
V
+6
V
L
EE
COMP-High
COMP-Low
V
+1
EE
-0.5
V
CC
V
+.5
EE
V
+6
V
EE
T
-40
-
+85
°C
°C
A
Junction Temperature
T
+150
J
Electrical Specifications Test Conditions: V = 12V, V = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, V = V and
EXT EE
CC
CC,
SYMBOL
EE
LOSWING = V
25°C; Unless Otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER DC CHARACTERISTICS
ISL55100B Output Resistance
ISL55100B DC Output Current
R
I
= ±125mA, data not toggling
O
6
±125
-
9
-
14
-
Ω
OUTD
Iout D
Per Individual driver
mA
mA
mV
µA
ISL55100B AC Output Current (Note 2) IOUTDAC Per Individual driver
600
-
-
ISL55100A Minimum Output Swing
Disabled HIZ Leakage Current
V
V
= 200mV, V = 0V
185
-1
-
OMIN
HIZ
H
L
V
V
= V
with V = V + V or
0
1
OUT
OUT
CC
H
L
EE
CC
= VEE with V = V = V
H
L
DRIVER TIMING CHARACTERISTICS
Data± to DOUT Propagation Delay
t
Lowswing Disabled (Note 4)
Lowswing Enabled (Note 4)
5
6
12
13
<1
18
16
17
-
ns
ns
ns
ns
PD
Driver Timing Skew, All Edges (Note 2)
Disable (HIZ) Time
-
t
DVREN± Transition from Enable to
Disable
15
26
DIS
Enable Time
t
DVREN± Transition from Disable to
13
13
15
18
23
23
ns
ns
EN
Enable: Lowswing Disabled (Note 4)
DVREN± Transition from Disable to
Enable: Lowswing Enabled (Note 4)
FN6229.0
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March 17, 2006
ISL55100B
Electrical Specifications Test Conditions: V = 12V, V = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, V = V and
EXT EE
CC
EE
LOSWING = V
25°C; Unless Otherwise specified. (Continued)
CC,
SYMBOL
PARAMETER
TEST CONDITIONS
100pF Load ∆V = 0.4V (20% - 80%)
MIN
TYP
2.5
2.5
3.0
3.5
3.5
9
MAX
UNITS
ns
ISL55100B Rise/Fall Times (Note 2)
t , t
-
-
-
-
-
-
-
-
-
-
-
-
-
R
F
∆V = 1V (20% - 80%)
∆V = 5V (10% - 90%)
∆V = 10V (10% - 90%)
∆V = 14V (10% - 90%)
ns
-
ns
-
ns
-
ns
ISL55100B Rise/Fall Times (Note 2)
t , t
1000pF Load ∆V = 1V (20% - 80%)
∆V = 5V (10% - 90%)
-
ns
R
F
-
11
ns
∆V = 10V (10% - 90%)
-
14
ns
ISL55100B Maximum Toggle Frequency FMAXD No Load, 50% Symmetry
50
-
65
MHz
ns
ISL55100B Min Driver Pulse Width
t
Standard Load, 1K/100pF
7.7
WIDD
OS
ISL55100B Overshoot Lowswing Mode
(Note 2)
Lowswing Enabled, (VH-VL<2v)
-
20mV+
10% of
output
swing
%+V
RECEIVER DC CHARACTERISTICS
Input Offset Voltage
V
CVA = CVB = 1.5V
-200
-
-
200
30
mV
nA
Ω
OS
Input Bias Current
I
V
- CV = ±5V
(A/B)
10
25
BIAS
INP
Output Resistance
RoutR
18
35
RECEIVER TIMING CHARACTERISTICS
Propagation Delay
t
7
50
-
12
65
18
-
ns
MHz
ns
PP
Maximum Operating Frequency
Min Pulse Width
F
Under No Load, PWOUT Symmetry 50%
MAXR
WIDR
t
7.7
<1
-
Rcvr Channel to Channel Skew (Note 2)
DIGITAL INPUTS
-
-
ns
Differential Input High Voltage
Differential Input Low Voltage
Input Current
V
V
V
V
V
V
- V
- V
200
-
-
-
-
mV
mV
nA
V
DIFFH
DIG+
DIG+
IN
DIG-
DIG-
V
-200
50
DIFFL
I
= V
or V
EE
-50
0
IN
CC
Common Mode Input Voltage Range
V
not greater than V
-0.2 Volts
V
-5V
CM
DIFFL
DIFFH
DIFFH
CC
not less than V
+0.2 Volts
V
+0.2V
-
-
V
DIFFL
EE
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS V
EXT
= V
EXTERNAL LOGIC POWER OPTION NOT USED. (Note 6)
EE,
Positive Supply Current
I
V
V
= V = 12V, V = V = -3V,
EE
EXT
-
-85
-
65
-65
<1
85
mA
mA
mA
CC
CC
H
L
= V , Outputs Unloaded
EE
Negative Supply Current
I
V
V
= V = 12V, V = V = -3V,
EE
-
EE
CC
H
L
= V , Outputs Unloaded
EE
EXT
V
Supply Current
I
V
V
= V = 12, V = V = -3V,
-
EXT
EXT
CC
H
EE
L
= V , Outputs Unloaded
EE
EXT
FN6229.0
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March 17, 2006
ISL55100B
Electrical Specifications Test Conditions: V = 12V, V = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp Low = 0V, V = V and
EXT EE
CC
EE
LOSWING = V
25°C; Unless Otherwise specified. (Continued)
CC,
SYMBOL
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
= V + 5.5V, EXTERNAL LOGIC POWER OPTION USED. (Note 7)
EE
EXT
Positive Supply Current
I
V
V
= V = 12V, V = V = -3V,
-
-50
-
35
-35
25
50
mA
mA
mA
CC
CC
H
EE
L
= V +5.5V, Outputs Unloaded
EXT
EE
Negative Supply Current
I
V
V
= V = 12V, V = V = -3V,
CC H EE L
-
EE
= V +5.5V, Outputs Unloaded
EE
EXT
V
Supply Current
I
V
V
= V = 12, V = V = -3V,
40
EXT
EXT
CC
H
EE
L
= V + 5.5V, Outputs Unloaded
EE
EXT
NOTES:
2. Lab characterization, room temp, Timing Parameters Matched Stimulus/Loads, Channel to Channel Skew < 500ps, 1ns Max by design.
3. Measured across 100pF/1K lump sum load + 15pF PCB/Scope Probe. Cap and Resistor Surface Mount/Stacked ~0.5inch from Pin.
4. To Enable LOWSWING, connect LOWSWING to V and keep VH < V +5. To disable LOWSWING, connect it to V
EE EE
CC.
5. When V
is connected to V (External Device Power not used) then the Minimum V -V is 12V. When V
EE CC EE
is connected to an external
EXT
EXT
5.5V supply, then the minimum V -V voltage is 9.0V.
CC EE
6. I
& I values are based on static conditions and will increase with pattern rates. I
CC EE
& I reach 400-500mA at maximum data rates (provided
CC EE
sufficient device cooling is employed). These currents can be reduced by 1) Reducing the V -V operating voltage 2) Utilizing the V
CC EE
EXT
option.
7. When using V
= 5.5V, current requirements of the V
input can approach 100mA at maximum pattern rates.
EXT
EXT
Test Circuits and Waveforms
VH
VL
DATA+
DATA-
(NOTE 3)
V
O
DRV EN+
DOUT
100pF
1kΩ
DRV EN-
FIGURE 1. DRIVER SWITCHING TEST CIRCUIT
DATA = 0
DATA = 1
400mV
0V
DATA-
DATA+
t
t
PDLH
PDHL
V
(≈V )
OH
OL
H
50%
50%
V
O
V
(≈V )
L
t
t
R
F
FIGURE 2. DRIVER PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
FN6229.0
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March 17, 2006
ISL55100B
Test Circuits and Waveforms (Continued)
DIS
EN
400mV
DRV EN-
DRV EN+
0V
t
t
DISL
ENH
V
REF
V
O
1V
2V
(FOR DATA = 0)
10%
V
(≈V )
L
OL
OH
t
t
DISH
ENL
V
(≈V )
H
90%
V
O
(FOR DATA = 1)
V
REF
FIGURE 3. DRIVER ENABLE AND DISABLE TIME MEASUREMENT POINTS
COMP HI
CVA
-
QA
+
5V
VINP
+
-
QB
CVB
COMP LO
FIGURE 4. RECEIVER SWITCHING TEST CIRCUIT
500mV
VINP
0V
0V
-500mV
t
t
PDLH
PDHL
V
(≈5V)
(≈0V)
OH
OL
50%
50%
QX
V
FIGURE 5. RECEIVER PROPAGATION DELAY MEASUREMENT POINTS
Receiver Features
Application Information
The receivers are four independent window comparators that
feature high output current capability, and user defined high
and low output levels to interface with a wide variety of logic
families. Each receiver, comprises two comparators and each
comparator has an independent threshold level input, making
it easy to implement window comparator functions. The CVA
and CVB pins set the threshold levels of the A and B
The ISL55100B provides Quad pin drivers and Quad dual
level comparator receivers in a small footprint. The four
channels may be used as bidirectional or split channels.
Drivers have per channel level, data, and high impedance
controls, while comparators have per channel high and low
threshold levels.
FN6229.0
7
March 17, 2006
ISL55100B
comparators respectively. COMP HIGH and COMP LOW set
Logic Inputs
all the comparator output levels, and COMP HIGH must be
more positive than COMP LOW. These two inputs are
unbuffered supply pins, so the sources driving these pins
must provide adequate current for the expected load. COMP
HIGH and COMP LOW typically connect to the power
supplies of the logic device driven by the comparator outputs.
The truth table for the receivers is given on page 3. Receiver
outputs cannot be placed in a HIZ state, and do not
incorporate any on-chip short circuit current protection.
Momentary short circuits to GND, or any supply voltage, won’t
cause permanent damage, but care must be taken to avoid
longer duration short circuits. If tolerable to the application,
current limiting resistors can be inserted in series with the
QA(0-3) and QB(0-3) outputs to protect the receiver outputs
from damage due to overcurrent conditions.
The ISL55100B uses differential mode digital inputs, and can
therefore mate directly with LVDS or CML outputs. Single
ended logic families are handled by connecting one of the
digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility).
LOSWING Circuit Option
The drivers include switchable circuitry that is optimized for
either low (VH-VL < 3V) or high output swings. Configuring
the part is accomplished via the LOSWING pin. Connecting
LOSWING to V selects the circuits optimized for low
EE
overshoots at low swing operation. Connecting the pin to
V
enables the large signal circuitry. (See Figure 6)
CC
With LOSWING = V , the low swing circuitry activates
EE
whenever VH < V + 5V. Set LOSWING = V only if the
EE
EE
output swing (VH-VL) is less than 3V, and better than 10%
overshoots are required.
Driver Features
The drivers are single ended outputs featuring a wide
voltage range, an output stage capable of delivering 125mA
while providing a low out resistance and HIZ capability. The
driver output can be toggled to drive one of two user defined
output levels High (VH) or Low (VL).
For the best small ( low swing) signal performance, the
VH/VL common mode voltage [(VH + VL)/2] must be V
+
EE
1.5V. So if V = 0V, and the desired swing is 500mV, set
EE
VH = 1.75V, and VL = 1.25V.
Driver and Receiver Overload Protection
Driver waveforms are greatly affected by load
characteristics. The ISL55100B actually double bonds the
VH(0-3) and VL(0-3) supply pins for each channel. The
Driver Output Pins (DOUT(0-3)) are triple bonded. Multiple
bond wires help reduce the effects of Inductance between
the IC Die (Wafer) and the packaging. Also the QFN style of
packaging reduces inductance over other types of
packaging.
The ISL55100 is designed to provide minimum and balanced
Driver ROUT. Great care should be taken when making use
of the ISL55100B low ROUT drivers as there is no internal
protection. There is no short circuit protection built into either
the driver or the receiver/comparator outputs. Also there are
no junction temperature monitors or thermal shutdown
features.
The driver or receiver outputs may be damaged by more
than a momentary short circuit directly to any low impedance
voltage. Driver Protection can be obtained with a 50Ω Series
Termination Resistor that is properly rated.
While the inductance of a bond wire might seem
insignificant, it can reduce high-frequency waveform fidelity.
So this should be borne in mind when doing PCB layout and
DUT interconnect. Lead lengths should be kept as short as
possible, maintaining as much decoupling on the drive rails
as possible and make sure scope measurements are made
properly. Often the inductance of a scope probe ground can
be the actual cause of the waveform distortion.
External Logic Supply Option (V
EXT
)
Connection of the V
Pin to a 5.5V DC Source
EXT
(Referenced to V ) will reduce the V -V current drain.
EE CC EE
Current drain is directly proportional to Data Rate. This
option will help with Power Supply/Dissipation should heat
distribution become an issue.
VH and VL (Driver Output Rails)
Sets of VH and VL pins are designated for each Driver.
These are unbuffered analog inputs that determine the Drive
High (VH) and Drive Low (VL) Voltages that the drivers will
deliver. These inputs are double bonded to reduce
inductance and decrease AC Impedance.
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit
board layout is necessary for optimum performance. Ground
plane construction is highly recommended, lead lengths
should be as short as possible, and the power supply pins
must be well bypassed to reduce the risk of oscillation. For
Each VH and VL should be decoupled with 4.7µF and 0.1µF
capacitors to ground. If all four Driver VH/VLs are bussed,
then one 4.7µF can be used. Layouts should also
accommodate the placement of capacitance “across” VH
and VL. So in addition to decoupling the VH/VL pins to
ground, they are also decoupled to each other.
normal single supply operation, where the V pin is
EE
connected to ground, one 0.1µF ceramic capacitor should be
placed from the V
pin to ground. A 4.7µF tantalum
CC
capacitor should then be connected from the V
pin to
CC
ground. This same capacitor combination should be placed
at each supply pin to ground if split supplies are to be used.
FN6229.0
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March 17, 2006
ISL55100B
especially true if the users applications require continuous,
high speed operation.
Power Dissipation Considerations
Specifying continuous data rates, driver loads and driver
level amplitudes are key in determining power supply
requirements as well as dissipation/cooling necessities.
Driver Output patterns also impact these needs. The faster
the pin activity, the greater the need to supply current and
remove heat.
The reader is cautioned agains t as s uming the s ame
level of thermal performance in actual applications . A
careful ins pection of conditions in your application
s hould be conducted. Great care mus t be taken to
ens ure Die Temperature does not exceed 150°C Abs olute
Maximum Thermal Limits .
Figures 16 and 17 address power consumption relative to
frequency of operation. These graphs are based on Driving
Important Note: The ISL55100B package metal plane is
used for heat sinking of the device. It is electrically
6.0/0.0V Out into a 1kΩ load. Theta J for the device
A
package is 23.0, 16.6 and 14.9°C/W based on Airflows of 0,
1 and 2.5 meters per second. Device mounted per Note 1
under Thermal Information. With the high speed data rate
capability of the ISL55100B, it is possible to exceed the
150°C “absolute-maximum junction temperature” as
operating conditions and frequencies increase. Therefore, it
is important to calculate the maximum junction temperature
for the application to determine if operating conditions need
to be modified for the device to remain in the safe operating
area.
connected to the negative supply potential (V ). If V
EE
EE
is tied to ground, the thermal pad can be connected to
ground. Otherwise, the thermal pad (V ) must be
EE
isolated from other power planes.
Power Supply Sequencing
The ISL55100B references every supply with respect to
VEE. Therefore apply VEE, then VCC followed by the VH,VL
busses, then the COMP High and Comp Low followed by the
CVA & CVB Supplies. Digital Inputs should be set with a
differential bias as soon as possible. In cases where V
is
EXT
The maximum power dissipation allowed in a package is
determined according to:
being utilized (V
= V + 5.5v), it should be powered up
EXT
EE
immediately after V . Basically, no pin should be biased
CC
or below V .
EE
T
- T
AMAX
above V
JMAX
CC
P
= --------------------------------------------
DMAX
Θ
JA
Data Rates
Please note that the Frequency - MHz in Figures 16 and 17
contain two transitions within each period. A digital
application that requires a new test pattern every 50ns would
be running at a 20MHz Data Rate. Figure 18 reveals 100ns
period, in 10MHz frequency parlance, results in two 50ns
digital patterns.
where:
• T
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
AMAX
• θ = Thermal resistance of the package
JA
• P
DMAX
= Maximum power dissipation in the package
The maximum power dissipation actually produced by an IC
is the total quiescent supply current times the total power
supply voltage, plus the power in the IC due to the loads.
Power also depends on number of channels changing state,
frequency of operation. The extent of continuous active
pattern generation/reception will greatly effect dissipation
requirements.
The power dissipation curves (Figure 16), provide a way to
see if the device will overheat. The maximum safe power
temperature vs operating frequency can be found
graphically in Figure 17. This graph is based on the package
type Theta J ratings and actual current/wattage
A
requirements of the ISL55100B when driving a 1K load with
a 6V High Level and a 0V Low Rail. The temperatures are
indicated as calculated junction temperature over the
ambient temperature of the user’s system. Plots indicate
temperature change as operating frequency increases. (The
graph assumes continuous operation.) The user should
evaluate various heat sink/cooling options in order to control
the ambient temperature part of the equation. This is
FN6229.0
9
March 17, 2006
ISL55100B
Typical Performance Curves Device installed on Intersil ISL55100B Evaluation Board.
VCC 12.0 DH 6.0
VEE - 3.0 DL 0.0
VCC 12.0 DH 6.0
VEE - 3.0 DL 0.0
0
Data In
680pF
/Lowswing Off
/Lowswing On
1k100pF
0
0
2200pF
0
1000pF
10ns/DIV
10ns/DIV
FIGURE 7. DRIVER WAVEFORMS UNDER VARIOUS LOADS
FIGURE 6. LOWSWING EFFECTS ON DRIVER SHAPE AND
T
(100pF-1K LOAD)
Tristate/Data/Dout Timing
DRVEN
PD
10.0
VH (6.00 Volts) Rout : Driver sources 125mA
0
0
Data In
5.0
VL (0.0V Volts) Rout : Driver sinks 125mA
Driver Out
0
0.0
12
13
14
15
16
17
18
VCC-VEE VOLTS (VEE -3.0 Fixed)
20ns/DIV
FIGURE 9. R
vs DEVICE VOLTAGE
FIGURE 8. DATA/HIZ/DRIVER OUT TIMING
OUT
20.0
18.0
16.0
14.0
12.0
10.0
8.0
8.0
VH (1V-15V) Rout : Driver sources 125mA
7.2
6.4
5.6
4.8
4.0
3.2
2.4
1.6
0.8
0.0
2200pF
1000pF
680pF
VL (0.0V Fixed) Rout : Driver sinks 125mA
1k100pF
6.0
4.0
2.0
0.0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
1
2
3
4
5
6
7
8
9
10 11 12 13 14
VH VOLTS (VL = 0.0)
VH VOLTS (VL = 0.0)
FIGURE 11. PROPAGATION DELAY vs VH RAIL, VARIOUS
FIGURE 10. R
vs VH RAIL
OUT
LOADS
FN6229.0
March 17, 2006
10
ISL55100B
Typical Performance Curves Device installed on Intersil ISL55100B Evaluation Board. (Continued)
20.0
18.0
16.0
14.0
12.0
10.0
8.0
45.0
40.5
36.0
31.5
27.0
22.5
18.0
13.5
9.0
2200pF
Driver TPD .. No Load
1000pF
680pF
Comparator TPD .. No Load
6.0
4.0
1k100pF
2.0
4.5
0.0
0.0
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
10 11 12 13 14
VCC-VEE (VEE = -3.0)
VH VOLTS (VL = 0.0)
FIGURE 13. DRIVER & RECEIVER TPD VARIANCE vs V
FIGURE 12. DRIVER FALL TIME vs VH RAIL, VARIOUS LOADS
CC
35.0
31.5
100
90
80
70
60
50
28.0
24.5
21.0
17.5
14.0
10.5
7.0
2200pF
1000pF
ICC STATIC CONDITIONS
40
680pF
30
20
10
0
3.5
1k100pF
0.0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
11
12
13
14
15
16
17
18
19
VH VOLTS (VL = 0.0)
V
-V (V = -3.0)
CC EE EE
FIGURE 14. DRIVER RISE TIME vs VH RAIL, VARIOUS LOADS
FIGURE 15. STATIC I
CC
vs V
CC
AIRFLOW LEGEND A = 0m/s : B = 1.0m/s : C = 2.5m/s
10.0
9.0
150
135
120
105
90
A
A
B
C
8.0
12V V
CC
B
C
12V V
CC
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
18V V
CC
A
B
C
75
18V V
CC
60
45
30
9V V
& V
= 5.5V
EXT
9V V
& V
= 5.5V
EXT
CC
CC
15
0
5
10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (MHz)
5
10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (MHz)
FIGURE 17. CALCULATED JUNCTION TEMP ABOVE
FIGURE 16. DEVICE POWER DISSIPATION WITH
-V = 18, 12 & 9.0 (V = 5.5V) VOLTS. All
AMBIENT WITH V -V = 18, 12 & 9.0
V
CC EE
= 5.5V) VOLTS. ALL FOUR PINS MAKING
CC EE
EXT
(V
FOUR PINS MAKING TWO TRANSITIONS PER
PERIOD
EXT
TWO TRANSITIONS PER PERIOD
FN6229.0
11
March 17, 2006
ISL55100B
Typical Performance Curves Device installed on Intersil ISL55100B Evaluation Board. (Continued)
VCC 12.0 DH 6.0
VEE - 3.0 DL 0.0
VCC 12.0 DH 6.0
VEE - 3.0 DL 0.0
0
0
0
10ns/DIV
FIGURE 18. FREQUENCY OF 10MHz = 50ns PATTERN RATE
FIGURE 19. MINIMUM PULSE WIDTH VH 6/8/10V
FN6229.0
March 17, 2006
12
ISL55100B
Quad Flat No-Lead Plas tic Package (QFN)
Micro Lead Frame Plas tic Package (MLFP)
L72.10x10
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
0.90
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
-
-
-
0.02
-
0.65
9
0.20 REF
0.25
9
0.18
5.85
5.85
0.30
6.15
6.15
5, 8
D
10.00 BSC
9.75 BSC
6.00
-
D1
D2
E
9
7, 8
10.00 BSC
9.75 BSC
6.00
-
E1
E2
e
9
7, 8
0.50 BSC
-
-
k
0.20
0.30
-
-
L
0.40
0.50
8, 10
N
72
2
Nd
Ne
P
18
3
18
3
-
-
-
0.60
12
9
θ
-
9
Rev. 1 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare provided toassistwith PCBLandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VNND-3 except for the "L" min
dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6229.0
13
March 17, 2006
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