ISL55100AIRZ-T7A [RENESAS]
Quad 18V Pin Electronics Driver/Window Comparator;
| 型号： | ISL55100AIRZ-T7A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Quad 18V Pin Electronics Driver/Window Comparator 驱动 接口集成电路 |
| 文件： | 总14页 (文件大小：954K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL55100A
Quad 18V Pin Electronics Driver/Window Comparator
FN7486
Rev 3.00
December 4, 2014
The ISL55100A is a Quad pin driver and window comparator
fabricated in a wide voltage CMOS process. It is designed
specifically for Test During Burn In (TDBI) applications, where
cost, functional density and power are all at a premium.
Features
• Low driver output resistance
- R
OUT
maximum: ISL55100A 7.0Ω
This IC incorporates four channels of programmable drivers
and window comparators into a small 72 Ld QFN package.
Each channel has independent driver levels, data and high
impedance control. Each receiver has dual comparators, which
provide high and low threshold levels.
• 18V I/O range
• 50MHz operation
• 4-channel driver/receiver pairs with per pin flexibility
• Dual level - per pin - input thresholds
• Differential or single-ended digital inputs
• User defined comparator output levels
• Low channel-to-channel timing skew
• Small footprint (72 Ld QFN)
The ISL55100A uses differential mode digital inputs and can
therefore mate directly with LVDS or CML outputs.
Single-ended logic families are handled by connecting one of
the digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility). The comparator outputs are
single-ended and the output levels are user defined to mate
directly with any digital technology.
• Pb-free (RoHS compliant)
Applications
• Burn in ATE
The 18V driver output and receiver input ranges allow this
device to interface directly with TTL, ECL, CMOS (3V, 5V and
7V), LVCMOS and custom level circuitry, as well as the high
voltage (super voltage) level required for many special test
modes for Flash Devices.
• Wafer level flash memory test
• LCD panel test
• Low cost ATE
• Instrumentation
• Emulation
• Device programmers
Functional Block Diagram
QUAD - WIDE RANGE, LOW ROUT, TRI-STATEABLE - DRIVERS
VH(0:3)
DATA+(0:3)
DOUT(0:3)
+
-
DATA-(0:3)
VL(0:3)
DRVEN+(0:3)
+
-
DRVEN-(0:3)
QUAD - DUAL LEVEL COMPARATOR - RECEIVERS
V
CC
COMP HIGH
QA(0:3)
+
-
CVA(0:3)
VINP(0:3)
COMP LOW
V
EE
CC
V
COMP HIGH
+
-
QB(0:3)
COMP LOW
CVB(0:3)
V
EE
FN7486 Rev 3.00
December 4, 2014
Page 1 of 14
ISL55100A
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PART MARKING
PKG. DWG. #
L72.10x10
ISL55100AIRZ
ISL55100 AIRZ
-40 to +85
72 Ld QFN
ISL55100AEVAL3Z
NOTES:
Evaluation Board
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ISL55100A For more information on MSL, please see tech brief TB363.
Pin Configuration
ISL55100A
(72 LD QFN)
TOP VIEW
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
DATA+ 0
DATA- 0
QA 1
V
EXT
1
2
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VH 0
DOUT 0
NC
3
QB 1
4
DRV EN+ 1
DRV EN- 1
VL 0
5
VH 1
6
DATA+ 1
DATA- 1
QA 2
DOUT 1
NC
7
8
VL 1
9
EP
QB 2
DRV EN+ 2
DRV EN- 2
DATA+ 2
VH 2
DOUT 2
NC
10
11
12
13
14
VL 2
DATA- 2
VH 3
QA 3
QB 3
DOUT 3
NC
15
16
17
18
40
39
38
37
DRV EN+ 3
DRV EN- 3
VL 3
LOWSWING
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
FN7486 Rev 3.00
December 4, 2014
Page 2 of 14
ISL55100A
Pin Descriptions
PIN NAME
FUNCTION
DATA+(0:3)
DATA-(0:3)
Positive differential digital input that determines the driver output state when it is enabled.
Negative differential digital input that determines the driver output state when it is enabled.
DRV EN+(0:3) Positive differential digital input that enables or disables the corresponding driver.
DRV EN-(0:3) Negative differential digital input that enables or disables the corresponding driver.
QA (0:3)
QB (0:3)
DOUT (0:3)
VINP (0:3)
VH (0:3)
VL (0:3)
Comparator digital outputs. QA(X) is high when VINP(X) exceeds CVA(X).
Comparator digital outputs. QB(X) is high when VINP(X) exceeds CVB(X).
Driver outputs.
Comparator inputs.
Unbuffered analog inputs that set each individual driver’s “high” voltage level.
Unbuffered analog inputs that set each individual driver’s “low” voltage level. VL must be a lower voltage than VH.
No internal connection.
NC
CVA (0:3)
CVB (0:3)
COMP HI
COMP LO
Analog inputs that set the threshold for the corresponding Channel’s A comparators.
Analog inputs that set the threshold for the corresponding Channel’s B comparators.
Supply voltage, unbuffered input that sets the high output level of all comparators. Must be greater than COMP LO.
Supply voltage, unbuffered input that sets the low output level of all comparators. Must be less than COMP HI.
Positive power supply (5% tolerance).
V
CC
V
Negative power supply (5% tolerance). This is also the potential of the exposed thermal pad on the package bottom.
EE
V
External 5.5VDC power supply (5.5VDC to 6.0VDC as referenced to V , NOT GND. Recommended V = 5.5V) for internal logic.
EE EXT
EXT
Connect pin to V when not using an external supply.
EE
LOWSWING
EP
Input that selects driver output configurations optimized to yield minimum overshoots for low level swings (VH < V +5V), or
EE
optimized for large output swings. Connect LOWSWING to V to select low swing circuitry, or connect it to V to select high swing
EE CC
circuitry.
QFN package exposed thermal pad; connect to V
.
EE
Truth Tables
RECEIVERS
INPUT
VINP
OUTPUTS
DRIVERS
QA
QB
0
INPUTS
OUTPUT
DOUT
Hi - Z
VH
<CVA
<CVA
>CVA
>CVA
<CVB
>CVB
<CVB
>CVB
0
0
1
1
DATA
DRV EN
+ > -
1
X
+ > -
0
+ < -
1
+ < -
+ < -
VL
X = DON’T CARE
FN7486 Rev 3.00
December 4, 2014
Page 3 of 14
ISL55100A
Absolute Maximum Ratings
Thermal Information
V
V
to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 19V
EE
Thermal Resistance (Typical, Notes 4, 5)
72 Ld QFN Package . . . . . . . . . . . . . . . . . . . 23
(°C/W)
JC
(°C/W)
2.0
CC
JA
to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
EXT
EE
Input Voltages
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
DATA, DRV EN, CVX, VH, VL, VINP, COMPX, LOWSWING
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V - 0.5V) to (V + 0.5V)
EE
CC
Output Voltages
DOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V - 0.5V) to (VH + 0.5V)
EE
QX. . . . . . . . . . . . . . . . . . . . . (COMP LOW - 0.5V) to (COMP HIGH + 0.5V)
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
JA
Brief TB379.
5. For , the “case temp” location is the center of the exposed metal pad on the package underside.
JC
6. Device temperature is closely tied to data-rates, driver loads and overall pin activity. Review “Power Dissipation Considerations” on page 9 for more
information.
Recommended Operating Conditions
MIN
MAX
PARAMETER
SYMBOL
(Note 13)
TYP
(Note 13)
UNITS
Device Power-(V
= V ) V
EE EXT
Not Used
V
- V
CC EE
12 (Note 10)
9 (Note 10)
15
18
18
6.0
V
V
EXT
EXT
Device Power-(V
= V + 5.5V)
EE
V - V
CC EE
15
V
Optional External Logic Power
V
- V
5.5 (Note 10)
5.75
V
EXT
EXT EE
Driver Output High Rail
Driver Output Low Rail
Comparator Output High Rail
Comparator Output Low Rail
Ambient Temperature
V
V
+ 1
-
-
-
-
-
-
V
V
- 0.5
+ 6
V
H
EE
CC
V
V
+ 0.5
V
V
L
EE
EE
COMP-High
COMP-Low
V
+ 1
- 0.5
+ 6
V
EE
CC
V
+ 0.5
V
V
EE
EE
T
-40
+85
°C
°C
A
Junction Temperature
T
-
+150
J
Electrical Specifications Test Conditions: V = 12V, V = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp-Low = 0V, V = V and
CC
EE
5V
EE
LOWSWING = V
.
CC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER DC CHARACTERISTICS
ISL55100A Output Resistance
ISL55100A DC Output Current
ISL55100A AC Output Current (Note 6)
ISL55100A Minimum Output Swing
Disabled HIZ Leakage Current
R
I
= ±200mA, data not toggling
O
3
±200
-
4.5
7.0
Ω
mA
A
OUTD
I
Per Individual driver
Per Individual driver
-
1.0
-
-
-
OUTD
I
OUTDAC
V
V
V
= 200mV, V = 0V
185
-1
-
mV
µA
OMIN
H
L
HIZ
= V with V = V + V or V
= VEE
0
1
OUT
CC
H
L
EE
OUT
with V = V = V
H
L
CC
DRIVER TIMING CHARACTERISTICS
Data to DOUT Propagation Delay
t
Lowswing Disabled (Note 9)
Lowswing Enabled (Note 9)
8
9
12
13
<1
18
16
17
-
ns
ns
ns
ns
PD
Driver Timing Skew, All Edges (Note 7)
Disable (HIZ) Time
-
t
DVREN Transition from Enable to Disable
16
26
DIS
FN7486 Rev 3.00
December 4, 2014
Page 4 of 14
ISL55100A
Electrical Specifications Test Conditions: V = 12V, V = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp-Low = 0V, V = V and
CC
EE
5V
EE
LOWSWING = V . (Continued)
CC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
13
TYP
15
MAX
23
UNITS
ns
Enable Time
t
DVREN Transition from Disable to Enable:
EN
Lowswing Disabled (Note 9)
DVREN Transition from Disable to Enable:
13
18
23
ns
Lowswing Enabled (Note 9)
ISL55100A Rise/Fall Times (Note 7)
t , t
100pF Load
V = 0.4V (20% to 80%)
V = 1V (20% to 80%)
V = 5V (10% to 90%)
V = 10V (10% to 90%)
V = 14V (10% to 90%)
V = 1V (20% to 80%)
V = 5V (10% to 90%)
V = 10V (10% to 90%)
-
2.5
2.5
2.5
2.5
2.5
8.0
10.0
14.0
65
-
-
ns
ns
R
F
-
-
-
ns
-
-
ns
-
-
ns
ISL55100A Rise/Fall Times (Note 7)
t , t
1000pF Load
-
-
ns
R
F
-
-
ns
-
-
ns
ISL55100A Maximum Toggle Frequency
ISL55100A Min Driver Pulse Width
FMAXD
No Load, 50% Symmetry
50
-
MHz
ns
t
Standard Load, 1k/100pF (Note 8)
Lowswing Enabled, (VH - VL < 2V)
-
-
7.7
-
WIDD
OS
ISL55100A Overshoot Lowswing Mode
(Note 7)
20mV+
10% of
output
swing
%V
RECEIVER DC CHARACTERISTICS
Input Offset Voltage
V
CVA = CVB = 1.5V
-50
-
-
50
30
35
mV
nA
Ω
OS
Input Bias Current
I
V
- CV = ±5V
(A/B)
10
25
BIAS
INP
Output Resistance
R
18
OUTR
RECEIVER TIMING CHARACTERISTICS
Propagation Delay
t
7
50
-
12
65
7.7
<1
18
ns
MHz
ns
PP
Maximum Operating Frequency
Minimum Pulse Width
F
Under No Load, PWOUT Symmetry 50%
-
-
-
MAXR
WIDR
t
Rcvr Channel-to-channel Skew (Note 7)
DIGITAL INPUTS
-
ns
Differential Input High Voltage
Differential Input Low Voltage
Input Current
V
V
V
V
V
V
- V
DIG+ DIG-
200
-
-
-
-
mV
mV
nA
V
DIFFH
V
- V
DIG+ DIG-
-200
50
DIFFL
I
= V or V
CC
-50
0
IN
IN
EE
Common Mode Input Voltage Range
V
> V
- 0.2V
V
- 5V
CC
CM
DIFFL
DIFFH
DIFFH
< V
+ 0.2V
V
+ 0.2V
EE
-
-
V
DIFFL
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS V
EXT
= V EXTERNAL LOGIC POWER OPTION NOT USED. (Notes 10, 11)
EE,
Positive Supply Current
I
V
= V = 12V, V = V = -3V, V
EE
= V
,
-
-85
-
65
-65
<1
85
mA
mA
mA
CC
CC
H
L
EXT
EXT
EXT
EE
Outputs Unloaded
Negative Supply Current
I
V
= V = 12V, V = V = -3V, V
EE
= V
,
-
-
EE
CC
H
L
EE
Outputs Unloaded
V
Supply Current
I
V
= V = 12, V = V = -3V, V
= V ,
EE
EXT
EXT
CC
H
EE
L
Outputs Unloaded
POWER SUPPLIES, DRIVER/RECEIVER STATIC CONDITIONS V
= V + 5.5V, EXTERNAL LOGIC POWER OPTION USED. (Notes 11, 12)
EXT EE
Positive Supply Current
I
V
= V = 12V, V = V = -3V, V
EE
= V
EE
-
35
50
mA
CC
CC
H
L
EXT
+ 5.5V, Outputs Unloaded
FN7486 Rev 3.00
December 4, 2014
Page 5 of 14
ISL55100A
Electrical Specifications Test Conditions: V = 12V, V = -3V, VH = 6V, VL = 0V, Comp-High = 5V, Comp-Low = 0V, V = V and
CC
EE
5V
EE
LOWSWING = V . (Continued)
CC
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
-50
TYP
-35
MAX
-
UNITS
mA
Negative Supply Current
I
V
= V = 12V, V = V = -3V, V
= V
EXT EE
EE
CC
H
EE
L
+ 5.5V, Outputs Unloaded
V
Supply Current
I
V
= V = 12, V = V = -3V, V
EE
= V +
EE
-
25
40
mA
EXT
EXT
CC
H
L
EXT
5.5V, Outputs Unloaded
NOTES:
7. Lab characterization, room temp, Timing Parameters Matched Stimulus/Loads, Channel to Channel Skew < 500ps, 1ns Max by design.
8. Measured across 100pF/1k lump sum load + 15pF PCB/Scope Probe. Capacitor and Resistor Surface Mount/Stacked ~0.5inch from Pin.
9. To Enable LOWSWING, connect LOWSWING to V and keep VH < V + 5. To disable LOWSWING, connect it to V
.
EE EE CC
10. When V
is connected to V (External Device Power not used) then the Minimum V - V is 12V. When V
is connected to an external 5.5V
EXT
EE
CC EE
EXT
supply, then the minimum V - V voltage is 9.0V. Recommended V
= 5.5V as referenced to V .
CC EE EXT
EE
11. I and I values are based on static conditions and will increase with pattern rates. I and I reach 400mA to 500mA at maximum data rates
CC EE CC EE
(provided sufficient device cooling is employed). These currents can be reduced by: Reducing the V - V operating voltage or by Utilizing the V
CC EE
EXT
option.
12. When using V
= 5.5V, current requirements of the V input can approach 100mA at maximum pattern rates.
EXT
EXT
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Test Circuits and Waveforms
VH
VL
DATA+
DATA-
DRV EN+
DRV EN-
Note 8
V
O
DOUT
100pF
1kΩ
FIGURE 1. DRIVER SWITCHING TEST CIRCUIT
DATA = 0
DATA = 1
400mV
DATA-
DATA+
0V
t
t
PDLH
PDHL
V
V
(V )
H
OH
OL
50%
50%
V
O
(V )
L
t
t
R
F
FIGURE 2. DRIVER PROPAGATION DELAY AND TRANSITION TIME MEASUREMENT POINTS
FN7486 Rev 3.00
December 4, 2014
Page 6 of 14
ISL55100A
Test Circuits and Waveforms(Continued)
DIS
EN
400mV
DRV EN-
DRV EN+
0V
t
t
DISL
ENH
V
REF
V
O
1V
2V
(FOR DATA = 0)
10%
V
(V )
L
OL
OH
t
t
DISH
ENL
V
(V )
H
90%
V
O
(FOR DATA = 1)
V
REF
FIGURE 3. DRIVER ENABLE AND DISABLE TIME MEASUREMENT POINTS
COMP HI
CVA
-
+
QA
5V
VINP
+
-
QB
CVB
COMP LO
FIGURE 4. RECEIVER SWITCHING TEST CIRCUIT
500mV
VINP
0V
0V
-500mV
t
t
PDLH
PDHL
V
(5V)
(0V)
OH
OL
50%
50%
QX
V
FIGURE 5. RECEIVER PROPAGATION DELAY MEASUREMENT POINTS
FN7486 Rev 3.00
December 4, 2014
Page 7 of 14
ISL55100A
deliver. These inputs are double bonded to reduce inductance
and decrease AC Impedance.
Application Information
The ISL55100A provides Quad pin drivers and Quad dual level
comparator receivers in a small footprint. The four channels
may be used as bidirectional or split channels. Drivers have per
channel level, data and high impedance controls, while
comparators have per channel high and low threshold levels.
Each VH and VL should be decoupled with 4.7µF and 0.1µF
capacitors to ground. If all four VH/VLs are bussed per device
then one 4.7µF can be used for multiple VH/VL pins. Layouts
should also accommodate the placement of capacitance
“across” VH and VL. So in addition to decoupling the VH/VL
pins to ground, they are also decoupled to each other.
Receiver Features
The receivers are four independent window comparators that
feature high output current capability, and user defined high and
low output levels to interface with a wide variety of logic
families. Each receiver, comprises two comparators and each
comparator has an independent threshold level input, making it
easy to implement window comparator functions. The CVA and
CVB pins set the threshold levels of the A and B comparators
respectively. COMP HIGH and COMP LOW set all the comparator
output levels, and COMP HIGH must be more positive than
COMP LOW. These two inputs are unbuffered supply pins, so the
sources driving these pins must provide adequate current for the
expected load. COMP HIGH and COMP LOW typically connect to
the power supplies of the logic device driven by the comparator
outputs. The “Truth Table” for Receivers is on page 3. Receiver
outputs are not tri-statable, and do not incorporate any on-chip
short-circuit current protection. Momentary short circuits to
GND, or any supply voltage, won’t cause permanent damage,
but care must be taken to avoid longer duration short circuits. If
tolerable to the application, current limiting resistors can be
inserted in series with the QA(0 to 3) and QB(0 to 3) Outputs to
protect the receiver outputs from damage due to overcurrent
conditions.
Logic Inputs
The ISL55100A uses differential mode digital inputs, and can
therefore mate directly with LVDS or CML outputs.
Single-ended logic families are handled by connecting one of
the digital input pins to an appropriate threshold voltage (e.g.,
1.4V for TTL compatibility).
LOWSWING Circuit Option
The drivers include switchable circuitry that is optimized for
either low (VH - VL < 3V) or high output swings, and this
selection is accomplished via the LOWSWING pin. Connecting
LOWSWING to VEE selects the circuits optimized for low
overshoots at low swings, while tying the pin V enables the
large signal circuitry (see Figure 7).
CC
With LOWSWING = V , the low swing circuitry activates
EE
whenever VH < V + 5V, and the VH and VL currents increase,
EE
so for the lowest power dissipation set LOWSWING = V only if
EE
the output swing (VH - VL) is less than 3V, and better than 10%
overshoots are required.
For the best small signal performance, the VH/VL common
mode voltage [(VH + VL)/2] must be V + 1.5V. So if V = 0V,
EE
EE
Driver Features
and the desired swing is 500mV, set VH = 1.75V, and
VL = 1.25V.
The drivers are single-ended outputs featuring a wide voltage
range, an output stage capable of delivering 200mA while
providing a low out resistance and tri-state capability.
Additionally, the driver output can be toggled to drive one of
two user defined output levels High (VH) or Low (VL).
Driver and Receiver Overload Protection
The ISL55100A is designed to provide minimum and balanced
Driver R . Great care should be taken when making use of
OUT
the ISL55100A low R
OUT
drivers as there is no internal
Driver waveforms are greatly affected by load characteristics.
The ISL55100A actually double bonds the VH(0 to 3) and
VL(0 to 3) supply pins for each channel. The Driver Output Pins
(DOUT(0 to 3)) are triple bonded. Multiple bond wires help
reduce the effects of Inductance between the IC Die (Wafer)
and the packaging. Also the QFN style of packaging reduces
inductance over other types of packaging.
protection. There is no short-circuit protection built into either
the driver or the receiver/comparator outputs. Also there are
no junction temperature monitors or thermal shutdown
features.
The driver or receiver outputs may be damaged by more than a
momentary short-circuit directly to any low impedance voltage.
If included, a 50Ω Series Termination Resistor provides
suitable driver protection, but should be properly rated.
While the inductance of a bond wire might seem insignificant,
it can reduce high-frequency waveform fidelity. Therefore, this
should be borne in mind when doing PCB layout and DUT
interconnect. Lead lengths should be kept as short as possible,
maintaining as much decoupling on the drive rails as possible
and make sure scope measurements are made properly. Often
the inductance of a scope probe ground can be the actual
cause of the waveform distortion.
External Logic Supply Option (V
)
EXT
Connection of the V
Pin to a 5.5V DC Source (Referenced to
EXT
V
) will reduce the V - V current drain. Current drain is
EE
CC EE
directly proportional to Data Rate. This option will help with
Power Supply/Dissipation should heat distribution become an
issue.
VH and VL (Driver Output Rails)
There are sets of VH and VL pins designated for each driver.
These are unbuffered analog inputs that determine the Drive
High (VH) and Drive Low (VL) Voltages that the drivers will
Power Supply Bypassing and Printed Circuit
Board Layout
As with any high frequency device, good printed circuit board
layout is necessary for optimum performance. Ground plane
FN7486 Rev 3.00
December 4, 2014
Page 8 of 14
ISL55100A
construction is highly recommended, lead lengths should be
as short as possible, and the power supply pins must be well
bypassed to reduce the risk of oscillation. For normal single
supply operation, where the VEE pin is connected to ground,
one 0.1µF ceramic capacitor should be placed from the VCC
pin to ground. A 4.7µF tantalum capacitor should then be
connected from the VCC pin to ground. This same capacitor
combination should be placed at each supply pin to ground if
split supplies are to be used.
options in order to control the ambient temperature part of the
equation. This is especially true if the user’s applications
require continuous, high speed operation.
The reader is cautioned against assuming the same level of
thermal performance in actual applications. A careful
inspection of conditions in your application should be
conducted. Great care must be taken to ensure Die
Temperature does not exceed Absolute Maximum Thermal
Limits.
Power Dissipation Considerations
Important Note: The ISL55100A package metal pad (EP) is
used for heat sinking of the device. It is electrically connected
Specifying continuous data rates, driver loads and driver level
amplitudes are key in determining power supply requirements
as well as dissipation/cooling necessities. Driver Output
patterns also impact these needs. The faster the pin activity,
the greater the need to supply current and remove heat.
to the negative supply potential (V ). If VEE is tied to ground,
EE
the thermal pad can be connected to ground. Otherwise, the
thermal pad (V ) must be isolated from other power planes.
EE
Power Supply Sequencing
Figures 17 and 18 address power consumption relative to
Frequency of Operation. These graphs are based on Driving
The ISL55100A references every supply with respect to V
.
EE
Therefore apply V , then V followed by the VH, VL busses,
EE CC
6.0/0.0V Out into a 1kΩ Load. T for the device package is
jA
then the COMP High and Comp Low followed by the CVA and
CVB Supplies. Digital Inputs should be set with a differential
23.0°C/W, 16.6°C/W and 14.9°C/W based on airflows of
0m/s, 1m/s and 2.5m/s. The device is mounted per Note 4
under “Thermal Information” on page 4. With the high speed
data rate capability of the ISL55100A, it is possible to exceed
the +150°C “absolute maximum junction temperature” as
operating conditions and frequencies increase. Therefore, it is
important to calculate the maximum junction temperature for
the application to determine if operating conditions need to be
modified for the device to remain in the safe operating area.
bias as soon as possible. In cases where V
is being utilized
EXT
(V
EXT
= V + 5.5V), it should be powered up immediately after
EE
V
. Basically, no pin should be biased above V or below V .
CC CC EE
Data Rates
Please note that the Frequency (MHz) in Figures 17 and 18
contain two transitions within each period. A digital application
that requires a new test pattern every 50ns would be running
at a 20MHz Data Rate. Figure 19 reveals that a 100ns period,
10MHz in frequency parlance, results in two 50ns digital
patterns.
The maximum power dissipation allowed in a package is
determined according to Equation 1:
T
- T
AMAX
JMAX
(EQ. 1)
--------------------------------------------
P
=
DMAX
JA
ESD Protection
Figure 6 is the block diagram depicting the ESD protection
networks. The DOUT-to-VH diode is the upper FET’s
drain-to-body diode.
where:
• T
= Maximum junction temperature
= Maximum ambient temperature
JMAX
• T
AMAX
• = Thermal resistance of the package
JA
• P
= Maximum power dissipation in the package
DMAX
The maximum power dissipation actually produced by an IC is
the total quiescent supply current times the total power supply
voltage, plus the power in the IC due to the loads. Power also
depends on the number of channels changing state, and the
frequency of operation. The extent of continuous active pattern
generation/reception will greatly effect dissipation
requirements.
The power dissipation curves (Figure 17), provide a way to see
if the device will overheat. The junction temperature rise above
ambient vs. operating frequency can be found graphically in
Figure 18. This graph is based on the package type T ratings
JA
and actual current/wattage requirements of the ISL55100A
when driving a 1k load with a 6V High Level and a 0V Low Rail.
The temperatures are indicated as calculated junction
temperature over the ambient temperature of the user’s
system. Plots indicate temperature change as operating
frequency increases (the graph assumes continuous
operation). The user should evaluate various heat sink/cooling
FN7486 Rev 3.00
December 4, 2014
Page 9 of 14
ISL55100A
FIGURE 6. ESD STRUCTURE BLOCK DIAGRAM
FN7486 Rev 3.00
December 4, 2014
Page 10 of 14
ISL55100A
Typical Performance Curves Device installed on Intersil ISL55100A Evaluation Board.
V
12.0 VH 6.0
- 3.0 VL 0.0
V
12.0 VH 2.0
- 3.0 VL 0.0
CC
CC
V
V
EE
EE
0
DATA IN
LOWSWING OFF
680pF
0
1k/100pF
LOWSWING ON
2200pF
1000pF
0
0
10ns/DIV
10ns/DIV
FIGURE 8. DRIVER WAVEFORMS UNDER VARIOUS LOADS
FIGURE 7. LOWSWING EFFECTS ON DRIVER SHAPE AND t
(100pF-1k LOAD)
PD
6
VH (6.00V) R
: DRIVER SOURCES 200mA
OUT
DRVEN
5
4
3
2
1
0
0
DATA IN
0
VL (0.0V) R
: DRIVER SINKS 200mA
OUT
DRIVER OUT
V
12.0 VH 6.0
- 3.0 VL 0.0
CC
0
V
EE
12
13
14
15
16
17
18
V
- V VOLTS (V - 3.0 FIXED)
EE EE
20ns/DIV
CC
FIGURE 10. R
vs DEVICE VOLTAGE
FIGURE 9. DATA/HIZ/DRIVER OUT TIMING
OUT
5.0
20
18
16
14
12
10
8
VH (1V-15V) R
: DRIVER SOURCES 200mA
OUT
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2200pF
1000pF
680pF
VL (0.0V FIXED) R
: DRIVER SINKS 200mA
OUT
1k/100pF
6
4
2
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
VH VOLTS (VL = 0.0)
VH VOLTS (VL = 0.0)
FIGURE 12. PROPAGATION DELAY vs VH RAIL, VARIOUS LOADS
FIGURE 11. R
OUT
vs VH RAIL
FN7486 Rev 3.00
December 4, 2014
Page 11 of 14
ISL55100A
Typical Performance Curves Device installed on Intersil ISL55100A Evaluation Board. (Continued)
30
27
24
21
18
15
12
9
20
18
16
14
12
10
8
2200pF
COMPARATOR T
PD
NO LOAD
DRIVER T
1000pF
680pF
NO LOAD
PD
6
6
4
1k/100pF
3
2
0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
11
12
13
14
15
16
17
18
19
VH VOLTS (VL = 0.0)
V -V (V = -3.0)
CC EE EE
FIGURE 14. DRIVER AND RECEIVER TPD VARIANCE vs V
FIGURE 13. DRIVER FALL TIME vs VH RAIL, VARIOUS LOADS
CC
30
27
24
100
90
80
70
60
50
2200pF
21
18
15
12
9
1000pF
680pF
ICC STATIC CONDITIONS
40
30
20
10
0
6
1k/100pF
3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
11
12
13
14
15
16
17
18
19
VH VOLTS (VL = 0.0)
V
-V (V = -3.0)
CC EE EE
FIGURE 15. DRIVER RISE TIME vs VH RAIL, VARIOUS LOADS
FIGURE 16. STATIC I vs V
CC CC
AIRFLOW LEGEND A = 0m/s : B = 1.0m/s : C = 2.5 m/s
A
150
135
120
105
90
10
9
A
B
C
8
12V V
CC
B
C
12V V
CC
7
6
5
4
3
2
1
0
18V V
CC
A
B
C
75
18V V
CC
60
45
30
9V V
AND V
= 5.5V
EXT
CC
9V V
AND V = 5.5V
EXT
CC
15
0
5
10 15 20 25 30 35 40 45 50 55 60
FREQUENCY (MHz)
5M 10M 15M 20M 25M 30M 35M 40M 45M 50M 55M 60M
FREQUENCY (Hz)
FIGURE 18. CALCULATED JUNCTION TEMP ABOVE AMBIENT WITH
- V = 18, 12 AND 9.0 (V = 5.5V) VOLTS. ALL
FIGURE 17. DEVICE POWER DISSIPATION WITH V - V = 18, 12
CC EE
V
CC EE
EXT
AND 9.0 (V
= 5.5V) VOLTS. All FOUR PINS MAKING
EXT
TWO TRANSITIONS PER PERIOD
FOUR PINS MAKING TWO TRANSITIONS PER PERIOD.
FN7486 Rev 3.00
December 4, 2014
Page 12 of 14
ISL55100A
Typical Performance Curves Device installed on Intersil ISL55100A Evaluation Board. (Continued)
V
+ 6.0 VH 6.0
- 3.0 VL 0.0
V
V
12.0 VH 6/8/10
- 3.0 VL 0.0
CC
CC
EE
V
EE
0
0
0
10ns/DIV
20ns/DIV
FIGURE 19. FREQUENCY OF 10MHz = 50ns PATTERN RATE
FIGURE 20. MINIMUM PULSE WIDTH VH 6/8/10V
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN7489.3
CHANGE
December 4, 2014
Update the datasheet throughout to Intersil’s new standard.
On page 2, updated the ordering information by adding MSL note.
On page 3, in “Pin Descriptions” table, added “This is also the potential of the exposed thermal pad on the
package bottom.” to the VEE row. Added “EP” row.
On page 4, under “Absolute Maximum Ratings”changed “DOUT” range from “VL – 0.5V” to “VEE - 0.5V”.
On page 9, changed a sentence in the 5th paragraph from “The maximum safe power temperature vs operating
frequency can be found graphically in Figure 18.” to “The junction temperature rise above ambient vs. operating
frequency can be found graphically in Figure 18.”
On page 9, edited “ESD Protection” paragraph.
On page 10, revised Figure 6 to represent actual ESD structures.
On page 12, changed the Y-axis label from “Temperature” to “Temperature Rise”.
Added Revision History and About Intersil sections.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2005-2014. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7486 Rev 3.00
December 4, 2014
Page 13 of 14
ISL55100A
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L72.10x10
72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
MIN
NOMINAL
0.90
MAX
1.00
0.05
1.00
NOTES
A
A1
A2
A3
b
0.80
-
-
-
0.02
-
0.65
9
0.20 REF
0.25
9
0.18
5.85
5.85
0.30
6.15
6.15
5, 8
D
10.00 BSC
9.75 BSC
6.00
-
D1
D2
E
9
7, 8
10.00 BSC
9.75 BSC
6.00
-
E1
E2
e
9
7, 8
0.50 BSC
-
-
k
0.20
0.30
-
-
L
0.40
0.50
8, 10
N
72
2
Nd
Ne
P
18
3
18
3
-
-
-
0.60
12
9
-
9
Rev. 1 11/04
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensionsare providedtoassist with PCB LandPattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & are present when
Anvil singulation method is used and not present for saw
singulation.
10. Compliant to JEDEC MO-220VNND-3 except for the "L" min
dimension.
FN7486 Rev 3.00
December 4, 2014
Page 14 of 14
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