ISL267450AIUZ-T [RENESAS]
12-Bit 1MSPS SAR ADCs; MSOP8, SOT8; Temp Range: -40° to 85°C;
| 型号： | ISL267450AIUZ-T |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 12-Bit 1MSPS SAR ADCs; MSOP8, SOT8; Temp Range: -40° to 85°C 光电二极管 转换器 |
| 文件： | 总18页 (文件大小：1154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
ISL267440, ISL267450A
10-Bit and 12-Bit, 1MSPS SAR ADCs
FN7708
Rev.2.00
June 28, 2012
The ISL267440 and ISL267450A are 10-bit and 12-bit, 1MSPS
sampling SAR-type ADCs featuring excellent linearity over
supply and temperature variations. These devices are drop-in
compatible with the AD7440 and AD7450A. The robust,
fully-differential input offers high impedance to minimize
errors due to leakage currents, and the specified
measurement accuracy is maintained with input signals up to
the supply rails.
Features
• Drop-in Compatible with AD7440, AD7450A
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 1MHz Sampling Rate
The reference accepts inputs from 0.1V to 2.2V for 3V
operation and 0.1V to 3.5V for 5V operation. This provides
design flexibility in a wide variety of applications. The
ISL267440, ISL267450A also feature up to 8kV Human Body
Model ESD survivability.
• 3V or 5V Operation
• Low Operating Current
- 1.25mA at 1MSPS with 3V Supplies
- 1.70mA at 1MSPS with 5V Supplies
• Power-down Current between Conversions: 1µA
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Power
dissipation is 8.5mW at a sampling rate of 1MSPS, and just
5µW between conversions utilizing Auto Power-Down mode
(with a 5V supply). The ISL267440, ISL267450A are excellent
solutions for remote industrial sensors and battery-powered
instruments.
• Pb-Free (RoHS Compliant)
• Available in MSOP Package
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
The ISL267440, ISL267450A are available in an 8 lead MSOP
package, and are specified for operation over the Industrial
temperature range (–40°C to +85°C).
• Flow Controllers
1.0
0.8
0.6
0.4
VREF
VDD
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
VIN+
SCLK
SDATA
CS
SAR
LOGIC
SERIAL
INTERFACE
VIN–
VREF
0
1024
2048
3072
4096
GND
CODE
FIGURE 1. BLOCK DIAGRAM
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
FN7708 Rev.2.00
June 28, 2012
Page 1 of 18
ISL267440, ISL267450A
Typical Connection Diagram
0.1µF
+3V/5V
SUPPLY
VREF
10µF
0.1µF
+
VREF
VDD
SCLK
SDATA
CS
VIN+
VIN–
REFP-P
REFP-P
µP/µC
GND
SERIAL
INTERFACE
Pin Configuration
ISL267440, ISL267450A
(8 LD MSOP)
TOP VIEW
1
2
3
4
8
7
6
5
VDD
VREF
VIN+
VIN–
GND
SCLK
SDATA
CS
Pin Descriptions
ISL267440, ISL267450A
PIN NAME PIN NUMBER
DESCRIPTION
VDD
SCLK
SDATA
CS
8
7
6
5
4
3
2
1
Supply voltage, +2.7V to 5.25V.
Serial clock input. Controls digital I/O timing and clocks the conversion.
Digital conversion output.
Chip select input. Generally controls the start of a conversion though not always the sampling signal.
GND
VIN–
VIN+
VREF
Ground
Negative analog input.
Positive analog input.
Reference voltage.
FN7708 Rev.2.00
June 28, 2012
Page 2 of 18
ISL267440, ISL267450A
Ordering Information
PART NUMBER
PART
MARKING
V
RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
PKG.
DWG. #
DD
(Note 4)
ISL267440IUZ (Note 3)
67440
67440
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
2.7 to 5.25
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
8 Ld MSOP
M8.118
ISL267440IUZ-T (Notes 1, 3)
ISL267440IUZ-T7A (Notes 1, 3)
ISL267450AIUZ (Note 3)
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld MSOP
8 Ld SOT-23
8 Ld SOT-23
8 Ld SOT-23
8 Ld SOT-23
M8.118
M8.118
M8.118
M8.118
M8.118
P8.064
P8.064
P8.064
P8.064
67440
7450A
ISL267450AIUZ -T (Notes 1, 3)
ISL267450AIUZ -T7A (Notes 1, 3)
ISL267440IHZ-T (Notes 1, 2)
ISL267440IHZ-T7A (Notes 1, 2)
ISL267450AIHZ-T (Notes 1, 2)
ISL267450AIHZ-T7A (Notes 1, 2)
NOTES:
7450A
7450A
7440 (Note 5)
7440 (Note 5)
450A (Note 5)
450A (Note 5)
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate
-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL267440 or ISL267450A. For more information on MSL please see
techbrief TB363.
5. The part marking is located on the bottom of the part.
FN7708 Rev.2.00
June 28, 2012
Page 3 of 18
ISL267440, ISL267450A
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal-to-(Noise + Distortion) Ratio (SINAD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Integral Nonlinearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Grounding and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M8.118. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
P8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FN7708 Rev.2.00
June 28, 2012
Page 4 of 18
ISL267440, ISL267450A
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Thermal Resistance (Typical)
8 Ld MSOP Package (Notes 6, 7). . . . . . . . .
8 Ld SOT-23 Package (Notes 6, 7). . . . . . . .
JA (°C/W)
165
JC (°C/W)
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
64
99
DD
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
DD
135
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
6. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
7. For , the “case temp” location is taken at the package top center.
JC
Electrical Specifications V = +3.0V to +3.6V, f
= 18MHz, f = 1MSPS, V
= 2.0V; V = +4.75V to +5.25V, f
DD
= 18MHz,
SCLK
DD
SCLK
S
REF
f
= 1MSPS, V
= 2.5V; V = V , unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply over the operating temperature
S
REF
CM REF
A
range, -40°C to +85°C.
ISL267440
TYP
ISL267450A
TYP
MIN
(Note 8)
MAX
(Note 8) (Note 8)
MIN
MAX
(Note 8) UNITS
SYMBOL
DYNAMIC PERFORMANCE
SINAD Signal-to (Noise + Distortion) Ratio f = 100kHz
PARAMETER
TEST CONDITIONS
61.0
60.7
61.6
61.5
-82
70.0
71.4
70.5
-84
dB
dB
IN
V
= +4.75V to +5.25V
DD
f
= 100kHz
68.5
IN
V
= +3.0V to +3.6V
DD
THD
Total Harmonic
Distortion
f
V
= 100kHz
-74
-72
-76
-74
-76
-74
-76
-74
dB
dB
dB
dB
dB
IN
= +4.75V to +5.25V
DD
f
= 100kHz
-80
-84
IN
V
= +3.0V to +3.6V
DD
SFDR Spurious Free Dynamic Range
f
= 100kHz
-82
-87
IN
V
= +4.75V to +5.25V
DD
f
= 100kHz
-82
-85
IN
V
= +3.0V to +3.6V
DD
IMD
Intermodulation Distortion
2nd and 3rd order, f = 90kHz,
IN
-92
-95
110kHz
tpd
Aperture Delay
1
1
ns
ps
tpd
3dB
Aperture Jitter
15
15
15
15
Full Power Bandwidth
@ –3dB
MHz
DC ACCURACY
N
Resolution
10
12
Bits
LSB
INL
DNL
Integral Nonlinearity
-0.5
-0.5
±0.1
±0.1
0.5
0.5
-1
±0.4
±0.3
1
Differential Nonlinearity
Guaranteed no missed codes to 12-
bits (ISL267450A) or 10 bits
(ISL267440)
-0.95
0.95 LSB
OFFSET Zero-Code Error
Zero Volt Differential Input
-2.5
-1
±0.2
±0.1
±0.1
2.5
1
-6
-2
-2
±0.2
±0.1
±0.1
6
2
2
LSB
LSB
LSB
Positive Gain Error
GAIN
± REF input range
Negative Gain Error
-1
1
ANALOG INPUT (Note 9)
|AIN| Full-Scale Input Span
2 x V
REF
VIN+ - VIN–
VIN+ - VIN–
V
FN7708 Rev.2.00
June 28, 2012
Page 5 of 18
ISL267440, ISL267450A
Electrical Specifications V = +3.0V to +3.6V, f
= 18MHz, f = 1MSPS, V
= 2.0V; V = +4.75V to +5.25V, f
DD
= 18MHz,
SCLK
DD
SCLK
S
REF
f
= 1MSPS, V
= 2.5V; V = V , unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply over the operating temperature
S
REF CM REF A
range, -40°C to +85°C. (Continued)
ISL267440
TYP
ISL267450A
TYP
MIN
(Note 8)
MAX
(Note 8) (Note 8)
MIN
MAX
(Note 8) UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
Absolute Input Voltage Range
VIN+, VIN– VIN+
VIN–
V
= V
REF
V
±V /2
V
±V /2
V
V
CM
CM REF
CM REF
V
±V /2
V
±V /2
CM REF
CM REF
I
Input DC Leakage Current
Input Capacitance
-1
1
-1
1
µA
pF
LEAK
C
Track/Hold mode
13/5
13/5
VIN
REFERENCE INPUT
Input Voltage Range
V
V
V
= 3V (1% tolerance for specified
2.0
2.5
2.0
2.5
V
V
REF
REF
DD
performance)
V
= 5V (1% tolerance for specified
DD
performance)
I
DC Leakage Current
-1
1
-1
1
µA
pF
LEAK
C
REF Input Capacitance
Track/Hold mode
21/18.5
21/18.5
REF
LOGIC INPUTS
V
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
2.4
-1
2.4
-1
V
V
IH
V
0.8
1
0.8
1
IL
I
µA
pF
LEAK
C
10
10
IN
LOGIC OUTPUTS
V
Output High Voltage
I
= 200µA
V
- 0.3
V - 0.3
DD
V
V
OH
SOURCE
= 200µA
SINK
DD
V
Output Low Voltage
I
0.4
1
0.4
1
OL
I
Floating-State Output Current
Floating-State Output Capacitance
Output Coding
-1
-1
µA
pF
OZ
C
10
10
OUT
Two’s Complement
CONVERSION RATE
t
Conversion Time
Acquisition Time
Throughput Rate
f
= 18MHz
888
200
888
200
ns
ns
CONV
SCLK
t
ACQ
f
1000
1000 kSPS
max
POWER REQUIREMENTS
V
Positive Supply Voltage Range
2.7
3.6
2.7
3.6
V
V
DD
4.75
5.25
4.75
5.25
I
Positive Supply Input Current
DD
Static
1
1
µA
µA
µA
Dynamic
3V
5V
1250
1700
1250
1700
Power Dissipation
Static Mode
V
V
V
V
= 3V
3
3
5
µW
µW
DD
DD
DD
DD
= 5V
5
Dynamic
= 3V, f
= 5V, f
= 1MSPS
= 1MSPS
3.75
8.50
3.75 mW
8.50 mW
smpl
smpl
NOTES:
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
9. The absolute voltage applied to each analog input must be between GND and V to guarantee datasheet performance.
DD
FN7708 Rev.2.00
June 28, 2012
Page 6 of 18
ISL267440, ISL267450A
Timing Specifications Limits established by characterization and are not production tested. V = 3.0V to 3.6V, f
= 18MHz,
SCLK
DD
f
= 1MSPS, V
REF
= 2.0V; V = 4.75V to 5.25V, f
= 18MHz, f = 1MSPS, V
REF
= 2.5V; V = V unless otherwise noted. Boldface limits apply over
S
DD
SCLK
S
CM REF
the operating temperature range, -40°C to +85°C.
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNITS
MHz
ns
f
t
Clock Frequency
Clock Period
0.01
55
18
SCLK
SCLK
t
Acquisition Time (Note 10)
Conversion Time
ns
ACQ
t
888
ns
CONV
t
CS Pulse Width
10
10
ns
CSW
t
CS Falling Edge to S
CLK
Falling Edge Setup Time
ns
CSS
t
CS Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Hold
SCLK Pulse Width
20
40
ns
CDV
t
ns
CLKDV
t
10
ns
SDH
t
0.4 x t
SCLK
0.6 x t
SCLK
ns
SW
DISABLE
t
SCLK Falling Edge to SDATA Disable Time
(Note 11)
Extrapolated back to true bus relinquish
10
35
ns
t
Quiet Time Before Sample
60
ns
QUIET
NOTE:
10. Read the “Acquisition Time” section on page 13 for a discussion of this parameter.
11. During characterization, t is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the
DISABLE
AD7440/450A loading (25pF) is calculated.
FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85k
OUTPUT
PIN
CL
10pF
FIGURE 4. EQUIVALENT LOAD CIRCUIT
FN7708 Rev.2.00
June 28, 2012
Page 7 of 18
ISL267440, ISL267450A
Typical Performance Characteristics
75
0
-20
8192-POINT FFT
5.25V
f
f
= 1MSPS
SAMPLE
= 95.2kHz
IN
SINAD = 72.0dB
THD = -91dB
SFDR = 93dB
70
-40
4.75V
3.6V
2.7V
-60
65
-80
-100
-120
-140
60
55
10
100
1k
0
100
200
300
400
500
INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 5. ISL267450A SINAD vs ANALOG INPUT FREQUENCY FOR
VARIOUS SUPPLY VOLTAGES
FIGURE 6. ISL267450A DYNAMIC PERFORMANCE WITH V = 5V
DD
1.0
0.8
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
10k
100k
FREQUENCY (Hz)
1k
10k
0
1024
2048
3072
4096
CODE
FIGURE 7. CMRR vs FREQUENCY FOR V = 5V
DD
FIGURE 8. TYPICAL DNL FOR THE ISL267450A FOR V = 5V
DD
0
-20
1.0
0.8
250mV
SINE WAVE ON VDD
P-P
NO DECOUPLING ON VDD
0.6
0.4
-40
0.2
-60
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-80
-100
-120
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (kHz)
0
1024
2048
3072
4096
CODE
FIGURE 9. PSRR vs SUPPLY RIPPLE FREQUENCY WITHOUT SUPPLY
DECOUPLING
FIGURE 10. TYPICAL INL FOR THE ISL267450A FOR V = 5V
DD
FN7708 Rev.2.00
June 28, 2012
Page 8 of 18
ISL267440, ISL267450A
Typical Performance Characteristics (Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
2.5
2.0
1.5
Pos INL
1.0
0.5
Pos DNL
0.0
Neg INL
-0.5
-1.0
-1.5
-2.0
Neg DNL
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
V
(V)
REF
REF
FIGURE 11. CHANGE IN DNL vs VREF FOR THE ISL267450A FOR
FIGURE 12. CHANGE IN INL vs VREF FOR THE ISL267450A FOR
= 3V
V
= 5V
V
DD
DD
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
6
5
4
3
Pos DNL
Neg DNL
2
3V V
DD
DD
1
0
5V V
1.0
-1
-2
0.0
0.5
1.5
2.0
(V)
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
V
(V)
V
REF
REF
FIGURE 13. CHANGE IN DNL vs VREF FOR THE ISL267450A FOR
= 3V
FIGURE 14. CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE
FOR V = 5V AND 3V FOR THE ISL267450A
V
DD
DD
12.0
11.5
11.0
10.5
10.0
9.5
5
4
3
5V V
DD
3V V
DD
2
Pos INL
Neg INL
1
0
9.0
-1
-2
-3
-4
-5
8.5
8.0
7.5
7.0
0.0
0.5
1.0
1.5
V
2.0
(V)
2.5
3.0
3.5
0.0
0.5
1.0
1.5
V
2.0
2.5
3.0
3.5
(V)
REF
REF
FIGURE 15. CHANGE IN INL vs VREF FOR THE ISL267450A FOR
= 5V
FIGURE 16. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR
= 5V AND 3V FOR THE ISL267450A
V
V
DD
DD
FN7708 Rev.2.00
June 28, 2012
Page 9 of 18
ISL267440, ISL267450A
Typical Performance Characteristics (Continued)
70k
60k
50k
40k
30k
20k
10k
0
0.5
0.4
0.3
0.2
0.1
0
65,516
CODES
-0.1
-0.2
-0.3
-0.4
-0.5
10
CODES
10
CODES
0
256
512
768
1024
2044
2045
2046
2047
2048
2049
2050
CODE
CODE
FIGURE 17. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT
FOR THE ISL267450A WITH V = 5V
FIGURE 18. TYPICAL DNL FOR THE ISL267440 FOR V = 5V
DD
DD
0.5
0.4
0.3
0.2
0.1
0
0
-20
8192-POINT FFT
f
f
= 1MSPS
SAMPLE
= 95.2kHz
IN
SINAD = 61.6dB
THD = -75dB
SFDR = 81dB
-40
-60
-80
-0.1
-0.2
-0.3
-0.4
-0.5
-100
-120
-140
0
100
200
300
400
500
FREQUENCY (kHz)
CODE
FIGURE 19. ISL267440 DYNAMIC PERFORMANCE WITH V = 5V
DD
FIGURE 20. TYPICAL INL FOR THE ISL267440 FOR V = 5V
DD
FN7708 Rev.2.00
June 28, 2012
Page 10 of 18
ISL267440, ISL267450A
Functional Description
1LSB = 2•VREF/4096
011...111
011...110
The ISL267440, ISL267450A are based on a successive
approximation register (SAR) architecture utilizing capacitive
charge redistribution digital to analog converters (DACs).
Figure 21 shows a simplified representation of the converter.
During the acquisition phase (ACQ) the differential input is stored
on the sampling capacitors (CS). The comparator is in a balanced
state since the switch across its inputs is closed. The signal is
000...001
000...000
111...111
fully acquired after t
has elapsed, and the switches then
ACQ
transition to the conversion phase (CONV) so the stored voltage
may be converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
100...010
100...001
100...000
–VREF
+VREF +VREF
– 1½LSB – 1LSB
0V
+ ½LSB
ANALOG INPUT
VIN+ – (VIN–)
FIGURE 22. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL267440, ISL267450A feature a fully differential input
with a nominal full-scale range equal to twice the applied VREF
voltage. Each input swings VREF V , 180° out of phase from
P-P
one another for a total differential input of 2*VREF (refer to
Figure 23). Differential signaling offers several benefits over a
single-ended input, such as:
CONV
CS
• Doubling of the full-scale input range (and therefore the
dynamic range)
VIN+
VIN–
ACQ
ACQ
SAR
LOGIC
ACQ
CS
CONV
• Improved even order harmonic distortion
CONV
• Better noise immunity due to common mode rejection
VREF
FIGURE 21. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
VREF P-P
VIN+
VIN–
ISL267440,
ISL267450A
An external clock must be applied to the SCLOCK pin to generate
a conversion result. The allowable frequency range for SCLOCK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLOCK to maximize set-up and hold times.
VCM
VREF P-P
FIGURE 23. DIFFERENTIAL INPUT SIGNALING
Figure 24 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 12 for more
details.
ADC Transfer Function
The output coding for the ISL267440, ISL267450A is twos
complement. The first code transition occurs at successive LSB
values (i.e., 1 LSB, 2 LSB, and so on). The LSB size of the
ISL267450A is 2*VREF/4096, while the LSB size of the
ISL267440 is 2*VREF/1024. The ideal transfer characteristic of
the ISL267440, ISL267450A is shown in Figure 22.
FN7708 Rev.2.00
June 28, 2012
Page 11 of 18
ISL267440, ISL267450A
VCM
V
2.5
2.5
2.0
1.5
1.0
0.5
5.0
4.0
VIN–
VCM
VIN+
2.0V
P-P
2.0V
1.0V
3.0
2.0
1.0
t
VREF=2V
VREF
V
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
FIGURE 26. RELATIONSHIP BETWEEN VREF AND VCM FOR V = 3V
DD
5.0
VIN–
VCM
VIN+
Voltage Reference Input
4.0
3.0
2.0
1.0
2.5V
P-P
An external low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range of the converter. The
reference input accepts voltages ranging from 0.1V to 2.2V for 3V
operation and 0.1V to 3.5V for 5V operation. The device is
specified with a reference voltage of 2.5V for 5V operation and
2.0V for 3V operation.
t
VREF=2.5V
Figures 27 and 28 illustrate possible voltage reference options
for the ISL267440/ISL26750A. Figure 27 uses the precision
ISL21090 voltage reference which exhibits exceptionally low drift
and low noise. The ISL21090 must use a power supply greater
than 4.7V. The VREF input pin of the ISL267XX devices uses very
low current, so the decoupling capacitor can be small (0.1µF).
FIGURE 24. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
Figure 28 illustrates the ISL21010 voltage reference being used
with these ADCs. The ISL21010 series voltage references have
higher noise and drift than the ISL26090 devices, but they
consume very low operating current and are excellent for
battery-powered applications.
and minimum voltages on the V + and V – pins within
specification. Figures 25 and 26 illustrate this relationship for 5V
and 3V operation, respectively. The dashed lines show the
IN IN
theoretical VCM range based solely on keeping the V + and V
–
IN IN
pins within the supply rails. Additional restrictions are imposed
due to the required headroom of the input circuitry, resulting in
practical limits shown by the shaded area.
VCM
5.0
4.25V
4.0
3.25V
3.0
2.0
1.75V
1.0
VREF
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 25. RELATIONSHIP BETWEEN VREF AND VCM FOR V = 5V
DD
FN7708 Rev.2.00
June 28, 2012
Page 12 of 18
ISL267440, ISL267450A
5V
BULK
+
0.1µF
DNC
DNC
DNC
1
8
7
6
5
V
DD
ISL267440
ISL267450A
V
2
3
4
IN
VREF
2.5V
COMP
GND
V
OUT
0.1µF
0.1µF
TRIM
ISL21090
FIGURE 27. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+2.7V TO +3.6V
OR +5V
+
BULK
0.1µF
V
1
2
0.1µF
IN
GND
3
V
DD
ISL267440
ISL267450A
VREF
V
OUT
1.25, 2.048 OR 2.5V
ISL21010
0.1µF
FIGURE 28. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
Power-On Reset
The ISL267440 and ISL267450A are designed to minimize
power consumption by only powering up the SAR comparator
during conversion time. When the converter is in track mode (its
sample capacitors are tracking the input signal) the SAR
comparator is powered down. The state of the converter is
dictated by the logic state of CS. When CS is high, the SAR
comparator is powered down while the sampling capacitor array
is tracking the input. When CS transitions low, the capacitor array
immediately captures the analog signal that is being tracked.
After CS is taken low, the SCLK pin is toggled 16 times. For the
first 3 clocks, the comparator is powered up and auto-zeroed,
then the SAR decision process is begun. This process uses 12
SCLK cycles for the 12-bit ISL267450A. Each SAR decision is
presented to the SDATA output on the next clock cycle after the
SAR decision is performed. The SAR process (12 bits) is
completed on SCLK cycle 15. At this point in time, the SAR
comparator is powered down and the capacitor array is placed
back into Track mode. The last SAR comparator decision is
output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
When power is first applied, the ISL267440/ISL267450A
performs a power-on reset that requires approximately 2.5ms to
execute. After this is complete, a single dummy conversion must
be executed (by taking CS low) in order to initialize the switched
capacitor track and hold. The dummy conversion cycle will take
1µs with an 18MHz SCLK. Once the dummy cycle is complete,
the ADC mode will be determined by the state of CS. Regular
conversions can be started immediately after this dummy cycle
is completed and time has been allowed for proper acquisition.
Acquisition Time
To achieve the maximum sample rate (1MSps) in the
ISL267450A device, the maximum acquisition time is 200ns. For
slower conversion rates, or for conversions performed using a
slower SCLK value than 18MHz, the minimum acquisition time is
200ns. This same minimum applies to the ISL267440. This
minimum acquisition time also applies to all the devices if short
cycling is utilized.
Short Cycling
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all SCLK falling edges have elapsed.
This is referred to as short cycling, and it can be used to further
optimize power dissipation. In this mode, a lower resolution
result will be output, but the ADC will enter static mode sooner
and exhibit a lower average power consumption than if the
complete conversion cycle were carried out. The minimum
Figures 29 and 30 on page 14 illustrate the system timing for the
12, and 10-bit converters respectively.
acquisition time (t
) requirement of 200ns must be met for
the next conversion to be valid.
ACQ
FN7708 Rev.2.00
June 28, 2012
Page 13 of 18
ISL267440, ISL267450A
FIGURE 29. ISL267450A SYSTEM TIMING
FIGURE 30. ISL267440 SYSTEM TIMING
Power vs Throughput Rate
Serial Digital Interface
The ISL267440 and ISL267450A provide reduced power
consumption at lower conversion rates by automatically
switching into a low-power mode after completing a conversion.
The average power consumption of the ADC decreases at lower
throughput rates. Figure 31 shows the typical power
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
The serial interface is designed around using 16 SCLK cycles to
perform an autozero on the SAR comparator and additional SCLK
cycles for SAR comparator decisions (12 SLCKs in the 12-bit
device, 10 SCLKs in the 10-bit device, and 8 SCLKs in the 8-bit
device). If short cycling is not used, all converter throughput
cycles take 16 SCLKs. The SDATA output goes low after the last
conversion decision has been presented to the SDATA output, as
shown in Figures 29 and 30.
consumption over a wide range of throughput rates.
100
10
V
= 5V
DD
1
0.1
V
= 3V
150
DD
0.01
0
50
100
200
250
300
350
THROUGHPUT (Ksps)
FIGURE 31. POWER CONSUMPTION vs THROUGHPUT RATE
FN7708 Rev.2.00
June 28, 2012
Page 14 of 18
ISL267440, ISL267450A
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
The ISL267440, ISL267450A is tested using the CCIF standard,
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second order terms are
usually distanced in frequency from the original sine waves,
while the third order terms are usually at a frequency close to the
input frequencies. As a result, the second and third order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
INPUT
–Full Scale
VOLTAGE
–VREF
DIGITAL OUTPUT
1000 0000 0000
1000 0000 0001
0000 0000 0000
0111 1111 1110
0111 1111 1111
–Full Scale + 1LSB
Midscale
–VREF+ 1LSB
0
+Full Scale – 1LSB
+Full Scale
+VREF– 1LSB
+VREF
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
to half the sampling frequency (f /2), excluding DC. The ratio
s
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
is dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by:
Signal-to-(Noise + Distortion) = 6.02 N + 1.76dB
(EQ. 1)
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
Thus, for a 12-bit converter this is 74dB, and for a 10-bit this is 62dB.
a 250mV
VIN+ and VIN– of frequency fs:
sine wave applied to the common-mode voltage of
P-P
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267440, ISL267450A,
it is defined as:
CMRRdB = 10logPfl Pfs
(EQ. 3)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
2
2
2
2
2
V
+ V + V + V + V
2
3 4 5 6
THDdB = 20log -----------------------------------------------------------------------
(EQ. 2)
2
V
Integral Nonlinearity (INL)
1
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
where V is the rms amplitude of the fundamental and V , V ,
1
2
3
V , V , and V are the rms amplitudes of the second to the
4
5
6
sixth harmonics.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of
the fundamental (also referred to as Spurious Free Dynamic
Range (SFDR)). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal VIN+ – VIN– (i.e., +REF – 1 LSB), after
the zero code error has been adjusted out.
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal VIN+ – VIN– (i.e., – REF + 1 LSB), after
the zero code error has been adjusted out.
FN7708 Rev.2.00
June 28, 2012
Page 15 of 18
ISL267440, ISL267450A
ground planes should be joined in only one place, and the
connection should be a star ground point established as close to
the GND pin on the ISL267440, ISL267450A as possible. Avoid
running digital lines under the device, as this will couple noise
onto the die. The analog ground plane should be allowed to run
under the ISL267440, ISL267450A to avoid noise coupling.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC VDD
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
supply of frequency f . The frequency of this input varies from
1kHz to 1MHz.
S
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
PSRRdB = 10logPf Pfs
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency f in the ADC output.
s
Application Hints
Grounding and Layout
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
The printed circuit board that houses the ISL267440,
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
ISL267450A should be designed so that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can be easily
separated. A minimum etch technique is generally best for
ground planes since it gives the best shielding. Digital and analog
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN7708.2
CHANGE
June 15, 2012
Page 2- Typical Connection Diagram: Added value to cap 0.1µF and removed ‘+’ from the 0.1 capacitor.
Page 3, Ordering Information Table: “Removed coming soon on all the SOT23’s.”
Page11- Figure22, Ideal Transfer Characteristics: replaced the diagram for clarity.
March 22, 2012
FN7708.1
FN7708.0
Page 12 - Updated Voltage Reference Input section
Page 13 - Removed Applications Information section
Pages 13, 14 - Replaced/updated the following sections: Power-Down/Standby Modes, Dynamic Mode, Static
Mode, Short Cycling, Power-on Reset, Power vs Throughput Rate, and Serial Digital Interface with:
Converter Operation, Power-On Reset, Acquisition Time, Short Cycling, Power vs Throughput Rate, and Serial
Digital Interface setions.
Page 18 - Added package outline drawing P8.064
December 5, 2011
Initial release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL267440, ISL267450A
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
FITs are available from our website at: http://rel.intersil.com/reports/search.php
FN7708 Rev.2.00
June 28, 2012
Page 16 of 18
ISL267440, ISL267450A
Package Outline Drawings
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN7708 Rev.2.00
June 28, 2012
Page 17 of 18
ISL267440, ISL267450A
Small Outline Transistor Plastic Packages (SOT23-8)
P8.064
0.20 (0.008) M
C
VIEW C
8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE
C
L
e
INCHES
MIN
MILLIMETERS
b
8
SYMBOL
MAX
0.057
0.0059
0.051
0.015
0.013
0.009
0.008
0.118
0.118
0.067
MIN
0.90
0.00
0.90
0.22
0.22
0.08
0.08
2.80
2.60
1.50
MAX
1.45
0.15
1.30
0.38
0.33
0.22
0.20
3.00
3.00
1.70
NOTES
A
A1
A2
b
0.036
0.000
0.036
0.009
0.009
0.003
0.003
0.111
0.103
0.060
-
-
-
-
7
2
6
5
4
C
E1
L
C
L
E
1
3
b1
c
6
6
3
-
e1
D
c1
D
C
C
L
E
E1
e
3
-
0.0256 Ref
0.0768 Ref
0.014 0.022
0.65 Ref
1.95 Ref
0.35 0.55
SEATING
PLANE
A2
A1
A
e1
L
-
-C-
4
L1
L2
N
0.024 Ref.
0.010 Ref.
8
0.60 Ref.
0.25 Ref.
8
0.10 (0.004) C
5
b
R
0.004
-
0.10
-
WITH
PLATING
b1
R1
0.004
0.010
0.10
0.25
o
o
o
o
0
8
0
8
-
c
c1
Rev. 2 9/03
NOTES:
BASE METAL
1. Dimensioning and tolerance per ASME Y14.5M-1994.
2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.
4X 1
3. Dimensions D and E1 are exclusive of mold flash, protrusions,
or gate burrs.
R1
4. Footlength L measured at reference to gauge plane.
5. “N” is the number of terminal positions.
R
6. These Dimensions apply to the flat section of the lead between
0.08mm and 0.15mm from the lead tip.
GAUGE PLANE
SEATING
PLANE
7. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
L
C
L2
L1
4X 1
VIEW C
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in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
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For information regarding Intersil Corporation and its products, see www.intersil.com
FN7708 Rev.2.00
June 28, 2012
Page 18 of 18
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