ISL267452IHZ-T_技术文档

12-Bit, 555kSPS SAR ADC

ISL267452

Features

The ISL267452 is a 12-bit, 555kSPS sampling SAR-type ADC

featuring excellent linearity over supply and temperature

variations, and is drop-in compatible with the AD7452. The

robust, fully-differential input offers high impedance to minimize

errors due to leakage currents, and the specified measurement

accuracy is maintained with input signals up to the supply rails.

• Drop-in Compatible with AD7452

• Differential Input (Span = 2VREF)

• Simple SPI-compatible Serial Digital Interface

• Guaranteed No Missing Codes

• 555kHz Sampling Rate

The reference accepts inputs from 0.1V to 2.2V for 3V operation

and 0.1V to 3.5V for 5V operation, which provides design

flexibility in a wide variety of applications. The ISL267452 also

features up to 8kV Human Body Model ESD survivability.

• 3V or 5V Operation

• Low Operating Current

- 1.25mA at 555kSPS with 3V Supplies

- 1.70mA at 555kSPS with 5V Supplies

The serial digital interface is SPI compatible and is easily

interfaced to all popular FPGAs and microcontrollers. Power

dissipation is 7mW at a sampling rate of 555kSPS, and just 5µW

between conversions utilizing Auto Power-Down mode (with a 5V

supply), making the ISL267452 an excellent solution for remote

industrial sensors and battery-powered instruments.

• Power-down Current between Conversions: 1µA

• Excellent Differential Non-Linearity

• Low THD: -83dB (typ)

• Pb-Free (RoHS Compliant)

The ISL267452 is available in an 8 LD SOT-23 package, and is

specified for operation over the Industrial temperature range

(-40°C to +85°C).

• Available in SOT-23 Package

Applications

• Remote Data Acquisition

• Battery Operated Systems

• Industrial Process Control

• Energy Measurement

• Data Acquisition Systems

• Pressure Sensors

• Flow Controllers

1.0

0.8

0.6

VREF

VDD

0.4

0.2

0.0

VIN+

SCLK

SDATA

CS

-0.2

-0.4

-0.6

-0.8

-1.0

SAR

LOGIC

SERIAL

INTERFACE

VIN–

VREF

GND

0

1024

2048

3072

4096

CODE

FIGURE 1. BLOCK DIAGRAM

FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE

July 26, 2012

FN8255.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

1

ISL267452

Typical Connection Diagram

0.1µF

+3V/5V

SUPPLY

VREF

10µF

0.1µF

+

VREF

VIN+

VIN–

VDD

SCLK

SDATA

CS

VREF_P-P

µP/µC

GND

SERIAL

INTERFACE

Pin Configuration

ISL267452

(8 LD SOT-23)

TOP VIEW

1

8

7

6

5

VDD

VREF

VIN+

VIN–

GND

2

3

4

SCLK

SDATA

CS

Pin Descriptions

ISL267452

PIN NAME PIN NUMBER

DESCRIPTION

VDD

SCLK

SDATA

CS

8

7

6

5

4

3

2

1

Supply voltage, +2.7V to 5.25V.

Serial clock input. Controls digital I/O timing and clocks the conversion.

Digital conversion output.

Chip select input. Controls the start of a conversion.

Ground

GND

VIN–

VIN+

VREF

Negative analog input.

Positive analog input.

Reference voltage.

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ISL267452

Ordering Information

PACKAGE

Tape & Reel

(Pb-free)

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

VDD RANGE

(V)

TEMP RANGE

(°C)

PKG.

DWG. #

ISL267452IHZ-T

ISL267452IHZ-T7A

NOTES:

7452 (Note 4)

2.7 to 5.25

-40 to +85

8 Ld SOT-23

P8.064

1. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate

-e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for ISL267452. For more information on MSL please see techbrief TB363.

4. The part marking is located on the bottom of the part.

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ISL267452

Table of Contents

Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Short Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Grounding and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Signal-to-(Noise + Distortion) Ratio (SINAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Total Harmonic Distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Aperture Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Integral Nonlinearity (INL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Differential Nonlinearity (DNL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

P8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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ISL267452

Absolute Maximum Ratings

Thermal Information

Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V

Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V

Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V

Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V

Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

ESD Rating

Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV

Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V

Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV

Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA

Thermal Resistance (Typical)

8 Ld SOT-23 Package (Notes 5, 6). . . . . . . .

Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

θ

_JA(°C/W)

135

θ

_JC(°C/W)

99

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

5. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

JA

6. For θ , the “case temp” location is taken at the package top center.

JC

Electrical Specifications VDD = +3.0V to +3.6V, f

= 10MHz, f = 555kSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, f

= 10MHz,

SCLK

S

SCLK

f

= 555kSPS, VREF = 2.5V; V = VREF, unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply over the operating temperature

S

CM

A

range, -40°C to +85°C.

ISL267452

TYP

MIN

(Note 7)

MAX

(Note 7) UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

DYNAMIC PERFORMANCE

SINAD

Signal-to (Noise + Distortion) Ratio

f

= 100kHz

70.0

68.5

71.4

70.5

-84

dB

IN

VDD = +4.75V to +5.25V

f

= 100kHz

IN

VDD = +3.0V to +3.6V

THD

Total Harmonic

Distortion

f

= 100kHz

-76

-74

-76

-74

dB

IN

VDD = +4.75V to +5.25V

f

= 100kHz

-84

IN

VDD = +3.0V to +3.6V

SFDR

Spurious Free Dynamic Range

f

= 100kHz

-87

IN

VDD = +4.75V to +5.25V

f

= 100kHz

-85

IN

VDD = +3.0V to +3.6V

IMD

tpd

Intermodulation Distortion

Aperture Delay

2nd and 3rd order, f = 90kHz, 110kHz

IN

-95

1

dB

ns

Δtpd

Aperture Jitter

15

ps

β3dB

Full Power Bandwidth

@ –3dB

MHz

DC ACCURACY

N

Resolution

12

-1

Bits

LSB

INL

Integral Nonlinearity

Differential Nonlinearity

Zero-Code Error

±0.4

±0.3

±0.2

±0.1

1

0.95

6

DNL

Guaranteed no missed codes to 12 bits

Zero Volt Differential Input

-0.95

-6

OFFSET

Positive Gain Error

Negative Gain Error

-2

2

GAIN

± VREF input range

-2

2

ANALOG INPUT (Note 8)

|AIN| Full-Scale Input Span

Absolute Input Voltage Range

2 x VREF

VIN+ - VIN–

V

VIN+, VIN– VIN+

VIN–

V

= VREF

V

±VREF/2

V

CM

V

CM

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ISL267452

Electrical Specifications VDD = +3.0V to +3.6V, f

= 10MHz, f = 555kSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, f

= 10MHz,

SCLK

S

SCLK

f

= 555kSPS, VREF = 2.5V; V = VREF, unless otherwise noted. Typical values are at T = +25°C. Boldface limits apply over the operating temperature

S

CM

A

range, -40°C to +85°C. (Continued)

ISL267452

TYP

MIN

(Note 7)

MAX

(Note 7) UNITS

SYMBOL

PARAMETER

TEST CONDITIONS

I

Input DC Leakage Current

Input Capacitance

-1

1

µA

pF

LEAK

C

Track/Hold mode

13/5

VIN

REFERENCE INPUT

VREF VREF Input Voltage Range

VDD = 3V (1% tolerance for specified

performance)

2.0

2.5

V

VDD = 5V (1% tolerance for specified

performance)

I

DC Leakage Current

-1

1

μA

LEAK

C

VREF Input Capacitance

Track/Hold mode

21/18.5

pF

VREF

LOGIC INPUTS

V

Input High Voltage

Input Low Voltage

Input Leakage Current

Input Capacitance

2.4

-1

V

IH

V

0.8

1

IL

I

µA

pF

LEAK

C

10

IN

LOGIC OUTPUTS

V

Output High Voltage

I

= 200µA

VDD - 0.3

-1

V

OH

SOURCE

= 200µA

SINK

V

Output Low Voltage

I

0.4

1

OL

I

Floating-State Output Current

Floating-State Output Capacitance

Output Coding

µA

pF

OZ

C

10

OUT

Two’s Complement

CONVERSION RATE

t

Conversion Time

Acquisition Time

Throughput Rate

f

= 10MHz

1.6

µs

ns

CONV

SCLK

t

200

555

ACQ

f

kSPS

max

POWER REQUIREMENTS

VDD Positive Supply Voltage Range

2.7

3.6

V

4.75

5.25

I

Positive Supply Input Current

DD

Static

1

µA

Dynamic

3V

5V

1250

1700

Power Dissipation

Static Mode

VDD = 3V

VDD = 5V

VDD = 3V, f

VDD = 5V, f

3

5

µW

Dynamic

= 555kSPS

3.75

8.5

mW

smpl

NOTES:

7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

8. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance.

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ISL267452

Timing Specifications Limits established by characterization and are not production tested. V = 3.0V to 3.6V, f

= 10MHz,

DD

SCLK

f

= 555kSPS, V

= 2.0V; V = 4.75V to 5.25V, f

= 10MHz, f = 555kSPS, V

REF

= 2.5V; V = V unless otherwise noted. Boldface limits apply

REF

DD

S

SCLK

S

CM

over the operating temperature range, -40°C to +85°C.

MIN

MAX

SYMBOL

PARAMETER

TEST CONDITIONS

(Note 7)

TYP

(Note 7)

UNITS

MHz

ns

f

t

Clock Frequency

Clock Period

0.01

100

10

SCLK

t

Acquisition Time

Conversion Time

CS Pulse Width

200

1.6

ns

ACQ

t

µs

CONV

t

10

ns

CSW

t

CS Falling Edge to S

CLK

Falling Edge Setup Time

ns

CSS

t

CS Falling Edge to SDATA Valid

SCLK Falling Edge to SDATA Valid

SCLK Falling Edge to SDATA Hold

SCLK Pulse Width

20

40

ns

CDV

t

ns

CLKDV

t

10

ns

SDH

t

0.4 x t

SCLK

ns

SW

DISABLE

t

SCLK Falling Edge to SDATA Disable Time

(Note 9)

Extrapolated back to true bus relinquish

10

35

ns

t

Quiet Time Before Sample

60

ns

QUIET

NOTE:

9. During characterization, t

is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the AD7452

DISABLE

loading (25pF) is calculated.

t_CSW

CS

t_CONV

t_CSS

SCLK

1

2

13

16

3

5

14

15

4

t_CLKDV

0

t_SW

MSB

t_ACQ

D0

t_CDV

t_QUIET

HI-Z

SDATA

D1

0

D2

FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM

VDD

R_L

2.85kΩ

OUTPUT

C_L

10pF

FIGURE 4. EQUIVALENT LOAD CIRCUIT

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ISL267452

Typical Performance Characteristics

75

70

65

60

55

0

5.25V

8192 POINT FFT

f

= 555kSPS

SAMPLE

= 92.5kHz

-20

IN

SINAD = 70.9dB

THD = 82.9dB

SFDR = 86.6dB

-40

4.75V

3.6V

2.7V

-60

-80

-100

-120

-140

-160

0

50

100

150

200

250 277.5

10

100

INPUT FREQUENCY (kHz)

1k

FREQUENCY (kHz)

FIGURE 5. ISL267452 SINAD vs ANALOG INPUT FREQUENCY FOR

VARIOUS SUPPLY VOLTAGES

FIGURE 6. ISL267452 DYNAMIC PERFORMANCE WITH VDD = 3V

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

8192 POINT FFT

f

= 555kSPS

SAMPLE

= 92.5kHz

-20

-40

IN

SINAD = 71.7dB

THD = 85dB

SFDR = 86.2dB

-60

-80

-100

-120

-140

-160

0

50

100

150

200

250 277.5

10k

100k

FREQUENCY (Hz)

1k

10k

FREQUENCY (kHz)

FIGURE 7. ISL267452 DYNAMIC PERFORMANCE WITH VDD = 5V

FIGURE 8. CMRR vs FREQUENCY FOR VDD = 5V

1.0

0.8

0

-20

250mV

SINE WAVE ON VDD

P-P

NO DECOUPLING ON VDD

0.6

0.4

-40

0.2

0.0

-60

-0.2

-0.4

-0.6

-0.8

-1.0

-80

-100

-120

0

1024

2048

3072

4096

0

100 200 300 400 500 600 700 800 900 1000

FREQUENCY (kHz)

CODE

FIGURE 9. TYPICAL DNL FOR THE ISL267452 FOR VDD = 5V

FIGURE 10. PSRR vs SUPPLY RIPPLE FREQUENCY WITHOUT SUPPLY

DECOUPLING

FN8255.0

July 26, 2012

8

ISL267452

Typical Performance Characteristics (Continued)

1.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

0.8

0.6

0.4

0.2

0.0

Pos DNL

-0.2

-0.4

-0.6

-0.8

-1.0

Neg DNL

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.5

3.5

0

1024

2048

3072

4096

CODE

VREF (V)

FIGURE 11. TYPICAL INL FOR THE ISL267452 FOR VDD = 5V

FIGURE 12. CHANGE IN DNL vs VREF FOR THE ISL267452 FOR

VDD = 5V

2.5

2.0

1.5

2.5

2.0

1.5

POS INL

1.0

0.5

POS DNL

NEG INL

0.0

-0.5

-1.0

-1.5

-2.0

0.5

0.0

-0.5

-1.0

NEG DNL

0.0

0.5

1.0

VREF (V)

1.5

2.0

2.5

0.0

0.5

1.0

VREF (V)

1.5

2.0

FIGURE 13. CHANGE IN INL vs VREF FOR THE ISL267452 FOR

VDD = 3V

FIGURE 14. CHANGE IN DNL vs VREF FOR THE ISL267452 FOR

VDD = 3V

5

4

3

6

5

4

3

2

POS INL

1

0

2

3V

-1

1

0

NEG INL

-2

-3

-4

-5

5V

-1

-2

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

VREF (V)

FIGURE 15. CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE

FOR VDD = 5V AND 3V FOR THE ISL267452

FIGURE 16. CHANGE IN INL vs VREF FOR THE ISL267452 FOR

VDD = 5V

FN8255.0

July 26, 2012

9

ISL267452

Typical Performance Characteristics (Continued)

12.0

11.5

11.0

10.5

10.0

9.5

70k

60k

50k

40k

30k

20k

10k

0

65,516

CODES

5V

3V

9.0

8.5

8.0

7.5

10

CODES

7.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2044

2045

2046

2047

2048

2049

2050

VREF (V)

CODE

FIGURE 17. CHANGE IN ENOB vs REFERENCE VOLTAGE FOR

VDD = 5V AND 3V FOR THE ISL267452

FIGURE 18. HISTOGRAM OF 10,000 CONVERSIONS OF A DC INPUT

FOR THE ISL267452 WITH VDD = 5V

An external clock must be applied to the SCLK pin to generate a

conversion result. The allowable frequency range for SCLK is

10kHz to 10MHz (555kSPS). Serial output data is transmitted on

the falling edge of SCLK. The receiving device (FPGA, DSP or

Microcontroller) may latch the data on the rising edge of SCLK to

maximize set-up and hold times.

Functional Description

The ISL267452 is based on a successive approximation register

(SAR) architecture utilizing capacitive charge redistribution

digital to analog converters (DACs). Figure 19 shows a simplified

representation of the converter. During the acquisition phase

(ACQ) the differential input is stored on the sampling capacitors

(CS). The comparator is in a balanced state since the switch

A stable, low-noise reference voltage must be applied to the

VREF pin to set the full-scale input range and common-mode

voltage. See “Voltage Reference Input” on page 11 for more

details.

across its inputs is closed. The signal is fully acquired after t

ACQ

has elapsed, and the switches then transition to the conversion

phase (CONV) so the stored voltage may be converted to digital

format. The comparator will become unbalanced when the

differential switch opens and the input switches transition

(assuming that the stored voltage is not exactly at mid-scale).

The comparator output reflects whether the stored voltage is

above or below mid-scale, which sets the value of the MSB. The

SAR logic then forces the capacitive DACs to adjust up or down by

one quarter of full-scale by switching in binarily weighted

capacitors. Again, the comparator output reflects whether the

stored voltage is above or below the new value, setting the value

of the next lowest bit. This process repeats until all 12 bits have

been resolved.

ADC Transfer Function

The output coding for the ISL267452 is twos complement. The

first code transition occurs at successive LSB values (i.e., 1 LSB,

2 LSB, and so on). The LSB size of the ISL267452 is

2*VREF/4096. The ideal transfer characteristic of the

ISL267452 is shown in Figure 20.

1LSB = 2•VREF/4096

011...111

011...110

000...001

000...000

111...111

CONV

C_S

VIN+

VIN–

ACQ

SAR

LOGIC

ACQ

C_S

CONV

100...010

100...001

100...000

CONV

VREF

–VREF

+ ½LSB

+VREF +VREF

– 1½LSB – 1LSB

0V

ANALOG INPUT

VIN+ – (VIN–)

FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM

FIGURE 20. IDEAL TRANSFER CHARACTERISTICS

FN8255.0

July 26, 2012

10

ISL267452

Note that there is a trade-off between VREF and the allowable

Analog Input

common mode input voltage (VCM). The full-scale input range is

proportional to VREF; therefore the VCM range must be limited

for larger values of VREF in order to keep the absolute maximum

and minimum voltages on the VIN+ and VIN– pins within

specification. Figures 23 and 24 illustrate this relationship for 5V

and 3V operation, respectively. The dashed lines show the

theoretical VCM range based solely on keeping the VIN+ and

VIN– pins within the supply rails. Additional restrictions are

imposed due to the required headroom of the input circuitry,

resulting in practical limits shown by the shaded area.

The ISL267452 features a fully differential input with a nominal

full-scale range equal to twice the applied VREF voltage. Each

input swings VREF V , 180° out-of-phase from one another for

P-P

a total differential input of 2*VREF (refer to Figure 21).

Differential signaling offers several benefits over a single-ended

input, such as:

• Doubling of the full-scale input range (and therefore the

dynamic range)

• Improved even order harmonic distortion

VCM

• Better noise immunity due to common mode rejection

5.0

4.25V

4.0

VREF_P-P

VIN+

VIN–

3.25V

3.0

ISL267452

2.0

V_CM

1.75V

1.0

FIGURE 21. DIFFERENTIAL INPUT SIGNALING

VREF

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Figure 22 shows the relationship between the reference voltage

and the full-scale input range for two different values of VREF.

FIGURE 23. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V

VCM

2.5

V

5.0

2.5

4.0

3.0

2.0

1.0

VIN–

VCM

VIN+

2.0

1.5

1.0

0.5

2.0V

1.0V

2.0V

P-P

t

VREF = 2V

VREF

V

0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

FIGURE 24. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V

5.0

4.0

3.0

2.0

1.0

VIN–

VCM

Voltage Reference Input

VIN+

2.5V

P-P

An external low-noise reference voltage must be applied to the VREF

pin to set the full-scale input range of the converter. The reference

input accepts voltages ranging from 0.1V to 2.2V for 3V operation

and 0.1V to 3.5V for 5V operation. The device is specified with a

reference voltage of 2.5V for 5V operation and 2.0V for 3V

operation.

t

VREF = 2.5V

Figures 26 and 27 illustrate possible voltage reference options for

the ISL267452. Figure 26 uses the precision ISL21090 voltage

reference, which exhibits exceptionally low drift and low noise. The

ISL21090 must use a power supply greater than 4.7V. The VREF

input pin of the ISL267452 uses very low current, so the decoupling

capacitor can be small (0.1µF).

FIGURE 22. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE

Figure 27 illustrates the ISL21010 voltage reference being used

with the ISL267452. The ISL21010 series voltage references have

higher noise and drift than the ISL26090 devices, but they consume

very low operating current and are excellent for battery-powered

applications.

FN8255.0

July 26, 2012

11

ISL267452

100

10

VDD = 5V

1

VDD = 3V

0.1

0.01

0

50

100

150

200

250

300

350

THROUGHPUT (kSPS)

FIGURE 25. POWER CONSUMPTION vs THROUGHPUT RATE

5V

BULK

+

0.1µF

DNC

1

8

7

6

5

VDD

ISL267452

V

2

3

4

IN

VREF

2.5V

COMP

GND

V

OUT

0.1µF

TRIM

ISL21090

FIGURE 26. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY

+3.0V TO +3.6V

OR +5V

+

BULK

0.1µF

V

1

2

0.1µF

IN

GND

3

VDD

ISL267452

VREF

V

OUT

1.25, 2.048 OR 2.5V

ISL21010

0.1µF

FIGURE 27. VOLTAGE REFERENCE FOR +3.0V TO +3.6V, OR FOR +5V SUPPLY

(12 bits) is completed on SCLK cycle 15. At this point in time, the

SAR comparator is powered down and the capacitor array is

placed back into Track mode. The last SAR comparator decision

is output from SDATA on the 16th SCLK cycle. When the last data

bit is output from SDATA, the output switches to a logic 0 until CS

is taken high, at which time, the SDATA output enters a High-Z

state.

Converter Operation

The ISL267452 is designed to minimize power consumption by

only powering up the SAR comparator during conversion time.

When the converter is in track mode (its sample capacitors are

tracking the input signal) the SAR comparator is powered down.

The state of the converter is dictated by the logic state of CS.

When CS is high, the SAR comparator is powered down while the

sampling capacitor array is tracking the input. When CS

transitions low, the capacitor array immediately captures the

analog signal that is being tracked. After CS is taken low, the

SCLK pin is toggled 16 times. For the first 3 clocks, the

Figure 28 on page 13 illustrates the system timing for the

ISL267452.

comparator is powered up and auto-zeroed, then the SAR

decision process is begun. This process uses 12 SCLK cycles.

Each SAR decision is presented to the SDATA output on the next

clock cycle after the SAR decision is performed. The SAR process

FN8255.0

July 26, 2012

12

ISL267452

FIGURE 28. ISL267452 SYSTEM TIMING

Power-On Reset

Application Hints

Grounding and Layout

When power is first applied, the ISL267452 performs a power-on

reset that requires approximately 2.5ms to execute. After this is

complete, a single dummy conversion must be executed (by

taking CS low) in order to initialize the switched capacitor track

and hold. The dummy conversion cycle will take 1.6µs with an

10MHz SCLK. Once the dummy cycle is complete, the ADC mode

will be determined by the state of CS. Regular conversions can be

started immediately after this dummy cycle is completed and

time has been allowed for proper acquisition.

The printed circuit board that houses the ISL267452 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes that can be easily separated. A minimum

etch technique is generally best for ground planes since it gives

the best shielding. Digital and analog ground planes should be

joined in only one place, and the connection should be a star

ground point established as close to the GND pin on the

ISL267452 as possible. Avoid running digital lines under the

device, as this will couple noise onto the die. The analog ground

plane should be allowed to run under the ISL267452 to avoid

noise coupling.

Acquisition Time

To achieve the maximum sample rate (555kSps) in the

ISL267452 device, the maximum acquisition time is 200ns. For

slower conversion rates, or for conversions performed using a

slower SCLK value than 10MHz, the minimum acquisition time is

200ns. This minimum acquisition time also applies to all the

devices if short cycling is utilized.

The power supply lines to the device should use as large a trace

as possible to provide low impedance paths and reduce the

effects of glitches on the power supply line.

Fast switching signals, such as clocks, should be shielded with

digital ground to avoid radiating noise to other sections of the

board, and clock signals should never run near the analog inputs.

Avoid crossover of digital and analog signals. Traces on opposite

sides of the board should run at right angles to each other. This

reduces the effects of feedthrough through the board. A

microstrip technique is by far the best but is not always possible

with a double-sided board.

Short Cycling

In cases where a lower resolution conversion is acceptable, CS

can be pulled high before all SCLK falling edges have elapsed.

This is referred to as short cycling, and it can be used to further

optimize power dissipation. In this mode, a lower resolution

result will be output, but the ADC will enter static mode sooner

and exhibit a lower average power consumption than if the

complete conversion cycle were carried out. The minimum

acquisition time (t

) requirement of 200ns must be met for

the next conversion to be valid.

In this technique, the component side of the board is dedicated

to ground planes, while signals are placed on the solder side.

ACQ

Good decoupling is also important. All analog supplies should be

decoupled with μF tantalum capacitors in parallel with 0.1μF

capacitors to GND. To achieve the best from these decoupling

components, they must be placed as close as possible to the

device.

FN8255.0

July 26, 2012

13

ISL267452

Aperture Jitter

Terminology

This is the sample-to-sample variation in the effective point in

time at which the actual sample is taken.

Signal-to-(Noise + Distortion) Ratio (SINAD)

This is the measured ratio of signal-to-(noise + distortion) at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals up

Full Power Bandwidth

The full power bandwidth of an ADC is that input frequency at

which the amplitude of the reconstructed fundamental is

reduced by 3dB for a full-scale input.

to half the sampling frequency (f /2), excluding DC. The ratio is

s

dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantization

noise. The theoretical signal-to-(noise + distortion) ratio for an

ideal N-bit converter with a sine wave input is given by

Equation 1:

Common-Mode Rejection Ratio (CMRR)

The common-mode rejection ratio is defined as the ratio of the

power in the ADC output at full-scale frequency, f, to the power of

(EQ. 1)

Signal-to-(Noise + Distortion) = (6.02 N + 1.76)dB

a 250mV

sine wave applied to the common-mode voltage of

P-P

VIN+ and VIN– of frequency fs:

Thus, for a 12-bit converter, this is 74dB.

CMRR(dB) = 10log(Pfl ⁄ Pfs)

(EQ. 3)

Total Harmonic Distortion

Pf is the power at the frequency f in the ADC output; Pfs is the

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the ISL267452, it is defined

as Equation 2:

power at frequency fs in the ADC output.

Integral Nonlinearity (INL)

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function.

2

V

+ V + V + V + V

2

3 4 5 6

THD(dB) = 20log -----------------------------------------------------------------------

(EQ. 2)

2

V

1

Differential Nonlinearity (DNL)

where V is the rms amplitude of the fundamental and V , V ,

V , V , and V are the rms amplitudes of the second to the sixth

1

2

3

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

4

5

6

harmonics.

Zero-Code Error

Peak Harmonic or Spurious Noise (SFDR)

This is the deviation of the midscale code transition (111...111 to

000...000) from the ideal VIN+ – VIN– (i.e., 0 LSB).

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to fS/2 and excluding DC) to the rms value of the

fundamental (also referred to as Spurious Free Dynamic Range

(SFDR)). Normally, the value of this specification is determined by

the largest harmonic in the spectrum, but for ADCs where the

harmonics are buried in the noise floor, it will be a noise peak.

Positive Gain Error

This is the deviation of the last code transition (011...110 to

011...111) from the ideal VIN+ – VIN– (i.e., +REF – 1 LSB), after

the zero code error has been adjusted out.

Negative Gain Error

Intermodulation Distortion

This is the deviation of the first code transition (100...000 to

100...001) from the ideal VIN+ – VIN– (i.e., – REF + 1 LSB), after

the zero code error has been adjusted out.

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa ± nfb where

m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those

for which neither m nor n are equal to zero. For example, the

second order terms include (fa + fb) and (fa – fb), while the third

order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).

Track and Hold Acquisition Time

The track and hold acquisition time is the minimum time

required for the track and hold amplifier to remain in track mode

for its output to reach and settle to within 0.5 LSB of the applied

input signal.

The ISL267452 is tested using the CCIF standard, where two

input frequencies near the top end of the input bandwidth are

used. In this case, the second order terms are usually distanced

in frequency from the original sine waves, while the third order

terms are usually at a frequency close to the input frequencies.

As a result, the second and third order terms are specified

separately. The calculation of the intermodulation distortion is as

per the THD specification, where it is the ratio of the rms sum of

the individual distortion products to the rms amplitude of the

sum of the fundamentals expressed in dBs.

Power Supply Rejection Ratio (PSRR)

The power supply rejection ratio is defined as the ratio of the

power in the ADC output at full-scale frequency, f, to ADC VDD

supply of frequency f . The frequency of this input varies from

S

1kHz to 1MHz.

PSRR(dB) = 10log(Pf ⁄ Pfs)

(EQ. 4)

Pf is the power at frequency f in the ADC output; Pfs is the power

at frequency f in the ADC output.

Aperture Delay

s

This is the amount of time from the leading edge of the sampling

clock until the ADC actually takes the sample.

FN8255.0

July 26, 2012

14

ISL267452

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you

have the latest revision.

DATE

REVISION

FN8255.0

CHANGE

July 26, 2012

Initial Release.

Products

Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products

address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.

Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a

complete list of Intersil product families.

For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

intersil.com: ISL267452

To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

FITs are available from our website at: http://rel.intersil.com/reports/search.php

For additional products, see www.intersil.com/product_tree

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

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For information regarding Intersil Corporation and its products, see www.intersil.com

FN8255.0

July 26, 2012

15

ISL267452

Small Outline Transistor Plastic Packages (SOT23-8)

P8.064

0.20 (0.008)

M

e

C

VIEW C

8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE

INCHES MILLIMETERS

MIN

C

L

b

8

SYMBOL

MAX

0.057

0.0059

0.051

0.015

0.013

0.009

0.008

0.118

0.067

MIN

0.90

0.00

0.90

0.22

0.08

2.80

2.60

1.50

MAX

1.45

0.15

1.30

0.38

0.33

0.22

0.20

3.00

1.70

NOTES

A

A1

A2

b

0.036

0.000

0.036

0.009

0.003

0.111

0.103

0.060

-

7

2

6

5

4

C

E1

L

C

E

L

1

3

b1

c

6

3

-

e1

D

c1

D

C

L

E

E1

e

3

-

0.0256 Ref

0.0768 Ref

0.014 0.022

0.65 Ref

1.95 Ref

0.55

SEATING

PLANE

A2

A1

A

e1

L

-

-C-

0.35

4

L1

L2

N

0.024 Ref.

0.010 Ref.

8

0.60 Ref.

0.25 Ref.

8

0.10 (0.004)

C

5

b

R

0.004

-

0.10

-

WITH

PLATING

b1

R1

α

0.004

0.010

0.25

o

0

8

0

8

-

c

c1

Rev. 2 9/03

NOTES:

BASE METAL

1. Dimensioning and tolerance per ASME Y14.5M-1994.

2. Package conforms to EIAJ SC-74 and JEDEC MO178BA.

4X θ1

3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate

burrs.

R1

4. Footlength L measured at reference to gauge plane.

5. “N” is the number of terminal positions.

R

6. These Dimensions apply to the flat section of the lead between 0.08mm

and 0.15mm from the lead tip.

GAUGE PLANE

SEATING

PLANE

7. Controlling dimension: MILLIMETER. Converted inch dimensions

are for reference only

L

C

α

L2

L1

4X θ1

VIEW C

FN8255.0

July 26, 2012

16


型号：	ISL267452IHZ-T
厂家：	Intersil
描述：	12-Bit, 555kSPS SAR ADC 12位， 555kSPS SAR ADC
文件：	总16页 (文件大小：716K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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