ISL267450IUZ [INTERSIL]
12-Bit, 1MSPS SAR ADCs; 12位， 1MSPS SAR型ADC
| 型号： | ISL267450IUZ |
| 厂家： | 
Intersil |
| 描述： | 12-Bit, 1MSPS SAR ADCs |
| 文件： | 总19页 (文件大小：747K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 1MSPS SAR ADCs
ISL267450
The ISL267450 is a 12-bit, 1MSPS sampling SAR-type ADC with
Features
• Drop-in Compatible with AD7450
a differential input span of 2*V
volts. The ISL267450 features
REF
• Differential Input
excellent linearity over supply and temperature variations and is
drop-in compatible with the AD7450. The device can operate
from a supply voltage of either 5V or 3V and maintain
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 1MHz Sampling Rate
measurement accuracy with input signals up to the supply rails.
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Power
dissipation is 9.0mW at a sampling rate of 1MSPS, and just 5µW
between conversions utilizing Auto Power-Down mode (with a 3V
supply).
• 3V or 5V Operation
• Low Operating Current
- 1.25mA at 833kSPS with 3V Supplies
- 1.7mA at 1MSPS with 5V Supplies
The ISL267450 is available in 8 Ld SOIC or MSOP packages, and
are specified for operation over the Industrial temperature range
(–40°C to +85°C).
• Power-down Current between Conversions: 1µA
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOIC and MSOP Packages
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
Block Diagram
+VDD
VREF
SCLK
V
IN+
SERIAL
INTERFACE
ADC
SDATA
VIN-
CS
GND
August 10, 2012
FN8341.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1
ISL267450
Typical Connection Diagram
0.1µF
+3V/5V
SUPPLY
VREF
+
0.1µF
10µF
VREF
VIN+
VIN–
VDD
SCLK
SDATA
CS
VREF(P-P)
VREF(P-P)
µP/µC
GND
SERIAL
INTERFACE
Pin Configuration
ISL267450
(8 LD SOIC, MSOP)
TOP VIEW
V
V
REF
1
2
3
4
8
7
6
5
DD
V
SCLK
IN+
V
SDATA
CS
IN-
GND
Pin Description
ISL267450
PIN NAME
PIN NUMBER
DESCRIPTION
V
8
7
6
5
4
3
2
1
Supply voltage, +2.7V to 5.25V.
DD
SCLK
SDATA
CS
Serial clock input. Controls digital I/O timing and clocks the conversion.
Digital conversion output.
Chip select input. Controls the start of a conversion when going low.
GND
Ground
V
V
Negative analog input.
Positive analog input.
Reference voltage.
IN–
IN+
REF
V
FN8341.0
August 10, 2012
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ISL267450
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(PB-free)
PKG.
DWG. #
PART MARKING
ISL267450IBZ
ISL267450IUZ
NOTES:
267450 IBZ
67450
2.7 to 5.25
2.7 to 5.25
-40 to +85
-40 to +85
8 Ld SOIC
8 Ld MSOP
M8.15
M8.118
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL267450. For more information on MSL please see techbrief TB363.
FN8341.0
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ISL267450
Table of Contents
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Typical Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
ADC Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Voltage Reference Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Converter Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Short Cycling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power vs Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Signal-to-(Noise + Distortion) Ratio (SINAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Peak Harmonic or Spurious Noise (SFDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Aperture Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Aperture Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Common-Mode Rejection Ratio (CMRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Integral Nonlinearity (INL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Differential Nonlinearity (DNL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Zero-Code Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Positive Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Negative Gain Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Track and Hold Acquisition Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Power Supply Rejection Ratio (PSRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FN8341.0
August 10, 2012
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ISL267450
Absolute Maximum Ratings
Thermal Information
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Thermal Resistance (Typical)
8 Ld SOIC Package (Notes 4, 5). . . . . . . . . .
8 Ld MSOP Package (Notes 4, 5). . . . . . . . .
θ
JA (°C/W)
120
θ
JC (°C/W)
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
64
64
DD
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
DD
165
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to V +0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
DD
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
5. For θ , the “case temp” location is taken at the package top center.
JC
Electrical Specifications
V
= +3.0V to +3.3V, F
= 15MHz, F = 833kSPS, V
REF
= 1.25V, F = 200kHz; V = +4.75V to
IN DD
DD
SCLK
S
+5.25V, F
SCLK
= 18MHz, F = 1MSPS, V
= 2.5V, F = 300kHz; V = V , T = T
to T
unless otherwise noted. Typical values are at
S
REF
IN CM REF
A
MIN
MAX
T
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C.
A
MIN
MAX
SYMBOL
DYNAMIC PERFORMANCE
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
SINAD
Signal-to (Noise + Distortion) Ratio
V
V
V
V
V
V
= 5V
= 3V
= 5V
= 3V
= 5V
= 3V
70
67
dB
dB
dB
dB
dB
dB
dB
dB
ns
DD
DD
DD
DD
DD
DD
THD
Total Harmonic
Distortion
-80
-78
-82
-80
–89
-85
10
-75
-73
-75
-73
SFDR
IMD
Spurious Free Dynamic Range
Intermodulation Distortion
2nd Order Terms
3rd Order Terms
tpd
Aperture Delay
Δtpd
β3dB
Aperture Jitter
50
ps
Full Power Bandwidth
@ –3dB
20
MHz
MHz
dB
@ –0.1dB
2.5
-87
PSRR
Power Supply Rejection Ratio
DC ACCURACY
N
INL
Resolution
12
-1
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
Zero-Code Error
1
0.95
3
DNL
Guaranteed no missed codes to 12 bits
-0.95
-3
OFFSET
V
V
V
V
V
V
= 5V
= 3V
= 5V
= 3V
= 5V
= 3V
DD
DD
DD
DD
DD
DD
-6
6
GAIN
Positive Gain Error
Negative Gain Error
-3
3
-6
6
-3
3
-6
6
FN8341.0
August 10, 2012
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ISL267450
Electrical Specifications
V
= +3.0V to +3.3V, F
= 15MHz, F = 833kSPS, V
REF
= 1.25V, F = 200kHz; V = +4.75V to
IN DD
DD
SCLK
S
+5.25V, F
SCLK
= 18MHz, F = 1MSPS, V
= 2.5V, F = 300kHz; V = V , T = T
to T
unless otherwise noted. Typical values are at
S
REF
IN CM REF
A
MIN
MAX
T
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
MAX
SYMBOL
ANALOG INPUT (Note 7)
|AIN| Full-Scale Input Span
, V
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
2 x V
REF
V
- V
V
V
V
IN+ IN–
V
Absolute Input Voltage Range
V
= V
IN–
CM REF
IN+
V
V
±
IN+
CM
V
/2
REF
VIN–
V
±
V
CM
V
/2
REF
I
Input Leakage Current
Input Capacitance
-1
1
µA
pF
pF
LEAK
C
Track Mode
Hold Mode
12
6
VIN
REFERENCE INPUT
V
V
Input Voltage Range
V
= 5V (±1% tolerance for specified
2.5
V
V
REF
REF
DD
performance)
V
= 3V (±1% tolerance for specified
1.25
DD
performance)
I
DC Leakage Current
Input Capacitance
-1
1
μA
LEAK
C
V
19
pF
VREF
REF
LOGIC INPUTS
V
Input High Voltage
Input Low Voltage
Input Leakage Current
Input Capacitance
2.4
-1
V
V
IH
V
0.8
1
IL
I
µA
pF
LEAK
C
10
IN
LOGIC OUTPUTS
V
Output High Voltage
I
= 200µA
V - 0.3
DD
V
V
OH
SOURCE
= 200µA
SINK
V
Output Low Voltage
I
0.4
1
OL
I
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
-1
µA
pF
LEAK
C
10
OUT
Two’s Complement
CONVERSION RATE
t
Conversion Time
888ns with F
SCLK
= 18MHz
= 15MHz
16
16
SCLK Cycles
SCLK Cycles
ns
CONV
1.07µs with F
SCLK
t
Acquisition Time (Note 8)
Throughput Rate
Sine Wave Input
200
1
ACQ
F
V
V
= 5V
= 3V
MSPS
max
DD
833
kSPS
DD
POWER REQUIREMENTS
V
Positive Supply Voltage Range
3.3V ± 10%
5V ± 5%
3.0
3.6
V
V
DD
4.75
5.25
FN8341.0
August 10, 2012
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ISL267450
Electrical Specifications
V
= +3.0V to +3.3V, F
= 15MHz, F = 833kSPS, V
REF
= 1.25V, F = 200kHz; V = +4.75V to
IN DD
DD
SCLK
S
+5.25V, F
SCLK
= 18MHz, F = 1MSPS, V
= 2.5V, F = 300kHz; V = V , T = T
to T
unless otherwise noted. Typical values are at
S
REF
IN CM REF
A
MIN
MAX
T
= +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
A
MIN
(Note 6)
MAX
(Note 6)
SYMBOL
PARAMETER
Positive Supply Input Current
Static
TEST CONDITIONS
TYP
UNITS
I
DD
V
V
V
= 3V/5V; SCLK ON or OFF
1
µA
mA
mA
DD
DD
DD
Dynamic
= 5V; f = 1MSPS
1.7
S
= 3V; f = 833kSPS
S
1.25
P
Power Dissipation
Static Mode
Dynamic
D
V
V
V
= 3V/5V; SCLK ON or OFF
5
µW
mW
mW
DD
DD
DD
= 5V; f = 1MSPS
8.5
S
= 3V; f = 833kSPS
3.75
S
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must not exceed V
.
DD
8. Read about “Acquisition Time” on page 14 for a discussion of this parameter.
Electrical Specifications Limits established by characterization and are not production tested. V = +4.75V to +5.25V,
DD
F
= 18MHz, F = 1MSPS, V
REF
= 2.5V, F = 300kHz; V = V , T = T
IN CM REF
to T
unless otherwise noted. Typical values are at T = +25°C.
SCLK
S
A
MIN
MAX
A
Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
SYMBOL
fSCLK
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
MHz
ns
Clock Frequency
Clock Period
0.05
55
18
t
SCLK
t
Conversion Time
16 x t
SCLK
888
ns
CONVERT
t
Quiet Time Before Sample
CS Falling Edge to S Falling Edge Setup Time
25
10
10
ns
QUIET
t
ns
CSS
CLK
t
CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish
Data Access Time after SCLK Falling Edge
SCLK High Pulsewidth
35
ns
DISABLE
t
0.4 x t
0.6 x t
ns
ns
ns
ns
ns
ns
ns
SWH
SCLK
SCLK
t
SCLK Low Pulsewidth
0.4 x t
0.6 x t
SWL
SCLK
SCLK
t
SCLK Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Hold
Acquisition Time (Note 8)
40
20
CLKDV
t
10
10
SDH
t
ACQ
t
CS Pulse Width
CSW
t
CS Falling Edge to SDATA Valid
CDV
Electrical Specifications Limits established by characterization and are not production tested. V = +3.0V to +3.3V, F
= 15MHz,
SCLK
DD
F
= 833kSPS, V
= 1.25V, F = 200kHz; V
IN REF
= 2.5V; V = V , T = T
CM REF
to T
unless otherwise noted. Typical values are at T = +25°C.
S
REF
A
MIN
MAX
A
Boldface limits apply over the operating temperature range, -40°C to +85°C.
MIN
MAX
SYMBOL
fSCLK
PARAMETER
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
MHz
ns
Clock Frequency
Clock Period
0.05
55
15
t
SCLK
t
Conversion Time
16 x t
SCLK
1.07
µs
CONVERT
FN8341.0
August 10, 2012
7
ISL267450
Electrical Specifications Limits established by characterization and are not production tested. V = +3.0V to +3.3V, F
= 15MHz,
SCLK
DD
F
= 833kSPS, V
= 1.25V, F = 200kHz; V
IN
= 2.5V; V = V , T = T
to T
unless otherwise noted. Typical values are at T = +25°C.
S
REF
REF
CM
REF
A
MIN
MAX
A
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN
MAX
SYMBOL
PARAMETER
Quiet Time Before Sample
CS Falling Edge to S Falling Edge Setup Time
TEST CONDITIONS
(Note 6)
TYP
(Note 6)
UNITS
ns
t
25
10
10
QUIET
t
ns
CSS
CLK
t
CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish
SCLK High Pulsewidth
35
µs
DISABLE
t
0.4 x t
0.6 x t
ns
SWH
SCLK
SCLK
t
SCLK Low Pulsewidth
0.4 x t
0.6 x t
ns
SWL
SCLK
SCLK
t
SCLK Falling Edge to SDATA Valid
SCLK Falling Edge to SDATA Hold
Acquisition Time (Note 8)
40
ns
CLKDV
t
10
10
ns
SDH
t
ns
ACQ
t
CS Pulse Width
ns
CSW
t
CS Falling Edge to SDATA Valid
20
ns
CDV
NOTE:
9. During characterization, t
is measured from the release point with a 10pF load (see Figure 2 on page 8) and the equivalent timing using the
DISABLE
AD7450 loading (50pF) is calculated.
FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM
VDD
RL
2.85k
OUTPUT
PIN
CL
10 pF
FIGURE 2. EQUIVALENT LOAD CIRCUIT
FN8341.0
August 10, 2012
8
ISL267450
Typical Performance Characteristics
0
0
-20
8192-POINT FFT
8192-POINT FFT
f
f
= 833kSPS
f
f
= 1MSPS
-20
SAMPLE
= 300kHz
SAMPLE
= 300kHz
IN
IN
SINAD = 69.83dB
THD = -82.02dB
SFDR = 82.93dB
SINAD = 71.55dB
THD = -80.88dB
SFDR = 84.08dB
-40
-40
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
100
200
300
400
500
0
100
200
300
400
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 4. DYNAMIC PERFORMANCE AT 833KSPS WITH V = 3V
DD
FIGURE 3. DYNAMIC PERFORMANCE AT 1MSPS WITH V = 5V
DD
1.0
0.8
74
72
70
68
0.6
0.4
0.2
2.7V
3.3V
0.0
66
64
62
60
4.75V
-0.2
-0.4
-0.6
-0.8
-1.0
5.25V
0
1024
2048
3072
4096
10
100
1k
TEST FREQUENCY (Hz)
CODE
FIGURE 5. SINAD vs ANALOG FREQUENCY FROM VARIOUS SUPPLY
VOLTAGES
FIGURE 6. TYPICAL DNL FOR V = 5V
DD
1.0
0.8
1.0
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
1024
2048
3072
4096
0
1024
2048
3072
4096
CODE
CODE
FIGURE 7. TYPICAL DNL FOR V = 3V
DD
FIGURE 8. TYPICAL INL FOR V = 5V
DD
FN8341.0
August 10, 2012
9
ISL267450
Typical Performance Characteristics (Continued)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
1.0
0.8
0.6
0.4
0.2
POS DNL
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
NEG DNL
2.0
0.0
0.5
1.0
1.5
V
2.5
3.0
3.5
0
1024
2048
3072
4096
CODE
(V)
REF
FIGURE 9. TYPICAL INL FOR V = 3V
DD
FIGURE 10. CHANGE IN DNL vs V
FOR V = 5V
DD
REF
3.0
2.0
2.0
1.5
1.0
1.0
POS INL
POS DNL
NEG DNL
0.5
0.0
0.0
NEG INL
-1.0
-2.0
-3.0
-0.5
-1.0
-1.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
(V)
V
REF
REF
FIGURE 11. CHANGE IN DNL vs V
FOR V = 3.3V
DD
FIGURE 12. CHANGE IN INL vs V
FOR V = 5V
DD
REF
REF
1.0
0.0
2.5
3.3V VDD
2.0
1.5
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
-9.0
1.0
POS INL
5V VDD
0.5
0.0
-0.5
-1.0
-1.5
-2.0
NEG INL
0.0
0.5
1.0
1.5
V
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
V
(V)
(V)
REF
REF
FIGURE 13. CHANGE IN INL vs V
FOR V = 3.3V
DD
FIGURE 14. CHANGE IN OFFSET ERROR vs V
FOR V = 5V
REF DD
REF
AND 3.3V
FN8341.0
August 10, 2012
10
ISL267450
Typical Performance Characteristics (Continued)
70000
60000
50000
40000
30000
20000
10000
0
70000
60000
50000
40000
30000
20000
10000
0
2044
2045
2046
2047
2048
2049
2050
2044
2045
2046
2047
2048
2049
2050
OUTPUT CODE
OUTPUT CODE
FIGURE 15. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT
FIGURE 16. HISTOGRAM OF THE OUTPUT CODES WITH A DC INPUT
FOR V = 3V
FOR V = 5V
DD
DD
-40
-50
12.0
11.5
11.0
10.5
10.0
9.5
-60
5V VDD
-70
3.3V VDD
-80
9.0
8.5
-90
8.0
-100
-110
7.5
7.0
0.0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
10
100
1k
10k
FREQUENCY (kHz)
V
REF
FIGURE 18. CMRR vs INPUT FREQUENCY FOR V = 5V AND 3V
DD
FIGURE 17. CHANGE IN ENOB vs V
FOR V = 5V AND 3.3V
DD
REF
Functional Description
The ISL267450 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital-to-analog converters (DACs). Figure 19 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
CONV
CS
VIN+
VIN-
ACQ
ACQ
SAR
LOGIC
ACQ CONV
CS
CONV
VREF
across its inputs is closed. The signal is fully acquired after t
ACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
FIGURE 19. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
FN8341.0
August 10, 2012
11
ISL267450
An external clock must be applied to the SCLK pin to generate a
V
conversion result. The allowable frequency range for SCLK is
50kHz to 18MHz. Serial output data is transmitted on the falling
edge of SCLK. The receiving device (FPGA, DSP or
Microcontroller) may latch the data on the rising edge of SCLK to
maximize set-up and hold times.
5.0
4.0
3.0
2.0
1.0
V
IN-
A stable, low-noise reference voltage must be applied to the V
REF
V
IN+
pin to set the full-scale input range and common-mode voltage.
See “Voltage Reference Input” on page 13 for more details.
2.0V
P-P
VCM
ADC Transfer Function
The output coding for the ISL267450 is two’s complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size of the ISL267450 is
2*V
/4096. The ideal transfer characteristic of the ISL267450
t
REF
is shown in Figure 20.
VREF = 2V
1LSB = 2•VREF/4096
V
011...111
011...110
5.0
4.0
3.0
2.0
1.0
V
IN-
000...001
000...000
111...111
V
IN+
2.5V
P-P
VCM
100...010
100...001
100...000
–VREF
+VREF +VREF
– 1½LSB – 1LSB
0V
ANALOG INPUT
+ ½LSB
V
IN+ – (VIN–)
t
FIGURE 20. IDEAL TRANSFER CHARACTERISTICS
VREF = 2.5V
Analog Input
The ISL267450 features a fully differential input with a nominal
full-scale range equal to twice the applied V voltage. Each
FIGURE 22. RELATIONSHIP BETWEEN V AND FULL-SCALE RANGE
REF
REF
, 180° out-of-phase from one another for
Figure 22 shows the relationship between the reference voltage
input swings V
V
REF P-P
a total differential input of 2*V
and the full-scale input range for two different values of V
.
REF
and the allowable
(see Figure 21).
REF
Note that there is a trade-off between V
REF
common mode input voltage (VCM). The full-scale input range is
proportional to V ; therefore the VCM range must be limited for
REF
VREF(P-P)
VIN+
larger values of V
in order to keep the absolute maximum and
and V pins within specification.
REF
minimum voltages on the V
ISL267450
IN+
IN–
Figures 23 and 24 illustrate this relationship for 5V and 3V
operation, respectively. The dashed lines show the theoretical
VCM
VIN-
VREF(P-P)
VCM range based solely on keeping the V
and V pins within
IN+
IN–
the supply rails. Additional restrictions are imposed due to the
required headroom of the input circuitry, resulting in practical
limits shown by the shaded area.
FIGURE 21. DIFFERENTIAL INPUT SIGNALING
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
FN8341.0
August 10, 2012
12
ISL267450
Voltage Reference Input
VCM
The voltage magnitude applied to the V
pin defines the full
REF
5.0
4.0
3.0
2.0
1.0
scale span of the ADC as 2* V . The device is specified with a
REF
voltage reference of 2.5V for 5V operation and with a voltage
reference of 2.0V for 3V operation. But, V
voltages ranging from 0.1V to 3.5V for operation from 5 V V
and voltages ranging from 0.1V to 2.2V for operation from a 3V
input accepts
REF
DD
V
.
DD
Figures 25 and 26 illustrate possible voltage reference options
for the ISL267450. Figure 25 uses the ISL21090 precision
voltage reference, which exhibits exceptionally low drift and low
noise. The ISL21090 must use a power supply greater than 4.7V.
VREF
0.5
1.0
1.5
2.0
2.5
3.0
3.5
FIGURE 23. RELATIONSHIP BETWEEN V
AND VCM FOR V = 5V
DD
REF
The V
input pin on the ISL267450 uses very low current, so
REF
the decoupling capacitor can be small (0.1µF).
VCM
Figure 26 illustrates the ISL21010 voltage reference. The
ISL21010 is available in various output voltages. It has higher
noise and drift than the ISL26090, but consumes very low
operating current, which makes it an excellent choice for
battery-powered applications.
3.0
2.5
2.0
1.5
1.0
0.5
VREF
0.5
1.0
1.5
2.0
2.5
FIGURE 24. RELATIONSHIP BETWEEN VREF AND VCM FOR V = 3V
DD
5V
BULK
+
0.1µF
DNC
VIN
DNC
DNC
1
8
7
6
5
V
DD
ISL267450
2
3
4
V
REF
2.5V
COMP VOUT
GND TRIM
0.1µF
0.1µF
ISL21090
FIGURE 25. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+3.0V TO +3.3V
OR +5V
+
BULK
0.1µF
VIN
1
2
0.1µF
GND
3
VDD
ISL267450
VREF
VOUT
1.25, 2.048 OR 2.5V
ISL21010
0.1µF
FIGURE 26. VOLTAGE REFERENCE FOR +3.0V TO +3.3V, OR FOR +5V SUPPLY
FN8341.0
August 10, 2012
13
ISL267450
FIGURE 27. NORMAL MODE OPERATION
SCLK value than 18MHz, the minimum acquisition time is 200ns.
CONVERTER OPERATION
This minimum acquisition time also applies to the device when
operated at 3V supply or if short cycling is utilized.
The ISL267450 is designed to minimize power consumption by
only powering up the SAR comparator during conversion time.
When the converter is in track mode (its sample capacitors are
tracking the input signal), the SAR comparator is powered down.
The state of the converter is dictated by the logic state of CS.
When CS is high, the SAR comparator is powered down while the
sampling capacitor array is tracking the input. When CS
transitions low, the capacitor array immediately captures the
analog signal that is being tracked. After CS is taken low, the
SCLK pin is toggled 16 times. For the first 3 clocks, the
comparator is powered up and auto-zeroed, then the SAR
decision process is begun. This process uses 12 SCLK cycles.
Each SAR decision is presented to the SDATA output on the next
clock cycle after the SAR decision is performed. The SAR process
(12 bits) is completed on SCLK cycle 15. At this point in time, the
SAR comparator is powered down and the capacitor array is
placed back into Track mode. The last SAR comparator decision
is output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA, the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
SHORT CYCLING
In cases where a lower resolution conversion is acceptable, CS
can be pulled high before all 12 bits are clocked out. This is
referred to as short cycling, and it can be used to further optimize
power dissipation. In this mode, a lower resolution result will be
output, but the ADC will enter static mode sooner and exhibit a
lower average power consumption than if the complete
conversion cycle were carried out. The minimum acquisition time
(tACQ) requirement of 200ns must be met for the next
conversion to be valid.
POWER vs THROUGHPUT RATE
The ISL267450 provides reduced power consumption at lower
conversion rates by automatically switching into a low-power
mode after completing a conversion. The average power
consumption of the ADC decreases at lower throughput rates.
Figure 28 shows the typical power consumption over a wide
range of throughput rates.
100
Figure 27 illustrates the serial port system timing for the
ISL267450.
POWER-ON RESET
10
When power is first applied, the ISL267450 performs a power-on
reset that requires approximately 2.5ms to execute. After this is
complete, a single dummy conversion must be executed (by
taking CS low) in order to initialize the switched capacitor track
and hold. The dummy conversion cycle will take 889ns with an
18MHz SCLK. Once the dummy cycle is complete, the ADC mode
will be determined by the state of CS. Regular conversions can be
started immediately after this dummy cycle is completed and
time has been allowed for proper acquisition.
V
= 5V
DD
1
0.1
V
= 3V
150
DD
0.01
0
50
100
200
250
300
350
ACQUISITION TIME
THROUGHPUT (kSPS)
To achieve the maximum sample rate (1MSps) in the ISL267450
device, the maximum acquisition time is 200ns. For slower
conversion rates, or for conversions performed using a slower
FIGURE 28. POWER CONSUMPTION vs THROUGHPUT RATE
FN8341.0
August 10, 2012
14
ISL267450
microstrip technique is by far the best but is not always possible
with a double-sided board.
Serial Interface
Conversion data is accessed with an SPI-compatible serial
interface. The interface consists of the serial clock (SCLK), serial
data output (SDATA), and chip select (CS).
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the
device.
A falling edge on the CS signal initiates a conversion by placing
the part into the acquisition (ACQ) phase. After t
has elapsed,
ACQ
the part enters the conversion (CONV) phase and begins
outputting the conversion result starting with a null bit followed
by the most significant bit (MSB) and ending with the least
significant bit (LSB). The CS pin can be pulled high at this point to
put the device into Standby mode and reduce the power
consumption. If CS is held low after the LSB bit has been output,
the conversion result will be repeated in reverse order until the
MSB is transmitted, after which the serial output enters a high
impedance state. The ISL267450 will remain in this state,
dissipating typical dynamic power levels, until CS transitions high
then low to initiate the next conversion.
Terminology
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (f /2), excluding DC. The ratio is
s
dependent on the number of quantization levels in the
digitization process; the more levels, the smaller the quantization
noise. The theoretical signal-to-(noise + distortion) ratio for an
ideal N-bit converter with a sine wave input is given by
Equation 1:
Data Format
Output data is encoded in two’s complement format as shown in
Table 1. The voltage levels in the table are idealized and don’t
account for any gain/offset errors or noise.
(EQ. 1)
Signal-to-(Noise + Distortion) = (6.02 N + 1.76)dB
TABLE 1. TWO’S COMPLEMENT DATA FORMATTING
INPUT
–Full Scale
VOLTAGE
DIGITAL OUTPUT
1000 0000 0000
1000 0000 0001
0000 0000 0000
0111 1111 1110
0111 1111 1111
Thus, for a 12-bit converter this is 74dB, and for a 10-bit it is
62dB.
–V
REF
–Full Scale + 1LSB
Midscale
–V
+V
+ 1LSB
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the ISL267450, it is defined
as Equation 2:
REF
0
+Full Scale – 1LSB
+Full Scale
– 1LSB
REF
REF
+V
2
2
2
2
2
V
+ V + V + V + V
2
3 4 5 6
THD(dB) = 20log -----------------------------------------------------------------------
(EQ. 2)
2
V
Application Hints
Grounding and Layout
1
where V is the rms amplitude of the fundamental and V , V ,
1
2
3
V , V , and V are the rms amplitudes of the second to the sixth
4
5
6
The printed circuit board that houses the ISL267450 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes since it gives
the best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the
ISL267450 as possible. Avoid running digital lines under the
device, as this will couple noise onto the die. The analog ground
plane should be allowed to run under the ISL267450 to avoid
noise coupling.
harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding DC) to the rms value of the
fundamental. It is also referred to as Spurious Free Dynamic
Range (SFDR). Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it will be
a noise peak.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m and n = 0, 1, 2 or 3. Intermodulation distortion terms are those
for which neither m nor n are equal to zero. For example, the
second order terms include (fa + fb) and (fa – fb), while the third
order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed-through through the board. A
FN8341.0
August 10, 2012
15
ISL267450
The ISL267450 is tested using the CCIF standard, where two
Differential Nonlinearity (DNL)
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is as
per the THD specification, where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal V
– V
(i.e., 0 LSB).
IN+
IN–
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal V – V (i.e., +V – 1 LSB), after
the zero code error has been adjusted out.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
IN+
IN–
REF
Negative Gain Error
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
This is the deviation of the first code transition (100...000 to
100...001) from the ideal V – VIN– (i.e., -V + 1 LSB), after
IN+
the zero code error has been adjusted out.
REF
Track and Hold Acquisition Time
Full Power Bandwidth
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1dB or 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC V
supply of frequency f . The frequency of this input varies from
S
a 200mV
sine wave applied to the common-mode voltage of
of frequency fs as shown by Equation 3.:
IN–
DD
P-P
and V
V
IN+
1kHz to 1MHz.
CMRR(dB) = 10log(Pfl ⁄ Pfs)
(EQ. 3)
PSRR(dB) = 10log(Pf ⁄ Pfs)
(EQ. 4)
Pf is the power at the frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency f in the ADC output.
s
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
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in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FN8341.0
August 10, 2012
16
ISL267450
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE
REVISION
FN8341.0
CHANGE
August 10, 2012
Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL267450
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FN8341.0
August 10, 2012
17
ISL267450
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN8341.0
August 10, 2012
18
ISL267450
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN8341.0
August 10, 2012
19
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