HC55151CM [RENESAS]
TELECOM-SLIC, PQCC32, PLASTIC, MS-016AE, LCC-32;
| 型号： | HC55151CM |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | TELECOM-SLIC, PQCC32, PLASTIC, MS-016AE, LCC-32 电池 电信 电信集成电路 |
| 文件： | 总36页 (文件大小：556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC55120, HC55121, HC55130, HC55131, HC55140,
HC55141, HC55142, HC55143, HC55150, HC55151
®
Data Sheet
June 2002
FN4659.10
Low Power UniSLIC14 Family
Features
The UniSLIC14 is a family of Ultra Low Power SLICs. The
feature set and common pinouts of the UniSLIC14 family
positions it as a universal solution for: Plain Old Telephone
Service (POTS), PBX, Central Office, Loop Carrier, Fiber in
the Loop, ISDN-TA and NT1+, Pairgain and Wireless Local
Loop.
• Ultra Low Active Power (OHT) < 60mW
• Single/Dual Battery Operation
• Automatic Silent Battery Selection
• Power Management/Shutdown
• Battery Tracking Anti Clipping
• Single 5V Supply with 3V Compatible Logic
The UniSLIC14 family achieves its ultra low power operation
through: Its automatic single and dual battery selection (based
on line length) and battery tracking anti clipping to ensure the
maximum loop coverage on the lowest battery voltage. This
architecture is ideal for power critical applications such as
ISDN NT1+, Pairgain and Wireless local loop products.
• Zero Crossing Ring Control
- Zero Voltage On/Zero Current Off
• Tip/Ring Disconnect
• Pulse Metering Capability
• 4 Wire Loopback
• Programmable Current Feed
• Programmable Resistive Feed
• Programmable Loop Detect Threshold
The UniSLIC14 family has many user programmable features.
This family of SLICs delivers a low noise, low component
count solution for Central Office and Loop Carrier universal
voice grade designs. The product family integrates advanced
pulse metering, test and signaling capabilities, and zero
crossing ring control.
• Programmable On-Hook and Off-Hook Overheads
• Programmable Overhead for Pulse Metering
• Programmable Polarity Reversal Time
• Selectable Transmit Gain 0dB/-6dB
• 2 Wire Impedance Set by Single Network
• Loop and Ground Key Detectors
• On-Hook Transmission
The UniSLIC14 family is designed in the Intersil “Latch” free
Bonded Wafer process. This process dielectrically isolates the
active circuitry to eliminate any leakage paths as found in our
competition’s JI process. This makes the UniSLIC14 family
compliant with “hot plug” requirements and operation in harsh
outdoor environments.
• Common Pinout
• HC55121
- Polarity Reversal
Block Diagram
• HC55130
- -63dB Longitudinal Balance
RRLY
STATE
DECODER
AND
C1
RING AND TEST
RELAY DRIVERS
• HC55140
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2 Wire Loopback
- -63dB Longitudinal Balance
C2
C3
TRLY1
TRLY2
DETECTOR
C4
C5
LOGIC
ZERO CURRENT
CROSSING
RING TRIP
DETECTOR
DT
LOOP CURRENT
DETECTOR
SHD
DR
GKD/LOOP LENGTH
DETECTOR
GKD_LVM
• HC55142
- Polarity Reversal
- Ground Start
CRT_REV_LVM
POLARITY
REVERSAL
- Line Voltage Measurement
ILIM
RSYNC_REV
ROH
CDC
RDC_RAC
RD
- 2.2V
Pulse Metering
RMS
LINE FEED
CONTROL
TIP
- 2 Wire Loopback
2-WIRE
• HC55150
- Polarity Reversal
- Line Voltage Measurement
RING
INTERFACE
BGND
AGND
- 2.2V
- 2 Wire Loopback
Pulse Metering
V
RMS
TX
4-WIRE INTERFACE
VF SIGNAL PATH
V
RX
PTG
V
BATTERY
SELECTION
AND
BIAS
NETWORK
BH
ZT
Related Literature
• AN9871, User’s Guide for UniSLIC14 Eval Board
C
H
V
BL
PULSE METERING
SIGNAL PATH
V
CC
• AN9903, UniSLIC14 and TI TCM38C17
SPM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Ordering Information
LINE
VOLTAGE
MEASUREMENT
2 WIRE
LOOP-
BACK
†
MAX
LOOP
CURRENT POLARITY
(mA)
2 TEST
RELAY
METERING DRIVERS
TEMP
PART
NUMBER
GND
GND
PULSE
LONGITUDINAL RANGE
PKG.
NO.
o
†
REVERSAL START KEY
BALANCE
( C)
HC55120CB
HC55120CM
HC55121IB
HC55121IM
HC55130IB
HC55130IM
HC55131IM
HC55140IB
HC55140IM
HC55141IM
HC55142IB
HC55142IM
HC55143IM
HC55150CB
HC55150CM
HC55151CM
30
53dB
0 to 70 M28.3
SOIC
•
30
30
30
45
45
45
45
45
45
45
45
45
45
45
45
53dB
53dB
53dB
63dB
63dB
63dB
63dB
63dB
63dB
63dB
63dB
63dB
55dB
55dB
55dB
0 to 70 N28.45
PLCC
•
-40 to M28.3
•
•
•
•
•
•
•
•
85
-40 to N28.45
85 PLCC
-40 to M28.3
85 SOIC
-40 to N28.45
85 PLCC
-40 to N32.45x55
85 PLCC
-40 to M28.3
85 SOIC
-40 to N28.45
85 PLCC
-40 to N32.45x55
85 PLCC
-40 to M28.3
85 SOIC
-40 to N28.45
85 PLCC
-40 to N32.45x55
85 PLCC
SOIC
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0 to 70 M28.3
SOIC
0 to 70 N28.45
PLCC
0 to 70 N32.45x55
PLCC
HC5514XEVAL1 Evaluation board
† Available by placing SLIC in Test mode.
Device Operating Modes
C3
C2
C1
DESCRIPTION
HC55120
HC55121
HC55130/1
HC55140/1
HC55142/3
HC55150/1
0
0
0
Open Circuit
•
•
•
•
•
•
4-Wire Loopback
Ringing
0
0
0
0
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Forward Active
Test Forward Active
2 Wire Loopback and
Line Voltage Measurement
1
1
1
1
0
0
1
1
0
1
0
1
Tip Open Ground Start
•
•
•
•
•
•
•
•
Reserved
•
•
•
•
•
•
•
Reverse Active
Test Reverse Active
Line Voltage Measurement
2
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
Temperature, Humidity
Storage Temperature Range . . . . . . . . . . . . . . . . -65 C to 150 C
Operating Temperature Range . . . . . . . . . . . . . . -40 C to 110 C
Thermal Resistance (Typical, Note 1)
θ
JA
o
o
o
o
o
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . .
28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . .
32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . .
52 C/W
o
45 C/W
o
o
o
Operating Junction Temperature Range . . . . . . . -40 C to 150 C
66.2 C/W
o
o
o
Power Supply (-40 C ≤ T ≤ 85 C)
A
Continuous Power Dissipation at 85 C
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . . .-0.4V to 7V
CC
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0W
32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.4W
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . . . . . 300 C
(PLCC, SOIC - Lead Tips Only)
Supply Voltage V to GND. . . . . . . . . . . . . . . . . . . .-V
to 0.4V
BL BH
BH
BH
Supply Voltage V
Supply Voltage V
Relay Driver
to GND, Continuous . . . . . . . . . -75V to 0.4V
to GND, 10ms . . . . . . . . . . . . . . -80V to 0.4V
o
o
Derate above 70 C
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 14V
Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_LVM)
Tip and Ring Terminals
Tipx or Ringx, Current, Pulse < 10ms, T
> 10s . . . . . . . . . .2A
> 10s . . . . . . . . . . .5A
> 10s . . . . . . . . .15A
REP
> 10s . . . . . . . . . .20A
> 10s 20A
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to V
Output Voltage (SHD, GKD_LVM Not Active) . . . . . -0.4V to V
REP
CC
Tipx or Ringx, Current, Pulse < 1ms, T
REP
Tipx or Ringx, Current, Pulse < 10µs, T
CC
Output Current (SHD, GKD_LVM) . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Gate Count. . . . . . . . . . . . . . . . . . . . . . . 543 Transistors, 51 Diodes
Tipx or Ringx, Current, Pulse < 1µs, T
Tipx or Ringx, Pulse < 250ns, T
REP
REP
o
o
Tipx and Ringx Terminals (-40 C ≤ T ≤ 85 C)
A
Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . -100mA to 100mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Typical Operating Conditions
These represent the conditions under which the device was developed and are suggested as guidelines.
PARAMETER
Ambient Temperature
CONDITIONS
HC55120, HC55150/1
MIN
0
TYP
MAX
70
UNITS
o
-
-
C
o
HC55121, HC55130/1, HC55140/1,
HC55142/3
-40
85
C
V
V
V
with Respect to GND
-58
-
-
-
-8
0
V
V
V
BH
BL
with Respect to GND
with Respect to GND
V
BH
4.75
5.25
CC
3
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
2-WIRE PORT
Overload Level, Off Hook
Forward and Reverse
1% THD, I
DCMET
(Note 2, Figure 1)
≥ 18mA
3.2
1.3
-
-
-
-
V
Forward
Only
Forward
Only
PEAK
•
•
•
•
Overload Level, On Hook
Forward and Reverse
1% THD, IDCMET ≤ 5mA
(Note 3, Figure 1)
V
Forward
Only
Forward
Only
PEAK
•
•
•
•
•
•
•
•
•
•
•
•
Input Impedance (Into Tip and Ring)
-
-
Z /200
T
-
-
Ω
•
•
Longitudinal Impedance (Tip, Ring) 0 < f < 100Hz (Note 4, Figure 2)
Forward and Reverse
0
Ω/Wire
Forward
Only
Forward
Only
LONGITUDINAL CURRENT LIMIT (TIP, RING)
On-Hook, Off-Hook (Active),
= 736Ω
No False Detections, (Loop
Current), LB > 45dB (Notes 5, 6,
Figures 3A, 3B)
28
-
-
mA
Wire Forward
Only
Forward
Only
/
RMS
R
•
•
•
•
L
Forward and Reverse
A
TIP
V
TX
T
1V
RMS
V
TX
TIP
0 < f < 100Hz
V
T
300Ω
300Ω
E
L
C
V
TR
R
L
I
DCMET
V
R
E
RX
RING
A
VRX
R
RING
VRX
LZ = V /A
LZ = V /A
R R
T
T
T
R
FIGURE 1. OVERLOAD LEVEL (OFF HOOK, ON HOOK)
FIGURE 2. LONGITUDINAL IMPEDANCE
368Ω
368Ω
V
TIP
TIP
V
TX
TX
A
A
A
A
V
TX
10µF
10µF
C
C
E
E
L
L
C
RING
RING
VRX
VRX
368Ω
368Ω
SHD
SHD
FIGURE 3A. LONGITUDINAL CURRENT LIMIT ON-HOOK (ACTIVE)
FIGURE 3B. LONGITUDINAL CURRENT LIMIT OFF-HOOK (ACTIVE)
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
OFF-HOOK LONGITUDINAL BALANCE
MIN
MIN
MIN
MIN
MIN
MIN
Longitudinal to Metallic (Note 7)
Forward and Reverse
IEEE 455 - 1985, R , R = 368Ω
Normal Polarity:
Forward
Only
Forward
Only
LR LT
o
o
0.2kHz < f < 1.0kHz, 0 C to 70 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
53
53
NA
NA
53
53
53
NA
NA
63
NA
NA
63
NA
NA
63
58
58
55
55
o
o
1.0kHz < f < 3.4kHz, 0 C to 70 C
o
o
0.2kHz < f < 1.0kHz, -40 C to 85 C
NA
NA
NA
NA
NA
55
o
o
1.0kHz < f < 3.4kHz, -40 C to 85 C
58
58
Reverse Polarity 0.2kHz < f < 3.4kHz,
(Figure 4)
NA
58
MIN
MIN
MIN
MIN
MIN
MIN
Longitudinal to Metallic (Note 7)
Forward and Reverse
R
, R = 300Ω,
LR LT
Forward
Only
Forward
Only
Normal Polarity:
o
o
0.2kHz < f < 1.0kHz, 0 C to 70 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
53
53
NA
NA
53
53
53
NA
NA
63
NA
NA
63
NA
NA
63
58
58
55
55
o
o
1.0kHz < f < 3.4kHz, 0 C to 70 C
o
o
0.2kHz < f < 1.0kHz, -40 C to 85 C
NA
NA
NA
NA
NA
55
o
o
1.0kHz < f < 3.4kHz, -40 C to 85 C
58
58
Reverse Polarity 0.2kHz < f < 3.4kHz,
(Figure 4)
NA
58
MIN
MIN
MIN
MIN
MIN
MIN
Longitudinal to 4-Wire (Note 9)
(Forward and Reverse)
Normal Polarity:
Forward
Only
Forward
Only
o
o
0.2kHz < f < 1.0kHz, 0 C to 70 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
53
53
NA
NA
53
53
53
NA
NA
63
NA
NA
63
NA
NA
63
58
58
61
61
o
o
1.0kHz < f < 3.4kHz, 0 C to 70 C
o
o
0.2kHz < f < 1.0kHz, -40 C to 85 C
NA
NA
NA
NA
NA
61
o
o
1.0kHz < f < 3.4kHz, -40 C to 85 C
58
58
Reverse Polarity 0.2kHz < f < 3.4kHz,
(Figure 4)
NA
58
Metallic to Longitudinal (Note 10)
Forward and Reverse
FCC Part 68, Para 68.310 (Note 8)
0.2kHz < f < 3.4kHz, (Figure 5)
40
40
50
-
-
-
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
4-Wire to Longitudinal (Note 11)
Forward and Reverse
0.2kHz < f < 3.4kHz, (Figure 5)
Forward
Only
Forward
Only
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS MIN TYP MAX UNITS HC55120 HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
R
LT
R
LT
V
TIP
TX
TIP
V
TX
300Ω
V
TX
E
L
2.16µF
E
C
TR
V
TR
E
RX
C
L
2.16µF
V
R
VRX
LR
VRX
RING
RING
R
300Ω
LR
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL
BALANCE
FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BALANCE
2-Wire Return Loss
Forward and Reverse
0.2kHz to 1.0kHz (Note 12, Figure 6)
1.0kHz to 3kHz (Note 12, Figure 6)
3kHz to 3.4kHz (Note 12, Figure 6)
30
23
21
35
25
23
-
-
-
dB
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
TIP IDLE VOLTAGE (User Programmable)
TIPX Idle Voltage
Active, I < 5mA
-2.6
-2.2
-1.8
V
Forward
Only
Forward
Only
L
•
•
Forward and Reverse
RING IDLE VOLTAGE (User Programmable)
RINGX Idle Voltage
Forward and Reverse
Active, I < 5mA
-46.4
-46.4
41
-45.3
-45.3
43.1
-44.2
-44.2
45
V
V
V
Forward
Only
Forward
Only
L
•
•
•
•
•
•
•
•
•
Tip open, I < 5mA
L
V
Active, I < 5mA
Forward
Only
Forward
Only
TR
Forward and Reverse
L
•
V
Pulse Metering
Active, I ≥ 8.5mA, R = 50kΩ
OH
36
38.1
-
V
NA
NA
NA
TR(ROH)
Forward and Reverse
L
Z
D
TIP
V
TX
TIP
V
TX
V
V
TX
TR
R
R
V
M
Z
L
E
G
R
600Ω
L
V
S
Z
IN
VRX
VRX
RING
RING
R
LR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET
VOLTAGE AND HARMONIC DISTORTION
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
4-WIRE TRANSMIT PORT (V
)
TX
Overload Level, Off Hook (I ≥ 18mA) (Z > 20kΩ, IL 1% THD) (Note 13,
Forward
Only
Forward
Only
L
L
•
•
•
•
o
o
Forward and Reverse
Figure 7) T = 0 C to 85 C
3.2
3.0
-
-
-
-
V
A
PEAK
PEAK
o
o
T
= -40 C to 0 C
A
V
V
Overload Level, On Hook (I ≤ 5mA) (Z > 20kΩ, 1% THD)
1.3
-200
-
-
-
-
200
1
Forward
Only
Forward
Only
L
L
PEAK
mV
•
•
•
•
•
•
•
•
•
•
•
•
Forward and Reverse
(Note 14, Figure 7)
V
Output Offset Voltage
E
= 0, Z = ∞, (Note 15, Figure 7)
Forward
Only
Forward
Only
TX
G
L
Forward and Reverse
Output Impedance
(Guaranteed by Design)
0.2kHz < f < 03.4kHz
0.2kHz < f < 3.4kHz
0.1
Ω
•
•
•
•
4-WIRE RECEIVE PORT (VRX)
VRX Input Impedance
(Guaranteed by Design)
-
500
600
kΩ
•
•
•
•
•
•
•
•
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
Relative to 0dBm at 1.0kHz, E = 0V
RX
Forward
Only
Forward
Only
Forward and Reverse
0.3kHz < f < 3.4kHz
-0.15
-
0.15
0.5
1.0
1.5
dB
dB
dB
dB
f = 8.0kHz (Note 16, Figure 8)
f = 12kHz (Note 16, Figure 8)
f = 16kHz (Note 16, Figure 8)
-
-
-
0.24
0.58
1.0
4-Wire to 2-Wire
Forward and Reverse
Relative to 0dBm at 1.0kHz, E = 0V
G
0.3kHz < f < 3.4kHz
Forward
Only
Forward
Only
-0.15
-0.5
-1.0
-1.5
-
0.15
dB
dB
dB
dB
f = 8kHz (Note 17, Figure 8)
f = 12kHz (Note 17, Figure 8)
f = 16kHz (Note 17, Figure 8)
0.24
0.58
1.0
-
-
-
•
•
•
•
•
•
•
•
4-Wire to 4-Wire
Forward and Reverse
Relative to 0dBm at 1.0kHz, E = 0V
Forward
Only
Forward
Only
G
0.3kHz < f < 3.4kHz (Note 18, Figure 8) -0.15
8kHz, 12kHz, 16kHz (Note 18, Figure 8) -0.5
-
0.15
0.5
dB
dB
0
V
V
TIP
TX
TIP
TX
V
V
TX
TX
R
L
600Ω
OPEN
R
L
E
G
V
TR
600Ω
V
PTG
VRX
TR
E
RX
RING VRX
RING
FIGURE 8. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING
AND HARMONIC DISTORTION
FIGURE 9. IDLE CHANNEL NOISE
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
INSERTION LOSS
2-Wire to 4-Wire
0dBm, 1kHz
Forward and Reverse
PTG = Open (Note 19, Figure 8)
PTG = GND (Note 20, Figure 8)
0dBm, 1kHz (Note 21, Figure 8)
-0.2
-6.22
-0.2
-
-6.02
-
0.2
-5.82
0.2
dB
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
4-Wire to 2-Wire
Forward and Reverse
Forward
Only
Forward
Only
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
Forward and Reverse
-40dBm to +3dBm (Note 22, Figure 8)
-0.1
-
-
-
-
0.1
0.2
0.1
0.2
dB
dB
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
-55dBm to -40dBm (Note 22, Figure 8) -0.2
4-Wire to 2-Wire
Forward and Reverse
-40dBm to +3dBm (Note 23, Figure 8)
-0.1
Forward
Only
Forward
Only
-55dBm to -40dBm (Note 23, Figure 8) -0.2
NOISE
Idle Channel Noise at 2-Wire
Forward and Reverse
C-Message Weighting
-
-
10.5
13
dBrnC
dBmp
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
Psophometric Weighting (Note 24,
Note 30, Figure 9)
-79.5
-77
Idle Channel Noise at 4-Wire
Forward and Reverse
C-Message Weighting
-
-
10.5
13
dBrnC
dBmp
Forward
Only
Forward
Only
Psophometrical Weighting
(Note 25, Note 30, Figure 9)
-79.5
-77
HARMONIC DISTORTION
2-Wire to 4-Wire
Forward and Reverse
0dBm, 0.3kHz to 3.4kHz
(Note 26, Figure 7)
-
-
-67
-67
-50
-50
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
4-Wire to 2-Wire
Forward and Reverse
0dBm, 0.3kHz to 3.4kHz
(Note 27, Figure 8)
Forward
Only
Forward
Only
7kΩ
V
V
TX
TIP
V
BH
TIP
TX
S
R
LIM
R
L
R
LIM
38.3kΩ
V
TR
600Ω
I
R1
R
1
RING
VRX
VRX
RING
FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE
FIGURE 11. TIPX VOLTAGE
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
= 26.5mA, R = 38.3kΩ
18mA ≤ IL ≤ 45mA,
(Note 27, Figure 10)
Forward
Only
Forward
Only
•
•
•
•
•
•
I
0.92I
-
I
1.08I
L
mA
L
LIM
L
L
Forward and Reverse
Tip Open State TIPX Leakage
Current
S = Closed (Figure 11)
-
-200
µA
•
•
•
•
•
•
•
•
Tip Open State RINGX Current
R
R
= 0Ω, V
BH
= 2.5kΩ, V
= -48V, R
= 38.3kΩ
22.6
15.5
-
26.8
17.1
42.8
31
18.2
-
mA
mA
V
1
1
LIM
= -48V (Figure 11)
•
•
•
•
•
•
BH
Tip Open State RINGX Voltage
Tip Voltage (Ground Start)
5mA < I < 26mA (Figure 11)
R1
•
NA
•
NA
•
NA
•
NA
Active State, (S Open) R = 150Ω
(Figure 11)
-5.3
-4.8
-4.3
V
1
Tip Voltage (Ground Start)
Active State, (S Closed) Tip Lead to
•
•
•
•
-48V Through 7kΩ, Ring Lead to
Ground Through 150Ω (Figure 11)
-5.3
-20
-4.8
0
-4.3
20
V
NA
NA
NA
NA
Open Circuit State Loop Current
(Active) R = 0Ω
µA
L
•
•
•
•
LOOP CURRENT DETECTOR
Programmable Threshold
Forward and Reverse
I
I
= (500/ R ) ≥ 5mA,
0.9I
I
1.1I
LTh
mA
Forward
Only
Forward
Only
LTh
D
LTh
LTh
= 8.5mA
•
•
•
•
LTh
R
= 58.8kΩ
D
GROUND KEY DETECTOR
Ground Key Detector Threshold
Tip/Ring Current Difference
Tip Open
5
8
11
mA
mA
NA
NA
NA
•
•
•
•
•
•
Active (Note 29, R1 = 2.5kΩ, Figure 12) 12.5
20
27.5
LINE VOLTAGE MEASUREMENT
Pulse Width (GKD_LVM)
Pulse Width = (20)(C
/I
)
0.32
0.36
0.4
ms/V
NA
NA
REV... LIM
•
RING TRIP DETECTOR (DT, DR)
Ring Trip Comparator Current
Source Res = 2MΩ
Source Res = 2MΩ
-
-
2
-
-
µA
•
•
•
•
•
•
•
•
•
•
•
•
Input Common-Mode Range
±200
V
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
RING RELAY DRIVER
V
at 30mA
at 40mA
I
I
= 30mA
-
-
-
0.2
0.52
0.1
0.5
0.8
10
V
V
SAT
SAT
OL
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
= 40mA
OL
Off State Leakage Current
V
= 13.2V
µA
OH
TEST RELAY DRIVER (TRLY1, TRLY2)
V
V
at 30mA
at 40mA
I
I
= 30mA
= 40mA
= 13.2V
-
-
-
0.3
0.65
-
0.5
1.3
10
V
V
NA
NA
NA
NA
NA
NA
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
NA/•
SAT
OL
SAT
OL
Off State Leakage Current
V
µA
OH
TIP
V
TX
VRX
SHD
RING
2.5kΩ
FIGURE 12. GROUND KEY DETECT
DIGITAL INPUTS (C1, C2, C3, C4, C5)
Input Low Voltage, V
0
2.0
-
-
-
0.8
V
V
IL
Input High Voltage, V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
IH
CC
Input Low Current, I
V
V
= 0.4V
= 2.5V
-
-10
µA
µA
IL
IL
Input High Current, I
-
25
50
IH
IH
DETECTOR OUTPUTS (SHD, GKD_LVM)
SHD Output Low Voltage, V
Forward, Reverse
I
I
I
= 1mA
-
2.7
-
-
-
0.5
V
V
Forward
Only
Forward
Only
OL
OL
OH
OL
•
•
•
•
•
•
SHD Output High Voltage, V
Forward, Reverse
= 100µA
-
0.5
-
Forward
Only
Forward
Only
OH
•
•
GKD_LVM Output Low Voltage,
Forward and Tip Open
= 1mA
= 2.5kΩ (Figure 11)
-
V
GKD
GKD
NA
GKD_
LVM
GKD_
LVM
LVM
V
R
OL
GKD_LVM Output High Voltage,
Forward and Tip Open
1
I
= 100µA
2.7
-
-
V
GKD
GKD
NA
GKD_
LVM
GKD_
LVM
LVM
OH
V
OH
Internal Pull-Up Resistor
15
-
kΩ
•
•
•
•
•
•
o
o
Electrical Specifications
T
= -40 C to 85 C, V
CC
= +5V ±5%, V
= -48V, V = -24V, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 50kΩ, RDC_RAC =
LIM D
A
BH
BL
P1
P2
T
20kΩ, R
= 40kΩ, C = 0.1µF, C
= 4.7µF, C
= 0.47µF, GND = 0V, RL = 600Ω. Unless Otherwise Specified.
Symbol used to indicate the
OH
H
DC
RT/REV
(•)
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
POWER DISSIPATION (V
= -48V, V = -24V)
BL
BH
Open Circuit State
C1, C2, C3 = 0, 0, 0
-
25
-
mW
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
•
•
•
•
On-Hook, Active
C1, C2, C3 = 0, 1, 0
C1, C2, C3 = 1, 1, 0
Forward and Reverse
I = 0mA, Longitudinal
L
Current = 0mA
-
52
-
mW
Forward
Only
Forward
Only
POWER SUPPLY CURRENTS (V
= -48V, V
= -24V)
BL
BH
Open Circuit State
V
V
V
V
Current, I
-
-
-
-
-
-
2.25
0.3
3.0
0.45
0.035
3.6
mA
mA
mA
mA
mA
mA
Forward
Only
Forward
Only
CC
BH
BL
CC
BH
BL
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Current, I
Forward
Only
Forward
Only
Current, I
0.022
2.7
Forward
Only
Forward
Only
Current, I
CC
Active State
Forward
Only
Forward
Only
CC
Forward and Reverse
I = 0mA, Longitudinal
Current = 0mA
L
V
Current, I
0.8
1.06
0.01
Forward
Only
Forward
Only
BH
BH
Forward and Reverse
V
Current, I
BL
-
Forward
Only
Forward
Only
BL
Forward and Reverse
POWER SUPPLY REJECTION RATIOS
to 2 or 4 Wire Port Active State R = 600Ω
V
-
-
-
40
40
40
-
-
-
dB
dB
dB
Forward
Only
Forward
Only
CC
Forward and Reverse
L
•
•
•
•
•
•
•
•
•
•
•
•
50Hz < f < 3400Hz, V =100mV
IN
V
to 2 or 4 Wire Port
Forward
Only
Forward
Only
BH
Forward and Reverse
V
to 2 or 4 Wire Port
Forward
Only
Forward
Only
BL
Forward and Reverse
TEMPERATURE GUARD
Junction Threshold Temperature
o
-
175
-
C
•
•
•
•
•
•
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
14. Overload Level (4-Wire Port On-Hook) - The overload level
Notes
is specified at the 4-wire transmit port (V ) with the signal
TX
2. Overload Level (Two-Wire Port, Off Hook) - The overload
level is specified at the 2-wire port (V ) with the signal source at
source (E ) at the 2-wire port, Z = 20kΩ, R = ∞ (Reference
G
L
L
TR
Figure 7). Increase the amplitude of E until 1% THD is
G
the 4-wire receive port (E ). R = 600Ω, I
Increase the amplitude of E until 1% THD is measured at V
Reference Figure 1.
≥ 18mA.
RX DCMET
L
measured at V . Note the PTG pin is open, and the gain from
TX
.
RX
TR
the 2-wire port to the 4-wire port is equal to 1.
15. Output Offset Voltage - The output offset voltage is specified
with the following conditions: E = 0, R = 600Ω, Z = ∞ and is
3. Overload Level (Two-Wire Port, On Hook) - The overload
G
L
L
level is specified at the 2-wire port (V ) with the signal source at
TR
the 4-wire receive port (E ). R = ∞, I = 0mA. Increase
DCMET
measured at V . E , R , V and Z are defined in Figure 7.
TX
G
L
TX
L
RX
L
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
the amplitude of E
Reference Figure 1.
until 1% THD is measured at V
.
RX
TR
4-wire frequency response is measured with respect to
E
= 0dBm at 1.0kHz, E = 0V (VRX input floating), R = 600Ω.
G
RX
L
4. LongitudinalImpedance - The longitudinal impedance is
The frequency response is computed using the following equation:
computed using the following equations, where TIP and RING
voltages are referenced to ground. L , L , V , V , A and
F
= 20 log (V /V ), vary frequency from 300Hz to 3.4kHz
2-4
TX TR
ZT ZR
T
R
R
and compare to 1kHz reading.
A
are defined in Figure 2.
T
V
, V , R and E are defined in Figure 8.
(TIP) L = V /A
TX TR
L
G
ZT
T
T
(RING) L = V /A
ZR
R
R
17. Four-Wireto Two-Wire Frequency Response - The 4-wire to 2-
where: E = 1V
(0Hz to 100Hz)
L
RMS
wire frequency response is measured with respect to E = 0dBm
RX
at 1.0kHz, E source removed from circuit, R = 600Ω. The
5. Longitudinal Current Limit (On-Hook Active) - On-Hook
G
L
frequency response is computed using the following equation:
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E (Figure 3A) until the 2-wire longitudinal current
L
F
= 20 log (V /E ), vary frequency from 300Hz to 3.4kHz
4-2
TR RX
and compare to 1kHz reading.
is greater than 28mA
/Wire. Under this condition, SHD pin
RMS
remains low (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
V
, R and E are defined in Figure 8.
TR
L
RX
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
(LB
= 20log VTX/E ).
L
2-4
to 4-wire frequency response is measured with respect to
E
R
6. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
= 0dBm at 1.0kHz, E source removed from circuit,
G
RX
= 600Ω. The frequency response is computed using the
longitudinal current limit is determined by increasing the (60Hz)
L
amplitude of E (Figure 3B) until the 2-wire longitudinal current
L
following equation:
is greater than 28mA
/Wire. Under this condition, SHD pin
RMS
F
= 20 log (V /E ), vary frequency from 300Hz to 3.4kHz
remains high (no false detection) and the 2-wire to 4-wire
longitudinal balance is verified to be greater than 45dB
4-4
TX RX
and compare to 1kHz reading.
(LB
= 20log VTX/E ).
L
V
R and E are defined in Figure 8.
2-4
TX ,
L
RX
7. Longitudinal to Metallic Balance - The longitudinal to
19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) - The
metallic balance is computed using the following equation:
2-wire to 4-wire insertion loss is measured with respect to
E
= 0dBm at 1.0kHz input signal, E
= 0 (VRX input floating),
BLME = 20 log (E /V ), where: E and V are defined in
TR TR
Figure 4.
G
RX
L
L
R = 600Ω and is computed using the following equation:
L
L
= 20 log (V /V )
TX TR
8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
2-4
metallic to longitudinal balance is defined in this spec.
where: V , V , R and E are defined in Figure 8. (Note:
TX TR
L
G
The fuse resistors, R , impact the insertion loss. The specified
9. Longitudinal to Four-Wire Balance - The longitudinalto 4-wire
F
insertion loss is for R = R = 0).
balance is computed using the following equation:
F1 F2
20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) - The
2-wire to 4-wire insertion loss is measured with respect to E
BLFE = 20 log (E /V ), E and V are defined in Figure 4.
TX TX
L
L
=
G
10. Metallic to Longitudinal Balance - The metallic to longitudinal
0dBm at 1.0kHz input signal, E
= 0 (VRX input floating), R =
RX
600Ω and is computed using the following equation:
L
balance is computed using the following equation:
BMLE = 20 log (E /V ), E
= 0
TR
V and E
L
RX
are defined in Figure 5.
L
= 20 log (V /V )
TX TR
2-4
where: E
TR,
L
RX
where: V , V , R and E are defined in Figure 8. (Note:
TX TR
L
G
11. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
The fuse resistors, R , impact the insertion loss. The specified
F
balance is computed using the following equation:
insertion loss is for R = R = 0).
F1 F2
BFLE = 20 log (E /V ), E = source is removed.
RX TR
L
21. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
insertion loss is measured based upon E = 0dBm, 1.0kHz
where: E
RX,
V and E are defined in Figure 5.
TR
RX
L
input signal, E source removed from circuit, R = 600Ω and is
G
L
12. Two-Wire Return Loss - The 2-wire return loss is computed
using the following equation:
computed using the following equation:
L
= 20 log (V /E
TR RX
)
r = -20 log (2V /V ) where: Z = The desired impedance; e.g.,
the characteristic impedance of the line, nominally 600Ω.
(Reference Figure 6).
4-2
where: V , R and E
M
S
D
are defined in Figure 8.
TR
L
RX
22. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
13. Overload Level (4-Wire Port Off-Hook) - The overload level
gain tracking is referenced to measurements taken for
E
R = 600Ω and is computed using the following equation.
is specified at the 4-wire transmit port (V ) with the signal
TX
= -10dBm, 1.0kHz signal, E
= 0 (VRX output floating),
G
RX
source (E ) at the 2-wire port, Z = 20kΩ, R = 600Ω
G
L
L
L
(Reference Figure 7). Increase the amplitude of E until 1%
G
G
= 20 • log (V /V ) vary amplitude -40dBm to +3dBm, or
TX TR
2-4
THD is measured at V . Note the PTG pin is open, and the
TX
-55dBm to -40dBm and compare to -10dBm reading.
gain from the 2-wire port to the 4-wire port is equal to 1.
V
, R and V are defined in Figure 8.
L
TX TR
12
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
23. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire
26. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic
gain tracking is referenced to measurements taken for
distortion is measured within the voice band with the following
E
= -10dBm, 1.0kHz signal, E source removed from circuit,
conditions. E = 0dBm at 1kHz, R = 600Ω. Measurement
RX
G
G L
R = 600Ω and is computed using the following equation:
taken at V . (Reference Figure 7).
TX
L
G
= 20 • log (V /E ) vary amplitude -40dBm to +3dBm, or
TR RX
27. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic
4-2
-55dBm to -40dBm and compare to -10dBm reading.
distortion is measured within the voice band with the following
conditions. E
= 0dBm0. Vary frequency between 300Hz and
RX
3.4kHz, R = 600Ω. Measurement taken at V . (Reference
V
, R and E are defined in Figure 8. The level is specified at
L
TR RX
L
TR
the 4-wire receive port and referenced to a 600Ω impedance level.
Figure 8).
24. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
28. Constant Loop Current - The constant loop current is
at V is specified with the 2-wire port terminated in 600Ω (R )
and with the 4-wire receive port (VTX) floating (Reference
TR
L
calculated using the following equation:
Figure 9).
I
= 1000/R
= V /600 (Reference Figure 10).
LIM TR
L
25. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
29. Ground Key Detector - (TRIGGER) Ground the Ring pin
through a 2.5kΩ resistor and verify that GKD goes low.
at V is specified with the 2-wire port terminated in 600Ω (R ).
TX
L
The noise specification is with respect to a 600Ω impedance
(RESET) Disconnect the Ring pin and verify that GKD goes
high.
level at V . The 4-wire receive port (VTX) floating (Reference
TX
Figure 9).
(Hysteresis) Compare difference between trigger and reset.
o
30. Electrical Test - Not tested in production at -40 C.
Circuit Operation and Design Information
.
The UniSLIC14 family of SLICs are voltage feed current
sense Subscriber Line Interface Circuits (SLIC). For short
loop applications, the voltage between the tip and ring
terminals varies to maintain a constant loop current. For long
loop applications, the voltage between the tip and ring
terminals are relatively constant and the loop current varies
in proportion to the load.
35
30
25
CONSTANT TIP TO RING
VOLTAGE REGION
CONSTANT
20 LOOP CURRENT
REGION
15
10
5
The tip and ring voltages for various loop resistances are
shown in Figure 13. The tip voltage remains relatively
constant as the ring voltage moves to limit the loop current
for short loops.
VBH = -48V
RD = 41.2kΩ
ROH = 38.3kΩ
RDC_RAC = 19.6kΩ
RILim = 33.2kΩ
The loop current for various loop resistances are shown in
Figure 14. For short loops, the loop current is limited to the
programmed current limit, set by RILIM. For long loop
applications, the loop current varies in accordance with
Ohms law for the given tip to ring voltage and the loop
resistance.
0
200 600 1K 1.4K 1.8K 2.2K 2.6K 3.0K 3.4K 3.8K
LOOP RESISTANCE (Ω)
FIGURE 14. LOOP CURRENT vs LOOP RESISTANCE
The following discussion separates the SLIC’s operation into
its DC and AC paths, then follows up with additional circuit
and design information.
0
-2.5V
TIP
-5
-10
-15
-20
-25
CONSTANT TIP TO RING
VOLTAGE REGION
DC Feed Curve
RING
VBH = -48V
RD = 41.2kΩ
The DC feed curve for the UniSLIC14 family is user
programmable. The user defines the on hook and off hook
overhead voltages (including the overhead voltage for off
hook pulse metering if applicable), the maximum and
minimum loop current limits, the switch hook detect
threshold and the battery voltage. From these requirements,
the DC feed curve is customized for optimum operation in
any given application. An Excel spread sheet to calculate the
external components can be downloaded off our web site
www.intersil.com/telecom/unislic14.xls.
ROH = 38.3kΩ
RDC_RAC = 19.6kΩ
RILim = 33.2kΩ
-30
-35
CONSTANT
LOOP CURRENT
REGION
-40
-45
-50
-44.5V
200 600 1000 1400 1800 2000 4K
6K
8K 10K
LOOP RESISTANCE (Ω)
FIGURE 13. TIP AND RING VOLTAGES vs LOOP RESISTANCE
13
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
VBH
SLIC SELF PROGRAMMING
2.5V†
VOH(on) AT LOAD
CONSTANT
CURRENT
REGION
VOH(off) AT LOAD
R
SAT
60kΩ SLOPE
IOH
ISH-
I
ILOOP(min)
LOOP CURRENT (mA)
ILOOP(max)
SHD
†Internal overhead voltage automatically generated by the SLIC.
FIGURE 15. UniSLIC14 DC FEED CURVE
R
R
= Protection Resistors (Typically 30Ω)
On Hook Overhead Voltage
P
S
The on hook overhead
voltage at the load (V (on)
= Internal Sense Resistors (40Ω)
DC FEED CURVE
BH
V
OH
Z = AC load impedance for (600Ω)
L
at Load) is independent of the
2.5V
V
battery voltage. Once
V
1.5V = Additional on hook overhead voltage requirement
ON HOOK
OVERHEAD
BH
OH(on)
set, the on hook voltage
remains constant as the V
battery voltage changes. The
on hook voltage also remains
constant over temperature
and line leakages up to 0.6
To account for any process and temperature variations in the
performance of the SLIC, 1.5V is added to the overhead
voltage requirement for the on hook case in Equation 1 and
2.0V for the off hook case in Equation 3. Note the 2.5V
overhead is automatically generated in the SLIC and is not
part of the external overhead programming.
BH
ISH-
LOOP CURRENT
(0.6)
I
SHD
ISH- = I
SHD
times the Switch Hook Detect threshold (I
). The
SHD
maximum loop current for a constant on hook overhead
voltage is defined as ISH-.
REQUIRED
OVERHEAD VOLTAGE
EXTERNAL PROTECTION
RESISTOR
V
(ON, OFF)
UniSLIC14
OH
The on hook overhead voltage, required for a given signal
level at the load, must take into account the AC voltage drop
2R
2R
P
S
TIP AND RING
AMPLIFIERS
V
ZL
across the 2 external protection resistors (R ) and the 2
P
internal sense resistors (R ) as shown in Figure 16. The AC
S
on hook overload voltage is calculated using Equation 1.
INTERNAL SENSE
RESISTORS
Z
L
2R + 2R
(LOAD)
P
S
V
=
----------------------------- V
OH(ON, OFF)
Where:
is the required on hook or offhook
ZL
Z
L
2R + 2R
P
S
V
(EQ. 1
ZL
transmission delivered to the load.
= V
× 1 + ----------------------------- + 1.5V
OH(on) at Load
sp(on)
Z
L
FIGURE 16. OVERHEAD VOLTAGE OF THE TIP AND RING
AMPLIFIERS
where
V
V
= On hook overhead voltage at load
OH(on) at Load
= Required on hook transmission for speech
sp(on)
14
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
DC FEED CURVE
When considering the Off
Off Hook Overhead Voltage
V
hook condition, R
is equal
BH
SAT
divided by
The off hook overhead
DC FEED CURVE
to V
2.5V
OH(off) at Load
V
SAT
voltage V (off) at Load is
also independent of the V
V
OH
BH
SAT
Iloop
(min)
(Equation 4).
R
SAT
V
BH
OH(off)
2.5V
V
battery voltage and remains
constant over temperature.
The required off hook
overhead voltage is the sum
of the AC and DC voltage
drops across the internal
For the given system
OFF HOOK
requirements (recommended
application circuit in back of
data sheet): Iloop (min) =
20mA, Iloop (max) = 30mA,
OVER HEAD
V
OH(off)
I
LOOP(min)
LOOP CURRENT
I
LOOP(min)
R
LOOP CURRENT
V
SAT
OH(off) AT LOAD
V
V
V
= 3.2V
,
sp(off)
PEAK
sense resistors (R , the
= 0V ,
PEAK
S)
spm(off)
I
LOOP(min)
protection resistors (R ), the required (peak) off hook
= 8.34V the
P
OH(off) at Load
voltage for speech (V
) and the required (peak) off hook
value of R
is equal to 417Ω as calculated in Equation 4.
sp(off)
voltage for the pulse metering (V
SAT(off)
V
), if applicable.
pm(off)
8.34V
OH(off) at Load
R
= --------------------------------------- = ---------------- = 417Ω
(EQ. 4)
SAT(off)
I
20mA
LOOP(min)
The off hook overhead voltage is defined in Equation 2 and
calculated using Equation 3.
V
= V
+ V
+ V
(EQ. 2)
Before using this R
value, to calculate the RDC_RAC
OH(off) at Load
OH(Rsense)
sp(off)
pm(off)
SAT
resistor, we need to verify that the on hook requirements will
also be met.
where:
V
= Off hook overhead voltage at load
The on hook overhead voltage
calculated with the off hook
DC FEED CURVE
OH(off) at Load
V
BH
V
(R ) = Required overhead for the DC voltage drop
OH sense
V
SAT
2.5V
R
(R
), is given in
SAT
SAT(off)
across sense resistors (2R x Iloop
(max)
)
S
Equation 5 and equals 3.0V.
The on hook overhead
V
OH(on)
V
= Required (peak) off hook AC voltage for speech
R
sp(off)
SAT
calculated with Equation 1
equals 2.85V for the given
system requirements
(recommended application
circuit in back of data sheet):
Switch Hook Detect threshold
= 12mA, ISH- = (0.6)12mA =
V
= Required (peak) off hook AC voltage for pulse
pm(off)
metering
ISH-(min)
LOOP CURRENT
2R + 2R
P
S
V
= 80 × I
+ V
× 1 + -----------------------------
V
OH(off) at Load
LOOP(max)
sp(off)
R
SAT
OH(on) AT LOAD
Z
L
2R + 2R
P
S
ISH-
(min)
+ V
× 1 + ----------------------------- + 2.0V
pm(off)
Z
(EQ. 3)
pm
7.2mA, V
sp(on)
= 0.775V
RMS
2.85V
= ----------------- = 395Ω
R
SAT(on)
where:
7.2mA
Thus, the on hook overhead
requirements of 2.85V will be
value.
80 = 2R + 2R
(reference Figure 17)
s
INT
met if we use the R
SAT(off)
Z
= Pulse metering load impedance (typically 200Ω).
pm
V
V
= (ISH-)(R
)
SAT(off)
(EQ. 5)
OH(on)
OH(on)
2.0V = Additional off hook overhead voltage requirement
= 7.2mA × 417Ω
= 3.0V
R
The R
Resistance Calculation
SAT
V
OH(on)
resistance of the DC feed curve is used to
SAT
determine the value of the RDC_RAC resistor (Equation 6).
The value of this resistor has an effect on both the on hook
and off hook overheads. In most applications the off hook
condition will dominate the overhead requirements.
If the on hook overhead requirement is not met, then we
need to use the R value to determine the RDC_RAC
SAT(on)
resistor value. The external saturation guard resistor
RDC_RAC is equal to 50 times R
.
SAT
Therefore, we’ll start by calculating the R
value for the
SAT
In the example above R
would equal 417Ω and
SAT
off hook conditions and then verify that the on hook
conditions are also satisfied.
RDC_RAC would then equal to 20.85kΩ (closest standard
value is 21kΩ).
(EQ. 6)
RDC_RAC = 50 x R
SAT
The Switch Hook Detect threshold current is set by resistor
and is calculated using Equation 7. For the above
R
D
15
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
example R is calculated to be 41.6kΩ (500/12mA). The
next closest standard value is 41.2kΩ.
SHD threshold, 2) minimum loop current requirement or 3)
the on and off hook signal levels.
D
500
V
–[V
+ 2V + V
]
OH(off)
(EQ. 7)
R
= ------------
BH
SAT
I
D
I
R
= ------------------------------------------------------------------------------- -2R
(EQ. 12)
LOOP(max)
P
SHD
LOOP(min)
The true value of ISH-, for the selected value of R is given
D
by Equation 8:
SLIC in the Active Mode
Figure 17 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
500
R
D
(EQ. 8)
ISH- = --------- (0.6)
1
80k
(EQ. 13)
V
= I × 2R × --------- × 200(Z
– 2R ) × 5
TR P
A
A
M
S
For the example above, ISH- equals 7.28mA (500 x 0.6/
41.2K). Verify that the value of ISH- is above the suspected
line leakage of the application. The UniSLIC family will
provide a constant on hook voltage level for leakage
currents up to this value of line leakage.
I
M
(EQ. 14)
(EQ. 15)
V
= ------- (Z
– 2R )
TR
P
2
Node Equation
DC FEED CURVE
The R
resistor, which
OH
V
V
A
RX
------------ - ------------ = I
is used to set the offhook
overhead voltage, is
calculated using
X
V
500k 500k
BH
2.5V
V
SAT
OH(off)
Substitute Equation 14 into Equation 15
(Z – 2R )
OFF HOOK
V
Equations 9 and 10.
V
I
M
OVER HEAD
RX
TR
1000k
P
I
= ------------ - -----------------------------------------
(EQ. 16)
(EQ. 17)
X
I
500k
OH
I
is defined as the
OH
difference between the
and ISH-.
I
ISH-
LOOP(min)
Loop Equation
I 500k - V ′ + I 500k = 0
I
LOOP(min)
Substituting Equation 8
for ISH- into Equation 9 and solving for R defines R in
LOOP CURRENT
X
TX
X
OH
OH
Substitute Equation 16 into Equation 17
′ = 2V – I (Z – 2R )
terms of I
and R .
D
LOOP(min)
(EQ. 18)
(EQ. 19)
500
500
V
(EQ. 9)
R
= --------- = -------------------------------------------
TX
RX
M
TR
P
OH
I
I
- ISH-
OH
LOOP(min)
Loop Equation
-I 2R + V ′ = 0
Equation 10 can be used to determine the actual ISH- value
resulting from the R resistor selected. The value of R
V
TR
M
P
TX
D
D
should be the next standard value that is lower than that
calculated. This will insure meeting the I
requirement. ROH for the above example equals 39.1kΩ.
Substitute Equation 18 into Equation 19
– 2V
LOOP(min)
(EQ. 20)
V
= I Z
M TR
TR
RX
R 500
D
(EQ. 10)
Substituting -V /Z into Equation 20 for I and rearranging
TR
R
= -----------------------------------------------------------
L
M
OH
R I
- 500(.6)
D
LOOP(min)
to solve for V
results in Equation 21
TR
Z
TR
The current limit is set by a single resistor and is calculated
using Equation 11.
(EQ. 21)
V
1 + ---------- = –2V
TR
RX
Z
L
1000
(EQ. 11)
R
= -----------------------------
where:
LIM
I
LOOP(max)
V
V
= The input voltage at the VRX pin.
RX
DC FEED CURVE
The maximum loop
= An internal node voltage that is a function of the loop
A
V
resistance is calculated
using Equation 12. The
resistance of the
current detector and the impedance matching networks.
BH
2.5V
V
SAT
I
= Internal current in the SLIC that is the difference
X
between the input receive current and the feedback current.
V
OH(off)
protection resistors
I
= The AC metallic current.
M
(2R ) is subtracted out
P
to obtain the maximum
loop length to meet the
required off hook
R
= A protection resistor (typical 30Ω).
P
I
LOOP(min)
LOOP CURRENT
Z = An external resistor/network for matching the line
T
impedance.
overhead voltage. If R
meets the loop length
requirements you are done. If the loop length needs to be
longer, then consider adjusting one of the following: 1) the
LOOP(MAX)
V ´= The tip to ring voltage at the output pins of the SLIC.
TX
16
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
V
= The tip to ring voltage including the voltage across the
From Equation 21 and the relationship Z = 200(Z -2R ).
TR
protection resistors.
T
TR
P
(EQ. 22)
o
V
Z
Z
TR
L
L
G
= ---------- = -2------------------------- = –2----------------------------------------------
4-2
V
Z
+ Z
Z
T
RX
L
TR
Z = The line impedance.
L
Z
+ ------- + 2R
P
L
200
Z
= The input impedance of the SLIC including the
TR
Notice that the phase of the 4-wire to 2-wire signal is 180
out of phase with the input signal.
protection resistors.
(AC) 4-Wire to 2-Wire Gain
The 4-wire to 2-wire gain is equal to V /V
TR RX
.
I
X
+
-
500K
I
M
A = 1
+
-
V
TIP
R
R
TX
S
INT
-
-
+
+
20Ω 20Ω
R
-
P
500K
Z
+
TX
-
TR
V
I
M
Z
L
I
I
X
X
-
PTG
500K
+
UniSLIC14
V
V
´
TR
TX
-
+
+
E
G
I
-
X
I
+
M
-
R
R
S
V
INT
RX
+
-
500K
20Ω
20Ω
R
P
I
RING
X
+
RX
-
-
+
V
500K
500K
1/80K
5
V
= I (Z -2R )
A
M
2
TR
P
Z
= 200 (Z - 2R )
TR
T
P
FIGURE 17. SIMPLIFIED AC TRANSMISSION CIRCUIT
Rearranging Equation 27 in terms of E , and substituting
G
into Equation 26 results in an equation for 2-wire to 4-wire
gain that’s a function of the synthesized input impedance of
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to V /E with V = 0
RX
TX
G
Loop Equation
the SLIC (Z ) and the protection resistors (R ).
TR
P
(EQ. 23)
(EQ. 24)
–E + Z I + 2R I – V ′ = 0
G
L M
P M
TX
(EQ. 28)
V
Z
- 2R
P
Z
TR
TX
TR
G
= ---------- = -----------------------------
2-4
V
From Equation 18 with V
= 0
TR
RX
V
′ = – I (Z
– 2R )
TR P
TX
M
Notice that the phase of the 2-wire to 4-wire signal is in
phase with the input signal.
Substituting Equation 24 into Equation 23 and simplifying.
(EQ. 25)
(EQ. 26)
E
= I (Z + Z
)
TR
(AC) 4-Wire to 4-Wire Gain
G
M
L
The 4-wire to 4-wire gain is equal to V /V , E = 0.
TX RX
G
By design, VTX = -VTX´, therefore
(Z – 2R ) (Z – 2R )
P
V
I
From Equation 18.
′ = –V = –2V
TX
M
TR
(Z + Z
P
TR
(Z + Z
G
= ---------- = --------------------------------------- = --------------------------------
2-4
E
I
)
)
TR
G
M
L
TR
L
V
+ I (Z
– 2R )
(EQ. 29)
TX
TX
RX
M
TR
P
A more useful form of the equation is rewritten in terms of
/V . A voltage divider equation is written to convert
V
TX TR
Substituting -V /Z into Equation 29 for I results in
Equation 30.
TR
L
M
from E to V
G
as shown in Equation 27.
TR
(EQ. 27)
Z
V
(Z
– 2R )
P
TR
+ Z
TR TR
V
=
----------------------- E
(EQ. 30)
V
= –2V
– ---------------------------------------------
TR
G
TX
RX
Z
Z
L
TR
L
17
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Substituting Equation 21 for V
in Equation 30 and
constant on hook overhead voltage (ISH- = I
(0.6)) and
TR
simplifying results in Equation 31.
SHD
is calculated in Equation 4.
the value of R
SAT(off)
V
Z + 2R
L P
On hook Ring Voltage
TX
(EQ. 31)
G
= ----------- = –2 ------------------------
4 – 4
V
Z + Z
R
RX
L TR
SAT(off)
+ 1.5V + (ISH ) -------------------------
V
= V
BH
(EQ. 36)
RING(onhook)
2
(AC) 2-Wire Impedance
The calculation of the ring voltage with respect to ground in
the off hook condition is dependent upon whether the SLIC
is in current limit or not.
The AC 2-wire impedance (Z ) is the impedance looking
TR
into the SLIC, including the fuse resistors. The formula to
calculate the proper Z for matching the 2-wire impedance is
T
shown in Equation 32.
= 200 • (Z – 2R )
The off hook ring to ground voltage (in current limit) is
(EQ. 32)
calculated using Equation 37. I
is the programmed loop
Z
LIM
T
TR
P
current limit and R is the load resistance across tip and
L
ring. The minus 0.2V is a correction factor for the 60kΩ slope
Equation 32 can now be used to match the SLIC’s
in Figure 15.
impedance to any known line impedance (Z ).
TR
Off hook Ring Voltage in Current Limit
EXAMPLE:
Calculate Z to make Z = 600Ω in series with 2.16µF.
T
TR
V
= V
– I
R – 0.2V
LOOP(MAX) L
(EQ. 37)
RING(CL)
TIP(offhook)
R
= 30Ω.
P
1
Z
= 200 600 + ----------------------------------- – (2)(30)
(EQ. 33)
The off hook ring to ground voltage (not in current limit) is
calculated using Equation 38. The 1.5V results from the
T
–6
jω2.16X10
SLIC self programming. I
current allowed by the design and the value of R
calculated in Equation 4.
is the minimum loop
LOOP(min)
Z = 108kΩ in series with 0.0108µF.
T
is
SAT(off)
Note: Some impedance models, with a series capacitor, will
cause the op-amp feedback to behave as an open circuit
DC. A resistor with a value of about 10 times the reactance
Off hook Ring Voltage not in Current Limit
R
SAT(off)
) -------------------------
2
of the Z capacitor (2.16µF/200 = 10.8nF) at the low
T
V
= V
+ 1.5V + (I
(EQ. 38)
RING(NCL)
–I
BH
× R
LOOP(min)
frequency of interest (200Hz for example) can be placed in
parallel with the capacitor in order to solve the problem
(736kΩ for a 10.8nF capacitor).
LOOP(MIN)
P
Layout Considerations
Calculating Tip and Ring Voltages
Systems with Dual Supplies (V
and V
)
BH
BL
supply, it is
The on hook tip to ground voltage is calculated using
Equation 34. The minus 1.0 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
If the V supply is not derived from the V
BL BH
recommended that an additional diode be placed in series
with the V supply. The orientation of this diode is anode
BH
constant on hook overhead voltage (ISH- = I
(0.6)) and
SHD
is calculated in Equation 4.
on pin 8 of the device and cathode to the external supply.
This external diode will inhibit large currents and potential
the value of R
SAT(off)
damage to the SLIC, in the event the V
supply is shorted
On hook Tip Voltage
BH
then this diode is not
to GND. If V is derived from V
BL
R
BH
required. Suggested (not required) supply sequence V
SAToff
= – 1.0V + – (ISH-) ---------------------
V
(EQ. 34)
-
TIP(onhook)
BH
2
V
- V .
BL CC
The off hook tip to ground voltage is calculated using
Equation 35. I is the minimum loop current
Floating the PTG Pin
LOOP(min)
The PTG pin is a high impedance pin (500kΩ) that is used to
program the 2-wire to 4-wire gain to either 0dB or -6dB.
allowed by the design and the value of R
is
SAT(off)
calculated in Equation 4.
If 0dB is required, it is necessary to float the PTG pin. The
PC board interconnect should be as short as possible to
minimize stray capacitance on this pin. Stray capacitance on
this pin forms a low pass filter and will cause the 2-wire to
4-wire gain to roll off at the higher frequencies.
Off hook Tip Voltage
R
SAT(off)
)--------------------------
LOOP(min)
V
= – 1V – (I
(EQ. 35)
TIP(offhook)
– I
2
× R
LOOP(MAX)
P
If a 2-wire to 4-wire gain of -6dB is required, the PTG pin
should be grounded as close to the device as possible.
The on hook ring to ground voltage is calculated using
Equation 36. The 1.5 volt results from the SLIC self
programming. ISH- is the maximum loop current for a
18
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
SPM Pin
Layout of the 2-Wire Impedance Matching
Resistor Z
For optimum performance, the PC board interconnect the
SPM pin should be as short as possible. If pulses metering is
not being used, then this pin should be grounded as close to
the device pin as possible.
T
Proper connection to the ZT pin is to have the external Z
network as close to the device pin as possible.
T
The ZT pin is a high impedance pin that is used to set the
proper feedback for matching the impedance of the 2-wire
side. This will eliminate circuit board capacitance on this pin
to maintain the 2-wire return loss across frequency.
RLIM Pin
The current limiting resistor R
RLIM pin as possible.
needs to be as close to the
LIM
TABLE 1. DETECTOR STATES
OUTPUT
GKD_ LVM
STATE
C3
0
C2
0
C1
SLIC OPERATING STATE
ACTIVE DETECTOR
4 wire loopback test capability
Ring Trip Detector
SHD
0
1
0
1
Open Circuit State
HIGH
HIGH
HIGH
0
0
Ringing State
(Previous State cannot be Reverse
Active State)
2
3
0
0
1
1
0
1
Forward Active State
Loop Current Detector
Ground Key Detector
Test Active State
On Hook Loopback Detector
Ground Key Detector
LOW
LOW
Requires previous state to be in the
Forward Active state to determine the
On hook or Off hook status of the line.
HIGH
N/A
Off Hook Loop Current Detector
Line Voltage Detector
4
1
0
0
Tip Open - Ground Start State
Ground Key Detector
5
6
1
1
0
1
1
0
Reserved
Reserved
N/A
Reverse Active State
Loop Current Detector
Ground Key Detector
7
8
1
1
1
Test Reversal Active State
On Hook Loop Current Detector
HIGH
LOW
Requires previous state to be in the
Reverse Active state to determine the
On hook or Off hook status of the line.
Off Hook Loop Current Detector
LOW
LOW
Line Voltage Detector
X
X
X
Thermal Shutdown
the PTG pin is grounded, then the amplitude will be
approximately the same as its input and 180 out of phase.
Digital Logic Inputs
o
Table 1 is the logic truth table for the 3V to 5V logic input
pins. A combination of the control pins C3, C2 and C1 select
1 of the possible 6 operating states. The 8th state listed is
Thermal Shutdown. Thermal Shutdown protection is invoked
if a fault condition on the tip or ring causes the junction
Ringing State (C3 = 0, C2 = 0, C1 = 1)
In this state, the output of the ring relay driver pin (RRLY)
goes low (energizing the ring relay to connect the ringing
signal to the phone) if either of the following two conditions
are satisfied:
o
temperature of the die to exceed 175 C. A description of
each operating state and the control logic follows:
(1) The RSYNC_REV pin is grounded through a resistor -
This connection enables the RRLY pin to go low the instant
the ringing state is invoked, without any regard for the
Open Circuit State (C3 = 0, C2 = 0, C1 = 0)
In this state, the tip and ring outputs are in a high impedance
condition (>1MΩ). No supervisory functions are available
and SHD and GKD outputs are at a TTL high level.
ringing voltage (90V
-120V
) across the relay
RMS
RMS
contacts. The resistor (34.8kΩ to 70kΩ) is required to limit
the current into the RSYNC_REV pin.
4-wire loopback testing can be performed in this state. With
o
the PTG pin floating, the signal on the V output is 180 out
(2) A ring sync pulse is applied to the RSYNC_REV pin -
This connection enables the RRLY pin to go low at the
command of a ring sync pulse. A ring sync pulse should go
TX
of phase and approximately 2 times the V
input signal. If
RX
19
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
low at zero voltage crossing of the ring signal. This pulse
should have a rise and fall time <400µs and a minimum
pulse width of 2ms.
Tip Open State (C3 = 1, C2 = 0, C1 = 0)
In this state, the tip output is in a high impedance state
(>250kΩ) and the ring output is capable of full operation, i.e.
has full longitudinal current capability. The Tip Open/Ground
Start state is used to interface to a PBX incoming 2-wire
trunk line. When a ground is applied through a resistor to the
ring lead, this current is detected and presented as a TTL
logic low on the SHD and GKD_LVM output pins.
Zero ring current detection is performed automatically inside
the SLIC. This feature de-energizes the ring relay slightly
before zero current occurs to partially compensate for the
delay in the opening of the relay.
The SHD output will go low when the subscriber goes off
hook. Once SHD is activated, an internal latch will prohibit
the re-ringing of the line until the ringing code is removed
and then reapplied.
Reserved (C3 = 1, C2 = 0, C1 = 1)
This state is undefined and reserved for future use.
Reverse Active State (C3 = 1, C2 = 1, C1 = 0)
The state prior to ringing the phone, can not be the Reverse
Active State. In the reverse active state the polarity of the
voltage on the CRT_REV_LVM capacitor, will make it
appear as if the subscriber is off hook. This subsequently will
activate an internal latch prohibiting the ringing of the line.
In this state, the SLIC is fully functional. The ring voltage is
more positive than the tip voltage. The tip and ring output
voltages are an unbalanced DC feed, reference Figure 13.
The polarity reversal time is determined by the RC time
constant of the RSYNC_REV resistor and the
CRT_REV_LVM capacitor. Capacitor CRT_REV_LVM
performs three different functions: Ring trip filtering, polarity
reversal time and line voltage measurement. It is
The GKD_LVM output is disabled (TTL high level) during the
ringing state. Reference the Section titled “Ringing the
Phone” for more information.
recommended that programming of the reversal time be
accomplished by changing the value of RSYNC_REV resistor
(see Figure 18). The value of RSYNC_REV resistor is limited
between 34.8K (10ms) and 73.2k (21ms). Equation 39 gives
the formula for programming the reversal time.
Forward Active State (C3 = 0, C2 = 1, C1 = 0)
In this state, the SLIC is fully functional. The tip voltage is more
positive than the ring voltage. The tip and ring output voltages
are an unbalanced DC feed, reference Figure 13. Both SHD
and GKD supervisory functions are active. Reference the
section titled “DC Feed Curve” for more information.
RSYNC – REV = 3.47kΩ × ReversalTime(ms)
(EQ. 39)
Test Active State (C3 = 0, C2 = 1, C1 = 1)
Both SHD and GKD supervisory functions are active.
Proper operation of the Test Active State requires the
previous state be the Forward Active state to determine the
on hook or off hook status of the line. In this state, the SLIC
can perform two different tests.
Reference the section titled “Polarity Reversal” for more
information.
Test Reversal Active State (C3 = 1, C2 = 1, C1 = 1)
Proper operation of the Test Reversal Active State requires
the previous state be the Reverse Active state to determine
the on hook or off hook status of the line.
If the subscriber is on hook when the state is entered, a
loopback test is performed by switching an internal 600Ω
resistor between tip and ring. The current flows through the
internal 600Ω is unidirectional via blocking diodes. (Cannot be
used in reverse.) When the loopback current flows, the SHD
output will go low and remain there until the state is exited. This
is intended to be a short test since the ability to detect
subscriber off hook is lost during loopback testing. Reference
the section titled “Loopback Tests” for more information.
If the subscriber is on hook when the state is entered, the
SLIC’s tip and ring voltages are the same as the Reverse
Active state. The SHD output will go low when the subscriber
goes off hook and the GKD_LVM output is disabled (TTL
level high). (Note: operation is the same as the Reverse
Active state with the GKD_LVM output disabled.)
If the subscriber is off hook when the state is entered, a Line
Voltage Measurement test is performed. The output of the
GKD_LVM pin is a pulse train. The pulse width of the active low
portion of the signal is proportional to the voltage across the tip
and ring pins. If the loop length is such that the SLIC is
operating in constant current, the tip to ring voltage can be used
to determine the length of the line under test. The longer the
line, the larger the tip to ring voltage and the wider the pulse.
This relationship can determine the length of the line for setting
gains in the system. Reference the section titled “Operation of
Line Voltage Measurement” for more information.
If the subscriber is off hook when the state is entered, a
Line Voltage Measurement test is performed.
The output of the GKD_LVM pin is a pulse train. The pulse width
of the active low portion of the signal is proportional to the voltage
across the tip and ring pins. If the loop length is such that the
SLIC is operating in constant current mode, the tip to ring voltage
can be used to determine the length of the line under test. The
longer the line, the larger the tip to ring voltage and the wider the
pulse. This relationship can determine the length of the line for
setting gains in the system. Reference the section titled
“Operation of Line Voltage Measurement” for more information.
20
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
The ring relay driver pin, RRLY, has an internal clamp
between it’s output and ground. This eliminates the need to
place an external snubber diode across the ring relay.
Thermal Shutdown
The UniSLIC14’s thermal shutdown protection is invoked if a
fault condition causes the junction temperature of the die to
o
exceed about 175 C. Once the thermal limit is exceeded,
Reducing Impulse Noise During Ringing
both detector outputs go low (SHD and GKD_LVM) and one
of two things can happen.
With an increase in digital data lines being installed next to
analog lines, the threat from impulse noise on analog lines is
increasing. Impulse noise can cause large blocks of high
speed data to be lost, defeating most error correcting
techniques. The UniSLIC14 family has the capability to
reduce impulse noise by closing the ring relay at zero
voltage and opening the ring relay at zero current.
For marginal faults where loop current is flowing during the
time of the over-temperature condition, foldback loop current
limiting reduces the loop current by reducing the tip to ring
voltage. An equilibrium condition will exist that maintains the
o
junction temperature at about 175 C until the fault condition
is removed.
CLOSING THE RING RELAY AT ZERO VOLTAGE
For short circuit faults (tip or ring to ground, or to a supply,
etc.) that result in an over-temperature condition, the
foldback current limiting will try to maintain an equilibrium at
Closing the ring relay at zero voltage is accomplished by
providing a ring sync pulse to the RSYNC_REV pin. The ring
sync pulse is synchronized to go low at the zero voltage
crossing of the ring signal. The resistor R1 in Figure 18 limits
the current into the RSYNC_REV pin. If a particular polarity
reversal time is required, then make R1 equal to the
calculated value in Equation 39. If a specific polarity reversal
time is not desired, R1 equal to 50kΩ is suggested.
o
about 175 C. If the junction temperature keeps rising, the
device will thermally shutdown and disconnect tip and ring
o
until the junction temperature falls to approximately 150 C.
Supervisory Functions
Switch Hook Detect Threshold
The RSYNC_REV pin is designed to allow the ring sync
pulse to be present at all times. There is no need to gate the
ring sync pulse on and off. The logic control for the
RSYNC_REV pin cannot be an open collector. It must be
high (push-pull logic output stage / pull up resistor to VCC),
low or being clocked by the ring sync pulse. When the
RSYNC_REV pin is high the ring relay pin is disabled. When
the RSYNC_REV pin is low the ring relay pin is activated the
instant the logic code for ringing is applied.
The Switch Hook Detect Threshold is programmed with a
single external resistor (R ). The output of the SHD pin goes
D
low when an off hook condition is detected.
Ground Key Detect Threshold
The Ground Key Detect Threshold is set internally and is not
user programmable.
Ringing the Phone
OPENING THE RING RELAY AT ZERO CURRENT
The UniSLIC14 family handles all the popular ringing
formats with high or low side ring trip detection. High side
detection is possible because of the high common mode
range on the ring signal detect input pins (DT, DR). To
minimize power drain from the ring generator, when the
phone is not being rung, the sense resistors are typically
2MΩ. This reduces the current draw from the ring generator
to just a few microamps.
The ring relay is automatically opened at zero current by the
SLIC. The SLIC logic requires zero ringing current in the
loop and either a valid switch hook detect (SHD) or a change
in the operating mode (cadence of the ringing signal) to
release the ring relay.
UniSLIC14
INPUT FOR THE
RING SYNC PULSE
R
50kΩ
1
When the subscriber goes off hook during ringing, the
UniSLIC14 family automatically releases the ring relay and
DC feed is applied to the loop. The UniSLIC14 family has
very low power dissipation in the on hook active mode. This
enables the SLIC (during the ring cadence) to be powered
up in the active state, avoiding unnecessary powering up
and down of the SLIC. The control logic is designed to
facilitate easy implementation of the ring cadence, requiring
only one bit change to go from active to ringing and back
again.
24
RSYNC_REV
5V
0V
FIGURE 18. REDUCING IMPULSE NOISE USING THE
RSYNC_REV PIN AND SETTING THE POLARITY
REVERSAL TIME
If the subscriber goes off hook during ringing, the SHD
output will go low. An internal latch will sense SHD is low
and disable the ring relay at zero ringing current. This
prevents the ring signal from being reapplied to the line. To
ring the line again, the SLIC must toggle between logic
states. (Note: The previous state can not be the Reverse
Active State. In the reverse state, the voltage on the
DT, DR AND RRLY INPUTS
Ring trip detection will occur when the DR pin goes more
positive than DT by approximately 4V.
21
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
CRT_REV_LVM capacitor will activate an internal latch
prohibiting the ringing of the line.
active state (forward or reverse) and the subscriber is
unaware the measurement is being taken.
Figure 19 shows the sequence of events from ringing the
phone to ring trip. The ring relay turns on when both the
ringing code and ring sync pulse are present (A). SHD is
high at this point. When the subscriber goes off hook the
SHD pin goes low and stays low until the ringing control
code is removed (B). This prevents the SHD output from
pulsing after ring trip occurs. At the next zero current
crossing of the ring signal, ring trip occurs and the ring relay
releases the line to allow loop current to flow in the loop (C).
RING
GEN
FREQ
UniSLIC14
GKD_LVM
TIP
RING
DR
PULSE WIDTH
PROPORTIONAL TO
LOOP LENGTH
DT
RING
GEN
LOOP LENGTH
RINGING VOLTAGE
FIGURE 20. OPERATION OF THE LINE VOLTAGE
MEASUREMENT CIRCUIT
RING SYNC
PULSE
(A)
Polarity Reversal
RINGING CODE
APPLIED
Most of the SLICs in the UniSLIC14 family feature full
polarity reversal. Full polarity reversal means that the SLIC
can: transmit, determine the status of the line (on hook and
off hook) and provide “silent” polarity reversal. The value of
RSYNC_REV resistor is limited between 34.8k (10ms) and
73.2k (21ms). Reference Equation 39 to program the polarity
reversal time.
(B)
SHD OUTPUT
RINGING CURRENT
IN LINE
(C)
RELAY DRIVER
FIGURE 19. RINGING SEQUENCE
OFF
ON
OFF
Transhybrid Balance
If a low cost CODEC is chosen that does not have a transmit
op-amp, the UniSLIC14 family of SLICs can solve this
problem without the need for an additional op-amp. The
solution is to use the Programmable Transmit Gain pin (PTG)
Operation of Line Voltage Measurement
A few of the SLICs in the UniSLIC14 family feature Line
Voltage Measurement (LVM) capability. This feature
provides a pulse on the GKD_LVM output pin that is
proportional to the loop voltage. Knowing the loop voltage
and thus the loop length, other basic cable characteristics
such as attenuation and capacitance can be inferred.
Decisions can be made about gain switching in the CODEC
to overcome line losses and verification of the 2-wire circuit
integrity.
as an input for the receive signal (V ). In theory, when the
RX
PTG pin is connected to a divider network (R1 and R2
Figure 21) and the value of R1 and R2 is much less than the
internal 500kΩ resistors, two things happen. First the transmit
gain from V to V is reduced by half. This is the result of
RX TX
shorting out the bottom 500kΩ resistor with the much smaller
external resistor. And second, the input signal from V is
RX
also decreased by the voltage divider R1 and R2. Transhybrid
balance occurs when these two, equal but opposite in phase,
signals are cancelled at the input to the output buffer. The
calculation of the value of R2, once R1 is selected, is effected
by the line feed resistors. EQ. 40 can be used to calculate the
The LVM function can only be activated in the off hook
condition in either the forward or reverse operating states. The
LVM uses the ring signal supplied to the SLIC as a timebase
generator. The loop resistance is determined by monitoring
the pulse width of the output signal on the GKD_LVM pin. The
output signal on the GKD_LVM pin is a square wave for which
the average duration of the low state is proportional to the
average voltage between the tip and ring terminals. The loop
resistance is determined by the tip to ring voltage and the
constant loop current. Reference Figure 20.
value of R2. Where : Z = Line Impedance, Z = input
L
TR
impedance of SLIC including the protection resistor, and
RP = protection resitors (typical 30Ω).
·
·
R II500K
1
1.02
Z
+ Z
R II500K
1
1.02
L
TR
R
= -------------------------- ----------------------------- – --------------------------
(EQ. 40)
2
Z
+ 2ZR
L
P
Although the logic state changes to the Test Active State
when performing this test, the SLIC is still powered up in the
22
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
network (including SLIC) to be tested up to the subscriber
loop.
V
-
TX
+
-
TX
+
500K
500K
A = 1
V
I
X
Pulse Metering
PTG
R1
The HC55121, HC55142, HC35143, HC55150 and the
HC55151 are designed to support pulse metering. They offer
solutions to the following pulse metering design issues:
R2
I
X
500K
V
RX
1) Providing adequate signal gain and current drive to the
subscriber metering equipment to overcome the attenuation
of this (12kHz, 16kHz) out of band signal.
+
RX
-
500K
V
5
UniSLIC14
2) Attenuating the pulse metering transhybrid signal without
severely attenuating the voice band signal to avoid clipping
in the CODEC/Filter.
FIGURE 21. TRANSHYBRID BALANCE USING THE PTG PIN
Loopback Tests
3) Tailoring the overload levels in the SLIC to avoid clipping
of the combined voiceband and pulse metering signal.
4-Wire Loopback Test
This feature can be very useful in the testing of line cards
during the manufacturing process and in field use. The test
is unobtrusive, allowing it to be used in live systems.
Reference Figure 22.
4) Having the provision of silent polarity reversal as a backup
in the case where the loop attenuates the out of band signal
too much for it to be detected by the subscriber’s metering
equipment.
Most systems do not provide 4-wire loopback test capability
because of costly relays needed to switch in external loads.
All the SLICs in the UniSLIC14 family can easily provide
this function when configured in the Open Circuit logic
Adequate Signal Gain
Adequate signal gain and current drive to the subscriber’s
metering equipment is made easier by the network shown in
Figure 23. The pulse metering signal is supplied to a
dedicated high impedance input pin called SPM. The circuit
in Figure 23 shows the connection of a network that sets the
state. With the PTG pin floating, the signal on the V
o
TX
output is 180 out of phase and approximately 2 times the
V
input signal. If the PTG pin is grounded, then the
RX
2-wire impedance (Z ), at the pulse metering frequencies,
amplitude will be approximately the same as the input
signal and 180 out of phase.
TR
o
to be approximately 200Ω. If the line impedance (Z ) is
L
equal to 200Ω at the pulse metering frequencies, then the 4-
Wire to 2-wire gain (V / SPM) is equal 4. Thereby lowering
TR
V
UniSLIC14
TX
the input signal requirements of the pulse metering signal.
TIP
-
+
Note: The automatic pulse metering 2-wire impedance
matching is independent of the programmed 2-wire
impedance matching at voiceband frequencies.
PTG
INTERNAL
600Ω
DUAL SUPPLY
CODEC/FILTER
RING
V
RX
Calculation of the pulse metering gain is achieved by
replacing V /500k in Equation 15 with SPM/125k and
2-WIRE LOOPBACK
4-WIRE LOOPBACK
RX
following the same process through to Equation 21. The
UniSLIC14 sets the 2-wire input impedance of the SLIC
FIGURE 22. 4-WIRE AND 2-WIRE LOOPBACK TESTS
(Z ), including the protection resistors, equal to 200Ω. The
results are shown in Equation 41.
TR
2-Wire Loopback Test
Most of the SLICs in the UniSLIC14 family feature 2-Wire
loopback testing. This loopback function is only activated
when the subscriber is on hook and the logic command to
the SLIC is in the Test Active State. (Note: if the subscriber
is off hook and in the Test Active State, the function
performed is the Line Voltage Measurement.)
V
Z
L
+ Z
200
200 + 200
TR
SPM
A
= ------------- = –8------------------------- = –8--------------------------- = –4
(EQ. 41)
4-2
Z
L
TR
Avoiding Clipping in the CODEC/Filter
The amplitude of the returning pulse metering signal is often
very large and could easily over drive the input to the
CODEC/Filter. By using the same method discussed in
section “Transhybrid Balance”, most if not all of the pulse
metering signal can be canceled out before it reaches the
input to the CODEC/Filter. This connection is shown in
Figure 23.
During the 2-wire loopback test, a 2kΩ internal resistor is
switched across the tip and ring terminals of the SLIC. This
allows the SHD function and the 4-wire to 4-wire AC
transmission, right up to the subscriber loop, to be tested.
Together with the 4-wire loopback test in the Open Circuit
logic state, this 2-wire loopback test allows the complete
23
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
of the CODEC/Filter, one of the DC blocking capacitors can
be eliminated (Figure 24B).
Overload Levels and Silent Polarity Reversal
The pulse metering signal and voice are simultaneously
transmitted, and therefore require additional overhead to
prevent distortion of the signal. Reference section “Off hook
Overhead Voltage” to account for the additional pulse
metering signal requirements.
V
TX
-
+
-
+
A = 1
DUAL SUPPLY
CODEC/FILTER
5V
V
V
OUT
RX
GND
-5V
UniSLIC14
FIGURE 24A.
V
V
TX
-
+
IN
500K
A = 1
PTG
V
V
SINGLE SUPPLY
DSP
CODEC/FILTER
REF
FIGURE 23. PULSE METERING WITH TRANSHYBRID
BALANCE
500K
5V
V
RX
OUT
GND
Most of the SLICs in the UniSLIC14 family feature full
polarity reversal. Full polarity reversal means that the SLIC
can: transmit, determine the status of the line (on hook and
off hook) and provide “silent” polarity reversal. Reference
Equation 39 to program the polarity reversal time.
UniSLIC14
FIGURE 24B.
FIGURE 24. INTERFACE TO DUAL AND SINGLE SUPPLY
CODECs
Interface to Dual and Single Supply
CODECs
Power Management
Great care has been taken to minimize the number of external
components required with the UniSLIC14 family while still
providing the maximum flexibility. Figures 24A, 24B) shows
the connection of the UniSLIC14 to both a dual supply
CODEC/Filter and a single supply DSP CODEC/Filter.
The UniSLIC14 family provides two distinct power
management capabilities:
Power Sharing and Battery Selection
Power Sharing
Power sharing is a method of redistributing the power away
from the SLIC in short loop applications. The total system
power is the same, but the die temperature of the SLIC is
much lower. Power sharing becomes important if the
application has a single battery supply (-48V on hook
requirements for faxes and modems) and the possibility of
high loop currents (reference Figure 25). This technique
would prevent the SLIC from getting too hot and thermally
shutting down on short loops.
To eliminate the DC blocking capacitors between the SLIC
and the CODEC/Filter when using a dual supply
CODEC/Filter, both the receive and transmit leads of the
SLIC are referenced to ground. This leads to a very simple
SLIC to CODEC/Filter interface, as shown in Figure 24A.
When using a single supply DSP CODEC/Filter the output
and input of the CODEC/Filter are no longer referenced to
ground. To achieve maximum voltage swing with a single
supply, both the output and input of the CODEC/Filter are
The power dissipation in the SLIC is the sum of the smaller
quiescent supply power and the much larger power that
results from the loop current. The power that results from the
loop current is the loop current times the voltage across the
referenced to its own V /2 reference. Thus, DC blocking
capacitors are once again required. By using the PTG pin of
the UniSLIC14 and the externally supplied V /2 reference
CC
CC
SLIC. The power sharing resistor (R ) reduces the voltage
PS
across the SLIC, and thereby the on-chip power dissipation.
The voltage across the SLIC is reduced by the voltage drop
across R . This occurs because R is in series with the
PS PS
loop current and the negative supply.
24
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
A mathematical verification follows:
Given: V = V = -48V, Loop current = 30mA, R (load
across tip and ring) = 600Ω, Quiescent battery power =
(48V) (0.8mA) = 38.4mW, Quiescent VCC power = (5V)
(2.7mA) = 13.5mW, Power sharing resistor = 600Ω.
Battery Selection
Battery selection is a technique, for a two battery supply
system, where the SLIC automatically diverts the loop
current to the most appropriate supply for a given loop
length. This results in significant power savings and lowers
the total power consumption on short loops. This technique
is particularly useful if most of the lines are short, and the on
hook condition requires a -48V battery. In Figure 26, it can
be seen that for long loops the majority of the current comes
BH
BL
L
1. Without power sharing, the on-chip power dissipation
would be 952mW (Equation 42).
2. With power sharing, the on-chip power dissipation is
412mW (Equation 43). A power redistribution of 540mW.
from the high battery supply (V ) and for short loops from
BH
On-chip power dissipation without power sharing resistor.
the low battery supply (V ).
BL
2
PD = (V )(30mA) + 38.4mW + 13.5mW – (RL)(30mA)
40
35
BH
(EQ. 42)
PD = 952mW
V
BL
V
BH
30
25
On-chip power dissipation with 600Ω power sharing resistor.
PD = (V )(30mA) + 38.4mW + 13.5mW
VBH = -48V
BH
20
15
VBL = -24V
RILim = 33.2kΩ
2
2
– (R )(30mA) – (R )(30mA)
L
PS
(EQ. 43)
PD = 412mW
10
5
0
V
BL
V
BH
UniSLIC14
TIP
V
TX
LOOP RESISTANCE (Ω)
RING
V
RX
FIGURE 26. BATTERY SELECTION (DUAL SUPPLY SYSTEMS)
ON SHORT LOOPS, THE
MAJORITY OF CURRENT
V
V
BH
FLOWS OUT THE V PIN
BL
BL
R
PS
-48V
-48V
FIGURE 25. POWER SHARING (SINGLE SUPPLY SYSTEMS)
Pinouts - 28 Lead PLCC Packages
HC55120
(28 LEAD PLCC)
TOP VIEW
HC55121
(28 LEAD PLCC)
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
AGND
RSYNC
ILIM
5
6
7
8
9
RING
BGND
TIP
RING
BGND
TIP
25 AGND
5
6
7
8
9
25
24
23
22
21
20
24 RSYNC_REV
ILIM
ROH
RD
23
22
21
20
ROH
RD
VBH
VBL
VBH
VBL
V
V
RDC_RAC 10
CRT_REV
RDC_RAC 10
CRT
CC
CC
11
19 GKD
11
19 GKD
12 13 14 15 16 17 18
12 13 14 15 16 17 18
25
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Pinouts - 28 Lead PLCC Packages (Continued)
HC55130
(28 LEAD PLCC)
TOP VIEW
HC55140
(28 LEAD PLCC)
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
RING
BGND
TIP
AGND
AGND
RSYNC
ILIM
5
6
25
24
5
6
25
24
23
22
21
20
19
RING
BGND
TIP
RSYNC_REV
7
23 ILIM
7
ROH
RD
VBH
8
8
VBH
22
21
20
19
ROH
RD
VBL
9
9
VBL
V
RDC_RAC
CRT
10
11
CC
10
11
RDC_RAC
V
CC
CRT_REV_
LVM
NC
GKD_LVM
12 13 14 15 16 17 18
12 13 14 15 16 17 18
HC55142
(28 LEAD PLCC)
TOP VIEW
HC55150
(28 LEAD PLCC)
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
RING
BGND
TIP
RING
BGND
TIP
AGND
RSYNC_REV
ILIM
5
6
25
24
23
22
21
20
19
5
6
25
24
23
22
21
20
19
AGND
RSYNC_REV
ILIM
7
7
ROH
ROH
8
VBH
8
VBH
RD
RD
9
9
VBL
VBL
V
V
10
11
10
11
RDC_RAC
RDC_RAC
CC
CC
CRT_REV_
LVM
LVM
GKD_LVM
CRT_REV_
LVM
12 13 14 15 16 17 18
12 13 14 15 16 17 18
26
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Pinouts - 32 Lead PLCC Packages
HC55131
(32 LEAD PLCC)
TOP VIEW
HC55141
(32 LEAD PLCC)
TOP VIEW
4
3
2
1
32 31 30
4
3
2
1
32 31 30
NC
NC
RING
BGND
TIP
RING
BGND
29
29
5
6
5
6
28 VRX
28 VRX
AGND
AGND
TIP
27
26
25
24
23
22
21
27
26
25
24
23
22
21
7
7
RSYNC
ILIM
RSYNC_REV
ILIM
VBH
VBH
8
8
VBL
VBL
9
9
ROH
RD
ROH
RDC_RAC
CRT
RDC_RAC
CRT_REV_LVM
CDC
10
11
12
13
10
11
12
13
RD
V
CC
V
CC
CDC
NC
GKD_LVM
DT
DT
14 15 16 17 18 19 20
14 15 16 17 18 19 20
HC55143
(32 LEAD PLCC)
TOP VIEW
HC55151
(32 LEAD PLCC)
TOP VIEW
4
3
2
1
32 31 30
4
3
2
1
32 31 30
SPM
SPM
RING
BGND
TIP
29
RING
BGND
TIP
29
28
27
26
25
24
23
22
21
5
6
5
6
28 VRX
VRX
AGND
AGND
27
26
25
24
23
22
21
7
7
RSYNC_REV
ILIM
RSYNC_REV
ILIM
VBH
VBH
8
8
VBL
9
VBL
9
RDC_RAC
ROH
RDC_RAC
ROH
10
11
12
13
10
11
12
CRT_REV_
LVM
CRT_REV_
LVM
RD
RD
V
CC
V
CDC
CC
CDC
LVM
GKD_LVM
DT
DT 13
14 15 16 17 18 19 20
14 15 16 17 18 19 20
27
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Pinouts - 28 Lead SOIC Packages
HC55120
(28 LEAD SOIC)
TOP VIEW
HC55121
(28 LEAD SOIC)
TOP VIEW
ZT
PTG
RRLY
CH
1
2
3
4
5
6
7
8
9
28 AGND
27 VTX
26 NC
ZT
PTG
RRLY
CH
1
2
3
4
5
6
7
8
9
28 AGND
27 VTX
26 SPM
25 VRX
24 RSYNC
23 ILIM
22 ROH
21 RD
25 VRX
RING
BGND
TIP
RING
BGND
TIP
24 RSYNC_REV
23 ILIM
22 ROH
21 RD
VBH
VBL
VBH
VBL
20
20
V
V
CC
CC
RDC_RAC 10
CDC 11
DT 12
19 SHD
18 C1
RDC_RAC 10
CDC 11
19 SHD
18 C1
17 C2
17 C2
DT 12
16 C3
16 C3
DR 13
DR 13
CRT 14
15 GKD
CRT_REV 14
15 GKD
HC55130
(28 LEAD SOIC)
TOP VIEW
HC55140
(28 LEAD SOIC)
TOP VIEW
ZT
PTG
RRLY
CH
1
2
3
4
5
6
7
8
9
28 AGND
27 VTX
26 NC
ZT
PTG
RRLY
CH
1
2
3
4
5
6
7
8
9
28 AGND
27 VTX
26 NC
25 VRX
24 RSYNC
23 ILIM
25 VRX
RING
BGND
TIP
RING
BGND
TIP
24 RSYNC_REV
23 ILIM
ROH
ROH
22
21 RD
20
22
21 RD
20
VBH
VBL
VBH
VBL
V
V
CC
CC
RDC_RAC 10
CDC 11
DT 12
19 SHD
18 C1
17 C2
16 C3
15 NC
RDC_RAC 10
CDC 11
19 SHD
18 C1
DT 12
17 C2
DR 13
DR 13
16 C3
CRT 14
CRT_REV_LVM 14
15 GKD_LVM
28
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Pinouts - 28 Lead SOIC Packages (Continued)
HC55142
(28 LEAD SOIC)
TOP VIEW
HC55150
(28 LEAD SOIC)
TOP VIEW
ZT
PTG
RRLY
CH
1
2
3
4
5
6
7
8
9
28 AGND
27 VTX
ZT
PTG
RRLY
CH
1
2
3
4
5
6
7
8
9
28 AGND
27 VTX
26 SPM
26 SPM
25 VRX
25 VRX
RING
BGND
TIP
24 RSYNC_REV
23 ILIM
RING
BGND
TIP
24 RSYNC_REV
23 ILIM
ROH
ROH
22
21 RD
20
22
21 RD
20
VBH
VBL
VBH
VBL
V
V
CC
CC
RDC_RAC 10
CDC 11
19 SHD
18 C1
RDC_RAC 10
CDC 11
19 SHD
18 C1
17 C2
17 C2
DT 12
DT 12
DR 13
16 C3
DR 13
16 C3
CRT_REV_LVM 14
15 GKD_LVM
CRT_REV_LVM 14
15 LVM
Pin Descriptions
28
32
28
PIN
PIN
PIN
PLCC PLCC SOIC
SYMBOL
DESCRIPTION
1
1
2
PTG
Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating
and -6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is
used. See Figure 23.
2
3
2
3
3
4
RRLY
CH
Ring Relay Driver Output - The relay coil may be connected to a maximum of 14V.
AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop
current. Recommended value 0.1µF.
4
4
1
ZT
2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing
an impedance between the ZT pin and ground. See Equation 32.
5
6
5
6
5
6
RING
BGND
TIP
Connects via protection resistor R to ring wire of subscriber pair.
P
Battery ground.
7
7
7
Connects via protection resistor R to tip wire of subscriber pair.
P
8
8
8
V
High Battery Supply (negative with respect to GND).
BH
9
9
9
V
Low Battery Supply (negative with respect to GND, magnitude ≤ V ).
BL
BH
10
10
10
RDC_RAC
Resistive Feed/Anti Clipping - Performs anti clipping function on constant current application and sets
the slope of the resistive feed curve for constant voltage applications.
11
11
14
CRT_REV
_LVM
Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between the
CRT_REV_LVM pin and +5V performs 3 mutually exclusive functions. When the SLIC is configured in the
Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC is transitioning
between the Forward Active State and Reverse Active State it provides Soft Polarity Reversal and
performs charge storage in the Line Voltage Measurement State. Recommended value 0.47µF.
12
13
12
13
11
12
CDC
DT
Filter Capacitor - The CDC Capacitor removes the VF signals from the battery feed control loop.
Tip side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network
to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more
negative than the voltage on DR.
14
-
14
15
13
-
DR
C5
Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external
network to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is
more positive than the voltage on DT.
Activates Test Relay TRLY2. TTL Compatible Logic Input. C5 input high, test relay TRLT2 Low(ON).
C5 input floating, test relay TRLY2 High(OFF). This is due to an internal 100kΩ pull down resistor.
29
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Pin Descriptions (Continued)
28
32
28
PIN
PIN
PIN
PLCC PLCC SOIC
SYMBOL
DESCRIPTION
-
16
17
18
19
-
C4
Activates Test Relay TRLY1. TTL Compatible Logic Input. C4 input high, test relay TRLT1 Low(ON).
C4 input floating, test relay TRLY1 High(OFF). This is due to an internal 100kΩ pull down resistor.
15
16
17
16
17
18
C3
C2
C1
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
18
19
20
21
20
21
22
23
19
15
20
21
SHD
Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details.
Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details.
5V Supply.
GKD_LVM
V
CC
RD
ROH
ILIM
Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the
trigger level for the loop current detect circuit. See Equation 7.
22
23
24
24
25
26
22
23
24
Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering
signals. See Equation 10.
Current Limit Programming Pin - A resistor between this pin and ground will determine the constant
current limit of the feed curve. See Equation 11.
RSYNC_REV Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND
determines the polarity reversal time. Synchronization of the closing of the relay at zero voltage is
achieved via a ring sync pulse (5V to 0V) synchronized to the ring signal zero voltage crossing
(Reference Figure 18).
25
26
27
27
28
29
28
25
26
AGND
VRX
Analog ground
Receive Input - Ground referenced 4-wire side.
SPM
Pulse Metering Signal Input. If pulse metering is not used, then this pin should be grounded as close
to the device pin as possible. Input impedance to ground = 125kΩ.
28
-
30
31
27
-
VTX
Transmit Output - Ground referenced 4-wire side.
TRLY2
Test Relay Driver 2. Open Collector Transistor. Internal Clamp between it’s output and ground
elimnates the need to place an external snubber diode across Test Relay Driver. TRLY2 may be
connected to maximum of 14V.
-
32
-
TRLY1
Test Relay Driver 1. Open Collector Transistor. Internal Clamp between it’s output and ground
elimnates the need to place an external snubber diode across Test Relay Driver. TRLY1 may be
connected to maximum of 14V.
30
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Basic Application Circuit
Voice Only 28 Lead PLCC Package
R
11
+5V
C
††C10
20
†R
9
28
V
U1
+5V OR
+12V
CC
V
TX
1
2
3
RELAY
RRLY
CH
1
PTG
SPM
27
C
†R
2
10
††C11
RING
TIP
R
P
26
5
6
V
RING
RX
C
U2
8
25
4
AGND
ZT
BGND
CODEC/FILTER
R
R
R
R
R
8
7
6
5
4
24
23
22
† PERFORM TRANSHYBRID BALANCE
WHEN USING A NON-DSP CODEC.
NOT REQUIRED FOR DSP CODEC.
C
R
P
9
RSYNC_REV
7
8
TIP
D
1
ILIM
ROH
RD
VBH
-24V
-48V
OPTIONAL
†† NOT REQUIRED FOR
NON-DSP CODEC’s.
C7
9
VBL
21
18
REQUIRED FOR DSP CODEC’s
C
5
R
1
10
12
13
RDC_RAC
CDC
SHD
C
R
+
-
6
19
17
16
GKD_LVM
C1
R
2
C
3
DT
12
14
11
C2
DR
15
C3
CRT_REV_LVM
R
3
RING
GENERATOR
C
4
VBAT
CONTROL LOGIC
+5V
FIGURE 27. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT
TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
RATING
N/A
U1 - SLIC
N/A
N/A
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
RP (Line Feed Resistors)
Matched 1%
1%
2.0W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
2W
R1 (RDC_RAC Resistor)
21kΩ
R2, R3
2MΩ
1%
R4 (RD Resistor)
41.2kΩ
38.3kΩ
33.2kΩ
34.8kΩ
107kΩ
1%
R5 (ROH Resistor)
1%
R6 (RILIM Resistor)
1%
R7 (RSYNC_REV Resistor)
1%
R8 (RZT Resistor)
1%
R9, R10, R11
20kΩ
1%
R12
400Ω
5%
C1 (Supply Decoupling), C2
0.1µF
20%
20%
20%
20%
20%
20%
-
10V
C5 (Supply Decoupling)
0.1µF
50V
C6 (Supply Decoupling)
0.1µF
100V
10V
C4, C7, C10, C11
0.47µF
4.7µF
C3
50V
C8, C9
2200pF
1N4004
100V
-
D1, Recommended if the VBL supply is not derived from the VBH Supply
Design Parameters: Maximum on hook voltage = 0.775V
, Maximum Off hook Voice = 3.2V
RMS
, Switch Hook Threshold = 12mA, Loop Current
PEAK
Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection resistors, impedance across Tip and Ring terminals = 600Ω.
Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3
and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
31
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Basic Application Circuit
Pulse Metering 28 Lead PLCC Package
R
11
+5V
C
††C10
20
†R
9
28
1
+5V OR
+12V
V
U1
CC
V
TX
1
2
3
PTG
RELAY
RRLY
CH
27
SPM
VRX
†R
10
C
††C11
2
RING
TIP
R
26
25
P
5
6
RING
C
U2
D
8
AGND
CODEC/FILTER
BGND
R
R
R
R
R
8
7
6
5
4
4
ZT
24
23
22
R
C
P
9
RSYNC_REV
ILIM
7
8
12/16kHz
PULSE METERING
INPUT SIGNAL
TIP
-24V
-48V
1
VBH
† PERFORM TRANSHYBRID BALANCE
WHEN USING A NON-DSP CODEC.
NOT REQUIRED FOR DSP CODEC.
OPTIONAL
R
C
5
OH
9
C7
VBL
21
18
RD
C
6
R
1
10
12
RDC_RAC
CDC
SHD
+
-
†† NOT REQUIRED FOR
NON-DSP CODEC’s.
19
17
16
GKD_LVM
C1
R
2
C
3
13
REQUIRED FOR DSP CODEC’s
DT
RING
R
12
14
11
GENERATOR
C2
DR
15
V
R
3
BAT
C3
CRT_REV_LVM
C
CONTROL LOGIC
4
+5V
FIGURE 28. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT
TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
RATING
N/A
U1 - SLIC
N/A
N/A
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
RP (Line Feed Resistors)
Matched 1%
1%
2.0W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
2W
R1 (RDC_RAC Resistor)
26.1kΩ
2MΩ
R2, R3
1%
R4 (RD Resistor)
41.2kΩ
38.3kΩ
33.2kΩ
34.8kΩ
107kΩ
1%
R5 (ROH Resistor)
1%
R6 (RILIM Resistor)
1%
R7 (RSYNC_REV Resistor)
1%
R8 (RZT Resistor)
1%
R9, R10, R11
20kΩ
1%
R12
400Ω
5%
C1 (Supply Decoupling), C2
0.1µF
20%
20%
20%
20%
20%
20%
-
10V
C5 (Supply Decoupling)
0.1µF
50V
C6 (Supply Decoupling)
0.1µF
100V
10V
C4, C7, C10, C11
0.47µF
4.7µF
C3
50V
C8, C9
2200pF
1N4004
100V
-
D1, Recommended if the VBL supply is not derived from the VBH Supply
Design Parameters: Maximum on hook voltage = 0.775V
, Maximum off hook voice = 1.1V
RMS
, Maximum simultaneous pulse metering
PEAK
signal = 2.2V
, Switch Hook Threshold = 12mA, Loop Current Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω
RMS
protection resistors, impedance across Tip and Ring terminals = 600Ω. Where applicable, these component values apply to the Basic Application
Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3 and HC55150/1. Pins not shown in the Basic Application Circuit are
no connect (NC) pins.
32
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Basic Application Circuit - Voice Only 28 Lead SOIC Package
R
11
+5V
††C10
20
†R
9
27
V
+5V OR
+12V
U1
CC
V
C
TX
1
3
4
RELAY
RRLY
CH
26
25
SPM
C
†R
10
2
††C11
RING
R
R
P
5
6
V
RING
RX
C
U2
8
28
1
AGND
ZT
CODEC/FILTER
BGND
R
R
R
R
R
8
7
6
5
4
24
23
22
21
TIP
† PERFORM TRANSHYBRID BALANCE
WHEN USING A NON-DSP CODEC.
NOT REQUIRED FOR DSP CODEC.
C
P
9
RSYNC_REV
ILIM
7
8
TIP
D
1
V
V
BH
BL
OPTIONAL
-24V
-48V
R
†† NOT REQUIRED FOR
NON-DSP CODEC’s.
OH
9
C7
RD
REQUIRED FOR DSP CODEC’s
C
R
5
1
10
11
19
15
18
17
RDC_RAC
CDC
SHD
C
+
-
6
GKD_LVM
C1
R
2
C
3
12
13
14
DT
R
12
C2
DR
16
R
RING
GENERATOR
C3
3
CRT_REV_LVM
C
4
V
BAT
CONTROL LOGIC
+5V
FIGURE 29. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT
TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
RATING
N/A
U1 - SLIC
N/A
N/A
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
RP (Line Feed Resistors)
Matched 1%
1%
2.0W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
1/16W
2W
R1 (RDC_RAC Resistor)
21kΩ
R2, R3
2MΩ
1%
R4 (RD Resistor)
41.2kΩ
38.3kΩ
33.2kΩ
34.8kΩ
107kΩ
1%
R5 (ROH Resistor)
1%
R6 (RILIM Resistor)
1%
R7 (RSYNC_REV Resistor)
1%
R8 (RZT Resistor)
1%
R9, R10, R11
20kΩ
1%
R12
400Ω
5%
C1 (Supply Decoupling), C2
0.1µF
20%
20%
20%
20%
20%
20%
-
10V
C5 (Supply Decoupling)
0.1µF
50V
C6 (Supply Decoupling)
0.1µF
100V
10V
C4, C7, C10, C11
0.47µF
4.7µF
C3
50V
C8, C9
2200pF
1N4004
100V
-
D1, Recommended if the VBL supply is not derived from the VBH Supply
Design Parameters: Maximum on hook voltage = 0.775V
, Maximum Off hook Voice = 3.2V
RMS
, Switch Hook Threshold = 12mA, Loop Current
PEAK
Limit = 31mA, Synthesize Device Impedance = 540Ω (600 - 60), with 30Ω protection resistors, impedance across Tip and Ring terminals = 600Ω.
Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130/1, HC55140/1, HC55142/3
and HC55150/1. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
33
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
N
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
17.70
7.40
MAX
2.65
0.30
0.51
0.32
18.10
7.60
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.7125
0.2992
-
-
1
2
3
L
9
SEATING PLANE
A
0.0091
0.6969
0.2914
-
3
-A-
o
h x 45
D
4
0.05 BSC
1.27 BSC
-
-C-
α
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
α
28
28
7
o
0
o
8
o
0
o
8
-
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
34
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.048 (1.22)
N28.45 (JEDEC MS-018AB ISSUE A)
0.042 (1.07)
0.056 (1.42)
0.004 (0.10)
C
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
PIN (1) IDENTIFIER
0.025 (0.64)
0.045 (1.14)
0.050 (1.27) TP
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
4.20
MAX
4.57
NOTES
A
A1
D
0.165
0.090
0.485
0.450
0.191
0.485
0.450
0.191
0.180
0.120
0.495
0.456
0.219
0.495
0.456
0.219
-
2.29
3.04
-
-
D2/E2
D2/E2
12.32
11.43
4.86
12.57
11.58
5.56
C
L
D1
D2
E
3
E1 E
4, 5
-
12.32
11.43
4.86
12.57
11.58
5.56
VIEW “A”
E1
E2
N
3
4, 5
6
0.020 (0.51)
MIN
28
28
A1
D1
D
Rev. 2 11/97
A
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
0.026 (0.66)
0.032 (0.81)
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
0.045 (1.14)
MIN
VIEW “A” TYP.
NOTES:
1. Controlling dimension: INCH. Converted millimeter dimensions are
not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Allowable
mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1
and E1 include mold mismatch and are measured at the extreme
material condition at the body parting line.
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic body.
6. “N” is the number of terminal positions.
35
HC55120,HC55121,HC55130,HC55131,HC55140,HC55141,HC55142,HC55143,HC55150,HC55151
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
N32.45x55 (JEDEC MS-016AE ISSUE A)
PIN (1)
IDENTIFIER
0.056 (1.42)
0.050 (1.27) TP
ND
0.004 (0.10)
C
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
0.042 (1.07)
0.048 (1.22)
0.025 (0.64)
0.045 (1.14)
INCHES
MILLIMETERS
R
C
L
SYMBOL
MIN
MAX
MIN
3.18
MAX
3.55
NOTES
A
A1
D
0.125
0.060
0.485
0.447
0.188
0.585
0.547
0.238
0.140
0.095
0.495
0.453
0.223
0.595
0.553
0.273
-
1.53
2.41
-
D2/E2
D2/E2
12.32
11.36
4.78
12.57
11.50
5.66
-
D1
D2
E
3
C
L
E1
E
4, 5
14.86
13.90
6.05
15.11
14.04
6.93
-
NE
E1
E2
N
3
VIEW “A”
4, 5
28
7
28
7
6
0.015 (0.38)
MIN
ND
NE
7
7
A1
D1
D
9
9
A
SEATING
PLANE
Rev. 0 7/98
0.020 (0.51) MAX
3 PLCS
-C-
NOTES:
0.026 (0.66)
0.032 (0.81)
1. Controlling dimension: INCH. Converted millimeter dimen-
sions are not necessarily exact.
0.050 (1.27)
MIN
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Al-
lowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are mea-
sured at the extreme material condition at the body parting
line.
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
(0.12)
0.005
M
A S - B S D S
-C-
4. To be measured at seating plane
contact point.
5. Centerline to be determined where center leads exit plastic
body.
VIEW “A” TYP.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the num-
ber of leads on the two long sides of the package.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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36
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