HC5515ICM [RENESAS]
TELECOM-SLIC, PQCC28, PLASTIC, LCC-28;
| 型号： | HC5515ICM |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | TELECOM-SLIC, PQCC28, PLASTIC, LCC-28 电信 电信集成电路 |
| 文件： | 总26页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC55120, HC55121, HC55130, HC55131, HC55140,
HC55141, HC55142, HC55143, HC55150, HC55151
Data Sheet
February 1999
File Number 4659
ADVANCE INFORMATION
Low Power Universal SLIC Family
Features
The UniSLIC14 is a family of Ultra Low Power SLICs. The
feature set and common pinouts of the UniSLIC14 family
positions it as a universal solution for: Plain Old Telephone
Service (POTS), PBX, Central Office, Loop Carrier, Fiber in
the Loop, ISDN-TA and NT1+, Pairgain and Wireless Local
• Ultra Low Active Power (OHT) < 60mW
• Low Standby Power < 25mW
• Single/Dual Battery Operation
• Automatic Silent Battery Switching
• Thermal Management/Shutdown
• Battery Tracking Saturation Guard
• Single 5V Supply
[ /Title
(HC55
120,
HC551 Loop.
21,
The UniSLIC14 family achieves it’s ultra low power operation
HC551 through: It’s automatic single and dual battery operation
• Zero Crossing Ring Control
- Zero Voltage On/Zero Current Off
• Tip/Ring Disconnect
• Pulse Metering Capability
• 4 Wire Loopback
• Programmable Constant Current Feed
• Programmable Resistive Feed
• Programmable Loop Detect Threshold
• Programmable On-Hook and Off-Hook Overheads
• Programmable Overhead for Pulse Metering
• Programmable Polarity Reversal Time
• Selectable Transmit Gain 0dB/-6dB
• 2 Wire Impedance Set by Single Network
• Loop and Ground Key Detectors
• On-Hook Transmission
• Common Pinout
• HC55121
- Polarity Reversal
• HC55130
- -63dB Longitudinal Balance
• HC55140
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
- 2 Wire Loopback
(based on line length), low power standby state and battery
30,
HC551
31,
HC551
40,
HC551
41,
HC551
42,
tracking saturation guard to ensure the maximum loop
coverage on the lowest battery voltage. This architecture is
ideal for power critical applications such as ISDN NT1+,
Pairgain and Wireless local loop products.
The UniSLIC14 family has many user programmable
features. This family of SLICs delivers a low noise, low
component count solution for Central Office and Loop
Carrier universal voice grade designs. The product family
integrates advanced pulse metering, test and signaling
capabilities, and zero crossing ring control.
HC551
43,
HC551
50,
HC551
51)
/Sub-
ject
(Low
Power
Uni-
versal
SLIC
Fam-
ily)
The UniSLIC14 family is designed in the Intersil “Latch” free
Bonded Wafer process. This process dielectrically isolates
the active circuitry to eliminate any leakage paths as found in
our competition’s JI process. This makes the UniSLIC14
family compliant with “hot plug” requirements and operation
in harsh outdoor environments.
Block Diagram
RRLY
STATE
DECODER
AND
C1
RING AND TEST
RELAY DRIVERS
C2
C3
TRLY1
TRLY2
DETECTOR
C4
C5
LOGIC
ZERO CURRENT
CROSSING
DT
DR
LOOP CURRENT
DETECTOR
- -63dB Longitudinal Balance
• HC55142
- Polarity Reversal
- Ground Start
- Line Voltage Measurement
SHD
RING TRIP
DETECTOR
GKD/LOOP LENGTH
DETECTOR
GKD_LVM
CRT_REV_LVM
POLARITY
REVERSAL
/Autho
r ()
/Key-
words
(Inter-
sil
- 2.2V
- 2 Wire Loopback
• HC55150
- Polarity Reversal
- Line Voltage Measurement
Pulse Metering
ILIM
RSYNC_REV
ROH
CDC
RDC_RSG
RD
RMS
LINE FEED
CONTROL
TIP
2-WIRE
RING
GND
INTERFACE
- 2.2V
Pulse Metering
RMS
V
V
TX
RX
- 2 Wire Loopback
4-WIRE INTERFACE
VF SIGNAL PATH
Corpo-
ration,
PTG
V
Related Literature
• AN9832, User’s Guide for Development Board
BATTERY
SWITCH
AND
BH
ZT
C
H
V
BL
BIAS
NETWORK
PULSE METERING
SIGNAL PATH
V
CC
ZSPM
SPM
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Ordering Information (PLCC Package Only)
MAX LOOP
LINE VOLTAGE
MEASUREMENT
†
2 WIRE
LOOPBACK
†
TEMP
PART
NUMBER
CURRENT POLARITY GROUND GROUND
(mA)
PULSE
METERING
2 TEST
RELAY DRIVERS
LONGITUDINAL
BALANCE
RANGE
PKG.
NO.
o
REVERSAL START
KEY
( C)
HC55120CM
HC55121IM
HC55130IM
HC55140IM
HC55142IM
HC55150CM
HC5514XEVAL1
30
53dB
53dB
63dB
63dB
53dB
55dB
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
M28.3
N28.45
•
30
45
45
45
45
M28.3
N28.45
•
•
•
•
HC55131IM
HC5514IM
M28.3
N28.45
M28.3
N28.45
•
•
•
•
•
•
•
•
•
•
•
•
•
M28.3
N28.45
HC55143IM
HC5515ICM
•
•
M28.3
N28.45
Evaluation board
† Available by placing SLIC in Test mode.
Device Operating Modes
C3
C2
C1
DESCRIPTION
HC55120
HC55121
HC55130/1
HC55140/1
HC55142/3
HC55150/1
0
0
0
Disconnect Tip and Ring.
Ringing
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
0
0
1
1
1
0
1
Forward Active
Test Forward Active
2 Wire Loopback and
Line Voltage Measurement
•
•
•
•
1
1
1
1
0
0
1
1
0
1
0
1
Tip Open Ground Start
Low Power Standby
Reverse Active
•
•
•
•
•
•
•
•
•
•
•
•
Test Reverse Active
Line Voltage Measurement
•
•
•
2
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
o
Absolute Maximum Ratings T = 25 C
Tip and Ring Terminals
A
Temperature, Humidity
Storage Temperature Range . . . . . . . . . . . . . . . . -65 C to 150 C
Operating Temperature Range. . . . . . . . . . . . . . . -40 C to 110 C
Tipx or Ringx, Current, Pulse < 10ms, T
> 10s . . . . . . . . . .2A
> 10s . . . . . . . . . . .5A
> 10s . . . . . . . . .15A
REP
o
o
Tipx or Ringx, Current, Pulse < 1ms, T
REP
o
o
Tipx or Ringx, Current, Pulse < 10µs, T
REP
o
o
Operating Junction Temperature Range. . . . . . . . -40 C to 150 C
Tipx or Ringx, Current, Pulse < 1µs, T
> 10s . . . . . . . . . .20A
REP
> 10s . . . . . . . . . . . . . . .20A
REP
o
o
Power Supply (-40 C ≤ T ≤ +85 C)
Tipx or Ringx, Pulse < 250ns, T
A
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . . .-.04V to 7V
CC
Supply Voltage V to GND . . . . . . . . . . . . . . . . . . . . -V to 0.4V
BL
BH
BH
BL
Thermal Information
Supply Voltage V
Supply Voltage V
Relay Driver
to GND, Continuous. . . . . . . . . .-75V to 0.4V
to GND, 10ms . . . . . . . . . . . . . .-80V to 0.4V
Thermal Resistance
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . .
28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . TBD C/W
32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . TBD C/W
Continuous Power Dissipation at +85 C
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .TBDW
32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .TBDW
Peak Power Dissipation at 70 C, t<100ms, t
θ
JA
o
53 C/W
o
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 0V to 14V
Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Digital Inputs, Outputs (C1, C2, C3, C4, C5, SHD, GKD_LVM)
o
o
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to V
Output Voltage (SHD, GKD_LVM Not Active). . . . . . -0.4V to V
CC
CC
Output Current (SHD, GKD_LVM) . . . . . . . . . . . . . . . . . . . . . 5mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
Gate Count. . . . . . . . . . . . . . . . . . . . . . . .543 Transistors, 51 Diodes
o
>1 sec
Rep
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .TBDW
28 Lead SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .TBDW
32 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . .TBDW
o
o
Tipx and Ringx Terminals (-40 C ≤ T ≤ 85 C)
A
Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . -100mA to 100mA
o
Lead Temperature (Soldering 10s, PLCC Lead Tips Only) . . . .300 C
o
Derate above 70 C
o
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4mW/ C
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBDW/ C
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER
Ambient Temperature
CONDITIONS
HC55120, HC55150/1
MIN
0
TYP
MAX
70
UNITS
o
-
-
C
o
HC55121, HC55130/1, HC55140/1,
HC55142/3
-40
85
C
V
V
V
with Respect to GND
-58
-
-
-
-8
-8
V
V
V
BH
BL
with Respect to GND
with Respect to GND
V
BH
4.75
5.25
CC
3
o
o
,
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
2-WIRE PORT
Overload Level, Off Hook
Forward and Reverse
1% THD, I
≥ 18mA
3.2
1.3
-
-
-
-
V
Forward
Only
Forward
Only
DCMET
(Note 2, Figure 1)
PEAK
•
•
•
•
Overload Level, On Hook
Forward and Reverse
1% THD, IDCMET ≤ 5mA
(Note 3, Figure 1)
V
Forward
Only
Forward
Only
PEAK
•
•
•
•
•
•
•
•
•
•
•
•
Input Impedance (Into Tip and Ring)
-
-
Z /200
T
-
-
Ω
•
4
•
Longitudinal Impedance (Tip, Ring) 0 < f < 100Hz (Note 4, Figure 2)
Forward and Reverse
0
Ω/Wire
Forward
Only
Forward
Only
LONGITUDINAL CURRENT LIMIT (TIP, RING)
On-Hook, Off-Hook (Active),
= 736Ω
Forward and Reverse
No False Detections, (Loop
Current), LB > 45dB (Note 5,
Figure 3A)
28
-
-
-
-
mA
RMS
Wire Forward
Only
Forward
Only
/
R
•
•
•
•
•
•
•
•
L
On-Hook (Low Power Standby),
No False Detections (Loop
Current) (Note 6, Figure 3B)
8.5 mAPEAK/Wire
•
•
R
= ∞, R = 58.8kΩ
D
L
A
T
TIP
V
TX
1V
RMS
V
TX
TIP
0 < f < 100Hz
V
T
300Ω
300Ω
E
L
C
V
TR
R
L
I
DCMET
V
R
E
RX
RING
A
VRX
R
RING
VRX
LZ = V /A
LZ = V /A
R R R
T
T
T
FIGURE 1. OVERLOAD LEVEL (OFF HOOK, ON HOOK)
FIGURE 2. LONGITUDINAL IMPEDANCE
368Ω
368Ω
V
TX
TIP
TIP
V
A
A
A
TX
V
10µF
10µF
C
TX
C
E
E
L
L
C
RING
A
RING
VRX
VRX
368Ω
368Ω
SHD
SHD
FIGURE 3A. LONGITUDINAL CURRENT LIMIT OFF-HOOK (ACTIVE)
FIGURE 3B. LONGITUDINAL CURRENT LIMIT ON-HOOK (STANDBY)
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
OFF-HOOK LONGITUDINAL BALANCE
MIN
MIN
MIN
MIN
MIN
MIN
Longitudinal to Metallic (Note 7)
Forward and Reverse
IEEE 455 - 1985, R , R = 368Ω
Normal Polarity:
Forward
Only
Forward
Only
LR LT
o
o
0.2kHz < f < 1.0kHz, 0 C to 70 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
53
53
NA
NA
53
53
53
NA
NA
63
NA
NA
63
58
58
NA
NA
53
53
53
55
55
o
o
1.0kHz < f < 3.4kHz, 0 C to 70 C
5
o
o
0.2kHz < f < 1.0kHz, -40 C to 85 C
NA
NA
NA
NA
NA
55
o
o
1.0kHz < f < 3.4kHz, -40 C to 85 C
58
Reverse Polarity 0.2kHz < f <
3.4kHz, (Figure 4)
NA
MIN
MIN
MIN
MIN
MIN
MIN
Longitudinal to Metallic (Note 7)
Forward and Reverse
R
, R = 300Ω,
LR LT
Forward
Only
Forward
Only
Normal Polarity:
o
o
0.2kHz < f < 1.0kHz, 0 C to 70 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
53
53
NA
NA
53
53
53
NA
NA
63
NA
NA
63
58
58
NA
NA
53
53
53
55
55
o
o
1.0kHz < f < 3.4kHz, 0 C to 70 C
o
o
0.2kHz < f < 1.0kHz, -40 C to 85 C
NA
NA
NA
NA
NA
55
o
o
1.0kHz < f < 3.4kHz, -40 C to 85 C
58
Reverse Polarity 0.2kHz < f <
3.4kHz, (Figure 4)
NA
MIN
MIN
MIN
MIN
MIN
MIN
Longitudinal to 4-Wire (Note 9)
(Forward and Reverse)
Forward
Only
Forward
Only
Normal Polarity:
o
o
0.2kHz < f < 1.0kHz, 0 C to 70 C
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dB
dB
dB
dB
dB
53
53
NA
NA
53
53
53
NA
NA
63
NA
NA
63
58
58
NA
NA
53
53
53
61
61
o
o
1.0kHz < f < 3.4kHz,0 C to 70 C
o
o
0.2kHz < f < 1.0kHz, -40 C to 85 C
NA
NA
NA
NA
NA
61
o
o
1.0kHz < f < 3.4kHz, -40 C to 85 C
58
Reverse Polarity 0.2kHz < f <
3.4kHz, (Figure 4)
NA
Metallic to Longitudinal (Note 10)
Forward and Reverse
FCC Part 68, Para 68.310 (Note 8)
0.2kHz < f < 3.4kHz, (Figure 5)
40
40
50
-
-
-
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
4-Wire to Longitudinal (Note 11)
Forward and Reverse
0.2kHz < f < 3.4kHz, (Figure 5)
Forward
Only
Forward
Only
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
R
LT
R
LT
V
TIP
TX
TIP
V
TX
300Ω
V
TX
E
2.16µF
L
E
C
TR
V
TR
E
RX
C
2.16µF
V
L
R
VRX
6
LR
VRX
RING
RING
R
LR
300Ω
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO LONGITUDINAL
BALANCE
FIGURE 4. LONGITUDINAL TO METALLIC AND LONGITUDINAL TO 4-WIRE BAL-
ANCE
2-Wire Return Loss
Forward and Reverse
0.2kHz to 1.0kHz (Note 12, Figure 6)
1.0kHz to 3.4kHz (Note 12, Figure 6)
30
23
35
25
-
-
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
•
TIP IDLE VOLTAGE (User Programmable)
TIPX Idle Voltage
Active, I < 5mA
-
-2.0
-
V
Forward
Only
Forward
Only
L
Forward and Reverse
RING IDLE VOLTAGE (User Programmable)
RINGX Idle Voltage
Forward and Reverse
Active, I < 5mA
-
-
-
V
V
+2.5
-
-
-
V
V
V
Forward
Only
Forward
Only
L
BH
•
•
•
•
•
•
•
•
•
Tip open, I < 5mA
+2.5
L
BH
V
Active, I < 5mA
V
-4.5
Forward
Only
Forward
Only
TR
Forward and Reverse
L
BH
•
V
Pulse Metering
Active, I > 8.5mA, R
OH
= 50kΩ
-
V
-8.9
-
V
NA
NA
NA
TR(ROH)
Forward and Reverse
L
BH
Z
D
TIP
V
TX
TIP
V
TX
2pF
V
V
TX
TR
R
R
V
M
Z
L
E
R
G
600Ω
L
V
S
Z
IN
VRX
VRX
RING
RING
R
LR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT), OUTPUT OFFSET
VOLTAGE AND HARMONIC DISTORTION
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
4-WIRE TRANSMIT PORT (V
)
TX
Overload Level, Off Hook (I ≥ 18mA) (Z > 20kΩ, IL 1% THD) (Note 13,
3.2
1.3
-100
-
-
-
-
-
V
Forward
Only
Forward
Only
L
L
PEAK
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Forward and Reverse
Figure 7)
Overload Level, On Hook (I ≤ 5mA) (Z > 20kΩ, 1% THD)
V
Forward
Only
Forward
Only
L
L
PEAK
Forward and Reverse
(Note 14, Figure 7)
Output Offset Voltage
Forward and Reverse
E
= 0, Z = ∞, (Note 15,
-
100
1
mV
Forward
Only
Forward
Only
G
L
7
Figure 7)
Output Impedance
0.2kHz < f < 03.4kHz
0.1
Ω
•
•
•
•
(Guaranteed by Design)
4-WIRE RECEIVE PORT (VRX)
VRX Input Impedance
(Guaranteed by Design)
0.2kHz < f < 3.4kHz
-
500
600
kΩ
•
•
•
•
•
•
•
•
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
Relative to 0dBm at 1.0kHz, E = 0V
RX
Forward
Only
Forward
Only
Forward and Reverse
0.3kHz < f < 3.4kHz
-0.2
-1.0
-
-
0.1
0
dB
dB
f = 8.0kHz, 12kHz, 16kHz
(Note 16, Figure 8)
4-Wire to 2-Wire
Forward and Reverse
Relative to 0dBm at 1.0kHz, E = 0V
G
Forward
Only
Forward
Only
0.3kHz < f < 3.4kHz
-0.2
-1.0
-2.0
-
-
-
0.1
0
dB
dB
dB
•
•
•
•
•
•
•
•
f = 8.0kHz, 12kHz
f = 16kHz (Note 17, Figure 8)
-
4-Wire to 4-Wire
Forward and Reverse
Relative to 0dBm at 1.0kHz, E = 0V
Forward
Only
Forward
Only
G
0.3kHz < f < 3.4kHz (Note 18, Figure 8) -0.2
-
0.1
dB
V
TIP
TX
V
TIP
TX
V
V
TX
TX
OPEN
R
L
600Ω
R
L
E
G
V
TR
600Ω
V
PTG
VRX
TR
E
RX
RING
RING VRX
FIGURE 8. FREQUENCY RESPONSE, INSERTION LOSS, GAIN TRACKING
AND HARMONIC DISTORTION
FIGURE 9. IDLE CHANNEL NOISE
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
INSERTION LOSS
2-Wire to 4-Wire
0dBm, 1kHz
Forward and Reverse
PTG = Open (Note 19, Figure 8)
PTG = GND (Note 20, (Figure 8)
0dBm, 1kHz (Note 21, Figure 8)
-0.2
-6.22
-0.2
-
-6.02
-
0.2
-5.82
0.2
dB
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
4-Wire to 2-Wire
Forward and Reverse
Forward
Only
Forward
Only
8
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
Forward and Reverse
-40dBm to +3dBm (Note 22,
Figure 8)
-0.1
-0.2
-0.1
-0.2
-
−
-
0.1
0.2
0.1
0.2
dB
dB
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
-55dBm to -40dBm (Note 22,
Figure 8)
4-Wire to 2-Wire
Forward and Reverse
-40dBm to +3dBm (Note 23,
Figure 8)
Forward
Only
Forward
Only
-55dBm to -40dBm (Note 23,
Figure 8)
−
NOISE
Idle Channel Noise at 2-Wire
Forward and Reverse
C-Message Weighting
-
-
-
-
12
dBrnC
dBmp
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
Psophometric Weighting (Note 24,
Figure 9)
-78
Idle Channel Noise at 4-Wire
Forward and Reverse
C-Message Weighting
-
-
-
-
12
dBrnC
dBmp
Forward
Only
Forward
Only
Psophometrical Weighting
(Note 25, Figure 9)
-78
HARMONIC DISTORTION
2-Wire to 4-Wire
Forward and Reverse
0dBm, 0.3kHz to 3.4kHz
(Note 26, Figure 7)
-
-
-67
-67
-50
-50
dB
dB
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
4-Wire to 2-Wire
Forward and Reverse
0dBm, 0.3kHz to 3.4kHz
(Note 27, Figure 8)
Forward
Only
Forward
Only
7kΩ
V
V
TX
TIP
V
BH
TIP
TX
S
R
LIM
R
L
R
LIM
38.3kΩ
V
TR
600Ω
I
R1
R
1
RING
VRX
VRX
RING
FIGURE 10. CONSTANT LOOP CURRENT TOLERANCE
FIGURE 11. TIPX VOLTAGE
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
= 26.5mA, R = 38.3kΩ
18mA ≤ IL ≤ 45mA,
(Note 27, Figure 10)
Forward
Only
Forward
Only
•
•
•
•
•
•
I
0.92I
-
I
1.08I
L
mA
L
LIM
L
L
Forward and Reverse
Tip Open State TIPX Leakage
Current
S = Closed (Figure 11)
-
-100
µA
•
•
•
•
•
•
•
•
9
Tip Open State RINGX Leakage
Current
R = 0Ω, V
= -48V
= 2.5kΩ, V = -48V (Figure 11)
-
-
-
26.8
17.6
-
-
-
mA
mA
V
1
BH
•
•
•
•
•
•
R
1
BH
Tip Open State RINGX Voltage
Tip Voltage (Ground Start)
5mA<I < 26mA (Figure 11)
V
+4.5
R1
BH
•
NA
•
NA
•
NA
•
NA
Active State, (S Open) R = 150Ω
(Figure 11)
-5
-4
-
V
1
Tip Voltage (Ground Start)
Active State, (S Closed) Tip Lead to
•
•
•
•
-48V Through 7kΩ, Ring Lead to
Ground Through 150Ω (Figure 11)
-5
-4
0
-
V
NA
NA
NA
NA
Open Circuit State Loop Current
(Active) R = 0Ω
-100
100
µA
L
•
•
•
•
LOOP CURRENT DETECTOR
Programmable Threshold
Forward and Reverse
I
I
= (500/ R ) ≥ 5mA,
0.9•I
I
1.1•I
LT
mA
Forward
Only
Forward
Only
LTh
D
LT
LTh
= 8.5mA
•
•
•
•
LTh
Th
Th
R
= 58.8kΩ
D
GROUND KEY DETECTOR
Ground Key Detector Threshold
Tip/Ring Current Difference
Tip Open
5
-
8
11
-
mA
mA
NA
NA
NA
•
•
•
•
•
•
Active (Note 29, R1 = 2.5kΩ, Figure 12)
20
LINE VOLTAGE MEASUREMENT
Pulse Width (GKD_LVM)
-
0.36
-
ms/V
NA
NA
•
RING TRIP DETECTOR (DT, DR)
Ring Trip Comparator Current
Source Res = 2MΩ
Source Res = 2MΩ
-
-
2
-
-
µA
•
•
•
•
•
•
•
•
•
•
•
•
Input Common-Mode Range
±200
V
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
RING RELAY DRIVER
V
at 50mA
I
= 50mA
-
-
0.3
-
0.5
10
V
SAT
OL
•
•
•
•
•
•
•
•
•
•
•
•
Off-State Leakage Current
V
= 13.2V
= 50mA
µA
OH
TEST RELAY DRIVER (TRLY1, TRLY2)
at 50mA
0
V
I
-
-
0.3
-
0.5
10
V
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
SAT
OL
Off-State Leakage Current
V
= 13.2V
µA
OH
TIP
27
V
TX
VRX
SHD
RING
28
2.5kΩ
FIGURE 12. GROUND KEY DETECT
DIGITAL INPUTS (C1, C2, C3)
Input Low Voltage, V
IL
0
2.0
-
-
-
0.8
V
V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input High Voltage, V
V
CC
IH
Input Low Current, I
V
V
= 0.4V
= 2.5V
-
-50
µA
µA
IL
IL
Input High Current, I
-
25
50
IH
IH
DETECTOR OUTPUTS (SHD, GKD_LVM)
SHD Output Low Voltage, V
Forward, Reverse and Low Power
Standby
I
I
I
= 1mA
-
-
-
0.5
V
V
Forward
Only
Forward
Only
OL
OL
OH
OL
•
•
•
•
•
•
SHD Output High Voltage, V
Forward, Reverse and Low Power
Standby
= 100µA
2.7
-
Forward
Only
Forward
Only
OH
•
•
GKD_LVM Output Low Voltage,
= 1mA
= 2.5kΩ (Figure 11)
-
-
-
0.5
V
V
GKD
GKD
GKD
NA
NA
GKD_
LVM
GKD_
LVM
LVM
LVM
V
Forward and Tip Open
R
OL
GKD_LVM Output High Voltage,
Forward and Tip Open
1
I
= 100µA
2.7
-
-
•GKD
GKD_
LVM
GKD_
LVM
OH
V
OH
Internal Pull-Up Resistor
15
kΩ
•
•
•
•
•
•
o
o
Electrical Specifications T = -40 C to 85 C, V = +5V ±5%, V = -48V, V = No connect, PTG = Open, R = R = 0Ω, Z = 120kΩ, R
= 38.3kΩ, R = 58.8kΩ, RDC_RSG
D
,
A
CC
BH
= 1.0µF, C
BL
F1
F2
T
LIM
= 20kΩ, R
= 50kΩ, C = 0.47µF, C
= 0.47µf, GND = 0V, RL = 600Ω. Unless Otherwise Specified. (•) symbol used to indicate the
OH
H
DC
RT/REV
test applies to the part. (NA) symbol used to indicate the test does not apply to the part. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
HC55120
HC55121 HC55130/1 HC55140/1 HC55142/3 HC55150/1
POWER DISSIPATION (V
= -48V, V = -24V)
BL
BH
Open Circuit State
Forward and Reverse
C1, C2, C3 = 0, 0,0
-
-
10
15
-
-
mW
mW
Forward
Only
Forward
Only
•
•
•
•
•
•
•
•
On-Hook, Low Power Standby
Forward and Reverse
C1, C2, C3 = 1, 0, 1
C1, C2, C3 = 0, 1, 0
Forward
Only
Forward
Only
1
On-Hook, Active
•
•
•
•
Forward and Reverse
I = 0mA, Longitudinal
L
Current = 0mA
-
52
-
mW
Forward
Only
Forward
Only
POWER SUPPLY CURRENTS (V
= -48V, V = -24V)
BL
BH
V
Current, I
,
CC
Open Circuit State
-
-
-
-
-
-
-
-
-
0.95
-0.1
-
-
-
-
-
-
-
-
-
mA
mA
mA
mA
mA
mA
mA
mA
mA
Forward
Only
Forward
Only
CC
Forward and Reverse
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
V
Current, I
Forward
Only
Forward
Only
BH
BH
Forward and Reverse
V
Current, I
-0.001
0.95
Forward
Only
Forward
Only
BL
BL
Forward and Reverse
V
Current, I
Low Power Standby State
Forward
Only
Forward
Only
CC
CC
Forward and Reverse
I = 0mA, Longitudinal
L
Current = 0mA
V
Current, I
-0.1
Forward
Only
Forward
Only
BH
BH
Forward and Reverse
V
Current, I
-0.001
2.7
Forward
Only
Forward
Only
BL
BL
Forward and Reverse
V
Current, I
Active State
I = 0mA, Longitudinal
L
Current = 0mA
Forward
Only
Forward
Only
CC
CC
Forward and Reverse
V
Current, I
-0.8
Forward
Only
Forward
Only
BH
BH
Forward and Reverse
V
Current, I
-0.001
Forward
Only
Forward
Only
BL
BL
Forward and Reverse
POWER SUPPLY REJECTION RATIOS
to 2 or 4 Wire Port Active State R = 600Ω
V
-
-
40
40
-
-
-
-
dB
dB
dB
Forward
Only
Forward
Only
CC
Forward and Reverse
L
•
•
•
•
•
•
•
•
50Hz < f < 3400Hz, V =100mV
IN
V
to 2 or 4 Wire Port
Forward
Only
Forward
Only
BH
Forward and Reverse
V
to 2 or 4 Wire Port
40
Forward
Only
Forward
Only
BL
•
•
•
•
•
•
•
•
Forward and Reverse
RFI Rejection
Figure 13, 50kHz≤ f ≤ 100MHz High
-
-
TBD
•
•
TEMPERATURE GUARD
o
Junction Threshold Temperature
160
-
C
•
•
•
•
•
•
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
14. Overload Level (4-Wire port On-Hook) - The overload level is
Notes
specified at the 4-wire transmit port (V ) with the signal source
TX
2. Overload Level (Two-Wire Port, Off Hook) - The
overload
≥ 18mA.
(E ) at the 2-wire port, Z = 20kΩ, R = ∞ (Reference Figure 7).
G L L
level is specified at the 2-wire port (V ) with the signal source at
Increase the amplitude of E until 1% THD is measured at V
.
TR
G
TX
the 4-wire receive port (E ). R = 600Ω, I
Note the PTG pin is open, and the gain from the 2-wire port to
RX DCMET
L
Increase the amplitude of E until 1% THD is measured at V
.
the 4-wire port is equal to 1.
RX
TR
Reference Figure 1.
15. Output Offset Voltage - The output offset voltage is specified
3. Overload Level (Two-Wire port, On Hook) - The
overload
with the following conditions: E = 0, R = 600Ω, Z = ∞ and is
G L L
level is specified at the 2-wire port (V ) with the signal source at
measured at V . E , R , V and Z are defined in Figure 7.
TX TX
TR
G
L
L
the 4-wire receive port (E ). R = ∞, I
= 0mA. Increase
RX DCMET
L
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
the amplitude of E
until 1% THD is measured at V . Refer-
RX
TR
4-wire frequency response is measured with respect to
ence Figure 1.
E
= 0dBm at 1.0kHz, E = 0V (VRX input floating), R = 600Ω.
G
RX
L
4. LongitudinalImpedance - The longitudinal impedance is
The frequency response is computed using the following equation:
computed using the following equations, where TIP and RING
F
= 20 • log (V /V ), vary frequency from 300Hz to
2-4
TX TR
voltages are referenced to ground. L , L , V , V , A and A
ZT ZR T
T
R
R
3.4kHz and compare to 1kHz reading.
are defined in Figure 2.
(TIP) L = V /A
V
, V , R and E are defined in Figure 8.
TX TR
L
G
ZT
T
T
(RING) L = V /A
ZR
where: E = 1V
R
R
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to
(0Hz to 100Hz)
L
RMS
2-wire frequency response is measured with respect to
E
= 0dBm at 1.0kHz, E source removed from circuit, R =
RX
G L
5. Longitudinal Current Limit (On/Off-Hook Active) - Off-Hook
600Ω. The frequency response is computed using the following
equation:
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E (Figure 3A) until the 2-wire longitudinal current
L
F
= 20 • log (V /E ), vary frequency from 300Hz to
TR RX
is greater than 28mA
/Wire. Under this condition, SHD pin
4-2
RMS
remains low (no false detection) and the 2-wire to 4-wire longi-
tudinal balance is verified to be greater than 45dB (LB
3.4kHz and compare to 1kHz reading.
V , R and E are defined in Figure 8.
TR
=
2-4
L
RX
20log VTX/E ).
L
18. Four-Wire to Four-Wire Frequency Response - The 4-wire to
6. Longitudinal Current Limit (On-Hook Standby) - On-Hook
longitudinal current limit is determined by increasing the (60Hz)
amplitude of E (Figure 3B) until the 2-wire longitudinal current
4-wire frequency response is measured with respect to
E
= 0dBm at 1.0kHz, E source removed from circuit, R =
RX
G L
L
600Ω. The frequency response is computed using the following
equation:
is greater than 8.5mA
/Wire. Under this condition, SHD pin
RMS
remains high (no false detection).
F
= 20 • log (V /E ), vary frequency from 300Hz to
TX RX
4-4
3.4kHz and compare to 1kHz reading.
7. Longitudinal to Metallic Balance - The longitudinal to metal-
lic balance is computed using the following equation:
V
R and E are defined in Figure 8.
TX ,
19. Two-Wire to Four-Wire Insertion Loss (PTG = Open) - The
2-wire to 4-wire insertion loss is measured with respect to E
L
RX
BLME = 20 • log (E /V ), where: E and V
TR TR
are defined in
L
L
Figure 4.
=
G
0dBm at 1.0kHz input signal, E
= 0 (VRX input floating), R =
8. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
RX
L
600Ω and is computed using the following equation:
= 20 • log (V /V
metallic to longitudinal balance is defined in this spec.
L
)
TX TR
2-4
9. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
where: V , V , R and E are defined in Figure 8. (Note:
balance is computed using the following equation:
TX TR
L
G
The fuse resistors, R , impact the insertion loss. The specified
F
BLFE = 20 • log (E /V ),: E and V are defined in Figure 4.
TX TX
L
L
insertion loss is for R = R = 0).
F1 F2
10. Metallic to Longitudinal Balance - The metallic to longitudinal
20. Two-Wire to Four-Wire Insertion Loss (PTG = AGND) - The
2-wire to 4-wire insertion loss is measured with respect to E
balance is computed using the following equation:
=
G
BMLE = 20 • log (E /V ), E
TR RX
= 0
L
0dBm at 1.0kHz input signal, E = 0 (VRX input floating), R =
RX L
600Ω and is computed using the following equation:
= 20 • log (V /V
where: E
V and E are defined in Figure 5.
TR,
L
RX
L
)
TX TR
2-4
11. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
where: V , V , R and E are defined in Figure 8. (Note:
balance is computed using the following equation:
TX TR
L
G
The fuse resistors, R , impact the insertion loss. The specified
F
BFLE = 20 • log (E /V ), E = source is removed.
RX TR
L
insertion loss is for R = R = 0).
F1 F2
where: E
V and E are defined in Figure 5.
TR
RX,
L
21. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
insertion loss is measured based upon E = 0dBm, 1.0kHz
12. Two-Wire Return Loss - The 2-wire return loss is computed
RX
using the following equation:
r = -20 • log (2V /V )
where: Z = The desired impedance; e.g., the characteristic
impedance of the line, nominally 600Ω. (Reference Figure 6).
input signal, E source removed from circuit, R = 600Ω and is
G
L
M
S
computed using the following equation:
D
L
= 20 • log (V /E )
TR RX
4-2
where: V , R and E
TR RX
are defined in Figure 8.
L
13. Overload Level (4-Wire port Off-Hook) - The overload level
is specified at the 4-wire transmit port (V ) with the signal
TX
source (E ) at the 2-wire port, Z = 20kΩ, R = 600Ω (Refer-
G
L
L
ence Figure 7). Increase the amplitude of E until 1% THD is
G
measured at V . Note the PTG pin is open, and the gain from
TX
the 2-wire port to the 4-wire port is equal to 1.
12
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
22. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
The noise specification is with respect to a 600Ω impedance
gain tracking is referenced to measurements taken for
level at V . The 4-wire receive port (VTX) floating (Reference
TX
E
= -10dBm, 1.0kHz signal, E
= 0 (VRX output floating), R
Figure 9).
G
RX
L
= 600Ω and is computed using the following equation.
26. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic dis-
G
= 20 • log (V /V ) vary amplitude -40dBm to +3dBm, or
2-4
TX TR
tortion is measured with the following conditions. E = 0dBm at
G
-55dBm to -40dBm and compare to -10dBm reading.
1kHz, R = 600Ω. Measurement taken at V . (Reference Fig-
L
TX
V
, R and V are defined in Figure 8.
TX TR
ure 7).
L
23. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire
27. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic dis-
gain tracking is referenced to measurements taken for
tortion is measured with the following conditions. E
= 0dBm0.
RX
Vary frequency between 300Hz and 3.4kHz, R = 600Ω. Mea-
E
= -10dBm, 1.0kHz signal, E source removed from circuit, R
G L
RX
= 600Ω and is computed using the following equation:
L
surement taken at V . (Reference Figure 8).
TR
G
= 20 • log (V /E ) vary amplitude -40dBm to +3dBm,
TR RX
4-2
28. Constant Loop Current - The constant loop current is calcu-
or -55dBm to -40dBm and compare to -10dBm reading.
lated using the following equation:
V
, R and E are defined in Figure 8. The level is specified at
TR RX
L
I
= 1000/R
LIM
= V /600 (Reference Figure 10).
TR
L
the 4-wire receive port and referenced to a 600Ω impedance level.
29. Ground Key Detector - (TRIGGER) Ground the Ring pin
through a 2.5kΩ resistor and verify that GKD goes low.
24. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
at V
TR
is specified with the 2-wire port terminated in 600Ω (R )
L
(RESET) Disconnect the Ring pin and verify that GKD goes
high.
and with the 4-wire receive port (VTX) floating (Reference Figure
9).
(Hysteresis) Compare difference between trigger and reset.
25. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
at V is specified with the 2-wire port terminated in 600Ω (R ).
TX
L
Circuit Operation and Design Information
The UniSLIC14 family of SLIC’s operate as a voltage feed
current sense subscriber line interface circuit on the 2-wire
side, yet appear as a current feed voltage sense SLIC on the
4-wire side. This architecture allows easy implementation of
thermal management on the 2-wire side and easy
connection to DSP CODEC’s on the 4-wire side. Thus, for
long loop applications the SLIC provides a programmed
constant voltage to the tip and ring terminals while sensing
the tip to ring current.
voltage, required for a given signal level, is calculated with
Equation 1.
2R + 50
P
(EQ. 1)
V
= V
× 1 + ------------------------
OH(on)
sp(on)
Z
O
where V
V
= On hook overhead voltage
OH(on)
= Required OHT (Vpeak) on hook voltage
= Protection Resistors (Typically 30Ω)
= Line impedance for (voice)
sp(on)
R
P
The following discussion separates the SLIC’s operation into
it’s DC and AC paths, then follows up with additional circuit
and design information.
Z
O
Reference Figure 13 for R and Z
P
O
The off hook overhead
DC FEED CURVE
DC Feed Curve
voltage V (off) is also
OH
independent of the V
V
BH
SAT
OH(off)
The DC feed curve for the UniSLIC14 family is user
programmable. The user has complete control over: The on
hook and off hook overhead voltages, resistance of the feed
curve, minimum open circuit voltage, the value of the current
limit and the saturation guard.
BH
2.5V
V
battery voltage and remains
constant over temperature.
The required off hook
overhead voltage is the sum
of the voltage drop across
the internal sense resistors,
the protection resistors, the
speech signal and pulse
OFF HOOK
OVER HEAD
V
The on hook overhead
I
LOOP(min)
DC FEED CURVE
voltage V (on) is
LOOP CURRENT
OH
V
BH
independent of the V
BH
battery voltage. So once set,
the on hook voltage remains
2.5V
ON HOOK
V
SAT
metering signal. The off hook overhead voltage is calculated
V
OH(on)
with Equations 2 and 3.
(EQ. 2)
OVERHEAD
constant as the V
BH
battery
V
= V
+ V
+ V
OH(sp) OH(pm)
voltage changes. V (on)
OH
OH(off)
OH(Rsense)
also remains constant over
temperature and line
leakages up to ISH-. ISH- is
equal to 0.6 times the Switch
where V
V
= Off hook overhead voltage
ISH-
LOOP CURRENT
OH(off)
(R
) = Required overhead for voltage drop
OH sense
across sense resistors as a result of the DC loop
current (reference Figure 13).
Hook Detect threshold current I
. The on hook overhead
SHD
13
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
V
= Required (peak) off hook voltage for
OH(sp)
DC FEED CURVE
For a constant current
design, the R resistance
speech.
V
SAT
of the DC feed curve is
BH
V
= Required (peak) off hook voltage for pulse
OH(pm)
2.5V
V
SAT
metering.
equal to the V (off)
OH
OFF HOOK
OVER HEAD
V
OH(off)
voltage divided by the
minimum loop current
requirement (Equation 4).
2R + 50
P
R
SAT
V
= 50 × I
+ V
× 1 + ------------------------
OH(off)
LOOP(max)
sp(off)
Z
O
I
LOOP(min)
2R + 50
P
The external saturation
guard resistor RDC_RSG
can now be calculated and
is given in Equation 5.
LOOP CURRENT
+ V
× 1 + ------------------------
pm(off)
(EQ. 3)
Z
pm
R
V
SAT
OH(off)
where I
= Desired loop current limit.
LOOP(max)
I
V
= Required (peak) off hook voltage for
LOOP(min)
sp(off)
speech.
V
= Required (peak) off hook voltage for pulse
pm(off)
metering.
V
OH(off)
(EQ. 4)
---------------------------
R
=
SAT
I
LOOP(min)
Z
= Line impedance (pulse metering, typically
pm
200Ω).
(EQ. 5)
RDC_RGS = 50 x R
SAT
EXTERNAL PROTECTION
The minimum ISH- is equal
RESISTOR
OVERHEAD VOLTAGE V (ON, OFF)
OH
DC FEED CURVE
to V (on) divided by R
OH
SAT
V
as shown in Equation 6.
2R
BH
50Ω
V
V
P
SP(on, off) OR
PM(off)
TIP OR RING
AMPLIFIER
2.5V
V
V
SAT
ISH- is used to find the
minimum and maximum
Switch Hook Detect
ON HOOK
OVER HEAD
OH(on)
INTERNAL SENSE
RESISTOR
LINE IMPEDANCE
OR Z
Z
thresholds (I
for a
O
PM
SHD)
given design. The minimum
is established by
ISH-(min)
Z
+ 2R + 50
P
O
I
--------------------------------------
V
=
=
A
SHD(min)
LOOP CURRENT
OH(on,off)
Z
O
the on hook overhead
voltage requirement. The
2R + 50
P
V
R
OH(on)
SAT
1 + ------------------------ A
Z
maximum I
is
O
SHD(max)
ISH-
established by the minimum
open circuit voltage
requirement.
(min)
V
V
WHERE A IS EITHER SP(on, off) OR PM(off)
FIGURE 13. OVERHEAD VOLTAGE OF THE TIP AND RING
AMPLIFIERS
2R
P + 50
(EQ. 6)
----------------------
V
x
1 +
SP(on)
Z
V
O
OH(on)
---------------------- ---------------------------------------------------------------------
ISH-min =
=
The Overhead voltage is defined at the output of the tip or
ring amplifiers. The off hook overhead voltage requirement is
the voltage drop across the internal sense resistors at
maximum loop current, plus the required voltage for both
speech and pulse metering. The two protection resistors
R
R
SAT
SAT
The minimum Switch Hook Detect threshold current
(I
) is defined by Equation 7.
SHD(min)
(R ) are considered as part of the load.
P
(EQ. 7)
I
= 1.7 x ISH-(min)
SHD(min)
14
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
The current limit is set by a single resistor and is calculated
using Equation 13:
The maximum ISH- is
determined by the
minimum open circuit
voltage requirement
(Typical value is -43 volts).
DC FEED CURVE
V
BH
SAT
OH(on)
(EQ. 13)
1000
2.5V
ON HOOK
V
-----------------------------
R
=
LIM
I
LOOP(max)
V
OVER HEAD
MIN O/C
VOLTAGE
The maximum loop resistance for the given conditions is
calculated by Equation 14.
Equation 8 determines the
maximum ISH- allowed for
a given minimum open
circuit voltage.
ISH-(max)
LOOP CURRENT
V
-V
V
2R + 50
P
BH SAT
SP(off)
----------------------------
LOOP(min)
---------------------------
------------------------
R
=
-50-
x
1 +
LOOP(max)
I
I
Z
0
LOOP(min)
R
SAT
V
OH(on)
(EQ. 14)
V
2R + 50
P
Z
PM
PM(off)
ISH-
(max)
--------------------------- x 1 + ------------------------- -2R
-
P
I
LOOP(min)
V
-V
-V
SLIC in the Standby Mode
BH SAT O/C
(EQ. 8)
--------------------------------------------
ISH-(max) =
R
SAT
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip
and ring amplifiers are disabled and internal resistors are
The maximum Switch Hook Detect Current threshold is
defined by Equation 9.
connected between tip to ground and ring to V . This
BH
(EQ. 9)
I
= 1.7 x ISH -(max)
connection enables a loop current to flow when the phone
goes off hook. The loop current detector then detects this
current and the SHD pin goes low.
SHD(MAX)
The above analysis establishes a range for the Switch Hook
Detect threshold current to meet the selected requirements.
SLIC in the Active Mode
After selecting an I
threshold between the I
and
SHD
SHD(min)
Figure 14 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
I
, the programming resistor is determined by
SHD(max)
Equation 10.
Node Equation
(EQ. 10)
500
------------
R
=
D
(EQ. 15)
I
V
V
A
SHD
RX
------------- ----------------
-
= I
X
500K 1000K
The true value of ISH-, for the selected value of I
by Equation 11:
is given
(EQ. 11)
SHD
Loop Equation
I 500k - V
(EQ. 16)
(EQ. 17)
ISH- = I
(0.6)
= I 500k = 0
SHD
X
TX′
X
Loop Equation
-I 2R + V = 0
TX′
Verify that the value of ISH- is above the suspected line
leakage of the application. The UniSLIC family will provide a
constant on hook voltage level for leakage currents up to this
value of line leakage.
V
TR
M
P
where:
= Is the input voltage at the VRX pin.
V
RX
The ROH resistor, which
is used to set the offhook
overhead voltage, is
calculated using
Equation 12.
DC FEED CURVE
V = Is an internal node voltage that is a function of the loop
A
current detector and the impedance matching networks
V
BH
2.5V
V
SAT
I
= Internal current in the SLIC that is the result between
X
OFF HOOK
OVER HEAD
the input receive current and the feedback current.
V
OH(off)
IOH is the difference
I
OH
I
= Is the AC metallic current.
= Is a fuse resistor.
P
M
between the I
and ISH-.
LOOP(min)
R
I
ISH-
LOOP(min)
LOOP CURRENT
Z = Is used to set the SLIC’s 2-wire impedance.
T
V ´= Is the tip to ring voltage at the output pins of the SLIC.
TX
V
= Is the tip to ring voltage including the voltage across
TR
the protection resistors.
500
IOH
500
---------- ------------------------------------------
(EQ. 12)
R
=
=
OH(max)
I
-ISH-
LOOP(min)
Z = Is the line impedance.
L
15
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
+ I
-
X
I
M
500k
+
-
V
TIP
R
TX
S
-
+
-
+
R
P
500k
500k
-
TX
+
V
Z
L
-
Z
PTG
TR
+
-
HC5514
V
V
´
TX
TR
+
+
I
I
X
E
-
X
I
G
X
I
X
I
+
M
-
R
S
V
RX
+
-
500K
R
P
RING
+
RX
-
500k
V
1M
-
+
I
X
10
1/80k
V
= I (Z -2R )
M O P
A
Z
T
FIGURE 14. SIMPLIFIED AC TRANSMISSION CIRCUIT
EXAMPLE:
(AC) 4-Wire to 2-Wire Gain
Calculate Z to make Z = 600Ω in series with 2.16µF.
The 4-wire to 2-wire gain is equal to V /V
.
T
TR
TR RX
R
= 30Ω.
P
From Equations 15, 16 and 17 with E = 0.
G
1
Z
(EQ. 18)
Z
= 200 • 600 + ----------------------------------------- – 2 • 30
(EQ. 22)
L
T
–6
---------------------
A
= -2
jω • 2.16 • 10
4-2
Z
+ Z
L
O
Z = 114kΩ in series with 0.0108µF.
T
(AC) 2-Wire to 4-Wire Gain
The 2-wire to 4-wire gain is equal to V / E with V
TX
= 0.
G
RX
Layout Considerations
Floating the PTG Pin:
V
Z
- 2R
O P
+ Z
O L
(EQ. 19)
TX
---------- -------------------------
= -
A
=
2-4
The PTG pin is a high impedance pin that is used to reduce
the 2-wire to 4-wire gain to 0dB. If 0dB is required, it is
necessary to float the PTG pin. The PC board interconnect
should be as short as possible to minimize stray capacitance
on this pin. Stray capacitance on this pin forms a low pass
filter and will cause the 2-wire to 4-wire gain to roll off at the
higher frequencies.
E
G
Z
(AC) 4-Wire to 4-Wire Gain
The 4-wire to 4-wire gain is equal to V /V
.
TX RX
From Equations 15, 16 and 17 with E = 0.
G
Z - 2R
V
L
P
TX
----------------------
(EQ. 20)
A
= ----------- = 2
If a 2-wire to 4-wire gain of -6dB is required in the design, the
PTG pin should be grounded at the pin.
4 – 4
Z
+ Z
0
V
L
RX
Layout of the 2-Wire Impedance Matching Resistor
(AC) 2-Wire Impedance
Z :
T
The AC 2-wire impedance (Z ) is the impedance looking
TR
into the SLIC, including the fuse resistors. The formula to
Proper connection to this pin is to have the external Z
network as close to the pin as possible.
T
calculate the proper Z for matching the 2-wire impedance is
T
shown in Equation 21.
The Z pin is a high impedance pin that is used to set the
T
(EQ. 21)
proper feedback for matching the impedance of the 2-wire
side. This will eliminate circuit board capacitance on this pin
to maintain the 2-wire return loss across frequency.
Z
= 200 • (Z
– 2R )
TR P
T
Equation 21 can now be used to match the SLIC’s
impedance to any known line impedance (Z ).
TR
SPM Pin:
For optimum performance, the PC board interconnect
connected to the SPM pin should be as short as possible.
16
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
TABLE 1. DETECTOR STATES
OUTPUT
STATE
C3
C2
C1
SLIC OPERATING STATE
ACTIVE DETECTOR
SHD
GKD_ LVM
HIGH
0
0
0
0
Open Circuit State
HIGH
1
2
0
0
0
1
1
0
Ringing State
Ring Trip Detector
HIGH
Forward Active State
Loop Current Detector
Ground Key Detector
3
0
1
1
Test Active State
On Hook Loopback Detector
LOW
LOW
Requires previous state to be in the
Forward Active state to determine
the On hook or Off hook status of the
line.
Ground Key Detector
On Hook Loop Current Detector
Line Voltage Detector
Ground Key Detector
4
5
1
1
0
0
0
1
Tip Open State
Low Power Standby State
Loop Current Detector
Ground Key Detector
Loop Current Detector
Ground Key Detector
6
7
1
1
1
1
0
1
Reverse Active State
Test Reversal Active State
Requires previous state to be in the
Reverse Active state to determine
the On hook or Off hook status of the
line.
On Hook Loop Current Detector
On Hook Loop Current Detector
Line Voltage Detector
HIGH
LOW
LOW
LOW
8
X
X
X
Thermal Shutdown
17
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
HC55120
(28 PIN PLCC)
TOP VIEW
HC55121
(28 PIN PLCC)
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
RING
GND
5
6
25 NC
RING
GND
5
6
25 ZSPM
24 RSYNC
23 ILIM
22 ROH
21 RD
24 RSYNC_
REV
TIP
7
TIP
7
23 ILIM
22 ROH
21 RD
VBH
8
VBH
8
9
9
VBL
VBL
10
11
V
10
11
RDC_RSG
CRT
20
RDC_RSG
CRT_REV
20
V
CC
CC
19 GKD
19 GKD
12 13 14 15 16 17 18
12 13 14 15 16 17 18
HC55130
(28 PIN PLCC)
TOP VIEW
HC55140
(28 PIN PLCC)
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
RING
GND
5
6
25 NC
RING
GND
5
6
25 NC
24 RSYNC
23 ILIM
22 ROH
21 RD
24 RSYNC_
REV
TIP
7
TIP
7
23 ILIM
22 ROH
21 RD
VBH
8
VBH
8
9
9
VBL
VBL
10
11
V
10
11
RDC_RSG
CRT
20
RDC_RSG
20
V
CC
CC
19 NC
CRT_REV_
LVM
19 GKD_LVM
12 13 14 15 16 17 18
12 13 14 15 16 17 18
HC55142
(28 PIN PLCC)
TOP VIEW
HC55150
(28 PIN PLCC)
TOP VIEW
4
3
2
1
28 27 26
4
3
2
1
28 27 26
RING
GND
TIP
5
6
7
8
9
25 ZSPM
RING
5
25 ZSPM
24 RSYNC_
GND
TIP
6
7
24 RSYNC_
REV
REV
23 ILIM
23 ILIM
22 ROH
21 RD
VBH
VBL
22 ROH
21 RD
VBH
8
9
VBL
10
11
V
CC
RDC_RSG
20
10
11
V
CC
RDC_RSG
20
CRT_REV_
LVM
19 LVM
CRT_REV_
LVM
19 GKD_LVM
12 13 14 15 16 17 18
12 13 14 15 16 17 18
18
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Pinouts SOIC Packages
HC55120
(28 PIN SOIC)
TOP VIEW
HC55121
(28 PIN SOIC)
TOP VIEW
1
2
1
2
ZT
PTG
28
27
26
25
ZT
PTG
28
27
26
25
NC
VTX
NC
ZSPM
VTX
RRLY
RRLY
3
3
SPM
CH
CH
4
VRX
4
VRX
RING
GND
RING
GND
5
24 RSYNC
23
5
24 RSYNC_REV
23
6
6
ILIM
ILIM
TIP
TIP
7
22 ROH
21 RD
7
22 ROH
21 RD
VBH
VBH
8
8
VBL
9
20
19
18
17
16
15
V
VBL
9
20
19
18
17
16
15
V
CC
CC
10
10
RDC_RSG
RDC_RSG
SHD
C1
SHD
C1
CDC 11
CDC 11
12
12
DT
C2
DT
C2
C3
C3
DR 13
DR 13
CRT 14
GKD
CRT_REV 14
GKD
HC55130
(28 PIN SOIC)
TOP VIEW
HC55140
(28 PIN SOIC)
TOP VIEW
1
2
1
2
ZT
PTG
28
NC
ZT
PTG
28 NC
27
26
25
27
26
25
VTX
NC
VTX
NC
RRLY
RRLY
3
3
CH
CH
4
VRX
4
VRX
RING
GND
RING
GND
5
24 RSYNC
23
5
24 RSYNC_REV
23
6
6
ILIM
ILIM
TIP
TIP
7
22 ROH
21 RD
7
22 ROH
21 RD
VBH
VBH
8
8
VBL
9
20
19
18
17
16
15
V
VBL
9
20
19
18
17
16
15
V
CC
CC
10
10
RDC_RSG
RDC_RSG
SHD
C1
SHD
CDC 11
CDC 11
C1
12
12
DT
C2
DT
C2
C3
C3
DR 13
DR 13
CRT 14
NC
CRT_REV_LVM 14
GKD_LVM
HC55142
(28 PIN SOIC)
TOP VIEW
HC55150
(28 PIN SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
ZT
PTG
28
1
ZSPM
ZT
28
ZSPM
27
26
25
PTG
RRLY
VTX
SPM
VRX
2
3
27
26
25
VTX
SPM
VRX
RRLY
CH
CH
4
RING
GND
TIP
RING
GND
24 RSYNC_REV
23
5
24 RSYNC_REV
23
ILIM
6
ILIM
TIP
22 ROH
21 RD
7
22 ROH
21 RD
VBH
VBL
VBH
8
20
19
18
17
16
15
V
CC
VBL
9
20
19
18
17
16
15
V
CC
10
RDC_RSG
10
RDC_RSG
SHD
SHD
C1
CDC 11
C1
CDC 11
12
DT
C2
12
DT
C2
C3
DR 13
C3
DR 13
CRT_REV_LVM 14
GKD_LVM
CRT_REV_LVM 14
LVM
19
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Pin Descriptions
28
32
28
PIN
PIN
PIN
PLCC PLCC SOIC
SYMBOL
DESCRIPTION
1
1
2
PTG
Programmable Transmit Gain - The 2-wire to 4-wire transmission gain is 0dB if this pin is left floating and
-6.02dB if tied to ground. The -6.02dB gain option is useful in systems where Pulse Metering is used.
See Figure 14.
2
3
2
3
3
4
RRLY
CH
Ring Relay Driver Output - The relay coil may be connected to a maximum of 14 volts.
AC/DC Separation Capacitor - CH is required to properly process the AC current from the DC loop cur-
rent. Recommended value 0.47µF.
4
4
1
ZT
2-Wire Impedance Matching Pin - Impedance matching of the 2-wire side is accomplished by placing
an impedance between the Z pin and ground. See Equation 21.
T
5
6
5
6
5
6
RING
GND
TIP
Connects via protection resistors (R reference Figure 15 - 18) to ring wire of subscriber pair.
P
Analog and Digital ground.
7
7
7
Connects via protection resistors (R reference Figure 19) to tip wire of subscriber pair.
P
8
8
8
V
High Battery Supply (negative with respect to GND pin 6).
BH
9
9
9
V
Low Battery Supply (negative with respect to GND pin 6, magnitude < V ).
BH
BL
10
10
10
RDC_RSG
Resistive Feed/Saturation Guard - Performs the saturation guard function on constant current designs
and sets the slope of the resistive feed curve for constant voltage designs.
11
11
14
CRT_REV
_LVM
Ring Trip, Soft Polarity Reversal and Line Voltage Measurement - A capacitor when placed between
the CRT_REV_LVM pin and ground performs 3 mutually exclusive functions. When the SLIC is config-
ured in the Ringing mode it provides filtering of the ringing signal to prevent false detect. When the SLIC
is transitioning between the Forward Active State and Reverse Active State it provides Soft Polarity Re-
versal and performs charge storage in the Line Voltage Measurement State. Recommended value
0.47µF.
12
13
12
13
11
12
CDC
DT
Filter Capacitor- The CDC Capacitor removes the VF signals from the battery feed control loop.
Tip side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network
to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DT is more
negative than the voltage on DR.
14
14
13
DR
Ring Side of Ring Trip Detector - Ring trip detection is accomplished by connecting an external network
to a detector in the SLIC with inputs DT and DR. Ring trip occurs when the voltage on DR is more
positive than the voltage on DT.
-
-
15
16
17
-
-
C5
C4
C3
Activates Test Relay TRLY1.
Activates Test Relay TRLY2.
15
16
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
16
17
18
19
17
18
C2
C1
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
TTL Compatible Logic Input. The logic states of C1, C2 and C3 determine the operating states of the
SLIC. Reference Table 1 for details.
18
19
20
20
21
22
19
15
20
SHD
GKD_LVM
VCC
Switch Hook Detect - Active during off hook, ground key and loopback. Reference Table 1 for details.
Ground Key Detector and Line Voltage Measurement - Reference Table 1 for details.
5V Supply.
20
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Pin Descriptions (Continued)
28
32
28
PIN
PIN
PIN
PLCC PLCC SOIC
SYMBOL
DESCRIPTION
21
22
23
24
23
24
25
26
21
22
23
24
RD
Loop Current Threshold Programming Pin - A resistor between this pin and ground will determine the
trigger level for the loop current detect circuit. See Equation 10.
ROH
ILIM
Off Hook Overload Setting Resistor - Used to set combined overhead for voice and pulse metering
signals. See Equation 12.
Current Limit Programming Pin - A resistor between this pin and ground will determine the constant
current limit of the feed curve. See Equation 13.
RSYNC_REV Ring Synchronization Input and Reversal Time Setting. A resistor between this pin and GND (pin 6)
determines the polarity reversal time. Synchronization of the closing of the relay to connect the ringing
signal to the subscriber pair is achieved via the grounding of this pin.
25
27
28
ZSPM
Pulse Metering Signal Impedance Pin - A resistor on the input of this pin will allow programming of the
source impedance of the pulse metering signal for maximum signal on the 2-wire loop.
26
27
28
-
28
29
30
31
32
25
26
27
-
VRX
SPM
Receive Input - Ground referenced 4-wire side.
Pulse Metering Signal Input.
VTX
Transmit Output - Ground referenced 4-wire side.
Test Relay Driver 1.
TRLY1
TRLY2
-
-
Test Relay Driver 2.
21
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Basis Application Circuit
Voice Only 28 Pin PLCC Package
R
11
+5V
C
20
R
9
28
1
V
U1
CC
V
TX
1
+12V
2
3
RELAY
RRLY
CH
PTG
R
10
C
2
RING
TIP
R
P
26
5
6
V
RING
GND
RX
U2
CODEC/FILTER
R
R
R
R
R
8
7
6
5
4
4
Z
T
24
23
22
R
P
RSYNC_REV
7
8
TIP
ILIM
ROH
RD
VBH
-24V
-48V
C7
9
VBL
21
18
C
5
R
1
10
12
13
RDC_RSG
CDC
SHD
C
R
6
19
17
16
GKD_LVM
C1
R
C
2
3
DT
12
14
11
C2
DR
15
C3
CRT_REV_LVM
R
3
RING
GENERATOR
C
4
VBAT
CONTROL LOGIC
+5V
FIGURE 15. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT
TABLE 2. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
RATING
N/A
U1 - SLIC
N/A
N/A
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
RP (Line Feed Resistors)
R1 (RDC_RSG Resistor)
R2, R3
Matched 1%
1%
2.0W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
2W
13kΩ
2 MegΩ
1%
R4 (RD Resistor)
R5 (ROH Resistor)
R6 (RILIM Resistor)
R7 (RSYNC_REV Resistor)
R8 (RZT Resistor)
R9, R10, R11
R12
43.2kΩ
1%
37.4kΩ
1%
33.2kΩ
1%
34.8kΩ
1%
107kΩ
1%
20kΩ
1%
400Ω
5%
C1
0.1µF + 1.0µF
0.1µF + 1.0µF
0.1µF + 1.0µF
0.47µF
20%
20%
20%
20%
20%
10V
C5
50V
C6
100V
10V
C2, C4, C7
C3
2.2µF
50V
Design Parameters: Maximum onhook voltage = 0.775V
, Maximum Offhook Voice = 3.1Vpeak, Switch Hook Threshold = 11.6mA, Loop
RMS
Current Limit = 29.6mA, Synthesize Device Impedance = 600 -60 = 540Ω, with 30Ω protection resistors, impedance across Tip and Ring terminals
= 600Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130, HC55140,
HC55142 and HC55150. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
22
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Basis Application Circuit
Pulse Metering 28 Pin PLCC Package
R
11
+5V
20
R
9
28
1
V
U1
CC
V
TX
C
1
+12V
2
3
PTG
RELAY
RRLY
CH
SPM
VRX
R
10
C
2
RING
TIP
R
26
P
5
6
RING
GND
R
R
14
U2
13
ZSPM
CODEC/FILTER
R
R
R
R
R
8
7
6
5
4
4
C
7
Z
T
24
23
22
R
P
7
8
RSYNC_REV
ILIM
12/16kHZ
PULSE METERING
INPUT SIGNAL
TIP
-24V
-48V
VBH
R
C
5
OH
9
C8
VBL
21
18
RD
C
6
R
1
10
12
RDC_RSG
CDC
SHD
19
17
16
GKD_LVM
C1
R
C
2
3
13
DT
RING
GENERATOR
R
12
14
11
C2
DR
15
V
R
BAT
3
C3
CRT_REV_LVM
C
CONTROL LOGIC
4
+5V
FIGURE 16. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT
TABLE 3. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
N/A
RATING
N/A
U1 - SLIC
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
N/A
RP (Line Feed Resistors)
R1 (RDC_RSG Resistor)
R2, R3
Matched 1%
1%
2.0W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
2W
19.1kΩ
2 MegΩ
1%
R4 (RD Resistor)
R5 (ROH Resistor)
R6 (RILIM Resistor)
R7 (RSYNC_REV Resistor)
R8 (RZT Resistor)
R9, R10, R11
R12
51.1kΩ
1%
34.8kΩ
1%
33.2kΩ
1%
34.8kΩ
1%
107kΩ
1%
20kΩ
1%
400Ω
5%
R13, R14
10.7kΩ
1%
1/4W
10V
C1
0.1µF + 1.0µF
0.1µF + 1.0µF
0.1µF + 1.0µF
0.47µF
20%
20%
20%
20%
20%
10%
C5
50V
C6
100V
10V
C2, C4, C8
C3
2.2µF
50V
C7
680pF
10V
Design Parameters: Maximum onhook voltage = 0.775V
, Maximum offhook voice = 1.1Vpeak, Maximum simultaneous pulse metering signal
RMS
= 3.1Vpeak, Switch Hook Threshold = 9.8mA, Loop Current Limit = 29.6mA, Synthesize Device Impedance = 600-60 = 540Ω, with 30Ω protection
resistors, impedance across Tip and Ring terminals = 600Ω. Where applicable, these component values apply to the Basic Application Circuits for
the HC55120, HC55121, HC55130, HC55140, HC55142 and HC55150. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
23
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Basis Application Circuit
Voice Only 28 Pin SOIC Package
R
11
+5V
C
20
R
9
27
25
V
U1
CC
V
V
TX
1
+12V
3
4
RELAY
RRLY
CH
R
10
C
2
RING
TIP
R
P
5
6
RING
GND
RX
U2
CODEC/FILTER
R
R
R
R
R
8
7
6
5
4
1
Z
T
24
23
22
21
R
P
RSYNC_REV
ILIM
7
8
TIP
V
V
BH
BL
-24V
-48V
C7
R
OH
9
RD
C
5
R
1
10
11
19
RDC_RSG
CDC
SHD
C
6
15
18
17
GKD_LVM
C1
R
C
2
3
12
13
14
DT
R
12
C2
C3
DR
16
R
RING
GENERATOR
3
CRT_REV_LVM
C
4
V
BAT
CONTROL LOGIC
+5V
FIGURE 17. UniSLIC14 VOICE ONLY BASIC APPLICATION CIRCUIT
TABLE 4. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
RATING
N/A
U1 - SLIC
N/A
N/A
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
RP (Line Feed Resistors)
R1 (RDC_RSG Resistor)
R2, R3
Matched 1%
1%
2.0W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
2W
13kΩ
2 MegΩ
1%
R4 (RD Resistor)
R5 (ROH Resistor)
R6 (RILIM Resistor)
R7 (RSYNC_REV Resistor)
R8 (RZT Resistor)
R9, R10, R11
R12
43.2kΩ
1%
37.4kΩ
1%
33.2kΩ
1%
34.8kΩ
1%
107kΩ
1%
20kΩ
1%
400Ω
5%
C1
0.1µF + 1.0µF
0.1µF + 1.0µF
0.1µF + 1.0µF
0.47µF
20%
20%
20%
20%
20%
10V
C5
50V
C6
100V
10V
C2, C4, C7
C3
2.2µF
50V
Design Parameters: Maximum onhook voltage = 0.775V
, Maximum offhook voice = 3.1Vpeak, Switch Hook Threshold = 11.6mA, Loop Cur-
RMS
rent Limit = 29.6mA, Synthesize Device Impedance = 600-60 = 540Ω, with 30Ω protection resistors, impedance across Tip and Ring terminals =
600Ω. Where applicable, these component values apply to the Basic Application Circuits for the HC55120, HC55121, HC55130, HC55140,
HC55142 and HC55150. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
24
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
Basis Application Circuit
Pulse Metering 28 Pin SOIC Package
R
11
+5V
R
9
20
27
2
V
V
U1
TX
CC
C
1
+12V
3
4
PTG
RELAY
RRLY
CH
26
SPM
R
10
C
2
RING
TIP
25
R
R
P
V
5
6
RX
RING
GND
R
R
14
13
U2
28
1
CODEC/FILTER
ZSPM
R
R
R
R
R
8
7
6
5
4
C
7
Z
T
12/16KHZ
PULSE METERING
INPUT SIGNAL
24
23
22
21
RSYNC_REV
ILIM
P
7
8
TIP
-24V
-48V
V
BH
R
OH
C
5
C8
9
V
BL
RD
C
R
6
R
1
10
11
12
19
RDC_RSG
CDC
SHD
15
18
17
GKD_LVM
C1
R
2
C
3
DT
RING
13
14
12
C2
C3
DR
GENERATOR
16
R
VBAT
3
CRT_REV_LVM
CONTROL LOGIC
C
4
+5V
FIGURE 18. UniSLIC14 PULSE METERING BASIC APPLICATION CIRCUIT
TABLE 5. BASIC APPLICATION CIRCUIT COMPONENT LIST
COMPONENT
VALUE
UniSLIC14 Family
TISP1072F3
30Ω
TOLERANCE
N/A
RATING
N/A
U1 - SLIC
U2 - Dual Asymmetrical Transient Voltage Suppressor
N/A
N/A
RP (Line Feed Resistors)
R1 (RDC_RSG Resistor)
R2, R3
Matched 1%
1%
2.0W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
1/4W
2W
19.1kΩ
2 MegΩ
1%
R4 (RD Resistor)
R5 (ROH Resistor)
R6 (RILIM Resistor)
R7 (RSYNC_REV Resistor)
R8 (RZT Resistor)
R9, R10, R11
R12
51.1kΩ
1%
34.8kΩ
1%
33.2kΩ
1%
34.8kΩ
1%
107kΩ
1%
20kΩ
1%
400Ω
5%
R13, R14
10.7kΩ
1%
1/4W
10V
C1
0.1µF + 1.0µF
0.1µF + 1.0µF
0.1µF + 1.0µF
0.47µF
20%
20%
20%
20%
20%
10%
C5
50V
C6
100V
10V
C2, C4, C8
C3
2.2µF
50V
C7
680pF
10V
Design Parameters: Maximum onhook voltage = 0.775V
, Maximum offhook voice = 1.1Vpeak, Maximum simultaneous pulse metering signal
RMS
= 3.1Vpeak, Switch Hook Threshold = 9.8mA, Loop Current Limit = 29.6mA, Synthesize Device Impedance = 600-60 = 540Ω, with 30Ω protection
resistors, impedance across Tip and Ring terminals = 600Ω. Where applicable, these component values apply to the Basic Application Circuits for
the HC55120, HC55121, HC55130, HC55140, HC55142 and HC55150. Pins not shown in the Basic Application Circuit are no connect (NC) pins.
25
HC55120, HC55121, HC55130, HC55131, HC55140, HC55141, HC55142, HC55143, HC55150, HC55151
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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26
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