HC55171 [INTERSIL]
5 REN Ringing SLIC for ISDN Modem/TA and WLL; 5 REN振铃SLIC的ISDN调制解调器/ TA和WLL
| 型号： | HC55171 |
| 厂家： | 
Intersil |
| 描述： | 5 REN Ringing SLIC for ISDN Modem/TA and WLL |
| 文件： | 总18页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC55171
Data Sheet
July 1998
File Number 4323.4
5 REN Ringing SLIC for
ISDN Modem/TA and WLL
Features
• 5 REN Thru SLIC Ringing Capability to 75V
PEAK
The HC55171 is backward compatible to the HC5517 with
the added capability of driving 5 REN loads. The HC55171 is
ideal for any modem or remote networking access
application that requires plain old telephone service POTS,
capability. The linear amplifier design allows a choice of
Sinusoidal, Square wave or Trapezoidal ringing. The voltage
feed architecture eliminates the need for a high current gain
node achieving improved system noise immunity, an
advantage in highly integrated systems.
• Trapezoid, Square and Sinusoid Ringing Capability
• Bellcore Compliant Ringing Voltage Levels
• Lowest Component Count Trapezoidal Solution
• Single Additional +5V Supply
• Pin For Pin Compatible With HC5517
• DI Provides Latch-Up Immunity
Applications
The device is manufactured in a high voltage Dielectric
Isolation (DI) process with an operating voltage range from
-16V, for off-hook operation and -80V for ring signal injection.
The DI process provides substrate latch up immunity,
resulting in a robust system design.
• ISDN Internal/External Modems
• ISDN Terminal Adapters/Routers
• Wireless Local Loop Subscriber Terminals
• Cable Telephony Set-Top Boxes
• Digital Added Main Line
Ordering Information
TEMP. RANGE
PKG.
NO.
• Integrated LAN/PBX
o
PART NUMBER
HC55171IM
( C)
PACKAGE
28 Ld PLCC
28 Ld PLCC
28 Ld SOIC
28 Ld SOIC
• Related Literature
-40 to 85
0 to 75
N28.45
N28.45
M28.3
M28.3
- AN9606, Operation of the HC5517/171 Evaluation
Board
HC55171CM
HC55171IB
- AN9607, Impedance Matching Design Equations
- AN9628, AC Voltage Gain
-40 to 85
0 to 75
HC55171CB
- AN9608, Implementing Pulse Metering
- AN9636, Implementing an Analog Port for ISDN Using
the HC5517
- AN549, The HC-5502X/4X Telephone Subscriber Line
Interface Circuits (SLIC)
Block Diagram
V
V
RX
TX
TIP FEED
4-WIRE
INTERFACE
TIP SENSE
2-WIRE
INTERFACE
V
RING
LOOP CURRENT
DETECTOR
RING FEED
RING SENSE 1
RING SENSE 2
- IN 1
-
+
FAULT
DETECTOR
OUT 1
V
REF
RTI
CURRENT
LIMIT
SHD
ALM
V
BAT
RING TRIP
DETECTOR
V
CC
I
LMT
BIAS
RTD
RDO
AGND
BGND
RELAY
DRIVER
IIL LOGIC INTERFACE
F1
F0
RS TST
RDI
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
62
HC55171
o
Absolute Maximum Ratings T = 25 C
Thermal Information
A
o
Maximum Supply Voltages
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
V
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7V
CC
CC
PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
55
70
- V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90V
BAT
o
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +15V
o
o
o
Operating Conditions
(SOIC, PLCC - Lead Tips Only)
Temperature Range
HC55171IM, HC55171IB . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
HC55171CM, HC55171CB . . . . . . . . . . . . . . . . . . . . 0 C to 75 C
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5V to +12V
Positive Power Supply, V . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
o
o
o
o
Die Characteristics
Transistor Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 x 144
CC
Negative Power Supply, V
. . . . . . . . . . . . . . . . . . . .-16V to -80V
BAT
Substrate Potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
BAT
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are over
A
Operating Temperature Range, V
= -24V, V = +5V, AGND = BGND = 0V. All AC Parameters are specified
BAT
CC
at 600Ω 2-Wire terminating impedance.
TEST CONDITIONS
PARAMETER
RINGING TRANSMISSION PARAMETERS
Input Impedance
MIN
TYP
MAX
UNITS
V
(Note 2)
-
-
5.4
40
-
-
kΩ
RING
4-Wire to 2-Wire Gain
V
to V
T-R
(Note 2)
V/V
RING
AC TRANSMISSION PARAMETERS
RX Input Impedance
300Hz to 3.4kHz (Note 2)
-
108
-
-
-
-
kΩ
V
OUT1 Positive Output Voltage Swing
OUT1 Negative Output Voltage Swing
4-Wire Input Overload Level
R
R
= 10kΩ (Note 2)
= 10kΩ (Note 2)
+2.5
-4.5
-
-
-
L
L
V
300Hz to 3.4kHz R = 1200Ω, 600Ω Reference
+3.1
V
PEAK
L
(Note 2)
2-Wire Return Loss
Matched for 600Ω, f = 300Hz (Note 2)
Matched for 600Ω, f = 1000Hz (Note 2)
Matched for 600Ω, f = 3400Hz (Note 2)
37
40
30
58
-
-
-
-
-
-
dB
dB
dB
dB
-
2-Wire Longitudinal to Metallic Balance
Off Hook
Per ANSI/IEEE STD 455-1976 300Hz to 3400Hz
(Note 2)
63
4-Wire Longitudinal Balance Off Hook
Longitudinal Current Capability
Insertion Loss, 2W-4W
300Hz to 3400Hz (Note 2)
o
-
-
-
-
-
-
55
40
-
dB
I
= 40mA, T = 25 C (Note 2)
-
mA
RMS
LINE
A
0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3
0dBmO,1kHz
±0.05
±0.05
-
±0.2
±0.2
±0.25
±0.06
dB
Insertion Loss, 4W-2W
dB
dB
dB
Insertion Loss, 4W-4W
0dBmO, 1kHz, Includes Tranhybrid Amp Gain = 3
Frequency Response
300Hz to 3400Hz Referenced to Absolute Level
±0.02
at 1kHz, 0dBm Referenced 600Ω
63
HC55171
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are over
A
Operating Temperature Range, V
= -24V, V = +5V, AGND = BGND = 0V. All AC Parameters are specified
BAT
CC
at 600Ω 2-Wire terminating impedance. (Continued)
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
±0.10
±0.12
±0.30
1.0
UNITS
dB
Level Linearity
+3 to 0dBm, Referenced to -10dBm (Note 2)
0 to -40dBm, Referenced to -10dBm (Note 2)
-40 to -55dBm, Referenced to -10dBm (Note 2)
300Hz to 3400Hz (Note 2)
-
-
-
-
dB
-
-
dB
Absolute Delay, 2W-4W
Absolute Delay, 4W-2W
Absolute Delay, 4W-4W
Transhybrid Loss
-
-
-
µs
300Hz to 3400Hz (Note 2)
-
1.0
µs
300Hz to 3400Hz (Note 2)
-
0.95
40
-
-
µs
V
= 1V
P-P
at 1kH (Note 2)
36
-
-
dB
IN
Total Harmonic Distortion
Reference Level 0dBm at 600Ω
-50
dB
2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire 300Hz to 3400Hz (Note 2)
Idle Channel Noise
2-Wire and 4-Wire
C-Message (Note 2)
-
3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
dBrnC
dBmp
dB
Psophometric (Note 2)
-
-87
35
47
28
38
35
46
50
60
34
40
40
50
PSRR, V
PSRR, V
to 2W
to 4W
30Hz to 200Hz, R = 600Ω (Note 2)
30
45
23
33
33
44
40
50
30
35
30
40
CC
CC
L
dB
PSRR, VBAT to 2W
PSRR, VBAT to 4W
dB
dB
PSRR, V
PSRR, V
to 2W
to 4W
200Hz to 3.4kHz, R = 600Ω (Note 2)
dB
CC
CC
L
dB
PSRR, VBAT to 2W
PSRR, VBAT to 4W
dB
dB
PSRR, V
PSRR, V
to 2W
to 4W
3.4kHz to 16kHz, R = 600Ω (Note 2)
dB
CC
CC
L
dB
PSRR, VBAT to 2W
dB
PSRR, VBAT to 4W
dB
DC PARAMETERS
Loop Current Programming Range
Loop Current Programming Accuracy
Loop Current During Power Denial
Fault Current, Tip to Ground
Fault Current, Ring to Ground
Fault Current, Tip and Ring to Ground
Switch Hook Detection Threshold
Ring Trip Comparator Voltage Threshold
Thermal ALARM Output
(Note 3)
20
-
-
60
mA
%
-10
+10
R
= 200Ω, V
BAT
= -48V
-
±4
-
mA
mA
mA
mA
mA
V
L
(Note 2)
-
90
-
-
100
130
12
-
(Note 2)
-
-
15
9
-0.28
-
-0.24
160
-0.22
-
o
Safe Operating Die Temperature Exceeded
(Note 2)
C
Dial Pulse Distortion
(Note 2)
-
0.1
0.5
ms
64
HC55171
o
Electrical Specifications Unless Otherwise Specified, Typical Parameters are at T = 25 C, Min-Max Parameters are over
A
Operating Temperature Range, V
= -24V, V = +5V, AGND = BGND = 0V. All AC Parameters are specified
BAT
CC
at 600Ω 2-Wire terminating impedance. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UNCOMMITTED RELAY DRIVER
On Voltage, V
OL
I
(RDO) = 30mA
-
-
0.2
0.5
V
OL
Off Leakage Current
±10
±100
µA
TTL/CMOS LOGIC INPUTS (F0, F1, RS, TST, RDI)
Logic Low Input Voltage
0
2.0
-
-
-
-
-
0.8
5.5
-1
V
V
Logic High Input Voltage
Input Current
I
I
, 0V ≤ V ≤ 5V
IN
µA
µA
IH
Input Current
, 0V ≤ V ≤ 5V
IN
-
-100
IL
LOGIC OUTPUTS (SHD, RTD, ALM)
Logic Low Output Voltage
Logic High Output Voltage
POWER DISSIPATION
Power Dissipation On Hook
I
I
= 800µA
= 40µA
-
0.1
-
0.5
V
V
LOAD
2.7
5.5
LOAD
-
-
-
-
-
-
-
-
-
V
V
V
= +5V, V
= -80V, R
= -48V, R
= -24V, R
= ∞
300
150
280
mW
mW
mW
CC
CC
CC
BAT
LOOP
LOOP
LOOP
= +5V, V
= +5V, V
= ∞
BAT
BAT
Power Dissipation Off Hook
= 600Ω,
I
= 25mA
L
I
V
V
V
V
V
V
= +5V, V
= +5V, V
= +5V, V
= -80V, R
= -48V, R
= -24V, R
= ∞
= ∞
= ∞
-
-
-
-
-
-
3
6
5
mA
mA
mA
mA
mA
mA
CC
CC
CC
CC
CC
CC
CC
BAT
BAT
BAT
LOOP
LOOP
LOOP
2
1.9
3.6
2.6
2.3
5
I
= +5V, V - = -80V, R
B
= ∞
7
BAT
LOOP
LOOP
LOOP
= +5V, V - = -48V, R
B
= ∞
= ∞
6
= +5V, V - = -24V, R
B
4.5
NOTES:
2. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon
initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and
specification compliance.
3. This parameter directly affects device junction temperature. Refer to Power Dissipation discussion of data sheet for design information.
65
HC55171
Functional Diagram
R
V
OUT 1
12
V
CC
-IN 1
13
V
V
AGND
RING
24
RX
17
TX
19
2
1
R
R
TF
22
27
25
-
BGND
TF
+
-
BIAS
OP AMP
+
NETWORK
R/2
R/20
V
BAT
+2V
4
5
6
9
R
R
2R
F1
F0
TA
-
SH
R
SHD
RTD
+
14
TIP
SENSE
RS
TST
R
2R
THERM
LTD
TSD
4.5K
25K
100K
100K
100K
15
GK
RA
RING
SENSE 1
-
+
100K
4.5K
25K
16
FAULT
DET
RING
SENSE 2
7
SHD
RTD
ALM
8
90K
90K
RFC
10
RF
26
21
GM
-
RF
90K
RDO
+
RF2
VB/2
REF
-
+
R = 108kΩ
3
11
LMT
20
18
NU
28
RTI
V
I
RDI
REF
Power Dissipation
HC55171 DEVICE TRUTH TABLE
F1
F0
0
STATE
Careful thermal design is required to guarantee that the
maximum junction temperature of 150 C of the device is not
exceeded. The junction temperature of the SLIC can be cal-
culated using:
o
0
0
Loop power Denial Active
1
Power Down Latch RESET, Power on
RESET
2
1
1
0
1
RD Active
T
= T + θ (I
V
+ I
V
– ((I
)
• R
))
LOOP
J
A
JA CC CC
BAT BAT
LOOP
Normal Loop feed
(EQ. 1)
The truth table for the internal logic of the HC55171 is pro-
vided in the above table. This family of ringing SLICS can be
configured to support traditional unbalanced ringing and thru
SLIC balanced ringing. Refer to the HC5509A1R3060 for
unbalanced ringing application information. The device oper-
ating states used by thru SLIC ringing applications are loop
power denial and normal feed. During loop power denial, the
tip and ring amplifiers are disabled (high impedance) and the
DC voltage of each amplifier approaches ground. The SLIC
will not provide current to the subscriber loop during this mode
and will not detect loop closure. Voice transmission occurs
during the normal loop feed mode. During normal loop feed
the SLIC is completely operational and performs all transmis-
sion and supervisory functions.
Where T is maximum ambient temperature and θ is junc-
JA
A
tion to air thermal resistance (and is package dependent).
The entire term in parentheses yields the SLIC power dissi-
pation. The power dissipation of the subscriber loop does
not contribute to device junction temperature and is sub-
o
tracted from the power dissipation term. Operating at 85 C,
the maximum PLCC SLIC power dissipation is 1.18W. Like-
wise, the maximum SOIC SLIC power dissipation is 0.92W.
66
HC55171
Circuit Operation and Design Information
Full Duplex Analog Transmission
Introduction
Familiarity with the signal paths of the SLIC is critical in
understanding the full duplex transmission capability of the
device. The analog interfaces of the SLIC are categorized as
2-wire interfaces and 4-wire interfaces.
The HC55171 is a high voltage Subscriber Line Interface Cir-
cuit (SLIC) specifically designed for through SLIC ringing
applications. Through SLIC ringing applications are broadly
defined as any application that requires ringing capability but
does not have the standard wired central office interface. The
most common implementation of the ringing SLIC is in the
analog pots port. The analog pots port provides the ringing
function as well as interface compatibility with answering and
fax machines.
The 2-wire interface of the SLIC consists of the bidirectional
Tip and Ring terminals of the device. A differential transmit-
ter drives AC signals out of the Tip and Ring terminals to the
handset. A differential receiver across Tip and Ring receives
AC signals from the handset. The differential receiver is con-
nected across sense resistors that are in the Tip and Ring
signal paths. The differential transmitter and receiver con-
cept is depicted in Figure 2.
Subscriber Line Interface Basics
The basic SLIC provides DC loop current to power the handset,
supports full duplex analog transmission between the handset
and CODEC, matches the impedance of the SLIC to the
impedance of the handset and performs loop supervision func-
tions to detect when the handset is off hook. The ringing SLIC
adds through the SLIC ringing capability to this suite of fea-
tures. The analog interfaces of the SLIC are categorized as the
2-wire interface (high voltage DC, differential AC) and the 4-wire
interface (low voltage DC, single ended AC).
DIFFERENTIAL
TRANSMITTER
-1
-
+
-
+
DC Loop Current
-
+
DIFFERENTIAL
RECEIVER
The Tip and Ring terminals of the subscriber line circuit are
biased at negative potentials with respect to ground. The Tip
terminal DC potential is slightly negative with respect to
ground, and the ring terminal DC potential is slightly positive
with respect to the battery voltage (resulting in a large nega-
tive voltage). The HC55171 typical Tip DC voltage is -4V and
FIGURE 2. DIFFERENTIAL TRANSMIT/RECEIVE CONCEPT
Since the receiver is connected across the transmit signal
path, one may deduce that in addition to receiving signals
from the handset, the receiver will detect part of the transmit
signal. Indeed this does occur and is the reason that all SLIC
circuits require a hybrid balance or echo cancellation func-
tion.
the typical ring DC voltage is defined as V
ple, when the battery voltage is -24V the ring voltage is -20V.
+ 4V. For exam-
BAT
To clearly comprehend the Tip and Ring interface it is helpful
to understand that the handset and the SLIC constitute a DC
and AC current loop as shown in Figure 1. The loop is often
referred to as the subscriber loop.
The 4-wire interface of the SLIC consists of the receive
(VRX) and transmit (OUT1) terminals. The 4-wire interfaces
are single ended signal paths. The receiver is a dedicated
input port and the transmitter is a dedicated output port. The
4-wire receive input of the SLIC drives the 2-wire differential
transmitter and the 2-wire differential receiver drives the 4-
wire transmit output.
TIP
LOOP
CURRENT
SLIC
RING
The complete signal path for voice signals includes two digi-
tal data busses, a CODEC and a SLIC. There is a receive
data bus and transmit data bus, each with an independent 3-
wire serial interface. The CODEC contains a coder and
decoder. The coder converts the SLIC analog transmit out-
put to digital data for the transmit data bus. The receive digi-
tal data bus is converted to analog data and drives the SLIC
receive input.
FIGURE 1. SUBSCRIBER LOOP
When the handset is on hook (idle) the phone is an open cir-
cuit load and the DC loop current is zero. The SLIC can still
provide AC transmission in this condition, which supports
caller id services. The DC resistance of the off hook handset
is typically 400Ω. Since the Tip DC voltage is more positive
than the ring DC voltage, DC loop current flows from Tip to
Ring when the handset is off hook. The SLIC is designed
with feedback to limit the maximum loop current when the
handset is off hook.
The CODECs use logarithmic compression schemes to
extend the resolution of the 8-bit data to 14 bits. The
accepted compression schemes are A-law (Intersil CODEC -
CD22357A) and µ-law (Intersil CODEC - CD22354A). The
complete signal path from the handset to the CODEC is
shown in Figure 3.
67
HC55171
LOAD IMPEDANCE
SLIC
CODEC
RSYNTH
RSYNTH
PCM
IN
RP
RP
RS
RS
TIP
RX
OUT
TIP
V
RX
TX
IN
RING
-1
OUT1
PCM
OUT
RING
SLIC SOURCE IMPEDANCE
ANALOG
DIGITAL
FIGURE 3. COMPLETE VOICE SIGNAL PATH
FIGURE 4. SLIC IMPEDANCE DIAGRAM
Impedance Matching
showing the impedance terms is shown in Figure 4.
Impedance matching is used to match the AC source imped-
ance of the SLIC to the AC source impedance of the load.
When the impedance is matched, the voltage level at the
receive input of the SLIC will be the same voltage level that is at
the 2-wire differential output (i.e., Tip and Ring). Impedance
matching applies only to the 2-wire interface, not the 4-wire
interface.
Loop Supervision
The SLIC must detect when the subscriber picks up the
handset when the SLIC is not ringing the phone and when
the SLIC is ringing the phone. The HC55171 uses a switch
hook detector output to indicate loop closure when the SLIC
is not ringing the phone. When the SLIC is ringing the
phone, loop closure is indicated by the ring trip detector.
Slic AC signal power levels are most commonly assigned the
units dBmO. The term dBmO refers to milliwatts in a 600Ω
load. The typical AC power level is 0dBmO which is 1mW
referenced to a 600Ω load. The relationship between dBmO
(Recall from earlier discussions that the subscriber loop is
open when the handset is on hook and closed when off
hook. The DC impedance of the handset when off hook is
typically 400Ω.)
and V
is provided in Equation 2.
RMS
2
When the handset is off hook, DC loop current flows from
Tip to Ring and the transmit output voltage increases to a
negative value. In addition to interfacing to the CODEC and
providing the feedback for impedance matching, the transmit
output also drives the input to a voltage comparator. When
the comparator threshold is exceeded, the SHD output goes
to a logic low, indicating the handset is off hook. When the
call is terminated and the handset is returned on hook, the
transmit voltage decreases to zero, crossing the comparator
threshold and setting SHD to a logic high.
(V
)
RMS
(EQ. 2)
------------------------
dBmO = 10 log 1000
600
Substituting 0dBmO into the equation should result in
0.7746 V . For sinusoidal signals, multiply the RMS
RMS
voltage by 1.414 to obtain the peak sinusoidal voltage.
The SLIC impedance matching is achieved by applying a feed
back loop from the transmit output of the SLIC to the receive
input of the SLIC. The transmit output voltage of the HC55171
is proportional to the loop current (DC + AC) flowing in the sub-
scriber loop. The impedance matching feedback only uses the
AC portion of the transmit output voltage. Applying a voltage
gain to the feedback term and injecting it into the receive signal
path, will cause the SLIC to “synthesize” a source impedance
that is nonzero. Recall that the impedance matching sets the
SLIC source impedance equal to the load impedance.
Loop closure must also be detected when the SLIC is ringing
the handset. The balanced ringing output of the SLIC coin-
cides with a zero DC potential between Tip and Ring. There-
fore the ring trip must be designed around an AC only
waveform at the transmit output. When the SLIC is ringing
and the handset is on hook, the echo of the ringing signal is
at the transmit output. When the handset goes off hook, the
amplitude of the ringing echo increases. The increase in
amplitude is detected by an envelope detector. When the
echo increases, the envelope detector output increases and
exceeds the ring trip comparator threshold. Then RTD goes
to a logic low, indicating the handset is off hook. When the
system controller detects a logic low on RTD, the ringing is
turned off and the Tip and Ring terminals return to their
typical negative DC potentials.
The SLIC application circuit requires external sense resistors
in the Tip and Ring signal paths to achieve the differential
receive function. The sense resistors contribute to the source
impedance of the SLIC and are accounted for in the design
equations. Specifically, if the load impedance is 600Ω and
each sense resistor is 50Ω, the SLIC must synthesize an
additional source impedance of 500Ω (i.e., 600Ω - 2(50Ω)).
In addition to the sense resistors, some applications may use a
protection resistor in each of the Tip and Ring leads as part of a
surge protection network. These resistors also contribute to the
SLIC source impedance and can be easily accounted for in the
design equations. If 50Ω protection resistors are added to the
prior example, the SLIC would then have to synthesize 400Ω to
match the load (i.e., 600Ω - 2(50Ω) - 2(50Ω)). A diagram
Design Equations and Operational Theory
The following discussion separates the SLICS’s operation
into its DC and AC path, then follows up with additional cir-
cuit design and application information.
68
HC55171
Current Limit
DC Operation of Tip and Ring Amplifiers
The tip feed to ring feed voltage (Equation 3 minus
Equation 5) is equal to the battery voltage minus 8V. Thus,
with a 48 (24) volt battery and a 600Ω loop resistance,
including the feed resistors, the loop current would be
66.6mA (26.6mA). On short loops the line resistance often
approaches zero and there is a need to control the maximum
DC loop current.
SLIC in the Active Mode
The tip and ring amplifiers are voltage feedback op amps
that are connected to generate a differential output (e.g., if
tip sources 20mA then ring sinks 20mA). Figure 5 shows the
connection of the tip and ring amplifiers. The tip DC voltage
is set by an internal +2V reference, resulting in -4V at the
output. The ring DC voltage is set by the tip DC output volt-
Current limiting is achieved by a feedback network (Figure 5)
age and an internal V
/2 reference, resulting in V +4V
BAT
BAT
that modifies the ring feed voltage (V ) as a function of the
D
at the output. (See Equation 3, Equation 4 and Equation 5.)
loop current. The output of the Transversal Amplifier (TA) has
a DC voltage that is directly proportional to the loop current.
R
R ⁄ 2
This voltage is scaled by R
and R . The scaled voltage
-----------
V
= V = –2V
= –4V
(EQ. 3)
IL1
IL2
TIPFEED
C
is the input to a transconductance amplifier (GM) that com-
pares it to an internal reference level. When the scaled volt-
age exceeds the internal reference level, the
transconductance amplifier sources current. This current
V
R
---
R
BAT
2
R
1 + --- – V
R
(EQ. 4)
(EQ. 5)
--------------
V
V
= V
=
RINGFEED
RINGFEED
D
TIPFEED
charges C in the positive direction causing the ring feed
IL
= V = V
+ 4
D
BAT
voltage (V ) to approach the tip feed voltage (V ). This
D
C
effectively reduces the tip feed to ring feed voltage (V ).
and holds the maximum loop current constant.
T-R
V
RX
R
R
The maximum loop current is programed by resistors R
IL1
R
and R
as shown in Equation 7 (Note: R
is typically
OUT1
IL2
100kΩ).
IL1
TIP FEED
R/20
R/2
R
R
TIP
P1
S1
V
-
RING
+
(0.6)(R
+ R
)
IL2
IL1
(EQ. 7)
I
= -------------------------------------------------
-
+
LIMIT
(200xR
)
V
IL2
C
INTERNAL
+2V REF
+
-
TRANSVERSAL
AMP
TA
-
0
V
TX
+
V
= -4V
TIP FEED
R
R
IL1
IL2
GM
-5
-10
-15
-20
-25
-
CONSTANT VOLTAGE
REGION
+
RF2
90kΩ
90kΩ
RING FEED
R
P2
R
S2
RING
V
GROUNDED FOR
DC ANALYSIS
V
= -20V
90kΩ
-
RING FEED
+
+
-
CURRENT LIMIT
V
-
BAT
2
, V
C
V
D
OUT1 RX
IL
+
REGION I
= 25mA
LOOP
250
500
LOOP RESISTANCE (Ω)
750
∞
0
FIGURE 5. OPERATION OF THE TIP AND RING AMPLIFIERS
FIGURE 6. V
T-R
vs R (V
= -24V, I
BAT
= 25mA)
LIMIT
L
Transmit Output Voltage
Figure 6 illustrates the relationship between V
T-R
and the
loop resistance. The conditions are shown for a battery
voltage of -24V and the loop current limit set to 25mA. For an
open circuit loop the tip feed and ring feed are at -4V and
-20V respectively. When the loop resistance decreases from
infinity to about 640Ω the loop current (obeying Ohm’s Law)
increases from 0mA to the set loop current limit. As the loop
resistance continues to decrease, the ring feed voltage
approaches the tip feed voltage as a function of the
programmed loop current limit (Equation 7).
The transmit output voltage in terms of loop current is
expressed as 200x I
. The 200 term is actually formed
LOOP
by the sum of twice the sense resistors and is shown in the
following equation.
(EQ. 6)
200 × I
= (2 R + 2 R ) × I
S1 S2 LOOP
LOOP
This is a relationship that is critical when modifying the
sense resistor (R , R ). The 200 term factors into the loop
S1 S2
current limit and loop detector functions of the SLIC.
69
HC55171
AC Voltage Gain Design Equations
R
Z0
-----------
2 × –4R ∆I
+ V
RX
S
L
R
RF
(EQ. 15)
The HC55171 uses feedback to synthesize the impedance
at the 2-wire tip and ring terminals. This feedback network
defines the AC voltage gains for the SLIC.
∆I = ------------------------------------------------------------------------------
L
R
+ R + R + R + R
P1 P2 S1 S2
L
Equation 15 simplifies to
The 4-wire to 2-wire voltage gain (V
RX
to V ) is set by the
TR
feedback loop shown in Figure 7. The feedback loop senses
2V
– 400∆I
RX L
800
(EQ. 16)
(EQ. 17)
∆I = ----------------------------------------
L
the loop current through resistors R and R , sums their volt-
S1
S2
age drop and multiplies it by 2 to produce an output voltage at
the V pin equal to +4R ∆I . The V voltage is then fed into
TX TX
S L
Solving for ∆I results in
L
the -IN1 input of the SLIC’s internal op amp. This signal is multi-
V
RX
plied by the ratio R /R and fed into the tip current summing
∆I = -----------
Z0 RF
L
600
node via the OUT1 pin. (Note: the internal V
/2 reference
BAT
(ring feed amplifier) and the internal +2V reference (tip feed
amplifier) are grounded for the AC analysis.)
Equation 17 is the loop current with respect to the feedback
network. From this, the 4-wire to 2-wire and the 2-wire to
4-wire AC voltage gains are calculated. Equation 18 shows
the 4-wire to 2-wire AC voltage gain is equal to 1.00.
The current into the summing node of TF amp is equal to:
4R ∆I
R
Z0
R
RF
S
L
(EQ. 8)
V
-------------------- -----------
= –
I
RX
OUT1
R
-----------
(600)
V
∆I (R )
L L
600
(EQ. 18)
TR
A
= ----------- = -------------------- = -------------------------- = 1
4W – 2W
V
V
V
RX
RX
RX
Equation 9 is the node equation for the tip amplifier summing
node. The current in the tip feedback resistor (I ) is given in
Equation 7.
R
Equation 19 shows the 2-wire to 4-wire AC voltage gain is
equal to -0.333.
4R ∆I
R
Z0
R
RF
V
R
S
L
RX
Z0
V
(EQ. 9)
-------------------- -----------
– I
–
+ ----------- = 0
-----------
–4R ∆I
RX
R
S
L
R
R
-----------
–200
(1)
R
V
RF
600
1
3
OUT1
A
= ------------------ = ----------------------------------------- = --------------------------------- = –--
2W – 4W
V
∆I (R )
V
TR
L
L
RX
-----------
(600)
4R ∆I
R
Z0
R
RF
V
600
S
L
RX
R
(EQ. 10)
-------------------- -----------
I
= –
+ -----------
R
(EQ. 19)
R
The AC voltage at V is then equal to:
C
Impedance Matching
The feedback network, described above, is capable of
synthesizing both resistive and complex loads. Matching the
SLIC’s 2-wire impedance to the load is important to maxi-
mize power transfer and maximize the 2-wire return loss.
The 2-wire return loss is a measure of the similarity of the
impedance of a transmission line (tip and ring) and the
impedance at it’s termination. It is a ratio, expressed in deci-
bels, of the power of the outgoing signal to the power of the
signal reflected back from an impedance discontinuity.
(EQ. 11)
(EQ. 12)
V
V
= (I )(R)
C
C
R
R
Z0
-----------
= –4R ∆I
+ V
RX
S
L
R
RF
and the AC voltage at V is:
D
R
Z0
(EQ. 13)
-----------
V
= 4R ∆I
– V
RX
D
S
L
R
RF
Requirements for Impedance Matching
Impedance matching of the HC55171 application circuit to the
transmission line requires that the impedance be matched to
points “A” and “B” in Figure 7. To do this, the sense and pro-
tection resistors R , R , R and R must be accounted
The values for R
Z0
and R
are selected to match the
RF
impedance requirements on tip and ring, for more
information refer to AN9607 “Impedance Matching Design
Equations for the HC5509 Series of SLICs”. The following
P1
P2
S1
S2
for by the feedback network to make it appear as if the output
of the tip and ring amplifiers are at points “A” and “B”. The
feedback network takes a voltage that is equal to the voltage
drop across the sense resistors and feeds it into the summing
node of the tip amplifier. The effect of this is to cause the tip
feed voltage to become more negative by a value that is pro-
loop current calculations will assume the proper R
and
Z0
R
values for matching a 600Ω load.
RF
The loop current (∆I ) with respect to the feedback network, is
L
calculated in Equations 14 through 17. Where R = 40kΩ,
Z0
R
= 40kΩ, R = 600Ω, R = R = R = R = 50Ω.
P1 P2 S1 S1
RF
L
portional to the voltage drop across the sense resistors R
and R . At the same time the ring amplifier becomes more
S1
P1
V
– V
D
C
(EQ. 14)
∆I = ------------------------------------------------------------------------------
L
R
+ R + R + R + R
P1 P2 S1 S2
L
positive by the same amount to account for resistors R
P2
and R
S2
.
Substituting the expressions for V and V
C
D
The net effect cancels out the voltage drop across the feed
resistors. By nullifying the effects of the feed resistors the
70
HC55171
feedback circuitry becomes relatively easy to match the
impedance at points “A” and “B”.
R
L
LOAD
Impedance Matching Design Equations
R
Z0
+
∆V
SLIC
8RS ------------ + 4R
IN
-
S
R
Matching the impedance of the SLIC to the load is
RF
accomplished by writing a loop equation starting at V and
D
going around the loop to V .
C
FIGURE 8. SCHEMATIC REPRESENTATION OF EQUATION 20
The loop equation to match the impedance of any load is as
The result is shown in Equation 23. Figure 8 is a schematic
representation of Equation 18. To match the impedance of
the SLIC to the impedance of the load, set:
follows (note: V
= 0 for this analysis):
RX
R
R
Z0
Z0
-----------
RF
-----------
–4R ∆I
+ 2R ∆I –∆V + R ∆I + 2R ∆I –4R ∆I
S
L
S
L
IN
L
L
S
L
S
L
R
R
RF
R
Z0
(EQ. 24)
(EQ. 20)
-----------
RF
8R
+ 4R = R
S L
S
R
R
Z0
If R is made to equal 8R then:
RF
(EQ. 21)
S
-----------
∆V = –8R ∆I
+ 4R ∆I + R ∆I
S L L L
IN
S
L
R
RF
(EQ. 25)
R
+ 4R = R
S L
Z0
R
Z0
(EQ. 22)
-----------
∆V = ∆I –8R
+ 4R + R
S L
Therefore to match the HC5517, with R equal to 50Ω, to a
600Ω load:
S
IN
L
S
R
RF
(EQ. 26)
R
= 8R = 8(50Ω) = 400Ω
Equation 22 can be separated into two terms, the feedback
RF
S
(-8R (R /R )) and the loop impedance (+4R +R ).
S
Z0 RF
S
L
and
(EQ. 27)
R
∆V
(EQ. 23)
R
= R –4R = 600Ω – 200Ω = 400Ω
Z0
IN
Z0
L
S
-----------
------------ = –8R
+ [4R + R ]
S
S
L
R
∆I
RF
L
To prevent loading of the V
output, the value of R and
Z0
TX
R
are typically scaled by a factor of 100:
RF
(EQ. 28)
KR
= 40kΩ
KR
= 40kΩ
RF
Z0
Since the impedance matching is a function of the voltage
gain, scaling of the resistors to achieve a standard value is
recommended.
R
–4(R ∆I ) R
V
S
L
Z0
RX
R
I
I
= ----------------------------- ------------ + ------------
R
R
R
R
RF
R
R
For complex impedances the above analysis is the same.
Reactive
∆I
∆I
+
L
-
R/20
+
L
-
(KR
= 40kΩ) KR = 100(Resistive – 200) + --------------------------
Z0
RF
100
R
R
S1
P1
-
TIP
A
R/2
(EQ. 29)
+
-
+
V
C
Refer to application note AN9607 (“Impedance Matching
Design Equations for the HC5509 Series of SLICs”) for the
V
= –4R
∆
C
S
values of KR
impedances.
and KR for many worldwide typical line
RF
Z0
-
∆I
V
TR
R
Through SLIC Ringing
L
L
+
R
= R = R = R = R
P2 S1 S2
P1
S
The HC55171 uses linear amplification to produce the ringing
signal. As a result the ringing SLIC can produce sinusoid,
trapezoid or square wave ringing signals. Regardless of the
wave shape, the ringing signal is balanced. The balanced
waveform is another way of saying that the tip and ring DC
potentials are the same during ringing. The following figure
shows the Tip and Ring waveforms for sinusoid and trapezoid
wave shapes as can be displayed using an oscilloscope.
∆V
-
IN
+
∆I
L
-
+
90kΩ
90kΩ
B
R
R
S2
P2
-
RING
+
+
-
∆I
∆I
-
L
+
L
-
+
V
D
V
D
= 4R
Pertinent Bellcore Ringing Specifications
S
Bellcore has defined bounds around the existing unbalanced
ringing signal that is supplied by the central office. The
FIGURE 7. AC VOLTAGE GAI
71
HC55171
circuit published in the HC5517 and HC55171 data sheet.
GROUND
TABLE 1. RING TRIP COMPONENT DIFFERENCES
COMPONENT HC5517 COMPONENT HC55171
47kΩ 51.1kΩ
TIP
R
R
C
R
R
C
15
17
10
RT3
RT1
RT
56.2kΩ
1.0µF
49.9kΩ
0.47µF
RING
BATTERY
GROUND
The sinusoidal circuit published in the HC5517 can be used
as an additional reference circuit for the HC55171. To gener-
ate a sinusoid ringing signal, two conditions must be met on
(A) SINUSOID
TIP
the ringing (V
) input of the SLIC.
RING
The first condition is that a positive DC voltage, which is directly
related to the battery voltage, must be present at the ringing
input. The DC voltage is used to force the Tip and Ring DC out-
puts to half the battery voltage. Having both the Tip and Ring
amplifiers biased at the same DC voltage during ringing is one
RING
BATTERY
(B) TRAPEZOID
characteristic of balanced ringing. The centering voltage (V )
C
can be calculated from the following equation.
V
FIGURE 9. BALANCED RINGING WAVESHAPES
HC55171 ringing SLIC meets the REN drive requirement, the
crest factor limitations and the minimum RMS ringing voltage.
BAT
(EQ. 30)
V
=
– 4 ⁄ 20
--------------
C
2
The foremost requirement is that the ringing source must be
able to drive 5 REN. A REN is a ringer equivalence number
modeled by a 6.93kΩ resistor in series with a 8µF capacitor
(see Figure 10). The impedance of 1 REN at 20Hz is approx-
imately 7kΩ. 5 REN is equivalent to five of the networks in
parallel. Figure 10 provides the Bellcore REN models.
Substituting values of battery voltage, the centering voltage
is +1.8V for a -80V battery and +1.3V for a -60V battery.
The second condition that must be met for sinusoidal ringing
is a low level ringing signal must be applied to the ringing
input of the SLIC. The AC signal that is present at V
will
RING
The crest factor of the ringing waveform is the ratio of the
peak voltage to the RMS voltage. For reference, the crest
factor of a sinusoid is 1.414 and of a square wave is 1.0.
Bellcore defines the crest factor range from 1.2 to 1.6. A sig-
nal with a crest factor between 1.2 and 1.414 resembles the
trapezoid of Figure 9. A signal with a crest factor between
1.414 and 1.6 resembles a “rounded triangular” wave shape
and is an inefficient waveform for the ringing SLIC.
be amplified by a gain of 20 through the Tip amplifier and a
then inverted through the ring amplifier, resulting in a differ-
ential gain of 40. The maximum low level amplitude that can
be injected for a given battery voltage can be determined
from the following equation.
(EQ. 31)
V
= (V
– 8) ⁄ 20
BAT
RING(Max)
The maximum output swing may be increased by driving the
negative by 200mV. Equation 31 can then by
40µF
1386Ω
V
RING
rewritten as:
5 REN
6930Ω
(EQ. 32)
V
= (V
– 5) ⁄ 20
BAT
RING(Max)
8µF
Exceeding the maximum signal calculated from the above
equation will cause the peaks of the sinusoid to clip at
ground and battery. The compression will reduce the crest
factor of the waveform, producing a trapezoidal waveform.
This is just one method, though inefficient, for achieving trap-
ezoidal ringing. The application circuit provided with the
HC55171 has been specifically developed for trapezoidal
ringing and may also be used with the HC5517.
1 REN
FIGURE 10. BELLCORE RINGER EQUIVALENCE MODELS
The third pertinent Bellcore requirement is the that RMS ringing
voltage must be greater than 40V
at the telephone instru-
at the end of
RMS
ment. The HC5517 is able to deliver 40V
RMS
500Ω loops. The 500Ω loop drive capability of the HC5517 is
achieved with trapezoidal ringing.
Trapezoidal Ringing
Sinusoidal Ringing
The trapezoidal ringing waveform provides a larger RMS
voltage to the handset. Larger RMS voltages to the handset
provide more power for ringing and also increase the loop
length supported by the ringing SLIC.
The HC55171 uses the same sinusoidal application circuit
as the HC5517. The only difference being the values of three
components in the ring trip filter. The following table lists the
components and the different values required by each
device. All reference designators refer to the application
The HC55171 trapezoidal ringing application circuit will oper-
ate for loop lengths ranging from 0Ω to 500Ω. In addition, one
72
HC55171
TABLE 5. CREST FACTOR PROGRAMMING RESISTOR FOR
= -60V
set of component values will satisfy the entire ringing loop
V
range of the SLIC. A single resistor sets the open circuit RMS
ringing voltage, which will set the crest factor of the ringing
waveform. The crest factor of the HC55171 ringing waveform
is independent of the ringing load (REN) and the loop length.
Another robust feature of the HC55171 ringing SLIC is the
ring trip detector circuit. The suggested values for the ring trip
detector circuit cover quite a large range of applications.
BAT
CF
R
RMS
R
CF
RMS
TRAP
TRAP
0Ω
1.10
1.15
1.20
48.2
45.6
43.7
1460Ω
1760Ω
2030Ω
1.25
1.30
1.35
42.0
40.4
38.8
740Ω
1129Ω
Ringing Voltage Limiting Factors
The assumptions used to design the trapezoidal ringing
application circuit are listed below:
As the load impedance decreases (increasing REN), the
feedback used for impedance synthesis slightly attenuates
the ringing signal. Another factor that attenuates the ringing
signal is the voltage divider formed by the sense resistors
and the impedance of the ringing load. As the load imped-
ance decreases, the 100Ω of sense resistors becomes a
larger percentage of the load impedance.
• Loop current limit set to 25mA.
• Impedance matching is set to 600Ω resistive.
• 2-wire surge protection is not required.
• System able to monitor RTD and SHD.
• Logic ringing signal is used to drive RC trapezoid network.
If surge protection resistance must be used with the
trapezoidal circuit, the loop length performance of the circuit
will decrease. The decrease in ringing loop length is caused
by the addition of protection resistors in series with the Tip
and Ring outputs. The amount of protection resistance that
is added will subtract directly from the loop length. For exam-
ple if 30Ω protection resistors is used in each of the Tip and
Ring leads, the ringing loop length will decrease by a total of
60Ω. Therefore, subtracting 60Ω from the graphs will provide
the reduced loop length data.
Crest Factor Programming
As previously mentioned, a single resistor is required to set
the crest factor of the trapezoidal waveform. The only design
variable in determining the crest factor is the battery voltage.
The battery voltage limits the peak signal swing and
therefore directly determines the crest factor.
A set of tables will be provided to allow selection of the crest
factor setting resistor. The tables will include crest factors
below the Bellcore minimum of 1.2 since many ringing SLIC
applications are not constrained by Bellcore requirements.
Lab Measurements
TABLE 2. CREST FACTOR PROGRAMMING RESISTOR FOR
The lab measurements of the trapezoidal ringing circuit were
made with the crest factor programming resistor set to 0Ω
and the battery voltage set to -80V. The Bellcore suggested
REN model was used to simulate the various ringing loads.
A resistor in series with the Tip terminal was used to emulate
loop length.
V
= -80V
BAT
R
CF
RMS
R
CF
RMS
TRAP
TRAP
0Ω
1.10
1.15
1.20
65.0
62.6
60.0
825Ω
964Ω
1.25
1.30
1.35
57.6
55.4
53.3
389Ω
640Ω
1095Ω
A logic gate is used to drive the RC shaping network. When
the crest factor programming resistor is set to 0Ω, the output
impedance of the logic gate results in a 0.8V/ms slewing
The RMS voltage listed in the table is the open circuit RMS
voltage generated by the SLIC.
voltage on C
.
TRAP
TABLE 3. CREST FACTOR PROGRAMMING RESISTOR FOR
Each graph shows the RMS ringing voltage into a fixed REN
load versus loop length. The ringing voltage was measured
across the test load. Each test also verified proper operation
of the ring trip detector. Proper ring trip detector operation is
defined as a constant logic high while ringing and on hook
and a constant logic low when off hook is detected. The
component values in the application circuit provide a ring trip
response in the 100ms to 150ms range.
V
= -75V
BAT
R
CF
RMS
R
CF
RMS
TRAP
TRAP
0Ω
1.10
1.15
1.20
60.9
58.3
55.9
1010Ω
1190Ω
1334Ω
1.25
1.30
1.35
53.7
51.6
49.7
500Ω
791Ω
TABLE 4. CREST FACTOR PROGRAMMING RESISTOR FOR
= -65V
V
BAT
CF
R
RMS
R
CF
RMS
TRAP
TRAP
0Ω
1.10
1.15
1.20
52.5
49.8
47.8
1330Ω
1600Ω
1800Ω
1.25
1.30
1.35
45.9
44.1
42.5
660Ω
1040Ω
73
HC55171
55
52
49
46
43
60
59
58
57
56
0
100
200
300
400
500
0
100
200
300
400
500
LOOP IMPEDANCE
LOOP IMPEDANCE
FIGURE 14. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 4
56
FIGURE 11. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 1
58
56
54
52
50
52
48
44
40
0
100
200
300
400
500
LOOP IMPEDANCE
0
100
200
300
400
500
FIGURE 15. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 5
Low Level Ringing Interface
LOOP IMPEDANCE
FIGURE 12. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 2
58
The trapezoidal application circuit only requires a cadenced
logic signal applied to the wave shaping RC network to
achieve ringing. When not ringing, the logic signal should be
held low. When the logic signal is low, Tip will be near
ground and Ring will be near battery. When the logic signal
is high, Tip will be near battery and Ring will be near ground.
55
52
49
46
0
100
200
300
400
500
LOOP IMPEDANCE
FIGURE 13. RMS RINGING VOLTAGE vs LOOP LENGTH REN = 3
74
HC55171
Loop Detector Interface
Tip-to-Ring Open Circuit Voltage
The RTD output should be monitored for off hook detection
during the ringing period. At all other times, the SHD should
be monitored for off hook detection. The application circuit
can be modified to redirect the ring trip information through
the SHD interface. The change can be made by rewiring the
application circuit, adding a pullup resistor to pin 23 and set-
ting F0 low for the entire duration of the ringing period. The
modifications to the application circuit for the single detector
interface are shown in Figure 16.
The tip-to-ring open-circuit voltage, V , of the HC55171
OC
may be programmed to meet a variety of applications. The
design of the HC5517 defaults the value of V
to:
OC
V
V
– 8
BAT
OC
Using a zener diode clamping circuit, the default open circuit
voltage of the SLIC may be defeated. Some applications that
have to meet Maintenance Termination Unit (MTU) compli-
ance have a few options with the HC55171. One option is to
reduce the ringing battery voltage until MTU compliance is
achieved. Another option is to use a zener clamping circuit
HC55171
ADDITIONAL PULL UP RESISTOR
on V
to over ride the default open circuit voltage when
REF
V
NU 23
RDI 20
CC
operating from a high battery.
If a clamping network is used it is important that it is disabled
during ringing. The clamping network must be disabled to
allow the SLIC to achieve its full ringing capability. A zener
clamping circuit is provided in Figure 18.
RDO 21
R
TRAP
V
V
24
RING
RING
D
TRAP
C
TRAP
HC55171
FIGURE 16. APPLICATION CIRCUIT WIRING FOR SINGLE
LOOP DETECTOR INTERFACE
C
IL
V
3
REF
+5V
47kΩ
SLIC Operating State During Ringing
The SLIC control pin F1 should always be a logic high during
ringing. The control pin F0 will either be a constant logic high
(two detector interface) or a logic low (single detector inter-
face). Figure 17 shows the control interface for the dual
detector interface and the single detector interface.
2N2907
EN
FIGURE 18. ZENER CLAMP CIRCUIT WITH DISABLE
The following equations are used to predict the DC output of
the ring feed amplifier when using the zener clamping net-
Additional Application Information
work, V
.
RDC
V
V
BAT
2
BAT
2
(EQ. 33)
(EQ. 34)
--------------
+ 4
< V
≥ V
V
V
= 2
--------------
Z
Z
RDC
RDC
(DUAL DETECTOR INTERFACE)
ACTIVE
ACTIVE
RINGING
MODE
V
BAT
--------------
= 2(–V + (V
– V )) + 4
BE
(LOGIC HI)
Z
CE
2
F1
F0
(LOGIC HI)
Where V is the zener diode voltage and V
CE
and V
are
BE
Z
the saturation voltages of the pnp transistor. Using Equa-
tions 31 and 32, the tip-to-ring open-circuit voltage can be
calculated for any value of zener diode and battery voltage.
V
RING
SHD
SHD
RTD
VALID DET
MODE
V
V
BAT
2
BAT
2
(EQ. 35)
--------------
– 4
< V
V
= V
– 2
--------------
Z
Z
OC
OC
TDC
TDC
(SINGLE DETECTOR INTERFACE)
RINGING
ACTIVE
ACTIVE
V
BAT
--------------
≥ V
V
= V
– 2(–V + (V
– V )) – 4
BE
Z
CE
(LOGIC HI)
2
(EQ. 36)
F1
F0
(LOGIC HI)
When the base of the pnp transistor is pulled high (+5V), the
transistor is off and the zener clamp is disabled. When the
base of the transistor is pulled low (0V) the transistor is on
and the zener will clamp as long as half the battery voltage is
greater than the zener voltage.
V
RING
SHD
SHD
SHD
VALID DET
FIGURE 17. DETECTOR LOGIC INTERFACES
75
HC55171
Polarity Reversal
The DC reference from the CODEC is used to bias the
analog signals between +5V and ground. The capacitors are
required so that the DC gain is unity for proper biasing from
the CODEC reference. Also, the capacitors block DC signals
that may interfere with SLIC or CODEC operation.
The HC55171 supports applications that use polarity reversal
outside the speech phase of a call connection. The most com-
mon implementation of this type of polarity reversal is used
with pay phones. By reversing the polarity of the tip and ring
terminals of a pay phone, DC current changes direction in a
solenoid and the coins are released from the phone. To
Layout Guidelines and Considerations
reverse the polarity of the HC55171, simply toggle the V
RING
The printed circuit board trace length to all high impedance
nodes should be kept as short as possible. Minimizing length
will reduce the risk of noise or other unwanted signal pickup.
The short lead length also applies to all high gain inputs. The
set of circuit nodes that can be categorized as such are:
input high. Setting the V
Ring to reverse polarity.
input high will cause Tip and
RING
Transhybrid Balance
Since the receive signal and its echo are 180 degrees out of
phase, the summing node of an operational amplifier can be
used to cancel the echo. Nearly all CODECs have an inter-
nal amplifier for echo cancellation. The following Figure 19
shows the cancellation amplifier circuit.
• V
pin 27, the 4-wire voice input.
• -IN1 pin 13, the inverting input of the internal amplifier.
RX
• V
• V
pin 3, the noninverting input to ring feed amplifier.
REF
pin 24, the 20V/V input for the ringing signal.
RING
R
R
F
A
For multi layer boards, the traces connected to tip should not
cross the traces connected to ring. Since they will be carry-
ing high voltages, and could be subject to lightning or surge
depending on the application, using a larger than minimum
trace width is advised.
V
RX
R
B
V
-
OUT1
VO
+
The 4-wire transmit and receive signal paths should not
FIGURE 19. TRANHYBRID AMPLIFIER CIRCUIT
cross. The receive path is any trace associated with the V
RX
input and the transmit path is any trace associated with V
TX
output. The physical distance between the two signal paths
should be maximized to reduce crosstalk.
When the SLIC is matched to a 600Ω load, the echo ampli-
tude is 1/3 the receive input amplitude. Therefore, by config-
uring the transhybrid amplifier with a gain of 3 in the echo
path, cancellation can be achieved. The following equations:
The mode control signals and detector outputs should be
routed away from the analog circuitry. Though the digital sig-
nals are nearly static, care should be taken to minimize cou-
pling of the sharp digital edges to the analog signals.
R
R
F
F
(EQ. 37)
-------
+ V
OUT1
-------
V
= – V
O
RX
R
A
R
B
The part has two ground pins, one is labeled AGND and the
other BGND. Both pins should be connected together as
close as possible to the SLIC. If a ground plane is available,
then both AGND and BGND should be connected directly to
the ground plane.
Substituting the fact that V
R
is -1/3 of V
RX
OUT1
R
F
1
F
(EQ. 38)
-------
-- -------
V
= – V
– V
O
RX
RX
R
A
3
R
B
Since cancellation implies that under these conditions, the
output V should be zero, set Equation 37 equal to zero and
A ground plane that provides a low impedance return path
for the supply currents should be used. A ground plane pro-
vides isolation between analog and digital signals. If the lay-
out density does not accommodate a ground plane, a single
point grounding scheme should be used.
O
solve for R .
B
R
A
3
(EQ. 39)
R
= -------
B
Another outcome of the transhybrid gain selection is the 2-
wire to 4-wire gain of the SLIC as seen by the CODEC. The
1/3 voltage gain in the transmit path is relevant to the receive
input as well as any signals from the 2-wire side. Therefore
CODEC
RX OUT
V
RX
R
A
by setting the V
the 2-wire to 4-wire gain was set to unity.
gain to three in the previous analysis,
R
F
OUT1
R
B
-
+
TX IN
Single Supply Codec Interface
VOUT1
HC55171
+
-
The majority of CODECs that interface to the ringing SLIC
operate from a single +5V supply and ground. Figure 20
shows the circuitry required to properly interface the ringing
SLIC to the single supply CODEC.
+2.5V
FIGURE 20. SINGLE SUPPLY CODEC INTERFACE
The CODEC signal names may vary from different
manufacturers, but the function provided will be the same.
76
HC55171
Pin Descriptions
PLCC
SYMBOL
DESCRIPTION
1
2
3
4
AGND
Analog Ground - Serves as a reference for the transmit output and receive input terminals.
Positive Voltage Source - Most Positive Supply.
V
CC
V
An external voltage connected to this pin will override the internal V /2 reference.
BAT
REF
F1
Power Denial - An active low TTL compatible logic control input. When enabled, the output of the ring amplifier will
ramp close to the output voltage of the tip amplifier.
5
6
7
8
F0
TTL compatible logic control input that must be tied high for proper SLIC operation.
TTL compatible logic control input that must be tied high for proper SLIC operation.
Switch Hook Detection - An active low TTL compatible logic output. Indicates an off-hook condition.
RS
SHD
RTD
Ring Trip Detection - An active low TTL compatible logic output. Indicates an off-hook condition when the phone is
ringing.
9
TST
A TTL logic input. A low on this pin will keep the SLIC in a power down mode. The TST pin in conjunction with the
ALM pin can provide thermal shutdown protection for the SLIC. Thermal shutdown is implemented by a system
controller that monitors the ALM pin. When the ALM pin is active (low) the system controller issues a command to the
TST pin (low) to power down the SLIC. The timing of the thermal recovery is controlled by the system controller.
10
ALM
A TTL compatible active low output which responds to the thermal detector circuit when a safe operating die
temperature has been exceeded.
11
12
13
14
I
Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions.
The analog output of the spare operational amplifier.
LMT
OUT1
-IN1
The inverting analog input of the spare operational amplifier. The non-inverting input is internally connected to AGND.
TIP SENSE
An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor. Functions
with the RING terminal to receive voice signals and for loop monitoring purpose.
15
RING SENSE 1 An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions
with the TIP terminal to receive voice signals and for loop monitoring purposes.
16
17
RING SENSE 2 This is an internal sense mode that must be tied to RING SENSE 1 for proper SLIC operation.
V
Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed
and Ring Feed amplifiers deferentially.
RX
18
19
NU
Not used in this application.This pin should be left floating.
V
Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP
and RING. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary.
TX
20
21
22
23
24
25
26
27
28
RDI
RDO
BGND
NU
TTL compatible input to drive the uncommitted relay driver.
This is the output of the uncommitted relay driver.
Battery Ground - All loop current and some quiescent current flows into this terminal.
Not used in this application. This pin should be either grounded or left floating.
Ring signal input.
V
RING
TF
This is the output of the tip amplifier.
RF
This is the output of the ring amplifier.
V
The negative battery source.
BAT
RTI
Ring Trip Input - This pin is connected to the external negative peak detector output for ring trip detection.
77
HC55171
Pinouts
HC55171 (PLCC)
HC55171 (SOIC)
TOP VIEW
TOP VIEW
AGND
1
2
3
4
5
6
7
8
9
28 RTI
27 V
V
CC
BAT
4
27
3
2
1
28
26
26 RF
VREF
F1
TF
F0
25
24
5
6
25 TF
VRING
RS
F0
24 VRING
23 NU
RS
23 NU
22
SHD
RTD
TST
7
8
SHD
RTD
TST
22 BGND
21 RDO
BGND
RDO
RDI
9
10
11
21
20
19
20
RDI
ALM
ILMT
ALM 10
ILMT 11
19 V
TX
18 NU
17 V
V
TX
12
13
14
15
17
16
18
OUT 1 12
RX
-IN 1 13
16 RING SENSE 2
15 RING SENSE 1
TIP SENSE 14
Trapezoidal Ringing Application Circuit
U1
HC55171
C
RX
14 TIP SENSE
TIP
V
17
V-REC
RX
R
S1
25 TF
R
IL2
ILIMT 11
26 RF
R
IL1
16 RING SENSE 2
15 RING SENSE 1
V
19
TX
R
C
R
S2
AC
RING
RF
-IN1 13
R
ZO
OUT1 12
V-XMIT
2 V
CC
V
CC
R
R
RT1
RT2
1 AGND
RTI 28
C
C
PS1
22 BGND
D
R
RT
C
RT3
RT
PS2
27 V
BAT
V
BAT
R
TRAP
V
V
24
RING
RING
D
TRAP
C
TRAP
C
IL
V
3
REF
4 F1
F1
F0
SHD
5 F0
SHD 7
RTD 8
RTD
ALM
VCC
6 RS
TST
9 TST
20 RDI
ALM 10
FIGURE 21. TRAPEZOIDAL RINGING APPLICATION CIRCUIT
78
HC55171
HC55171 Trapezoidal Ringing Application Circuit Parts List
COMPONENT
VALUE
HC55171
49.9Ω
TOLERANCE
RATING
N/A
COMPONENT
VALUE
7.68kΩ
TOLERANCE
RATING
1/8W
1/8W
100V
50V
U1 - Ringing Slic
N/A
1%
1%
1%
1%
1%
1%
R
R
C
1%
1%
IL2
TRAP
R
R
R
R
R
R
, R
S1 S2
1/2W
1/8W
1/8W
1/8W
1/8W
1/8W
App Driven
0.1µF
, R
56.2kΩ
49.9kΩ
1.5MΩ
, C
PS1 PS2
10%
10%
10%
ZO IL1
C , C , C , C
IL RT AC RX
0.47µF
4.7µF
RT1
RT2
RT3
RF
C
D
10V
TRAP
51.1kΩ
45.3kΩ
, D
RT TRAP
1N914
Generic Rectifier Diode
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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79
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