HC5515IP [INTERSIL]
ITU CO/PABX SLIC with Low Power Standby; ITU CO / PABX SLIC与低功耗待机
| 型号： | HC5515IP |
| 厂家： | 
Intersil |
| 描述： | ITU CO/PABX SLIC with Low Power Standby |
| 文件： | 总17页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HC5515
Data Sheet
October 1998
File Number 4235.4
ITU CO/PABX SLIC with Low Power
Standby
Features
• DI Monolithic High Voltage Process
The HC5515 is a subscriber line interface circuit which is
interchangeable with Ericsson’s PBL3860 for distributed
central office applications. Enhancements include immunity
to circuit latch-up during hot plug and absence of false
signaling in the presence of longitudinal currents.
• Programmable Current Feed (20mA to 60mA)
• Programmable Loop Current Detector Threshold and
Battery Feed Characteristics
• Ring Trip Detection
The HC5515 is fabricated in a High Voltage Dielectrically
Isolated (DI) Bipolar Process that eliminates leakage
currents and device latch-up problems normally associated
with junction isolated ICs. The elimination of the leakage
currents results in improved circuit performance for wide
temperature extremes. The latch free benefit of the DI
process guarantees operation under adverse transient
conditions. This process feature makes the HC5515 ideally
suited for use in harsh outdoor environments.
• Compatible with Ericsson’s PBL3860
• Thermal Shutdown
• On-Hook Transmission
• Wide Battery Voltage Range (-24V to -58V)
• Low Standby Power
o
o
• -40 C to 85 C Ambient Temperature Range
Applications
Ordering Information
• Digital Loop Carrier Systems
• Fiber-In-The-Loop ONUs
• Wireless Local Loop
• Pair Gain
TEMP.
PKG.
NO.
o
PART NUMBER RANGE ( C)
PACKAGE
28 Ld PLCC
22 Ld PDIP
28 Ld PLCC
22 Ld PDIP
• POTS
• PABX
HC5515CM
HC5515CP
HC5515IM
HC5515IP
0 to 70
0 to 70
N28.45
E22.4
• Hybrid Fiber Coax
-40 to 85
-40 to 85
N28.45
E22.4
• Related Literature
- AN9632, Operation of the HC5523/15 Evaluation Board
Block Diagram
RING RELAY
DRIVER
4-WIRE
RINGRLY
V
INTERFACE
TX
VF SIGNAL
PATH
RSN
DT
DR
RING TRIP
DETECTOR
TIP
RING
2-WIRE
INTERFACE
HPT
HPR
LOOP CURRENT
DETECTOR
E0
C1
C2
DIGITAL
MULTIPLEXER
V
BAT
V
CC
DET
V
BIAS
EE
R
R
D
AGND
BGND
DC
RSG
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
55
HC5515
Absolute Maximum Ratings
Thermal Information
o
Temperature, Humidity
Storage Temperature Range . . . . . . . . . . . . . . . . -65 C to 150 C
Operating Temperature Range. . . . . . . . . . . . . . . -40 C to 110 C
Thermal Resistance (Typical, Note 1)
θ
( C/W)
JA
o
o
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . .
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . .
53
53
o
o
o
o
o
Operating Junction Temperature Range. . . . . . . . -40 C to 150 C
Continuous Power Dissipation at 70 C
o
o
Power Supply (-40 C ≤ T ≤ 85 C)
A
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5W
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . . . 0.5V to 7V
CC
o
Supply Voltage V to GND. . . . . . . . . . . . . . . . . . . . .-7V to 0.5V
EE
Package Power Dissipation at 70 C, t < 100ms, t
> 1s
REP
Supply Voltage V
to GND . . . . . . . . . . . . . . . . . . .-80V to 0.5V
BAT
22 Lead PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
28 Lead PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
Derate above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 C
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/ C
PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.8mW/ C
Maximum Junction Temperature Range . . . . . . . . . -40 C to 150 C
Maximum Storage Temeprature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C
Ground
o
Voltage between AGND and BGND . . . . . . . . . . . . . -0.3V to 0.3V
Relay Driver
Ring Relay Supply Voltage . . . . . . . . . . . . . . . . 0V to V
Ring Relay Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Ring Trip Comparator
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
o
o
+75V
BAT
o
o
o
o
o
to 0V
BAT
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5mA to 5mA
Digital Inputs, Outputs (C1, C2, E0, DET)
(PLCC - Lead Tips Only)
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to V
Output Voltage (DET Not Active) . . . . . . . . . . . . . . . . . .0V to V
CC
Die Characteristics
CC
Gate Count . . . . . . . . . . . . . . . . . . . . . . .543 Transistors, 51 Diodes
Output Current (DET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
o
o
Tipx and Ringx Terminals (-40 C ≤ T ≤ 85 C)
A
Tipx or Ringx Voltage, Continuous (Referenced to GND)V
to +2V
BAT
-20V to +5V
Tipx or Ringx, Pulse < 10ms, T
> 10s . . . . V
REP
BAT
Tipx or Ringx, Pulse < 10µs, T
Tipx or Ringx, Pulse < 250ns, T
> 10s . . . V
-40V to +10V
-70V to +15V
REP
BAT
> 10s. . . V
REP
BAT
Tipx or Ringx Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70mA
ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on an evaluation PC board in free air.
JA
Typical Operating Conditions
These represent the conditions under which the part was developed and are suggested as guidelines.
PARAMETER
Case Temperature
CONDITIONS
MIN
-40
TYP
MAX
100
UNITS
o
-
-
-
-
C
o
o
V
V
V
with Respect to AGND
-40 C to 85 C
4.75
-5.25
-58
5.25
-4.75
-24
V
V
V
CC
EE
o
o
with Respect to AGND
-40 C to 85 C
o
o
with Respect to BGND
-40 C to 85 C
BAT
o
o
Electrical Specifications
T = -40 C to 85 C, V = +5V ±5%, V = -5V ±5%, V
CC EE BAT
= -48V, AGND = BGND = 0V, R
DC1
= R
DC2
= 41.2kΩ,
A
R
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All pin
D
SG F1 F2 HP DC
L
number references in the figures refer to the 28 lead PLCC package.
PARAMETER
Overload Level
CONDITIONS
MIN
3.1
-
TYP
-
MAX
-
UNITS
1% THD, Z = 600Ω, (Note 2, Figure 1)
V
L
PEAK
Longitudinal Impedance (Tip/Ring)
0 < f < 100Hz (Note 3, Figure 2)
20
35
Ω/Wire
A
V
V
T
TX
19
TIP
27
TX
19
1V
TIP
27
RMS
0 < f < 100Hz
V
300Ω
T
E
L
C
R
T
R
L
R
T
600kΩ
600Ω
600kΩ
V
TRO
2.16µF
I
300Ω
DCMET
23mA
V
R
E
RX
R
RX
R
RX
A
R
RING
28
RSN
16
RING
28
RSN
16
300kΩ
300kΩ
LZ = V /A
LZ = V /A
R R R
T
T
T
FIGURE 1. OVERLOAD LEVEL (TWO-WIRE PORT)
FIGURE 2. LONGITUDINAL IMPEDANCE
56
HC5515
o
o
Electrical Specifications
T = -40 C to 85 C, V = +5V ±5%, V = -5V ±5%, V
CC EE BAT
= -48V, AGND = BGND = 0V, R
DC1
= R = 41.2kΩ,
DC2
A
R
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All pin
D
SG F1 F2 HP DC
L
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
LONGITUDINAL CURRENT LIMIT (TIP/RING)
Off-Hook (Active)
CONDITIONS
MIN
TYP
MAX
UNITS
No False Detections, (Loop Current),
LB > 45dB (Note 4, Figure 3A)
20
5
-
-
-
-
mA
/
/
PEAK
Wire
On-Hook (Standby), R = ∞
No False Detections (Loop Current) (Note 5,
Figure 3B)
mA
L
PEAK
Wire
368Ω
368Ω
TIP
27
RSN
16
A
TIP
27
RSN
16
A
2.16µF
C
39kΩ
C
39kΩ
R
DC1
R
E
R
D
E
DC1
R
D
L
L
41.2kΩ
41.2kΩ
-5V
A
-5V
A
2.16µF
2.16µF
C
C
R
C
DC
DC2
DC
R
DC2
R
RING
28
R
RING
28
DC
14
DC
368Ω
41.2kΩ
14
368Ω
1.5µF
1.5µF
41.2kΩ
DET
DET
FIGURE 3A. OFF-HOOK
FIGURE 3B. ON-HOOK
FIGURE 3. LONGITUDINAL CURRENT LIMIT
OFF-HOOK LONGITUDINAL BALANCE
Longitudinal to Metallic
IEEE 455 - 1985, R , R = 368Ω
0.2kHz < f < 4.0kHz (Note 6, Figure 4)
53
53
50
70
70
55
-
-
-
dB
LR LT
Longitudinal to Metallic
Metallic to Longitudinal
R
, R = 300Ω, 0.2kHz < f < 4.0kHz
LR LT
dB
dB
(Note 6, Figure 4)
FCC Part 68, Para 68.310
0.2kHz < f < 1.0kHz
1.0kHz < f < 4.0kHz (Note 7)
50
53
50
55
70
55
-
-
-
dB
dB
dB
Longitudinal to 4-Wire
Metallic to Longitudinal
0.2kHz < f < 4.0kHz (Note 8, Figure 4)
R
, R = 300Ω, 0.2kHz < f < 4.0kHz
LR LT
(Note 9, Figure 5)
4-Wire to Longitudinal
0.2kHz < f < 4.0kHz (Note 10, Figure 5)
50
55
-
dB
R
LT
R
LT
V
TIP
27
V
TX
19
TIP
27
TX
19
300Ω
E
2.16µF
L
E
R
C
TR
T
R
T
V
V
600kΩ
TR
TX
600kΩ
C
2.16µF
V
L
E
RX
R
R
R
LR
RX
RX
RSN
16
RING
28
RSN
16
RING
28
R
LR
300kΩ
300Ω
300kΩ
FIGURE 4. LONGITUDINAL TO METALLIC AND
LONGITUDINAL TO 4-WIRE BALANCE
FIGURE 5. METALLIC TO LONGITUDINAL AND 4-WIRE TO
LONGITUDINAL BALANCE
2-Wire Return Loss
= 20nF
0.2kHz to 0.5kHz (Note 11, Figure 6)
0.5kHz to 1.0kHz (Note 11, Figure 6)
1.0kHz to 3.4kHz (Note 11, Figure 6)
25
27
23
-
-
-
-
-
-
dB
dB
dB
C
HP
TIP IDLE VOLTAGE
Active, I = 0
-
-
-1.5
<0
-
-
V
V
L
Standby, I = 0
L
RING IDLE VOLTAGE
Active, I = 0
-
-46.5
-
V
L
57
HC5515
o
o
Electrical Specifications
T = -40 C to 85 C, V = +5V ±5%, V = -5V ±5%, V
CC EE BAT
= -48V, AGND = BGND = 0V, R
DC1
= R = 41.2kΩ,
DC2
A
R
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All pin
D
SG F1 F2 HP DC
L
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
-
TYP
>-48
-
MAX
-
UNITS
Standby, I = 0
L
V
V
TIP-RING Open Loop Metallic Voltage, V
V
= -52V, R
BAT SG
= 0Ω
43
47
TR
4-WIRE TRANSMIT PORT (V
Overload Level
)
TX
Z
> 20kΩ, 1% THD (Note 12, Figure 7)
3.1
-60
-
-
-
-
V
L
PEAK
mV
Output Offset Voltage
E
= 0, Z = ∞ (Note 13, Figure 7)
60
G
L
Output Impedance (Guaranteed by Design)
0.2kHz < f < 03.4kHz
5
20
Ω
2-Wire to 4-Wire (Metallic to V ) Voltage Gain 0.3kHz < f < 03.4kHz (Note 14, Figure 7)
0.98
1.0
1.02
V/V
TX
Z
2.16µF
D
TIP
27
V
V
TX
19
TIP
27
TX
19
R
L
C
600Ω
V
R
R
TR
R
V
T
M
Z
R
600kΩ
T
V
V
TXO
TX
V
Z
L
S
600kΩ
I
DCMET
23mA
E
G
IN
R
R
RX
RX
RING
28
RSN
16
RING RSN
28 16
R
300kΩ
300kΩ
LR
FIGURE 6. TWO-WIRE RETURN LOSS
FIGURE 7. OVERLOAD LEVEL (4-WIRE TRANSMIT PORT),
OUTPUT OFFSET VOLTAGE, 2-WIRE TO 4-WIRE
VOLTAGE GAIN AND HARMONIC DISTORTION
4-WIRE RECEIVE PORT (RSN)
DC Voltage
I
= 0mA
-
-
0
-
-
V
Ω
RSN
R
Sum Node Impedance (Gtd by Design)
0.2kHz < f < 3.4kHz
20
X
Current Gain-RSN to Metallic
FREQUENCY RESPONSE (OFF-HOOK)
2-Wire to 4-Wire
0.3kHz < f < 3.4kHz (Note 15, Figure 8)
900
1000
1100
Ratio
0dBm at 1.0kHz, E
= 0V
-0.2
-0.2
-0.2
-
-
-
0.2
0.2
0.2
dB
dB
dB
RX
0.3kHz < f < 3.4kHz (Note 16, Figure 9)
4-Wire to 2-Wire
4-Wire to 4-Wire
0dBm at 1.0kHz, E = 0V
G
0.3kHz < f < 3.4kHz (Note 17, Figure 9)
0dBm at 1.0kHz, E = 0V
G
0.3kHz < f < 3.4kHz (Note 18, Figure 9)
INSERTION LOSS
2-Wire to 4-Wire
0dBm, 1kHz (Note 19, Figure 9)
0dBm, 1kHz (Note 20, Figure 9)
-0.2
-0.2
-
-
0.2
0.2
dB
dB
4-Wire to 2-Wire
GAIN TRACKING (Ref = -10dBm, at 1.0kHz)
2-Wire to 4-Wire
+3dBm to +7dBm (Note 21, Figure 9)
-40dBm to +3dBm (Note 21, Figure 9)
-55dBm to -40dBm (Note 21, Figure 9)
-40dBm to +7dBm (Note 22, Figure 9)
-0.15
-0.1
-0.2
-0.1
-
-
-
-
0.15
0.1
0.2
0.1
dB
dB
dB
dB
2-Wire to 4-Wire
2-Wire to 4-Wire
4-Wire to 2-Wire
58
HC5515
o
o
Electrical Specifications
T = -40 C to 85 C, V = +5V ±5%, V = -5V ±5%, V
CC EE BAT
= -48V, AGND = BGND = 0V, R
DC1
= R = 41.2kΩ,
DC2
A
R
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All pin
D
SG F1 F2 HP DC
L
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
4-Wire to 2-Wire
-55dBm to -40dBm (Note 22, Figure 9)
-0.2
-
0.2
dB
GRX = ((V )(300k))/(-3)(600)
- V
is the Tip to Ring Voltage with V
TR1 TR2
Where: V
TR1
= 0V
RSN
and V
is the Tip to Ring Voltage with V
RSN
= -3V
TR2
V
V
= 0V
RSN
RSN
C
R
RX
= -3V
TIP
27
V
TIP
27
RSN
16
TX
19
R
300kΩ
L
600Ω
R
T
R
R
L
DC1
600kΩ
V
TX
600Ω
I
41.2kΩ
V
V
DCMET
TR
TR
E
G
E
RX
C
R
R
DC
RX
DC2
1/ωC < R
L
RING
28
R
RING RSN
28 16
DC
14
1.5µF
41.2kΩ
300kΩ
FIGURE 8. CURRENT GAIN-RSN TO METALLIC
FIGURE 9. FREQUENCY RESPONSE, INSERTION LOSS,
GAIN TRACKING AND HARMONIC DISTORTION
NOISE
Idle Channel Noise at 2-Wire
C-Message Weighting (Note 23, Figure 10)
-
-
8.5
-
-
dBrnC
dBrnp
Psophometrical Weighting
(Note 23, Figure 10)
-81.5
Idle Channel Noise at 4-Wire
C-Message Weighting (Note 24, Figure 10)
-
-
8.5
-
-
dBrnC
dBrnp
Psophometrical Weighting
(Note 23, Figure 10)
-81.5
HARMONIC DISTORTION
2-Wire to 4-Wire
0dBm, 1kHz (Note 25, Figure 7)
-
-
-65
-65
-54
-54
dB
dB
4-Wire to 2-Wire
0dBm, 0.3kHz to 3.4kHz (Note 26, Figure 9)
BATTERY FEED CHARACTERISTICS
Constant Loop Current Tolerance
I = 2500/(R
DC1
-40 C to 85 C (Note 27)
+ R
),
0.85I
0.75I
14
I
I
1.15I
1.25I
20
mA
mA
V
L
DC2
L
L
L
L
o
o
R
= 41.2kΩ
DCX
Loop Current Tolerance (Standby)
I = (V -3)/(R +1800),
L
BAT
L
L
L
o
o
-40 C to 85 C (Note 28)
o
o
Open Circuit Voltage (V
TIP
- V
RING
)
-40 C to 85 C, (Active) R
= ∞
16.67
SG
LOOP CURRENT DETECTOR
On-Hook to Off-Hook
o
o
R
R
R
= 33kΩ, -40 C to 85 C
11
9.5
-
465/R
405/R
17.2
15.0
-
mA
mA
mA
D
D
D
D
o
o
Off-Hook to On-Hook
= 33kΩ, -40 C to 85 C
D
o
o
Loop Current Hysteresis
= 33kΩ, -40 C to 85 C
60/R
D
TIP
27
V
TX
19
R
R
L
T
V
600Ω
TR
V
TX
600kΩ
R
RX
RING RSN
28 16
300kΩ
FIGURE 10. IDLE CHANNEL NOISE
59
HC5515
o
o
Electrical Specifications
T = -40 C to 85 C, V = +5V ±5%, V = -5V ±5%, V
CC EE BAT
= -48V, AGND = BGND = 0V, R
DC1
= R = 41.2kΩ,
DC2
A
R
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All pin
D
SG F1 F2 HP DC
L
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
RING TRIP DETECTOR (DT, DR)
Offset Voltage
CONDITIONS
MIN
TYP
MAX
UNITS
Source Res = 0
Source Res = 0
Source Res = 0
-20
-
-
-
-
-
20
mV
nA
V
Input Bias Current
-360
360
Input Common-Mode Range
Input Resistance
V
+1
0
-
BAT
Source Res = 0, Unbalanced
Source Res = 0, Balanced
1
MΩ
MΩ
3
-
RING RELAY DRIVER
V
at 25mA
I
= 25mA
= 12V
-
-
0.2
-
0.6
10
V
SAT
OL
Off-State Leakage Current
V
µA
OH
DIGITAL INPUTS (E0, C1, C2)
Input Low Voltage, V
IL
0
2
-
-
-
-
-
0.8
V
Input High Voltage, V
V
V
IH
CC
-
Input Low Current, I : C1, C2
V
V
V
= 0.4V
= 0.4V
= 2.4V
-200
-100
-
µA
µA
µA
IL
IL
IL
IH
Input Low Current, I : E0
IL
-
Input High Current
40
DETECTOR OUTPUT (DET)
Output Low Voltage, V
I
I
= 2mA
-
2.7
8
-
-
0.45
-
V
V
OL
OL
Output High Voltage, V
= 100µA
OH
OH
Internal Pull-Up Resistor
POWER DISSIPATION (V
Open Circuit State
15
25
kΩ
= -48V)
BAT
C1 = C2 = 0
C1 = C2 = 1
-
-
-
-
26.3
37.5
110
1.1
70
85
mW
mW
mW
W
On-Hook, Standby
On-Hook, Active
C1 = 0, C2 = 1, R = High Impedance
300
1.4
L
Off-Hook, Active
C1 = 0, C2 = 1, R = 600Ω
L
TEMPERATURE GUARD
Thermal Shutdown
o
150
-
180
C
SUPPLY CURRENTS (V
= -28V)
BAT
Open Circuit State (C1, 2 = 0, 0)
On-Hook
I
I
I
I
I
I
I
I
I
-
-
-
-
-
-
-
-
-
1.3
0.6
2.8
2.0
1.2
3.5
2.0
1.6
9.5
4.0
5.2
mA
mA
mA
mA
mA
mA
mA
mA
mA
CC
EE
0.35
1.6
BAT
CC
EE
Standby State (C1, 2 = 1, 1)
On-Hook
0.62
0.55
3.7
BAT
CC
EE
Active State (C1, 2 = 0, 1)
On-Hook
1.1
2.2
BAT
PSRR
V
V
to 2 or 4-Wire Port
to 2 or 4-Wire Port
(Note 29, Figure 11)
(Note 29, Figure 11)
-
-
40
40
-
-
dB
dB
CC
EE
60
HC5515
o
o
Electrical Specifications
T = -40 C to 85 C, V = +5V ±5%, V = -5V ±5%, V
CC EE BAT
= -48V, AGND = BGND = 0V, R
DC1
= R = 41.2kΩ,
DC2
A
R
= 39kΩ, R = 0Ω, R = R = 0Ω, C = 10nF, C = 1.5µF, Z = 600Ω, Unless Otherwise Specified. All pin
D
SG F1 F2 HP DC
L
number references in the figures refer to the 28 lead PLCC package. (Continued)
PARAMETER
CONDITIONS
(Note 29, Figure 11)
MIN
TYP
MAX
UNITS
V
to 2 or 4-Wire Port
-
40
-
dB
BAT
-48V SUPPLY
+5V SUPPLY
-5V SUPPLY
100mV
, 50Hz TO 4kHz
RMS
TIP
27
V
TX
19
PSRR = 20 log (VTX/VIN
)
R
T
R
L
V
600kΩ
TX
600Ω
R
RX
RING RSN
28 16
300kΩ
FIGURE 11. POWER SUPPLY REJECTION RATIO
Circuit Operation and Design Information
The HC5515 is a current feed voltage sense Subscriber Line
Interface Circuit (SLIC). This means that for short loop
For loop resistances that result in a tip to ring voltage less than
the saturation guard voltage the loop current is defined as:
applications the SLIC provides a programed constant current to
the tip and ring terminals while sensing the tip to ring voltage.
2.5V
-------------------------------------
I
=
× 1000
(EQ. 1)
L
R
+ R
DC1
DC2
The following discussion separates the SLIC’s operation into
its DC and AC paths, then follows up with additional circuit
and design information.
where: I = Constant loop current, and
L
R
and R
= Loop current programming resistors.
DC1
DC2
Capacitor C
between R
DC1
and R removes the VF
Constant Loop Current (DC) Path
DC
DC2
signals from the battery feed control loop. The value of C
is determined by Equation 2:
DC
SLIC in the Active Mode
The DC path establishes a constant loop current that flows
out of tip and into the ring terminal. The loop current is
1
1
(EQ. 2)
C
= T × --------------- + ---------------
DC
R
R
programmed by resistors R and the voltage on
, R
DC1
DC2
DC1 DC2
the R
DC
pin (Figure 12). The R
voltage is determined by
DC
the voltage across R in the saturation guard circuit. Under
where T = 30ms.
1
constant current feed conditions, the voltage drop across R
1
NOTE: The minimum C
value is obtained if R
DC1
= R
.
DC
DC2
sets the R
voltage to -2.5V. This occurs when current
DC
flows through R into the current source I . The R
voltage
Figure 13 illustrates the relationship between the tip to ring
voltage and the loop resistance. For a 0Ω loop resistance
1
2
DC
/(R
establishes a current (I
) that is equal to V
RSN
RDC DC1
+R
). This current is then multiplied by 1000, in the loop
both tip and ring are at V
/2. As the loop resistance
DC2
BAT
current circuit, to become the tip and ring loop currents.
increases, so does the voltage differential between tip and
ring. When this differential voltage becomes equal to the
saturation guard voltage, the operation of the SLIC’s loop
feed changes from a constant current feed to a resistive
feed. The loop current in the resistive feed region is no
longer constant but varies as a function of the loop
resistance.
For the purpose of the following discussion, the saturation
guard voltage is defined as the maximum tip to ring voltage
at which the SLIC can provide a constant current for a given
battery and overhead voltage.
61
HC5515
V
TX
I
+
-
RSN
R
R
R
RX
RSN
LOOP CURRENT
CIRCUIT
I
TIP
TIP
I
DC1
DC2
TIP
I
RING
RING
I
C
DC
RING
R
DC
SATURATION GUARD
CIRCUIT
-
-2.5V
+
-
+
A
2
A
1
R
1
-
+
I
17.3kΩ
2
R
I
SG
1
-5V
R
SG
HC5515
-5V
-5V
FIGURE 12. DC LOOP CURRENT
The Saturation Guard circuit (Figure 12) monitors the tip to
ring voltage via the transconductance amplifier A . A
generates a current that is proportional to the tip to ring
V
= -48V, I = 23mA, R
= 4.0kΩ
SG
BAT
L
0
-10
-20
-30
-40
-50
V
1
1
TIP
SATURATION
GUARD VOLTAGE
voltage difference. I is internally set to sink all of A ’s
1
1
CONSTANT CURRENT
FEED REGION
RESISTIVE FEED
REGION
current until the tip to ring voltage exceeds 12.5V. When the
tip to ring voltage exceeds 12.5V (with no R resistor) A
SG
1
supplies more current than I can sink. When this happens
1
A amplifies its input current by a factor of 12 and the current
2
through R becomes the difference between I and the
1
2
output current from A . As the current from A increases, the
2
2
voltage across R decreases and the output voltage on R
1
DC
SATURATION
GUARD VOLTAGE
decreases. This results in a corresponding decrease in the
V
RING
loop current. The R pin provides the ability to increase the
SG
saturation guard reference voltage beyond 12.5V. Equation 3
gives the relationship between the R resistor value and
∞
0
1.2K
LOOP RESISTANCE (Ω)
SG
FIGURE 13. V vs R
TR
L
the programmable saturation guard reference voltage:
Figure 14 shows the relationship between the saturation
guard voltage, the loop current and the loop resistance.
Notice from Figure 14 that for a loop resistance <1.2kΩ
5
5 • 10
(EQ. 3)
V
= 12.5 + -----------------------------------
SGREF
R
+ 17300
SG
where:
(R
= 4.0kΩ) the SLIC is operating in the constant current
SG
feed region and for resistances >1.2kΩ the SLIC is operating
in the resistive feed region. Operation in the resistive feed
region allows long loop and off-hook transmission by
keeping the tip and ring voltages off the rails. Operation in
this region is transparent to the customer.
V
= Saturation Guard reference voltage, and
= Saturation Guard programming resistor.
SGREF
R
SG
When the Saturation guard reference voltage is exceeded,
the tip to ring voltage is calculated using Equation 4:
50
5
16.66 + 5 • 10 ⁄ (R
+ 17300)
CONSTANT CURRENT
SG
V
= -48V, R
SG
= 4.0kΩ
(EQ. 4)
BAT
FEED REGION
------------------------------------------------------------------------------------
= R ×
L
V
TR
R
+ (R
+ R
) ⁄ 600
DC2
40
30
20
10
0
L
DC1
SATURATION GUARD
VOLTAGE, V = 38V
TR
where:
= Voltage differential between tip and ring, and
V
TR
R = Loop resistance.
V
= -24V, R = ∞
SG
BAT
L
SATURATION GUARD
RESISTIVE FEED
REGION
VOLTAGE, V = 13V
For on-hook transmission R = ∞, Equation 4 reduces to:
TR
L
5
5 • 10
0
10
20
LOOP CURRENT (mA)
30
(EQ. 5)
V
= 16.66 + -----------------------------------
TR
R
+ 17300
SG
R
R
100kΩ
100kΩ
4kΩ
2kΩ
<1.2kΩ
<400Ω
R
R
= 4.0kΩ
= ∞Ω
L
L
SG
The value of R
should be calculated to allow maximum
SG
1.5kΩ
700Ω
SG
loop length operation. This requires that the saturation guard
reference voltage be set as high as possible without clipping
the incoming or outgoing VF signal. A voltage margin of -4V
FIGURE 14. V vs I and R
TR
L
L
62
HC5515
on tip and -4V on ring, for a total of -8V margin, is
recommended as a general guideline. The value of R
calculated using Equation 6:
V
= Is the analog ground referenced receive signal,
= Is used to set the 4-wire to 2-wire gain,
RX
RX
is
Z
E
SG
= Is the AC open circuit voltage, and
G
Z = Is the line impedance.
L
5
5 • 10
(R
R
= --------------------------------------------------------------------------------------------------------------------------------------------- – 17300
SG
+ R
)
(AC) 2-Wire Impedance
DC1
DC2
( V
– V
) × 1 + --------------------------------------------- – 16.66V
BAT
MAR
600R
The AC 2-wire impedance (Z ) is the impedance looking
TR
L
into the SLIC, including the fuse resistors, and is calculated
(EQ. 6)
as follows:
where:
Let V
= 0. Then from Equation 10:
RX
T
V
V
= Battery voltage, and
BAT
I
(EQ. 12)
(EQ. 13)
M
= Voltage Margin. Recommended value of -8V to
MAR
------------
V
= Z
•
TX
1000
allow a maximum overload level of 3.1V
.
PEAK
Z
is defined as:
TR
For on-hook transmission R = ∞, Equation 6 reduces to:
L
5
V
5 • 10
– V
TR
R
= ------------------------------------------------------------------ – 17300
Z
= -----------
(EQ. 7)
SG
TR
V
– 16.66V
I
BAT
MAR
M
Substituting in Equation 9 for V
TR
:
SLIC in the Standby Mode
V
2R • I
F M
TX
Overall system power is saved by configuring the SLIC in the
standby state when not in use. In the standby state the tip
and ring amplifiers are disabled and internal resistors are
(EQ. 14)
(EQ. 15)
(EQ. 16)
Z
= ---------- + -----------------------
TR
I
I
M
M
Substituting in Equation 12 for V
:
TX
connected between tip to ground and ring to V
. This
BAT
connection enables a loop current to flow when the phone
goes off-hook. The loop current detector then detects this
current and the SLIC is configured in the active mode for
voice transmission. The loop current in standby state is
calculated as follows:
Z
T
1000
Z
= ------------ + 2R
TR
F
Therefore:
Z
= 1000 • (Z
– 2R )
T
TR
F
V
– 3V
BAT
(EQ. 8)
-------------------------------
≈
I
L
R
+ 1800Ω
Equation 16 can now be used to match the SLIC’s
L
impedance to any known line impedance (Z ).
TR
where:
I = Loop current in the standby state,
L
Example:
R = Loop resistance, and
L
Calculate Z to make Z = 600Ω in series with 2.16µF.
T
TR
R = 20Ω.
V
= Battery voltage.
F
BAT
1
(AC) Transmission Path
Z
= 1000 • 600 + ----------------------------------------- – 2 • 20
T
–6
jω • 2.16 • 10
SLIC in the Active Mode
Z = 560kΩ in series with 2.16nF.
T
Figure 15 shows a simplified AC transmission model. Circuit
analysis yields the following design equations:
(AC) 2-Wire to 4-Wire Gain
(EQ. 9)
(EQ. 10)
(EQ. 11)
The 2-wire to 4-wire gain is equal to V / V
.
V
= V + I • 2R
TX TR
TR
TX
M
F
From Equations 9 and 10 with V
= 0:
RX
V
V
I
TX
RX
M
---------- + ----------- = ------------
V
Z ⁄ 1000
T
Z ⁄ 1000 + 2R
T F
Z
Z
1000
= E – I • Z
L
TX
(EQ. 17)
T
RX
A
= ----------- = -----------------------------------------
2 – 4
V
TR
V
TR
G
M
(AC) 4-Wire to 2-Wire Gain
where:
= Is the AC metallic voltage between tip and ring,
The 4-wire to 2-wire gain is equal to V /V
TR RX
.
V
TR
including the voltage drop across the fuse resistors R ,
From Equations 9, 10 and 11 with E = 0:
G
F
V
= Is the AC metallic voltage. Either at the ground
Z
V
Z
T
Z
RX
TX
referenced 4-wire side or the SLIC tip and ring terminals,
L
TR
--------------------------------------------
A
= ----------- = –----------- •
4 – 2
Z
V
(EQ. 18)
T
RX
------------ + 2R + Z
I
= Is the AC metallic current,
F
L
M
1000
R = Is a fuse resistor,
F
Z = Is used to set the SLIC’s 2-wire impedance,
T
63
A
= ----------- = –---------
- •
A
= –---------
- •
HC5515
I
M
TIP
A = 250
R
F
Z
L
V
TX
+
-
Z
TR
+
TX
-
+
1
V
V
TR
+
TX
-
V
+
-
Z
T
E
G
-
I
M
A = 4
RSN
Z
A = 250
RX
R
I
F
M
RING
+
RX
1000
V
-
HC5515
FIGURE 15. SIMPLIFIED AC TRANSMISSION CIRCUIT
For applications where the 2-wire impedance (Z
TR
Equation 15) is chosen to equal the line impedance (Z ), the
,
Example:
L
Given: R = 20kΩ, Z
TX
= 280kΩ, Z = 562kΩ (standard
T
RX
expression for A
simplifies to:
4-2
value), R = 20Ω and Z = 600Ω,
F
Z
1
2
T
(EQ. 19)
The value of Z = 18.7kΩ
--
B
4 – 2
Z
RX
R
FB
(AC) 4-Wire to 4-Wire Gain
I
2
R
V
TX
TX
The 4-wire to 4-wire gain is equal to V /V
TX RX
.
-
+
From Equations 9, 10 and 11 with E = 0:
G
+
TX
-
I
1
V
Z
+ 2R
F
V
Z
T
Z
RX
L
TX
--------------------------------------------
(EQ. 20)
4 – 4
Z
V
T
RX
------------ + 2R + Z
F
L
Z
Z
B
HC5515
1000
T
+
RX
-
Transhybrid Circuit
The purpose of the transhybrid circuit is to remove the
V
RSN
Z
RX
receive signal (V ) from the transmit signal (V ), thereby
RX
TX
preventing an echo on the transmit side. This is
accomplished by using an external op amp (usually part of
the CODEC) and by the inversion of the signal from the
CODEC/
FILTER
4-wire receive port (RSN) to the 4-wire transmit port (V ).
TX
Figure 16 shows the transhybrid circuit. The input signal will
FIGURE 16. TRANSHYBRID CIRCUIT
be subtracted from the output signal if I equals I . Node
1
2
analysis yields the following equation:
Supervisory Functions
V
V
RX
Z
B
The loop current and the ring trip detector outputs are
TX
(EQ. 21)
(EQ. 22)
----------- + ----------- = 0
multiplexed to a single logic output pin called DET. See Table
1 to determine the active detector for a given logic input. For
further discussion of the logic circuitry see section titled
“Digital Logic Inputs”.
R
TX
The value of Z is then:
B
V
RX
-----------
Z
= –R
•
TX
Before proceeding with an explanation of the loop current
detector and the longitudinal impedance, it is important to
understand the difference between a “metallic” and
“longitudinal” loop currents. Figure 17 illustrates 3 different
types of loop current encountered.
B
V
TX
Where V /V equals 1/ A
RX TX
.
4-4
Therefore:
Z
T
Case 1 illustrates the metallic loop current. The definition of
a metallic loop current is when equal currents flow out of tip
and into ring. Loop current is a metallic current.
------------ + 2R + Z
Z
(EQ. 23)
F
L
1000
RX
---------- --------------------------------------------
Z
= R
•
TX
•
B
Z
Z + 2R
L
T
F
64
HC5515
Cases 2 and 3 illustrate the longitudinal loop current. The
definition of a longitudinal loop current is a common mode
current, that flows either out of or into tip and ring
simultaneously. Longitudinal currents in the on-hook state
result in equal currents flowing through the sense resistors
Taking into account the hysteresis voltage, the typical value
of R for the off-hook to on-hook condition is:
D
375
R
= --------------------------------------------------------------------------
(EQ. 26)
D
I
OFF – HOOK to ON – HOOK
R and R (Figure 17). And longitudinal currents in the off-
hook state result in unequal currents flowing through the
1
2
A filter capacitor (C ) in parallel with R will improve the
accuracy of the trip point in a noisy environment. The value
of this capacitor is calculated using the following Equation:
D
D
sense resistors R and R . Notice that for case 2,
1
2
longitudinal currents flowing away from the SLIC, the current
T
C
= -------
(EQ. 27)
through R is the metallic loop current plus the longitudinal
D
1
R
D
current; whereas the current through R is the metallic loop
2
current minus the longitudinal current. Longitudinal currents
are generated when the phone line is influenced by
magnetic fields (e.g. power lines).
where: T = 0.5ms.
Ring Trip Detector
Ring trip detection is accomplished with the internal ring trip
comparator and the external circuitry shown in Figure 18.
The process of ring trip is initiated when the logic input pins
are in the following states: E0 = 0, C1 = 1 and C2 = 0. This
logic condition connects the ring trip comparator to the DET
output, and causes the Ringrly pin to energize the ring relay.
The ring relay connects the tip and ring of the phone to the
external circuitry in Figure 18. When the phone is on-hook
the DT pin is more positive than the DR pin and the DET
output is high. For off-hook conditions DR is more positive
than DT and DET goes low. When DET goes low, indicating
that the phone has gone off-hook, the SLIC is commanded
by the logic inputs to go into the active state. In the active
state, tip and ring are once again connected to the phone
and normal operation ensues.
Loop Current Detector
Figure 17 shows a simplified schematic of the loop current
detector. The loop current detector works by sensing the
metallic current flowing through resistors R and R . This
1
2
results in a current (I ) out of the transconductance
RD
amplifier (gm ) that is equal to the product of gm and the
1
1
metallic loop current. I
then flows out the R pin and
RD
D
through resistor R to V . The value of I
is equal to:
RD
D
EE
I
– I
I
L
300
TIP
RING
(EQ. 24)
I
= ----------------------------------- = ---------
RD
600
The I
current results in a voltage drop across R that is
D
RD
compared to an internal 1.25V reference voltage. When the
voltage drop across R exceeds 1.25V, and the logic is
D
configured for loop current detection, the DET pin goes low.
Figure 18 illustrates battery backed unbalanced ring injected
ringing. For tip injected ringing just reverse the leads to the
phone. The ringing source could also be balanced.
The hysteresis resistor R adds an additional voltage
H
effectively across R , causing the on-hook to off-hook
D
threshold to be slightly higher than the off-hook to on-hook
threshold.
NOTE: The DET output will toggle at 20Hz because the DT input is
not completely filtered by C . Software can examine the duty cycle
RT
and determine if the DET pin is low for more that half the time, if so
the off-hook condition is indicated.
Taking into account the hysteresis voltage, the typical value
of R for the on-hook to off-hook condition is:
D
465
R
= --------------------------------------------------------------------------
(EQ. 25)
D
I
ON – HOOK to OFF – HOOK
gm (I
)
METALLIC
1
R
D
R
H
+
-
I
RD
C
D
R
CURRENT
LOOP
COMPARATOR
D
+
-
+
TIP
-
V
R
R
REF
1.25V
1
V
EE
gm
1
-5V
2
RING
CASE 1
CASE 2
CASE 3
DIGITAL MULTIPLEXER
DET
-
+
I
I
I
LONGITUDI-
METAL-
LONGITUDI-
LIC
←
NAL
←
NAL
→
HC5515
FIGURE 17. LOOP CURRENT DETECTOR
65
HC5515
transconductance amplifiers GT and GR. The output of GT
and GR are the differential currents DI1 and DI2, which in
turn feed the differential inputs of current sources IT and IR
respectively. IT and IR have current gains of 250 single
ended and 500 differentially, thus leading to a change in IT
and IR that is equal to 500(DI) and 500(DI2).
R
R
R
C
RT
1
RT
DT
DR
-
DET
R
+
3
RING TRIP
COMPARATOR
TIP
R
4
2
The circuit shown in Figure 19(B) illustrates the tip side of
the longitudinal network. The advantages of a differential
input current source are: improved noise since the noise due
E
RG
to current source 2I is now correlated, power savings due
V
O
BAT
to differential current gain and minimized offset error at the
Operational Amplifier inputs via the two 5kΩ resistors.
RING
RINGRLY
HC5515
RING
RELAY
Digital Logic Inputs
Table 1 is the logic truth table for the TTL compatible logic
input pins. The HC5515 has an enable input pin (E0) and
two control inputs pins (C1, C2).
FIGURE 18. RING TRIP CIRCUIT FOR BATTERY BACKED
RINGING
The enable pin E0 is used to enable or disable the DET
output pin. The DET pin is enabled if E0 is at a logic level 0
and disabled if E0 is at a logic level 1.
Longitudinal Impedance
The feedback loop described in Figure 19(A, B) realizes the
desired longitudinal impedances from tip to ground and from
ring to ground. Nominal longitudinal impedance is resistive
and in the order of 22Ω.
A combination of the control pins C1 and C2 is used to
select 1 of the 4 possible operating states. A description of
each operating state and the control logic follow:
In the presence of longitudinal currents this circuit
attenuates the voltages that would otherwise appear at the
tip and ring terminals, to levels well within the common mode
range of the SLIC. In fact, longitudinal currents may exceed
the programmed DC loop current without disturbing the
SLIC’s VF transmission capabilities.
Open Circuit State (C1 = 0, C2 = 0)
In this state the SLIC is effectively off. All detectors and
both the tip and ring line drive amplifiers are powered
down, presenting a high impedance to the line. Power
dissipation is at a minimum.
The function of this circuit is to maintain the tip and ring
Active State (C1 = 0, C2 = 1)
voltages symmetrically around V
/2, in the presence of
BAT
The tip output is capable of sourcing loop current and for
open circuit conditions is about -4V from ground. The ring
output is capable of sinking loop current and for open circuit
longitudinal currents. The differential transconductance
amplifiers G and G accomplish this by sourcing or sinking
T
R
the required current to maintain V at V
/2.
C
BAT
conditions is about V
+4V. VF signal transmission is
BAT
When a longitudinal current is injected onto the tip and ring
inputs, the voltage at VC moves from it’s equilibrium value
VBAT/2. When VC changes by the amount DVC, this change
appears between the input terminals of the differential
normal. The loop current detector is active, E0 determines if
the detector is gated to the DET output.
I
LONG
TIP CURRENT SOURCE
WITH DIFFERENTIAL INPUTS
I
I
LONG
T
TIP
20Ω
+
∆I
1
∆I
TIP
1
∆V
T
-
5kΩ
5kΩ
G
T
R
-
LARGE
+
R
LARGE
V
/2
∆I
BAT
+
∆I
1
1
V
C
-
V
C
V
/2
BAT
G
R
R
LARGE
2I
0
I
LONG
R
∆I
∆I
LARGE
2
2
RING
HC5515
+
TIP DIFFERENTIAL
TRANSCONDUCTANCE
AMPLIFIER
I
R
RING
I
∆V
LONG
R
-
FIGURE 19A.
FIGURE 19. LONGITUDINAL IMPEDANCE NETWORK
FIGURE 19B.
66
HC5515
Surge Voltage Protection
Ringing State (C1 = 1, C2 = 0)
The ring relay driver and the ring trip detector are activated.
Both the tip and ring line drive amplifiers are powered down.
Both tip and ring are disconnected from the line via the
external ring relay.
The HC5515 must be protected against surge voltages and
power crosses. Refer to “Maximum Ratings” TIPX and
RINGX terminals for maximum allowable transient tip and
ring voltages. The protection circuit shown in Figure 20
utilizes diodes together with a clamping device to protect tip
and ring against high voltage transients.
Standby State (C1 = 1, C2 = 1)
Both the tip and ring line drive amplifiers are powered down.
Internal resistors are connected between tip to ground and ring
Positive transients on tip or ring are clamped to within a
couple of volts above ground via diodes D and D . Under
1
2
to V
to allow loop current detect in an off-hook condition.
BAT
normal operating conditions D and D are reverse biased
1
2
The loop current and ground key detectors are both active, E0
determines if the detector is gated to the DET output.
and out of the circuit.
Negative transients on tip and ring are clamped to within a
couple of volts below ground via diodes D and D with the
help of a Surgector. The Surgector is required to block
AC Transmission Circuit Stability
To ensure stability of the AC transmission feedback loop two
3
4
conduction through diodes D and D under normal
3
4
compensation capacitors C and C
are required.
TC RC
operating conditions and allows negative surges to be
returned to system ground.
Figure 20 (Application Circuit) illustrates their use.
Recommended value is 2200pF.
The fuse resistors (R ) serve a dual purpose of being
F
nondestructive power dissipaters during surge and fuses
when the line in exposed to a power cross.
AC-DC Separation Capacitor, C
The high pass filter capacitor connected between pins HPT
and HPR provides the separation between circuits sensing
tip to ring DC conditions and circuits processing AC signals.
HP
Power-Up Sequence
A 10nf C
3dB break point at 48Hz. Where:
will position the low end frequency response
The HC5515 has no required power-up sequence. This is a
result of the Dielectrically Isolated (DI) process used in the
fabrication of the part. By using the DI process, care is no
longer required to insure that the substrate be kept at the
most negative potential as with junction isolated ICs.
HP
1
(EQ. 28)
f
= ----------------------------------------------------
3dB
(2 • π • R
• C
)
HP
HP
where R
= 330kΩ.
HP
Printed Circuit Board Layout
Thermal Shutdown Protection
Care in the printed circuit board layout is essential for proper
operation. All connections to the RSN pin should be made as
close to the device pin as possible, to limit the interference
that might be injected into the RSN terminal. It is good
practice to surround the RSN pin with a ground plane.
The HC5515’s thermal shutdown protection is invoked if a
fault condition on the tip or ring causes the temperature of
o
the die to exceed 160 C. If this happens, the SLIC goes into
a high impedance state and will remain there until the
temperature of the die cools down by about 20 C. The SLIC
will return back to its normal operating mode, providing the
fault condition has been removed.
o
The analog and digital grounds should be tied together at
the device.
SLIC Operating States
TABLE 1. LOGIC TRUTH TABLE
SLIC OPERATING STATE ACTIVE DETECTOR
E0
0
C1
0
C2
0
DET OUTPUT
Logic Level High
Open Circuit
Active
No Active Detector
Loop Current Detector
Ring Trip Detector
0
0
1
Loop Current Status
Ring Trip Status
0
1
0
Ringing
0
1
1
Standby
Loop Current Detector
Loop Current Status
1
1
1
1
0
0
1
1
0
1
0
1
Open Circuit
Active
No Active Detector
Loop Current Detector
Ring Trip Detector
Logic Level High
Ringing
Standby
Loop Current Detector
67
HC5515
in Figure 7. Note: I
DCMET
resistor between tip and ring.
is established with a series 600Ω
Notes
2. Overload Level (Two-Wire port) - The overload level is
specified at the 2-wire port (V ) with the signal source at the
14. Two-Wire to Four-Wire (Metallic to V ) Voltage Gain - The
TX
TR0
2-wire to 4-wire (metallic to V ) voltage gain is computed
TX
4-wire receive port (E ). I
= 30mA, R = 4kΩ,
RX DCMET
SG
using the following equation.
increase the amplitude of E until 1% THD is measured at
RX
V
. Reference Figure 1.
TRO
G
= (V /V ), E = 0dBm0, V , V , and E are defined
TX TR TX TR
2-4
in Figure 7.
G
G
3. LongitudinalImpedance - The longitudinal impedance is
computed using the following equations, where TIP and RING
voltages are referenced to ground. L , L , V , V , A and
15. Current Gain RSN to Metallic - The current gain RSN to
Metallic is computed using the following equation:
ZT ZR
T
R
R
A are defined in Figure 2.
T
K = I [(R
+ R
)/(V
DC2
- V
)] K, I , R
DC1
, R ,
DC2
M
DC1
RDC
are defined in Figure 8.
RSN
RSN
M
(TIP) L = V /A ,
V
and V
ZT
T
T
RDC
(RING) L = V /A ,
ZR
R
R
16. Two-Wire to Four-Wire Frequency Response - The 2-wire to
4-wire frequency response is measured with respect to
where: E = 1V
RMS
(0Hz to 100Hz).
L
E
= 0dBm at 1.0kHz, E
= 0V, I = 23mA. The fre-
G
RX
DCMET
4. Longitudinal Current Limit (Off-Hook Active) - Off-Hook
(Active, C = 1, C = 0) longitudinal current limit is determined
quency response is computed using the following equation:
1
2
F
= 20 • log (V /V ), vary frequency from 300Hz to
2-4
TX TR
by increasing the amplitude of E (Figure 3A) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains low
(no false detection).
L
3.4kHz and compare to 1kHz reading.
V
, V , and E are defined in Figure 9.
TX TR
G
5. Longitudinal Current Limit (On-Hook Standby) - On-Hook
17. Four-Wire to Two-Wire Frequency Response - The 4-wire to
(Active, C = 1, C = 1) longitudinal current limit is determined
2-wire frequency response is measured with respect to
1
2
by increasing the amplitude of E (Figure 3B) until the 2-wire
longitudinal balance drops below 45dB. DET pin remains high
(no false detection).
E
= 0dBm at 1.0kHz, E = 0V, I = 23mA. The
L
RX
G
DCMET
frequency response is computed using the following equation:
F
= 20 • log (V /E ), vary frequency from 300Hz to
4-2
TR RX
6. Longitudinal to Metallic Balance - The longitudinal to metallic
3.4kHz and compare to 1kHz reading.
balance is computed using the following equation:
V
and E are defined in Figure 9.
TR
RX
BLME = 20 • log (E /V ), where: E and V
TR TR
Figure 4.
are defined in
L
L
18. Four-Wire to Four-Wire Frequency Response - The 4-wire
to 4-wire frequency response is measured with respect to
7. Metallic to Longitudinal FCC Part 68, Para 68.310 - The
E
= 0dBm at 1.0kHz, E = 0V, I = 23mA. The
RX
G
DCMET
metallic to longitudinal balance is defined in this spec.
frequency response is computed using the following equation:
F
= 20 • log (V /E ), vary frequency from 300Hz to
8. Longitudinal to Four-Wire Balance - The longitudinal to 4-wire
4-4
TX RX
3.4kHz and compare to 1kHz reading.
balance is computed using the following equation:
V
and E are defined in Figure 9.
BLFE = 20 • log (E /V ),: E and V are defined in Figure 4.
TX
RX
L
TX
L
TX
19. Two-Wire to Four-Wire Insertion Loss - The 2-wire to 4-wire
9. Metallic to Longitudinal Balance - The metallic to longitudi-
insertion loss is measured with respect to E = 0dBm at 1.0kHz
nal balance is computed using the following equation:
G
input signal, E
the following equation:
= 0, I = 23mA and is computed using
DCMET
RX
BMLE = 20 • log (E /V ), E
TR RX
= 0,
L
where: E , V and E
are defined in Figure 5.
TR RX
L
L
= 20 • log (V /V )
TX TR
2-4
10. Four-Wire to Longitudinal Balance - The 4-wire to longitudinal
where: V , V , and E are defined in Figure 9. (Note: The
TX TR
G
balance is computed using the following equation:
fuse resistors, R , impact the insertion loss. The specified
F
insertion loss is for R = 0).
BFLE = 20 • log (E /V ), E = source is removed.
RX TR
F
L
20. Four-Wire to Two-Wire Insertion Loss - The 4-wire to 2-wire
where: E , V and E are defined in Figure 5.
RX TR
L
insertion loss is measured based upon E
= 0dBm, 1.0kHz
= 23mA and is computed using
RX
11. Two-Wire Return Loss - The 2-wire return loss is computed
input signal, E = 0, I
G
DCMET
using the following equation:
the following equation:
r = -20 • log (2V /V ).
M
S
L
= 20 • log (V /E ),
TR RX
4-2
where: Z = The desired impedance; e.g., the characteristic
D
impedance of the line, nominally 600Ω. (Reference Figure 6).
where: V and E
are defined in Figure 9.
TR RX
21. Two-Wire to Four-Wire Gain Tracking - The 2-wire to 4-wire
12. Overload Level (4-Wire port) - The overload level is specified
gain tracking is referenced to measurements taken for
at the 4-wire transmit port (V
) with the signal source (E ) at
TXO
G
E
= -10dBm, 1.0kHz signal, E
= 0, I = 23mA and is
G
RX
DCMET
the 2-wire port, I
= 23mA, Z = 20kΩ, R
= 4kΩ (Refer-
DCMET
L
SG
computed using the following equation.
ence Figure 7). Increase the amplitude of E until 1% THD is
G
G
= 20 • log (V /V ) vary amplitude -40dBm to +3dBm, or
measured at V
TXO
. Note that the gain from the 2-wire port to
2-4
TX TR
-55dBm to -40dBm and compare to -10dBm reading.
the 4-wire port is equal to 1.
V
and V are defined in Figure 9.
TR
TX
13. Output Offset Voltage - The output offset voltage is specified
with the following conditions: E = 0, I
= 23mA, Z = ∞
G
DCMET
L
22. Four-Wire to Two-Wire Gain Tracking - The 4-wire to 2-wire
and is measured at V . E , I
, V and Z are defined
TX
G
DCMET TX
L
gain tracking is referenced to measurements taken for
68
HC5515
E
= -10dBm, 1.0kHz signal, E = 0, I
DCMET
= 23mA and is
at 1kHz, I
= 23mA. Measurement taken at V
.
TX
RX
G
DCMET
(Reference Figure 7).
computed using the following equation:
G
= 20 • log (V /E ) vary amplitude -40dBm to +3dBm,
TR RX
26. Harmonic Distortion (4-Wire to 2-Wire) - The harmonic dis-
4-2
or -55dBm to -40dBm and compare to -10dBm reading.
tortion is measured with the following conditions. E
= 0dBm0.
= 23mA.
RX
Vary frequency between 300Hz and 3.4kHz, I
DCMET
V
and E are defined in Figure 9. The level is specified at
TR
RX
Measurement taken at V . (Reference Figure 9).
TR
the 4-wire receive port and referenced to a 600Ω impedance
level.
27. Constant Loop Current - The constant loop current is
calculated using the following equation:
23. Two-Wire Idle Channel Noise - The 2-wire idle channel noise
at V
is specified with the 2-wire port terminated in 600Ω (R )
I
= 2500 / (R
DC1
+ R
).
DC2
TR
L
L
and with the 4-wire receive port grounded (Reference Figure 10).
28. Standby State Loop Current - The standby state loop current
24. Four-Wire Idle Channel Noise - The 4-wire idle channel noise
is calculated using the following equation:
at V is specified with the 2-wire port terminated in 600Ω (R ).
The noise specification is with respect to a 600Ω impedance
TX
L
o
I
= [|V
| - 3] / [R +1800], T = 25 C.
L
BAT
L
A
level at V . The 4-wire receive port is grounded (Reference
Figure 10).
TX
29. Power Supply Rejection Ratio - Inject a 100mV
signal
RMS
supplies. PSRR is
(50Hz to 4kHz) on V
, V
and V
BAT
CC EE
computed using the following equation:
25. Harmonic Distortion (2-Wire to 4-Wire) - The harmonic dis-
tortion is measured with the following conditions. E = 0dBm
G
PSRR = 20 • log (V /V ). V and V are defined in Figure 11.
TX IN TX IN
Pin Descriptions
PLCC PDIP
SYMBOL
DESCRIPTION
Internally connected to output of RING power amplifier.
1
RING
SENSE
2
7
BGND
Battery Ground - To be connected to zero potential. All loop current and longitudinal current flow from this ground.
Internally separate from AGND but it is recommended that it is connected to the same potential as AGND.
4
5
6
7
8
9
8
V
+5V power supply.
CC
9
RINGRLY Ring relay driver output.
10
11
12
13
V
Battery supply voltage, -24V to -56V.
BAT
R
Saturation guard programming resistor pin.
SG
NC
E0
This pin is used during manufacturing.This pin is to be left open for proper SLIC operation .
TTL compatible logic input. Enables the DET output when set to logic level zero and disables DET output when set to
a logic level one.
11
14
DET
Detector output. TTL compatible logic output. A zero logic level indicates that the selected detector was triggered (see
Truth Table for selection of Ground Key detector, Loop Current detector or the Ring Trip detector). The DET output is
an open collector with an internal pull-up of approximately 15kΩ to V
CC.
12
13
14
15
16
17
C2
C1
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
TTL compatible logic input. The logic states of C1 and C2 determine the operating states (Open Circuit, Active, Ringing
or Standby) of the SLIC.
R
DC feed current programming resistor pin. Constant current feed is programmed by resistors R
DC1
and R
DC2
DC
connected in series from this pin to the receive summing node (RSN). The resistor junction point is decoupled to AGND
to isolate the AC signal components.
15
16
18
19
AGND
RSN
Analog ground.
Receive Summing Node. The AC and DC current flowing into this pin establishes the metallic loop current that flows
between tip and ring. The magnitude of the metallic loop current is 1000 times greater than the current into the RSN
pin. The constant current programming resistors and the networks for program receive gain and 2-wire impedance all
connect to this pin.
18
19
20
21
V
V
-5V power supply.
EE
Transmit audio output. This output is equivalent to the TIP to RING metallic voltage. The network for programming the
2-wire input impedance connects between this pin and RSN.
TX
69
HC5515
Pin Descriptions (Continued)
PLCC PDIP
SYMBOL
DESCRIPTION
20
21
22
23
25
22
HPR
RING side of AC/DC separation capacitor C . C is required to properly separate the ring AC current from the DC
HP HP
loop current. The other end of C is connected to HPT.
HP
1
HPT
RD
DT
TIP side of AC/DC separation capacitor C . C is required to properly separate the tip AC current from the DC loop
HP HP
current. The other end of C is connected to HPR.
HP
2
Loop current programming resistor. Resistor R sets the trigger level for the loop current detect circuit. A filter capacitor
D
C
is also connected between this pin and V .
D
EE
3
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR.
4
DR
Input to ring trip comparator. Ring trip detection is accomplished by connecting an external network to a comparator
in the SLIC with inputs DT and DR.
26
27
28
TIP
Internally connected to output of tip power amplifier.
Output of tip power amplifier.
SENSE
5
6
TIPX
RINGX
N/C
Output of ring power amplifier.
3, 10
No internal connection.
17, 24
Pinouts
HC5515
(PLCC)
HC5515
(PDIP)
TOP VIEW
TOP VIEW
HPT
RD
1
2
22
21
HPR
V
TX
EE
DT
3
20 V
4
3
2
1
28 27 26
DR
4
19 RSN
TIPX
RINGX
BGND
5
18 AGND
RINGRLY
5
6
25 DR
24 N/C
23 DT
6
17
R
DC
7
16 C1
15 C2
V
BAT
V
8
CC
R
7
SG
14
13
12
RINGRLY
9
DET
NC
8
22 RD
V
10
11
E0
BAT
9
E0
21 HPT
20 HPR
R
NC
SG
10
11
N/C
DET
19 V
TX
12 13 14 15 16 17 18
70
HC5515
Application Circuit
C
(NOTE 32)
HP
R
C
R
RT
RT
1
R
U
FB
R
R
3
D
U
1
21 HPT
HPR 20
2
-5V
R
R
R
TX
2
4
22 RD
23 DT
V
V
19
18
-
TX
+
-5V
R
R
B
EE
T
V
BAT
R
RX
25 DR
RSN 16
AGND 15
PTC
PTC
R
F1
27 TIPX
R
DC1
D
D
TIP
D
1
3
CODEC/FILTER
C
TC
2 BGND
R
14
DC
NOTE 31
R
C
DC
DC2
C
4 V
CC
C1 13
C2 12
RC
D
RING
4
2
28 RINGX
6 V
R
Surgector
F2
V
BAT
K
A
DET 11
BAT
G
5 RINGRLY
E
9
8
O
D
5
R
SG
E
7 R
SG
1
RINGING
+ 90V
+5V
OR
12V
RELAY
-5V
(V
)
RMS
BAT
D
6
R , R 200kΩ, 5%, 1/4W
U1 SLIC (Subscriber Line Interface Circuit)
HC5515
1
3
R
R
910kΩ, 5%, 1/4W
2
U2 Combination CODEC/Filter e.g.
CD22354A or Programmable CODEC/
Filter, e.g. SLAC
1.2MΩ, 5%, 1/4W
18.7kΩ,1%, 1/4W
39kΩ, 5%, 1/4W
41.2kΩ, 5%, 1/4W
20.0kΩ, 1%, 1/4W
280kΩ, 1%, 1/4W
562kΩ, 1%, 1/4W
20kΩ, 1%, 1/4W
150Ω, 5%, 2W
4
R
B
R
D
C
1.5µF, 20%, 10V
DC
R
, R
DC1 DC2
C
10nF, 20%, 100V (Note 2)
0.39µF, 20%, 100V
2200pF, 20%, 100V
HP
R
FB
C
RT
R
RX
C
, C
TC RC
R
T
TX
RT
Relay Relay, 2C Contacts, 5V or 12V Coil
- D IN4007 Diode
R
D
1
5
R
Surgector SGT27S10
R
V
= -28V, R
= -48V, R
= ∞
SG BAT
SG
SG
PTC Polyswitch TR600-150
V
= 4.0kΩ, 1/4W 5%
BAT
D
Diode, 1N4454
6
R
, R
Line Resistor, 20Ω, 1% Match, 2 W
Carbon column resistor or thick film on
ceramic
F1 F2
NOTES:
30. It is recommended that the anodes of D and D be shorted to ground through a battery referenced surgector (SGT27S10).
3
4
31. To meet the specified 25dB 2-wire return loss at 200Hz, C
needs to be 20nF, 20%, 100V.
HP
FIGURE 20. APPLICATION CIRCUIT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
71
相关型号：
©2020 ICPDF网 联系我们和版权申明