RTL8201FN-VB-CG [REALTEK]
Ethernet Transceiver, CMOS, GREEN, MO-220, QFN-48;
| 型号： | RTL8201FN-VB-CG |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | Ethernet Transceiver, CMOS, GREEN, MO-220, QFN-48 以太网：16GBASE-T 电信 电信集成电路 |
| 文件： | 总66页 (文件大小：1150K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8201F-VB-CG
RTL8201FL-VB-CG
RTL8201FN-VB-CG
SINGLE-CHIP/PORT 10/100M ETHERNET
PHYCEIVER WITH AUTO MDIX
DATASHEET
(CONFIDENTIAL: Development Partners Only)
Rev. 1.4
30 November 2011
Track ID: JATR-2265-11
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
COPYRIGHT
©2011 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document ‘as is’, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
LICENSE
This product is covered by one or more of the following patents: US5,307,459, US5,434,872,
US5,732,094, US6,570,884, US6,115,776, and US6,327,625.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Datasheet
REVISION HISTORY
Revision Release Date Summary
1.0
1.1
2010/12/17 First release.
2011/02/18 Revised to VB model.
Revised Table 22 Register 30 Interrupt Indicators and SNR Display Register, page 21.
Added interrupt function.
Added MMD Register Mapping and Definition section.
Revised section 8.2 Interrupt, page 31.
Revised Table 46 Absolute Maximum Ratings, page 44.
Revised 9.1.3 Power On and PHY Reset Sequence, page 45.
Revised Table 49 RMII Input Mode Power Dissipation (Whole System), page 46.
1.2
2011/04/21 Revised Figure 2 Block Diagram, page 4.
Revised Table 3 RMII Interface, page 10.
Revised Table 7 Device Configuration Interface, page 11.
Revised Table 9 Reset and Other Pins, page 14.
Revised Table 11 Register 0 Basic Mode Control Register, page 15.
Revised Table 15 Register 4 Auto-Negotiation Advertisement Register (ANAR), page 17.
Revised Table 20 Register 24, page 20.
Revised Table 24 Page4 Register 16 EEE Capability Enable Register, page 22.
Revised Table 25 Page4 Register 21 EEE Capability Register, page 22.
Revised Table 30 Page7 Register 19 , page 24.
Added section 7.21 Page 7 Register 24 Spread Spectrum Clock Register, page 25.
Revised section 8.1.2 Serial Management Interface, page 29.
Revised section 8.7 Reset and Transmit Bias, page 38.
Added section 8.13 Spread Spectrum Clock (SSC), page 43.
Added Figure 21 MII Interface Setup/Hold Time Definitions, page 47.
Added Figure 26 RMII Interface Setup, Hold Time, and Output Delay Time Definitions,
page 49.
Added Figure 28 MDC/MDIO Interface Setup, Hold Time, and Valid from MDC Rising Edge
Time Definitions, page 51.
1.3
2011/07/14 Added Figure 1 Application Diagram, page 3.
Revised Table 30 Page7 Register 19 Interrupt, WOL Enable, and LEDs Function Registers,
page 24.
Added Table 34 EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00), page 25.
Added Table 35 EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01), page 26.
Added section 8.4.1 LED and PHY Address, page 32.
Added section 8.4.8 EEE LED, page 36.
Revised section 8.7 Reset and Transmit Bias, page 38.
1.4
2011/11/30 Revised Figure 2 Block Diagram, page 4.
Revised Table 4 Clock Interface, page 10 (CKXTAL2 pin revised from I to IO).
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Datasheet
Table of Contents
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
APPLICATIONS................................................................................................................................................................3
1.
2.
3.
3.1.
APPLICATION DIAGRAM...............................................................................................................................................3
BLOCK DIAGRAM...........................................................................................................................................................4
PIN ASSIGNMENTS .........................................................................................................................................................5
4.
5.
5.1.
RTL8201F (32-PIN).....................................................................................................................................................5
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................5
RTL8201FL (48-PIN) ..................................................................................................................................................6
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................6
RTL8201FN (48-PIN)..................................................................................................................................................7
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................7
5.2.
5.3.
5.4.
5.5.
5.6.
6.
PIN DESCRIPTIONS.........................................................................................................................................................8
6.1.
MII INTERFACE............................................................................................................................................................8
SERIAL MANAGEMENT INTERFACE ............................................................................................................................10
RMII INTERFACE .......................................................................................................................................................10
CLOCK INTERFACE.....................................................................................................................................................10
10MBPS/100MBPS NETWORK INTERFACE .................................................................................................................11
TRANSMIT BIAS REFERENCE......................................................................................................................................11
DEVICE CONFIGURATION INTERFACE ........................................................................................................................11
POWER AND GROUND PINS ........................................................................................................................................13
RESET AND OTHER PINS.............................................................................................................................................14
NC (NOT CONNECTED) PINS......................................................................................................................................14
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
REGISTER DESCRIPTIONS.........................................................................................................................................15
7.1.
REGISTER 0 BASIC MODE CONTROL REGISTER..........................................................................................................15
REGISTER 1 BASIC MODE STATUS REGISTER.............................................................................................................16
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................17
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................17
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ...................................................................17
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)....................................................18
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ............................................................................19
PAGE 0 REGISTER 13 MACR (MMD ACCESS CONTROL REGISTER; ADDRESS 0X0D)...............................................20
PAGE 0 REGISTER 14 MAADR (MMD ACCESS ADDRESS DATA REGISTER; ADDRESS 0X0E)...................................20
REGISTER 24 POWER SAVING MODE REGISTER (PSMR) ...........................................................................................20
REGISTER 28 FIBER MODE AND LOOPBACK REGISTER...............................................................................................21
REGISTER 30 INTERRUPT INDICATORS AND SNR DISPLAY REGISTER........................................................................21
REGISTER 31 PAGE SELECT REGISTER .......................................................................................................................21
PAGE 4 REGISTER 16 EEE CAPABILITY ENABLE REGISTER .......................................................................................22
PAGE 4 REGISTER 21 EEE CAPABILITY REGISTER .....................................................................................................22
PAGE 7 REGISTER 16 RMII MODE SETTING REGISTER (RMSR)................................................................................22
PAGE 7 REGISTER 17 CUSTOMIZED LEDS SETTING REGISTER...................................................................................23
PAGE 7 REGISTER 18 EEE LEDS ENABLE REGISTER .................................................................................................23
PAGE 7 REGISTER 19 INTERRUPT, WOL ENABLE, AND LEDS FUNCTION REGISTERS ................................................24
PAGE 7 REGISTER 20 MII TX ISOLATE REGISTER ......................................................................................................25
PAGE 7 REGISTER 24 SPREAD SPECTRUM CLOCK REGISTER......................................................................................25
MMD REGISTER MAPPING AND DEFINITION .............................................................................................................25
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
7.13.
7.14.
7.15.
7.16.
7.17.
7.18.
7.19.
7.20.
7.21.
7.22.
7.22.1.
EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) .............................................................25
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Datasheet
7.22.2.
7.22.3.
7.22.4.
7.22.5.
7.22.6.
EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01) ................................................................26
EEECR (EEE Capability Register, MMD Device 3; Address 0x14)................................................................26
EEEWER (EEE Wake Error Register, MMD Device 3; Address 0x16) ..........................................................26
EEEAR (EEE Advertisement Register, MMD Device 7; Address 0x3c)..........................................................27
EEELPAR (EEE Link Partner Ability Register, MMD Device 7; Address 0x3d)............................................27
8.
FUNCTIONAL DESCRIPTION.....................................................................................................................................28
8.1.
MII AND MANAGEMENT INTERFACE..........................................................................................................................29
8.1.1. Data Transition ....................................................................................................................................................29
8.1.2. Serial Management Interface ...............................................................................................................................29
8.2.
8.3.
INTERRUPT.................................................................................................................................................................31
AUTO-NEGOTIATION AND PARALLEL DETECTION .....................................................................................................31
8.3.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................31
8.4.
LED FUNCTIONS........................................................................................................................................................32
8.4.1. LED and PHY Address.........................................................................................................................................32
8.4.2. Link Monitor.........................................................................................................................................................32
8.4.3. RX LED ................................................................................................................................................................33
8.4.4. TX LED.................................................................................................................................................................33
8.4.5. TX/RX LED...........................................................................................................................................................34
8.4.6. LINK/ACT LED ....................................................................................................................................................34
8.4.7. Customized LED...................................................................................................................................................35
8.4.8. EEE LED Behavior...............................................................................................................................................36
8.5.
8.6.
POWER DOWN AND LINK DOWN POWER SAVING MODES..........................................................................................36
10M/100M TRANSMIT AND RECEIVE.........................................................................................................................37
8.6.1. 100Base-TX Transmit and Receive Operation .....................................................................................................37
8.6.2. 100Base-FX Fiber Transmit and Receive Operation ...........................................................................................37
8.6.3. 10Base-T Transmit and Receive Operation..........................................................................................................37
8.7.
8.8.
8.9.
8.10.
8.11.
RESET AND TRANSMIT BIAS.......................................................................................................................................38
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT......................................................................................38
AUTOMATIC POLARITY CORRECTION ........................................................................................................................39
FAR END FAULT INDICATION.....................................................................................................................................39
WAKE-ON-LAN (WOL)............................................................................................................................................39
8.11.1.
8.11.2.
8.11.3.
8.11.4.
8.11.5.
Magic Packet and Wake-Up Frame Format....................................................................................................39
Active Low Wake-On-LAN...............................................................................................................................40
Pulse Low Wake-On-LAN................................................................................................................................41
Wake-On-LAN Pin Types (MII Mode).............................................................................................................42
Wake-On-LAN Pin Types (RMII Mode)...........................................................................................................42
8.12.
8.13.
ENERGY EFFICIENT ETHERNET (EEE)........................................................................................................................43
SPREAD SPECTRUM CLOCK (SSC) .............................................................................................................................43
9.
CHARACTERISTICS......................................................................................................................................................44
9.1.
DC CHARACTERISTICS...............................................................................................................................................44
9.1.1. Absolute Maximum Ratings..................................................................................................................................44
9.1.2. Recommended Operating Conditions...................................................................................................................44
9.1.3. Power On and PHY Reset Sequence.....................................................................................................................45
9.1.4. RMII Input Mode Power Dissipation ...................................................................................................................46
9.1.5. Input Voltage: Vcc................................................................................................................................................46
9.2.
AC CHARACTERISTICS...............................................................................................................................................47
9.2.1. MII Transmission Cycle Timing ...........................................................................................................................47
9.2.2. MII Reception Cycle Timing.................................................................................................................................48
9.2.3. RMII Transmission and Reception Cycle Timing.................................................................................................49
9.2.4. MDC/MDIO Timing .............................................................................................................................................51
9.2.5. Transmission without Collision............................................................................................................................52
9.2.6. Reception without Error.......................................................................................................................................52
9.3.
CRYSTAL CHARACTERISTICS .....................................................................................................................................53
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Datasheet
9.4.
9.5.
9.6.
OSCILLATOR REQUIREMENTS ....................................................................................................................................53
CLOCK REQUIREMENTS .............................................................................................................................................54
TRANSFORMER CHARACTERISTICS ............................................................................................................................54
10.
MECHANICAL DIMENSIONS.................................................................................................................................55
10.1.
10.2.
10.3.
RTL8201F (QFN-32) ................................................................................................................................................55
RTL8201FL (LQFP-48)............................................................................................................................................56
RTL8201FN (QFN-48) .............................................................................................................................................57
11.
ORDERING INFORMATION...................................................................................................................................58
11.1.
RTL8201F SERIES SELECTION GUIDE .......................................................................................................................58
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Datasheet
List of Tables
TABLE 1. MII INTERFACE ..............................................................................................................................................................8
TABLE 2. SERIAL MANAGEMENT INTERFACE ..............................................................................................................................10
TABLE 3. RMII INTERFACE .........................................................................................................................................................10
TABLE 4. CLOCK INTERFACE.......................................................................................................................................................10
TABLE 5. 10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................11
TABLE 6. TRANSMIT BIAS REFERENCE ........................................................................................................................................11
TABLE 7. DEVICE CONFIGURATION INTERFACE...........................................................................................................................11
TABLE 8. POWER AND GROUND PINS ..........................................................................................................................................13
TABLE 9. RESET AND OTHER PINS...............................................................................................................................................14
TABLE 10. NC (NOT CONNECTED) PINS........................................................................................................................................14
TABLE 11. REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................15
TABLE 12. REGISTER 1 BASIC MODE STATUS REGISTER...............................................................................................................16
TABLE 13. REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................17
TABLE 14. REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................17
TABLE 15. REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR).....................................................................17
TABLE 16. REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................18
TABLE 17. REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ..............................................................................19
TABLE 18. PAGE 0 REGISTER 13 MACR (MMD ACCESS CONTROL REGISTER; ADDRESS 0X0D).................................................20
TABLE 19. PAGE 0 REGISTER 14 MAADR (MMD ACCESS ADDRESS DATA REGISTER; ADDRESS 0X0E) ....................................20
TABLE 20. REGISTER 24 POWER SAVING MODE REGISTER (PSMR).............................................................................................20
TABLE 21. REGISTER 28 FIBER MODE AND LOOPBACK REGISTER ................................................................................................21
TABLE 22. REGISTER 30 INTERRUPT INDICATORS AND SNR DISPLAY REGISTER..........................................................................21
TABLE 23. REGISTER 31 PAGE SELECT REGISTER .........................................................................................................................21
TABLE 24. PAGE4 REGISTER 16 EEE CAPABILITY ENABLE REGISTER..........................................................................................22
TABLE 25. PAGE4 REGISTER 21 EEE CAPABILITY REGISTER........................................................................................................22
TABLE 26. PAGE7 REGISTER 16 RMII MODE SETTING REGISTER (RMSR)...................................................................................22
TABLE 27. CUSTOMIZED LED MATRIX TABLE .............................................................................................................................23
TABLE 28. PAGE7 REGISTER 17 CUSTOMIZED LEDS SETTING REGISTER .....................................................................................23
TABLE 29. PAGE7 REGISTER 18 EEE LEDS ENABLE REGISTER....................................................................................................23
TABLE 30. PAGE7 REGISTER 19 INTERRUPT, WOL ENABLE, AND LEDS FUNCTION REGISTERS...................................................24
TABLE 31. PAGE7 REGISTER 20 MII TX ISOLATE REGISTER.........................................................................................................25
TABLE 32. PAGE7 REGISTER 24 SPREAD SPECTRUM CLOCK REGISTER ........................................................................................25
TABLE 33. MMD REGISTER MAPPING AND DEFINITION ...............................................................................................................25
TABLE 34. EEEPC1R (PCS CONTROL 1 REGISTER, MMD DEVICE 3, ADDRESS 0X00) ................................................................25
TABLE 35. EEEPS1R (PCS STATUS 1 REGISTER, MMD DEVICE 3, ADDRESS 0X01)....................................................................26
TABLE 36. EEECR (EEE CAPABILITY REGISTER, MMD DEVICE 3; ADDRESS 0X14)...................................................................26
TABLE 37. EEEWER (EEE WAKE ERROR REGISTER, MMD DEVICE 3; ADDRESS 0X16).............................................................26
TABLE 38. EEEAR (EEE ADVERTISEMENT REGISTER, MMD DEVICE 7; ADDRESS 0X3C)...........................................................27
TABLE 39. EEELPAR (EEE LINK PARTNER ABILITY REGISTER, MMD DEVICE 7; ADDRESS 0X3D) ...........................................27
TABLE 40. MANAGEMENT FRAME FORMAT ..................................................................................................................................29
TABLE 41. SERIAL MANAGEMENT ................................................................................................................................................30
TABLE 42. SETTING THE MEDIUM TYPE AND INTERFACE MODE TO MAC....................................................................................31
TABLE 43. POWER SAVING MODE PIN SETTINGS ..........................................................................................................................36
TABLE 44. WAKE-ON-LAN PIN TYPES (MII MODE) ....................................................................................................................42
TABLE 45. WAKE-ON-LAN PIN TYPES (RMII MODE)..................................................................................................................42
TABLE 46. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................44
TABLE 47. RECOMMENDED OPERATING CONDITIONS...................................................................................................................44
TABLE 48. POWER ON AND PHY RESET SEQUENCE......................................................................................................................45
TABLE 49. RMII INPUT MODE POWER DISSIPATION (WHOLE SYSTEM)........................................................................................46
TABLE 50. INPUT VOLTAGE: VCC .................................................................................................................................................46
TABLE 51. MII TRANSMISSION CYCLE TIMING .............................................................................................................................48
TABLE 52. MII RECEPTION CYCLE TIMING...................................................................................................................................49
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Datasheet
TABLE 53. RMII TRANSMISSION AND RECEPTION CYCLE TIMING................................................................................................50
TABLE 54. MDC/MDIO TIMING...................................................................................................................................................51
TABLE 55. CRYSTAL CHARACTERISTICS .......................................................................................................................................53
TABLE 56. OSCILLATOR REQUIREMENTS ......................................................................................................................................53
TABLE 57. CLOCK REQUIREMENTS ...............................................................................................................................................54
TABLE 58. TRANSFORMER CHARACTERISTICS ..............................................................................................................................54
TABLE 59. ORDERING INFORMATION ............................................................................................................................................58
TABLE 60. RTL8201F SERIES SELECTION GUIDE .........................................................................................................................58
List of Figures
FIGURE 1. APPLICATION DIAGRAM................................................................................................................................................3
FIGURE 2. BLOCK DIAGRAM..........................................................................................................................................................4
FIGURE 3. RTL8201F QFN-32 PIN ASSIGNMENTS ........................................................................................................................5
FIGURE 4. RTL8201FL LQFP-48 PIN ASSIGNMENTS....................................................................................................................6
FIGURE 5. RTL8201FN QFN-48 PIN ASSIGNMENTS .....................................................................................................................7
FIGURE 6. READ CYCLE...............................................................................................................................................................30
FIGURE 7. WRITE CYCLE .............................................................................................................................................................30
FIGURE 8. LED AND PHY ADDRESS CONFIGURATION ................................................................................................................32
FIGURE 9. RX LED......................................................................................................................................................................33
FIGURE 10. TX LED .....................................................................................................................................................................33
FIGURE 11. TX/RX LED...............................................................................................................................................................34
FIGURE 12. LINK/ACT LED ........................................................................................................................................................34
FIGURE 13. CUSTOMIZED LED WITH/WITHOUT LPI LED MODE...................................................................................................35
FIGURE 14. EEE LED BEHAVIOR..................................................................................................................................................36
FIGURE 15. ACTIVE LOW WHEN RECEIVING A MAGIC PACKET ....................................................................................................40
FIGURE 16. ACTIVE LOW WHEN RECEIVING A WAKE-UP FRAME.................................................................................................40
FIGURE 17. PULSE LOW WHEN RECEIVING A MAGIC PACKET ......................................................................................................41
FIGURE 18. PULSE LOW WHEN RECEIVING A WAKE-UP FRAME...................................................................................................41
FIGURE 19. SPECTRUM SPREAD CLOCK ........................................................................................................................................43
FIGURE 20. POWER ON AND PHY RESET SEQUENCE ....................................................................................................................45
FIGURE 21. MII INTERFACE SETUP/HOLD TIME DEFINITIONS.......................................................................................................47
FIGURE 22. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................47
FIGURE 23. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................47
FIGURE 24. MII RECEPTION CYCLE TIMING-1 ..............................................................................................................................48
FIGURE 25. MII RECEPTION CYCLE TIMING-2 ..............................................................................................................................48
FIGURE 26. RMII INTERFACE SETUP, HOLD TIME, AND OUTPUT DELAY TIME DEFINITIONS........................................................49
FIGURE 27. RMII TRANSMISSION AND RECEPTION CYCLE TIMING...............................................................................................50
FIGURE 28. MDC/MDIO INTERFACE SETUP, HOLD TIME, AND VALID FROM MDC RISING EDGE TIME DEFINITIONS .................51
FIGURE 29. MDC/MDIO TIMING..................................................................................................................................................51
FIGURE 30. MAC TO PHY TRANSMISSION WITHOUT COLLISION ..................................................................................................52
FIGURE 31. PHY TO MAC RECEPTION WITHOUT ERROR .............................................................................................................52
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Datasheet
1. General Description
The RTL8201F-VB-CG, RTL8201FL-VB-CG, and RTL8201FN-VB-CG are single-chip/single-port
10/100Mbps Ethernet PHYceivers that support:
• MII (Media Independent Interface)
• RMII (Reduced Media Independent Interface)
The RTL8201F/FL/FN implement all 10/100M Ethernet Physical-layer functions including the Physical
Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent
Sublayer (TP-PMD), 10Base-TX Encoder/Decoder, and Twisted-Pair Media Access Unit (TPMAU). The
RTL8201F/FL/FN support auto MDIX.
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides
excellent performance under all operating conditions.
Note: Version differences are listed in section 11 Ordering Information, page 58.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
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Datasheet
2. Features
Supports IEEE 802.3az-2010 (EEE)
100Base-TX IEEE 802.3u Compliant
10Base-T IEEE 802.3 Compliant
Supports MII mode
Automatic Polarity Correction
LEDs
RTL8201F and RTL8201FL provide
two network status LEDs
RTL8201FN provides three network
status LEDs
Supports RMII mode
Supports 25MHz external crystal or OSC
Supports 50MHz external OSC Clock input
Provides 50MHz clock source for MAC
Full/half duplex operation
Twisted pair or fiber mode output
Supports Auto-Negotiation
Supports power down mode
Supports Link Down Power Saving
Low power supply 1.1V and 3.3V; 1.1V is
generated by an internal regulator
0.11µm CMOS process
Packages:
Supports Base Line Wander (BLW)
compensation
32-pin MII/RMII QFN ‘Green’
package (RTL8201F)
Supports auto MDIX
48-pin MII/RMII LQFP ‘Green’
Supports Interrupt function
Supports Wake-On-LAN (WOL)
Adaptive Equalization
package (RTL8201FL)
48-pin MII/RMII QFN ‘Green’
package (RTL8201FN)
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
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Datasheet
3. Applications
DTV (Digital TV)
Printer and Office Machine
DVD Player and Recorder
Ethernet Hub
MAU (Media Access Unit)
CNR (Communication and Network Riser)
Game Console
Ethernet Switch
In addition, the RTL8201F/FL/FN can be used in any embedded system with an Ethernet MAC that needs
a UTP physical connection or Fiber PECL interface to an external 100Base-FX optical transceiver
module.
3.1. Application Diagram
Figure 1. Application Diagram
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
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Datasheet
4. Block Diagram
100M
LPI
Indication
Data
Alignment
5B
4B
RXD
Descrambler
Decoder
RXC25M
(LPI Detection)
MII/RMII
Interface
10/100
Half/Full
Switch
Logic
4B
5B
TXD
Scrambler
Encoder
25M
TXC
(LPI Generation)
PMEB
WOL
10/100M Auto- Negotiation
Control Logic
(EEE Capability Exchange)
Link Pulse
10M
TXC10
TXD10
10M Output Waveform
Shaping
(Amplitude Reduction)
Manchester Coded
Waveform
RXC10
RXD10
Data Recovery
Receive Low Pass Filter
TXD
TD+
TXO+
TXO-
Supports
EEE Quiet
3 Level
Driver
Parallel to Serial
25M
TXC
Variable
Current
RXIN+
RXIN-
3Level
MLT-3
to NRZI
Adaptive
Equalizer
Comparator
RXD
RXC
ck
Master
PLL
Serial to
Parallel
Slave
PLL
25M
data
25M or 50M
Figure 2. Block Diagram
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
5. Pin Assignments
5.1. RTL8201F (32-Pin)
Figure 3. RTL8201F QFN-32 Pin Assignments
5.2. Green Package and Version Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 3). The version is shown in the location
marked ‘V’.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
5.3. RTL8201FL (48-Pin)
Figure 4. RTL8201FL LQFP-48 Pin Assignments
5.4. Green Package and Version Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 4). The version is shown in the location
marked ‘V’.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
5.5. RTL8201FN (48-Pin)
Figure 5. RTL8201FN QFN-48 Pin Assignments
5.6. Green Package and Version Identification
Green package is indicated by the ‘G’ in GXXXV (Figure 5). The version is shown in the location
marked ‘V’.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
6. Pin Descriptions
I: Input
LI: Latched Input during Power up or Reset
IO: Bi-directional input and output
O: Output
P: Power
HZ: High impedance during power on reset
PD: Internal Pull down during power on reset
PU: Internal Pull up during power on reset
OD: Open Drain output
6.1. MII Interface
Table 1. MII Interface
Pin No. Description
(8201F) (8201FL) (8201FN)
Name
Type
Pin No.
Pin No.
TXC
O/PD
15
22
22
Transmit Clock.
This pin provides a continuous clock as a timing reference
for TXD [3:0] and TXEN signals.
TXC is 25MHz in 100Mbps mode and 2.5MHz in
10Mbps mode.
TXEN
I/PD
20
27
27
Transmit Enable.
The input signal indicates the presence of valid nibble
data on TXD [3:0]. An internal weakly pulled low resistor
prevents the bus floating.
TXER
I/PD
I/PD
I/PD
I/PD
I/PD
O/PD
-
12
23
24
25
26
19
12
23
24
25
26
19
Transmit Error.
TXD[0]
TXD[1]
TXD[2]
TXD[3]
RXC
16
17
18
19
13
Transmit Data.
The MAC will source TXD [0:3] synchronous with TXC
when TXEN is asserted. An internal weakly pulled low
resistor prevents the bus floating.
Receive Clock.
This pin provides a continuous clock reference for RXDV
and RXD [0:3] signals. RXC is 25MHz in 100Mbps mode
and 2.5MHz in 10Mbps mode.
COL
O/PD
O/PD
27
26
38
36
38
36
Collision Detect.
COL is asserted high when a collision is detected on the
media.
CRS/
Carrier Sense.
CRS_DV
This pin’s signal is asserted high if the media is not in Idle
state.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Name
Type
Pin No.
Pin No.
Pin No. Description
(8201F) (8201FL) (8201FN)
RXDV
LI/O/PD
8
13
13
Receive Data Valid.
This pin’s signal is asserted high when received data is
present on the RXD[3:0] lines. The signal is de-asserted at
the end of the packet. The signal is valid on the rising
edge of the RXC.
This pin should be pulled low when operating in MII
mode.
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the
default of MII mode. It is possible to use an external
4.7KΩ pulled high resistor to enable RMII mode.
After power on, the pin operates as the Receive Data Valid
pin.
RXD[0]
RXD[1]
O/PD
LI/O/PD
9
10
14
16
14
16
Receive Data.
These are the four parallel receive data lines aligned on
the nibble boundaries driven synchronously to the RXC
for reception by the external physical unit (PHY).
Note 1: An internal weakly pulled low resistor sets
RXD[1] to the LED function (default). Use an external
4.7KΩ pulled high resistor to enable the WOL function for
the RTL8201F.
RXD[2]
O/PD
O/PD
-
17
-
17
-
RXD[2]/
INTB
11
Note 2: The RTL8201F Pin11 is named RXD[2]/INTB.
When in RMII mode, this pin is used for the interrupt
function. See Table 9, page 14 for INTB descriptions.
RXD[3]/
LI/O/PD
12
18
18
Receive Data.
CLK_CTL
This is the parallel receive data line aligned on the nibble
boundaries driven synchronously to the RXC for reception
by the external physical unit (PHY).
RXD[3]/CLK_CTL pin is the Hardware strap in RMII
Mode.
1: REF_CLK input mode
0: REF_CLK output mode
Note: An internal weakly pulled low resistor sets
RXD[3]/CLK_CTL to REF_CLK output mode (default).
RXER/
FXEN
LI/O/PD
28
39
39
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid
/T/R/, or invalid symbol, this pin will go high.
Fiber/UTP Enable.
This pin’s status is latched at power on reset to determine
the media mode to operate in.
1: Fiber mode
0: UTP mode
An internal weakly pulled low resistor sets this to the
default of UTP mode. It is possible to use an external
4.7KΩ pulled high resistor to enable fiber mode. After
power on, the pin operates as the Receive Error pin.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
6.2. Serial Management Interface
Table 2. Serial Management Interface
Pin No. Pin No. Description
(8201F) (8201FL) (8201FN)
Name
Type
Pin No.
MDC
I/PU
22
30
30
Management Data Clock.
This pin provides a clock synchronous to MDIO, which
may be asynchronous to the transmit TXC and receive
RXC clocks. The clock rate can be up to 2.5MHz. Use an
internal weakly pulled high resistor to prevent the bus
floating.
MDIO
IO/PU
23
31
31
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer
management information.
6.3. RMII Interface
Table 3. RMII Interface
Name
Type
Pin No.
Pin No.
Pin No. Description
(8201F) (8201FL) (8201FN)
TXC
IO/PD
15
22
22
Synchronous 50MHz Clock Reference for Receive,
Transmit, and Control Interface. The direction is decided
by Page 7, Register 16.
The default direction is reference clock output mode if
RXD[3]/CLK_CTL pin floating.
CRS/
CRS_DV
O/PD
26
36
36
Carrier Sense/Receive Data Valid.
CRS_DV shall be asserted by the PHY when the receive
medium is non-idle.
TXEN
I/PD
I/PD
20
16, 17
9, 10
28
27
27
Transmit Enable.
Transmit Data.
Receive Data.
TXD[0:1]
RXD[0:1]
23, 24
14, 16
39
23, 24
14, 16
39
O/PD
RXER/
FXEN
LI/O/PD
Receive Error. RX_ER is a required output of the PHY,
but is an optional input for the MAC.
6.4. Clock Interface
Table 4. Clock Interface
Name
Type
Pin No.
Pin No.
Pin No. Description
(8201F) (8201FL) (8201FN)
CKXTAL2
IO
32
43
43
25MHz Crystal Output.
This pin provides the 25MHz crystal output.
If an external 25MHz/50MHz oscillator or clock is used,
connect CKXTAL2 to the oscillator or clock output (see
section 9.4 Oscillator Requirements, page 53).
CKXTAL1
I
31
42
42
25MHz Crystal Input.
This pin provides the 25MHz crystal input.
Must be shorted to GND when an external
25MHz/50MHz oscillator or clock drives CKXTAL2.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
6.5. 10Mbps/100Mbps Network Interface
Table 5. 10Mbps/100Mbps Network Interface
Pin No. Pin No. Description
(8201F) (8201FL) (8201FN)
Name
Type
Pin No.
MDI+[0]
MDI-[0]
IO
3
4
1
2
1
2
Transmit Output.
Differential transmit output pair shared by 100Base-TX,
100Base-FX, and 10Base-T modes. When configured as
100Base-TX, output is an MLT-3 encoded waveform.
When configured as 100Base-FX, the output is pseudo-
ECL level.
MDI+[1]
MDI-[1]
IO
5
6
4
5
4
5
Receive Input.
Differential receive input pair shared by 100Base-TX,
100Base-FX, and 10Base-T modes.
6.6. Transmit Bias Reference
Table 6. Transmit Bias Reference
Pin No. Pin No. Description
(8201F) (8201FL) (8201FN)
46 46
Name
Type
Pin No.
RSET
I
1
Transmit Bias Resistor Connection.
This pin should be pulled to GND by a 2.49KΩ (1%)
resistor to define driving current for the transmit DAC.
6.7. Device Configuration Interface
Table 7. Device Configuration Interface
Pin No. Pin No. Description
(8201F) (8201FL) (8201FN)
Name
Type
Pin No.
RXDV
LI/O/PD
8
13
13
Receive Data Valid.
This pin’s signal is asserted high when received data is
present on the RXD [3:0] lines. The signal is de-asserted at
the end of the packet. The signal is valid on the rising edge
of the RXC.
This pin should be pulled low when operating in MII mode.
0: MII mode
1: RMII mode
An internal weakly pulled low resistor sets this to the default
of MII mode. It is possible to use an external 4.7KΩ pulled
high resistor to enable RMII mode.
After power on, the pin operates as the Receive Data Valid
pin.
RXD[1]
LI/O/PD
10
16
16
An internal weakly pulled low resistor sets RXD[1] to the
LED function (default). Use an external 4.7KΩ pulled high
resistor to enable the WOL function for the RTL8201F.
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Name
Type
Pin No.
Pin No.
Pin No. Description
(8201F) (8201FL) (8201FN)
LED0/
PHYAD[0]
LI/O/PU
-
34
-
34
-
PHY Address and Customized LED Settings.
The default available PHY addresses are:
RTL8201F: 00000~00011.
LED0/
LI/O/PU
24
RTL8201FL:
PHYAD[0]/
PMEB
00100~00111 (when PMEB pin is pulled high)
00000~00011 (when PMEB pin is pulled low)
RTL8201FN: 00000~00111.
LED1/
PHYAD[1]
LI/O/PD
LI/O/PD
25
-
35
-
35
32
Traditional LED Function Selection
LED
_Sel
00
01
10
11
LED2/
PHYAD[2]
LinkALL
ACTALL ACTALL
/
Link10/
LINK10
/ACT10
LED0 ACTALL
LINK100
ACT100
/
LED1 LINK100 LINK100 LINK100
LED2 Reserved Reserved Reserved Reserved
Note 1: For Customized LED Settings, see section
7.17, page 23.
Note 2: LED_Sel default is 11. Refer to section 7.19,
page 24.
An internal weakly pulled low resistor sets RXD[1] to the
LED function for RTL8201F (default).
Use an external 4.7KΩ pulled high resistor to enable the
WOL function for RTL8201F.
Traditional LED Function Selection for the RTL8201F
with WOL Enabled
With the RTL8201F WOL function enabled, the PHY
address must be 00001 or 00011.
LED
_Sel
00
01
10
11
LINK100
ACT100
/
LED1 LINK100 LINK100 LINK100
RXD[3]/
LI/O/PD
12
18
18
Receive Data.
CLK_CTL
This is the parallel receive data line aligned on the nibble
boundaries driven synchronously to the RXC for reception
by the external physical unit (PHY).
RXD [3]/CLK_CTL pin is the Hardware strap in RMII
Mode.
1: REF_CLK input mode
0: REF_CLK output mode
Note: An internal weakly pulled low resistor sets
RXD[3]/CLK_CTL to REF_CLK output mode (default).
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Name
Type
Pin No.
Pin No.
Pin No. Description
(8201F) (8201FL) (8201FN)
RXER/
FXEN
LI/O/PD
28
39
39
Fiber/UTP Interface.
This pin’s status is latched at power on reset to determine
the media mode to operate in.
1: Fiber mode
0: UTP mode
An internal weakly pulled low resistor sets this to the default
of UTP mode. It is possible to use an external 4.7KΩ pulled
high resistor to enable fiber mode.
EN_LDO_ LI/O/PU
OUT
-
-
11
LDO Mode Strap.
1: LDO enable
2: LDO disable
6.8. Power and Ground Pins
Table 8. Power and Ground Pins
Pin No. Pin No. Description
(8201F) (8201FL) (8201FN)
Name
Type Pin No.
AVDD33
P
P
7, 30
6, 41
6, 41
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well
decoupled.
DVDD33
14
15, 21, 37 15, 21, 37 3.3V Digital Power Input.
3.3V power supply for digital circuit.
1.1V Digital Power.
DVDD10
P
-
28
48
28
48
AVDD10OUT
O
2
Power Output.
Be sure to connect a 0.1µF ceramic capacitor for
decoupling purposes.
The connection method is outlined in section 8.8
3.3V Power Supply and Voltage Conversion Circuit,
page 38.
DVDD10OUT
O
P
29
40
40
Power Output.
Be sure to connect a 0.1µF ceramic capacitor for
decoupling purposes.
The connection method is outlined in section 8.8
3.3V Power Supply and Voltage Conversion Circuit,
page 38.
GND
E-PAD
7, 20, 33,
47
E-PAD
Ground. Should be connected to a larger GND plane.
Exposed Pad (E-Pad) is Analog and Digital Ground.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
6.9. Reset and Other Pins
Table 9. Reset and Other Pins
Pin No. Pin No. Description
(8201F) (8201FL) (8201FN)
Name
Type Pin No.
PHYRSTB
I/HZ
21
29
29
RESETB.
Set low to reset the chip. For a complete reset, this pin
must be asserted low for at least 10ms.
Note: When the WOL function is enabled, keep the pin
high (RTL8201FN only).
INTB
O/OD
-
32
20
Interrupt.
Set low if link status changed, duplex changed, or auto
negotiation failed. Active Low.
This pin is an open-drain design, and for default value
should be pulled high by an external 4.7KΩ. If not used,
keep floating.
RXD[2]/INTB
O/PD
11
24
-
-
Interrupt.
Set low if link status changed, duplex changed, or auto
negotiation failed. Active Low.
This pin is an open-drain design, and for default value
should be pulled high by an external 4.7KΩ. If not used,
keep floating.
Note: This pin is used for the interrupt function only
when in the RMII mode.
PMEB
O/OD
10
33
Power Management Enable.
Set low if received a magic packet or wake up frame;
active low.
6.10. NC (Not Connected) Pins
Table 10. NC (Not Connected) Pins
Name
Type Pin No.
Pin No.
Pin No.
Description
(8201F) (8201FL)
(8201FN)
NC
-
-
3, 8, 9, 11, 3, 7, 8, 9, 10, Not Connected.
44, 45 44, 45, 47
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7. Register Descriptions
This section describes the functions and usage of the registers available in this file. In this section the
following abbreviations are used.
RW: Read/Write
RO: Read Only
RC: Read Clear
SC: Self-Clear
RW/EFUS: Read/Write/eFUSE Burnable
RW/LI: Read/Write/Latch In
RW/SC: Read/Write/Self-Clearing
Note: RW/EFUS and RW/LI types will return to default values after a software reset (set Reg.0 Bit15 to 1).
7.1. Register 0 Basic Mode Control Register
Table 11. Register 0 Basic Mode Control Register
Address Name
Description
Mode Default
0:15
Reset
This bit sets the status and control registers of the PHY in the
default state. This bit is self-clearing.
RW/
SC
0
1: Software reset
0: Normal operation
Register 0 and register 1 will return to default values after a
software reset (set Bit15 to 1).
This action may change the internal PHY state and the state of the
physical link associated with the PHY.
0:14
0:13
Loopback
This bit enables loopback of transmit data nibbles TXD3:0 to the
receive data path.
RW
RW
0
1
1: Enable loopback
This bit sets the network speed.
1: 100Mbps
0: Normal operation
Speed Selection
0: 10Mbps
After completing auto negotiation, this bit will reflect the speed
status.
1: 100Base-T
0: 10Base-T
When 100Base-FX mode is enabled, this bit=1 and is read only.
0:12
Auto Negotiation
Enable
This bit enables/disables the NWay auto-negotiation function.
1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the
link speed and the data transfer mode, respectively
RW
1
When 100Base-FX mode is enabled, this bit=0 and is read only.
0:11
0:10
Power Down
Isolate
This bit turns down the power of the PHY chip, including the
internal crystal oscillator circuit.
The MDC, MDIO is still alive for accessing the MAC.
RW
RW
0
0
1: Power down
0: Normal operation
1: Electrically isolate the PHY from MII/GMII/RGMII/RSGMII.
PHY is still able to respond to MDC/MDIO.
0: Normal operation
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Address Name
Description
This bit allows the NWay auto-negotiation function to be reset.
1: Re-start auto-negotiation 0: Normal operation
Mode Default
0:9
Restart Auto
RW/
SC
0
Negotiation
0:8
Duplex Mode
This bit sets the duplex mode if auto-negotiation is disabled (bit
0:12=0).
RW
1
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex
status.
1: Full duplex
0: Half duplex
0:7
Collision Test
Collision Test.
RW
0
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted in
response to the TXEN assertion within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the
TXEN de-assertion.
0:6
Speed Selection[1] Speed Select Bit 1.
Refer to bit 0.13.
RW
-
0
-
0:5~0
Reserved
Reserved.
7.2. Register 1 Basic Mode Status Register
Table 12. Register 1 Basic Mode Status Register
Address Name
Description
Mode Default
1:15
1:14
1:13
1:12
1:11
100Base-T4
1: Enable 100Base-T4 support
RO
RO
RO
RO
RO
0
1
1
1
1
0: Suppress 100Base-T4 support
1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
Reserved.
100Base_TX_FD
100Base_TX_HD
10Base_T_FD
10_Base_T_HD
1:10~7 Reserved
-
-
1:6
MF Preamble Suppression
The RTL8201F/FL/FN will accept management frames
with preamble suppressed.
RO
1
A minimum of 32 preamble bits are required for the first
management interface read/write transaction after reset.
One idle bit is required between any two management
transactions as per IEEE 802.3u specifications.
1:5
1:4
Auto Negotiation Complete 1: Auto-negotiation process completed
RO
RC
0
0
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band
signal Far-End-Fault has been detected (see 8.10 Far End
Fault Indication, page 39).
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Datasheet
Address Name
Description
Mode Default
1:3
Auto-Negotiation Ability
1: PHY is able to perform auto-negotiation
0: PHY is not able to perform auto-negotiation
RO
1
1:2
Link Status
1: Valid link established
RO
0
0: No valid link established
This bit indicates whether the link was lost since the last
read. For the current link status, read this register twice.
1:1
1:0
Jabber Detect
1: Jabber condition detected
RO
RO
0
1
0: No jabber condition detected
1: Extended register capable (permanently=1)
0: Not extended register capable
Extended Capability
7.3. Register 2 PHY Identifier Register 1
Table 13. Register 2 PHY Identifier Register 1
Address Name
Description
Mode
Default
Composed of the 6th to 21st bits of the Organizationally Unique
Identifier (OUI), respectively.
2:15~0 OUI
RO
001Ch
7.4. Register 3 PHY Identifier Register 2
Table 14. Register 3 PHY Identifier Register 2
Address Name
Description
Mode
RO
Default
110010
000001
0110
3:15~10 OUI_LSB
Assigned to the 0 through 5th bits of the OUI.
Model Number
3:9~4
3:3~0
Model Number
RO
Revision Number Revision Number
RO
7.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Table 15. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Address Name
Description
Mode
Default
4:15
Next Page
Next Page Bit.
RW
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
1: Acknowledge reception of link partner capability data word
0: Do not acknowledge reception
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
Reserved.
4:14
4:13
Acknowledge
Remote Fault
Reserved
RO
0
0
RW
4:12
4:11
-
-
Asymmetric
PAUSE
1: Advertise asymmetric pause support
0: No support of asymmetric pause
Reserved.
RW
0
4:10
Pause
RW
0
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Address Name
Description
Mode
Default
4:9
100Base-T4
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full duplex supported by local node
0: 10Base-T full duplex not supported by local node
1: 10Base-T is supported by local node
0: 10Base-T not supported by local node
RO
0
4:8
100Base-TX-FD
100Base-TX
10Base-T-FD
10Base-T
RW
RW
RW
RW
RO
1
4:7
1
4:6
1
1
4:5
4:4~0
Selector Field
Binary Encoded Selector Supported by This Node.
Currently only CSMA/CD 00001 is specified. No other
protocols are supported.
00001
7.6. Register 5 Auto-Negotiation Link Partner Ability Register
(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during auto-negotiation. The
content changes after a successful auto-negotiation if Next-pages are supported.
Table 16. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Address Name
Description
Mode
Default
5:15
5:14
5:13
Next Page
Next Page Bit.
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
RO
0
Acknowledge
Remote Fault
1: Link partner acknowledges reception of local node’s
capability data word
0: No acknowledgement
RO
RO
0
0
1: Link partner is indicating a remote fault
0: Link partner is not indicating a remote fault
Reserved.
5:12
5:11
Reserved
-
-
Asymmetric Pause
1: Asymmetric Flow control supported by Link Partner
0: No Asymmetric flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link
Partner ability.
RO
0
5:10
Pause
1: Flow control supported by Link Partner
0: No flow control supported by Link Partner
When auto-negotiation is enabled, this bit reflects Link
Partner ability (read only).
RO
0
5:9
5:8
100Base-T4
1: 100Base-T4 is supported by link partner
0: 100Base-T4 not supported by link partner
RO
RO
0
0
100Base-TX-FD
1: 100Base-TX full duplex is supported by link partner
0: 100Base-TX full duplex not supported by link partner
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Address Name
Description
Mode
Default
5:7
100Base-TX
1: 100Base-TX is supported by link partner
0: 100Base-TX not supported by link partner
This bit will also be set if the link in 100Base-TX is
established by parallel detection.
RO
0
5:6
5:5
10Base-T-FD
10Base-T
1: 10Base-T full duplex is supported by link partner
0: 10Base-T full duplex not supported by link partner
RO
RO
0
0
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
This bit will also be set if the link in 10Base-T is established
by parallel detection.
5:4~0
Selector Field
Link Partner’s Binary Encoded Node Selector.
Currently only CSMA/CD 00001 is specified.
RO
00001
7.7. Register 6 Auto-Negotiation Expansion Register (ANER)
This register contains additional status for NWay auto-negotiation.
Table 17. Register 6 Auto-Negotiation Expansion Register (ANER)
Address Name
Description
Mode Default
6:15~5 Reserved
Reserved.
-
-
6:4
6:3
6:2
6:1
6:0
Parallel Detection 1: A fault has been detected via the Parallel Detection function
Fault
Link Partner Next 1: Link Partner is Next Page able
Page Ability
Local Next Page 1: Next Page is able
RC
0
0: No fault has been detected via the Parallel Detection function
RO
RO
RC
RO
0
0
0
0
0: Link Partner is not Next Page able
Ability
0: Not Next Page able
Page Received
1: A New Page has been received
0: A New Page has not been received
If Auto-Negotiation is Enabled, This Bit Means:
1: Link Partner is Auto-Negotiation able
0: Link Partner is not Auto-Negotiation able
Link Partner
Auto-Negotiation
Ability
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.8. Page 0 Register 13 MACR (MMD Access Control Register;
Address 0x0D)
Table 18. Page 0 Register 13 MACR (MMD Access Control Register; Address 0x0D)
Bit
Name
RW
Default
Description
13.15:14 Function
WO
0
00: Address
01: Data; no post increment
10: Data; post increment on reads and writes
11: Data; post increment on writes only
13.13:5 RSVD
13.4:0 DEVAD
RO
000000000 Reserved.
Device Address.
WO
0
Note 1: Used in conjunction with the MAADR (Register 14) to provide access to the MMD address space.
Note 2: If the access of MAADR is for address (Function=00) then it is directed to the address register within the MMD
associated with the value in the DEVAD field.
Note 3: If the access of MAADR is for data (Function=00) then both the DEVAD field and the MMD address register
direct the MAADR data accesses to the appropriate registers within the MMD.
7.9. Page 0 Register 14 MAADR (MMD Access Address Data
Register; Address 0x0E)
Table 19. Page 0 Register 14 MAADR (MMD Access Address Data Register; Address 0x0E)
Bit
Name
RW
Default
Description
14.15:0 Address Data
RW
0x0000
13.15:14=00
Æ MMD DEVAD’s address register
13.15:14=01, 10, or 11
Æ MMD DEVAD’s data register as indicated by the contents of
its address register
Note: Used in conjunction with the MACR (Register 13) to provide access to the MMD address space.
7.10. Register 24 Power Saving Mode Register (PSMR)
Table 20. Register 24 Power Saving Mode Register (PSMR)
Address Name
Description
Mode Default
24:15
Enpwrsave
Enable Power Saving Mode.
The bit will return to default value by software reset.
Reserved.
RW
1
24:14~0 Reserved
-
-
Note: If the REF_CLK output is needed in RMII output mode, LDPS (Link Down Power Saving) must be disabled (see
Table 43, page 36).
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.11. Register 28 Fiber Mode and Loopback Register
Table 21. Register 28 Fiber Mode and Loopback Register
Address Name
Description
Reserved.
Mode
-
Default
28:15~6
28:5
Reserved
-
0
-
Fxmode
Enable Fiber Mode.
Reserved.
RW
-
28:4~3
28:2
Reserved
En_autoMDIX
Force_MDI
Enable Auto MDIX Function.
Force MDI/MDIX Mode.
If enable auto MDIX function is disabled:
1: Force MDI
RW
RW
1
1
28:1
0: Force MDIX
28:0
Reserved
Reserved.
-
-
7.12. Register 30 Interrupt Indicators and SNR Display Register
Table 22. Register 30 Interrupt Indicators and SNR Display Register
Address Name
Description
Mode
Default
30:15
30:14
30:13
Anerr
Auto-Negotiation Error Interrupt.
1: Enable
0: Disable
RC
0
Spdchg
Duplexchg
Speed Mode Change Interrupt.
1: Enable
0: Disable
RC
RC
0
0
Duplex Mode Change Interrupt.
1: Enable
0: Disable
30:12
30:11
Reserved
Reserved.
-
-
Linkstatuschg
Link Status Change Interrupt.
1: Enable
RC
0
0: Disable
30:10~4
30:3~0
Reserved
SNR_O
Reserved.
-
-
These 4-Bits Show the Signal to Noise Ratio Value.
RO
0000
7.13. Register 31 Page Select Register
Table 23. Register 31 Page Select Register
Address Name
Description
Mode
-
Default
-
31:15~8
31:7~0
Reserved
PAGE SEL
Reserved for Internal Testing.
Select Page Address: 00000000~11111111.
RW
00000000
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.14. Page 4 Register 16 EEE Capability Enable Register
Table 24. Page4 Register 16 EEE Capability Enable Register
Address Name
16:15~14 Reserved
16:13
Description
Mode
-
Default
Reserved.
-
EEE_10_cap
Enable EEE 10M Capability.
RW
1
1
16:12
EEE_nway_en Enable Next Page Exchange in NWay for EEE 100M.
RW/
EFUS
16:11~10 Reserved
Reserved.
-
-
16:9
16:8
Tx_quiet_en
Enable Ability to Turn Off Power 100TX when TX in Quiet State.
This bit is recommended to be set to 1 when EEE is enabled.
Enable Ability to Turn Off Power 100RX when RX in Quiet state.
This bit is recommended to be set to 1 when EEE is enabled.
Reserved.
RW/
EFUS
1
Rx_quiet_en
Reserved
RW/
EFUS
1
-
16:7:0
-
7.15. Page 4 Register 21 EEE Capability Register
Table 25. Page4 Register 21 EEE Capability Register
Address Name
Description
Mode
Default
21:15~13 Reserved
Reserved.
-
-
0
-
21:12
21:11~1
21:0
Rg_dis_ldvt
Reserved
Set to 1 to Disable the Line Driver of the Analog Circuit.
Reserved.
RW
-
EEE_100_cap NWay Result to Indicate Link Partner Supports EEE 100M.
RO
0
7.16. Page 7 Register 16 RMII Mode Setting Register (RMSR)
Table 26. Page7 Register 16 RMII Mode Setting Register (RMSR)
Address Name
Description
Mode
-
Default
16:15~13 Reserved
Reserved.
-
16:12
Rg_rmii_clkdir
This Bit Sets the Type of TXC in RMII Mode.
0: Output
RW/LI
0
1: Input
16:11~8
16:7~4
16:3
Rg_rmii_tx_offset
Rg_rmii_rx_offset
Adjust RMII TX Interface Timing.
Adjust RMII RX Interface Timing.
RW/EFUS
RW/EFUS
RW/LI
1111
1111
0
0: MII Mode
1: RMII Mode
RMII Mode
16:2
16:1
16:0
0: CRS/CRS_DV pin is CRS_DV signal
1: CRS/CRS_DV pin is RXDV signal
0: RMII data only
1: RMII data with SSD Error
Reserved.
RW/EFUS
RW/EFUS
-
0
1
-
Rg_rmii_rxdv_sel
Rg_rmii_rxdsel
Reserved
Note: Set Page7, Register 16 to ‘7FFB’when an external clock (25MHz and 50MHz) inputs to the CKXTAL2 pin.
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.17. Page 7 Register 17 Customized LEDs Setting Register
This register is for setting customized LEDs. Table 27 shows the customized LED matrix table.
Table 27. Customized LED Matrix Table
LINK
ACT
10M
Bit0
Bit4
Bit8
100M
Bit1
LED0
LED1
LED2
Bit3
Bit7
Bit5
Bit9
Bit11
LED Pin
ACT=0
Floating
ACT=1
LINK=0
LINK>0
All Speed ACT
Selected Speed LINK
Selected Speed LINK+ACT
Note: The RTL8201F/FL only supports LED0 and LED1. The RTL8201FN supports LED0, LED1, and LED2.
Table 28. Page7 Register 17 Customized LEDs Setting Register
Address Name
Description
Mode
Default
-
17:15~12 Reserved
Reserved.
-
17:11~8
17:7~4
17:3~0
LED_sel2
LED_sel1
LED_sel0
Customized LED2 Setting.
Set Bit3 (Page7 Register 19; Table 30, page 24) to 1 to
enable customized LED function.
RW/
EFUS
0000
Customized LED1 Setting.
Set Bit3 (Page7 Register 19; Table 30, page 24) to 1 to
enable customized LED function.
RW/
EFUS
0000
0000
Customized LED0 Setting.
RW/
EFUS
Set Bit3 (Page7 Register 19; Table 30, page 24) to 1 to
enable customized LED function.
7.18. Page 7 Register 18 EEE LEDs Enable Register
Table 29. Page7 Register 18 EEE LEDs Enable Register
Address Name
Description
Mode
-
Default
18:15~3
18:2
Reserved
Reserved.
-
EEE_LED_en2
EEE_LED_en1
EEE_LED_en0
Enable LED2 in EEE/LPI Mode.
Enable LED1 in EEE/LPI Mode.
Enable LED0 in EEE/LPI Mode.
RW
RW
RW
0
0
0
18:1
18:0
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.19. Page 7 Register 19 Interrupt, WOL Enable, and LEDs
Function Registers
Table 30. Page7 Register 19 Interrupt, WOL Enable, and LEDs Function Registers
Address Name
Description
Mode Default
19:15~14 Reserved
Reserved.
-
-
19:13
19:12
19:11
19:10
Int_linkchg
Int_dupchg
Int_anerr
Link Change Interrupt Mask.
1: Interrupt pin Enable
0: Interrupt pin Disable
This bit set to 0 only masks the link change interrupt event in the
INTB pin. Reg30 Bit11 always reflects the link change interrupt
behavior (see Table 22, page 21).
RW
0
Duplex Change Interrupt Mask.
1: Interrupt pin Enable
0: Interrupt pin Disable
This bit set to 0 only masks the duplex change interrupt event in
the INTB pin. Reg30 Bit13 always reflects the duplex change
interrupt behavior (see Table 22, page 21).
RW
RW
0
0
0
NWay Error Interrupt Mask.
1: Interrupt pin Enable
0: Interrupt pin Disable
This bit set to 0 only masks the NWay Error interrupt event in the
INTB pin.Reg30 Bit15 always reflects the NWay Error interrupt
behavior (see Table 22, page 21).
Rg_led0_wol_sel
LED and Wake-On-LAN Function Selection (RTL8201F Only). RW/LI
1: Wake-On-LAN Function Enable
0: LED Function Enable
An internal weakly pulled low resistor sets RXD[1] to the LED
function (default). Use an external 4.7KΩ pulled high resistor to
enable the WOL function for the RTL8201F.
19:9~6
19:5~4
Reserved
Reserved.
-
-
LED_sel[1:0]
Traditional LED Function Selection.
RW/
11
EFUS
LED_sel 00
01
10
11
LinkALL
/
Link10/
ACTALL
LINK10
/ACT10
LED0
ACTALL
ACTALL
LINK100
Reserved
LINK100/A
CT100
LED1
LED2
LINK100
LINK100
Reserved
Reserved Reserved
19:3
Customized_LED
Customized LED Enable.
RW/
0
EFUS
1: Customized LED function enable
0: Customized LED function disable
See the section 8.4.7 Customized LED, page 35 for detail.
19:2~1
19:0
Reserved
En10mlpi
Reserved.
-
-
Enable 10M LPI LED Function.
RW
0
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.20. Page 7 Register 20 MII TX Isolate Register
Table 31. Page7 Register 20 MII TX Isolate Register
Address Name
Description
Mode Default
20:15
Rg_tx_isolate_en
Reserved
Isolate MII TX Path Signals when TX Idle.
Reserved.
RW
-
0
-
20:14~0
7.21. Page 7 Register 24 Spread Spectrum Clock Register
Table 32. Page7 Register 24 Spread Spectrum Clock Register
Address Name
Description
Mode
-
Default
24:15~1
24:0
Reserved
Rg_dis_ssc
Reserved.
-
0: SSC function is enabled
1: SSC function is disabled
RW
0
7.22. MMD Register Mapping and Definition
Note: MMD registers are placed at Page 0 Register 13 and Register 14.
Table 33. MMD Register Mapping and Definition
Device Offset
Access
Name
Description
3
3
3
3
7
7
0
RW
EEEPC1R
EEE PCS Control 1 Register
EEE PCS Status Control 1 Register
EEE Capability Register
1
RO/RO, LH EEEPS1R
20
22
60
61
RO
RC
RW
RO
EEECR
EEEWER
EEEAR
EEE Wake Error Register
EEE Advertisement Register
EEE Link Partner Ability Register
EEELPAR
Note: LH: Latching High.
7.22.1. EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00)
Table 34. EEEPC1R (PCS Control 1 Register, MMD Device 3, Address 0x00)
Bit
Name
RW Default Description
3.0.15:11 RSVD
RW
RW
0
0
Reserved.
3.0.10 Clock Stop Enable
1: PHY stops RXC in LPI
0: RXC not stoppable
Reserved.
3.0.9:0 RSVD
RW
0
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.22.2. EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01)
Table 35. EEEPS1R (PCS Status 1 Register, MMD Device 3, Address 0x01)
Bit
Name
RW
RO
Default Description
3.1.15:12 RSVD
0
0
Reserved.
3.1.11 TX LPI Received
RO, LH
1: TX PCS has received LPI
0: LPI not received
3.1.10 RX LPI Received
RO, LH
RO
0
0
0
1: RX PCS has received LPI
0: LPI not received
3.1.9
3.1.8
TX LPI Indication
RX LPI Indication
1: TX PCS is currently receiving LPI
0: TX PCS is not currently receiving LPI
1: RX PCS is currently receiving LPI
0: RX PCS is not currently receiving LPI
Reserved.
RO
3.1.7
3.1.6
RSVD
RO
RO
0
1
Clock Stop Capable
1: MAC stops TXC in LPI
0: TXC not stoppable
3.1.5:0 RSVD
RO
0
Reserved.
7.22.3. EEECR (EEE Capability Register, MMD Device 3; Address 0x14)
Table 36. EEECR (EEE Capability Register, MMD Device 3; Address 0x14)
Bit
Name
RW
RO
RO
Default Description
3.20.15:2 RSVD
0
1
Reserved.
3.20.1 100Base-TX EEE
1: EEE is supported for 100Base-TX EEE
0: EEE is not supported for 100Base-TX EEE
Reserved.
3.20.0 RSVD
RO
1
7.22.4. EEEWER (EEE Wake Error Register, MMD Device 3;
Address 0x16)
Table 37. EEEWER (EEE Wake Error Register, MMD Device 3; Address 0x16)
Bit
Name
RW
Default Description
3.22.15:0 EEE Wake Error Counter
RC
0
Used by PHY types that support EEE to count wake time
faults where the PHY fails to complete its normal wake
sequence within the time required for the specific PHY type.
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
7.22.5. EEEAR (EEE Advertisement Register, MMD Device 7;
Address 0x3c)
Table 38. EEEAR (EEE Advertisement Register, MMD Device 7; Address 0x3c)
Bit
Name
RW
RW
RW
Default Description
7.60.15:3 RSVD
0
1
Reserved.
7.60.1 100Base-TX EEE
Advertise 100Base-TX EEE Capability.
1: Advertise
0: Do not advertise
Reserved.
7.60.0 RSVD
RW
0
7.22.6. EEELPAR (EEE Link Partner Ability Register, MMD Device 7;
Address 0x3d)
Table 39. EEELPAR (EEE Link Partner Ability Register, MMD Device 7; Address 0x3d)
Bit
Name
RW
RO
RO
Default Description
7.61.15:3 RSVD
0
0
Reserved.
7.61.1 LP 100Base-TX EEE
1: Link Partner is capable of 100Base-TX EEE
0: Link Partner is not capable of 100Base-TX EEE
7.61.0 RSVD
RO
0
Reserved.
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
8. Functional Description
The RTL8201F/FL/FN PHYceiver is a physical layer device that integrates 10Base-T and
100Base-TX/100Base-FX functions, and some extra power management features. This device supports
the following functions:
• MII interface with MDC/MDIO management interface to communicate with the MAC
• IEEE 802.3u clause 28 Auto-Negotiation ability
• Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
• Power Down mode support
• 4B/5B transform
• Scrambling/De-scrambling
• NRZ to NRZI, NRZI to MLT-3
• Manchester Encode and Decode for 10Base-T operation
• Clock and Data recovery
• Adaptive Equalization
• Automatic Polarity Correction
• Far End Fault Indication (FEFI) in fiber mode
• Network status LEDs
• Wake-On-LAN (WOL)
• Energy Efficient Ethernet (EEE)
• Spread Spectrum Clock (SSC) for RMII REF_CLK output mode
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
8.1. MII and Management Interface
8.1.1. Data Transition
The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying
a standard interface between the PHY and MAC layer.
This interface operates at two frequencies; 25MHz and 2.5MHz, to support 100Mbps/10Mbps bandwidth
for both transmit and receive functions.
Transmission
The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the
PHY via TXD[3:0]. The PHY will sample TXD[3:0] synchronously with TXC – the transmit clock signal
supplied by the PHY – during the interval TXEN is asserted.
Reception
The PHY asserts the RXDV signal. It passes the received nibble data RXD[3:0] clocked by RXC. CRS
and COL signals are used for collision detection and handling.
In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is
recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble
has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.
The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/
or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur, e.g., an invalid J/K,
invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the
reconciliation sublayer that an error was detected somewhere in the frame.
8.1.2. Serial Management Interface
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 4
(RTL8201F/FL) or 8 (RTL8201FN) devices, configured with different PHY addresses (00b to 11b for the
RTL8201F/FL; 000b to 111b for the RTL8201FN). Frames transmitted on the MDC/MDIO Management
Interface should have the frame structure shown in Table 40.
Table 40. Management Frame Format
Management Frame Fields
Preamble
1…1
ST
01
01
OP
10
PHYAD REGAD TA
DATA
IDLE
Read
Write
AAAAA RRRRR
AAAAA RRRRR
Z0
10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
1…1
01
During a hardware reset, the logic levels of pins 34/24, 35/25, and 32/22 (only RTL8201FN) are latched
to be set as the PHY address for management communication via the serial interface. The read and write
frame structure for the management interface is illustrated in Figure 6 and Figure 7, page 30.
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Figure 6. Read Cycle
MDC
MDIO(MAC)
z
z
0 0 0 0 0 0
1
1...1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Write
OP
(Code)
Pre
PHY Address
0x01
Reg. Address
0x00(BMCR)
Turn
Around
Reg. Data
0x1340
Start
Idle
Figure 7. Write Cycle
Table 41. Serial Management
Name
Description
Preamble
32 Contiguous Logical 1’s Sent by the MAC on MDIO, along with 32 Corresponding Cycles on MDC.
This provides synchronization for the PHY.
Start of Frame.
ST
Indicated by a 01 pattern.
Operation Code.
OP
Read: 10
Write: 01
PHYAD
REGAD
TA
PHY Address.
Up to 4 PHYs can be connected to one MAC. This 2-bit field selects which PHY the frame is directed to.
Register Address.
This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Turnaround.
This is a 2-bit-time spacing between the register address and the data field of a frame to avoid contention
during a read transaction. For a read transaction, both the STA and the PHY remain in a high-impedance
state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit time of the
turnaround of a read transaction.
DATA
IDLE
Data.
These are the 16 bits of data.
Idle Condition.
Not truly part of the management frame. This is a high impedance state. Electrically, the PHY’s pull-up
resistor will pull the MDIO line to a logical ‘1’.
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RTL8201F/RTL8201FL/RTL8201FN
Datasheet
8.2. Interrupt
Whenever there is a status change on the media detected by the RTL8201F/FL/FN, they will drive the
interrupt pin (INTB) low to issue an interrupt event. The MAC senses the status change and accesses the
page0 register30 through the MDC/MDIO interface in response.
Once these status registers page0 register30 have been read by the MAC through the MDC/MDIO, the
INTB is de-asserted. The RTL8201FN/FL interrupt function removes the need for continuous polling
through the MDC/MDIO management interface.
Note 1: The RTL8201F RXD[2]/INTB pin (Pin11) is used for the interrupt function only when in the RMII
mode.
Note 2: The Interrupt function is disabled by default. To enable this function, refer to Table 30, page 24
(Page7 Register 19 Bit[13:11]).
8.3. Auto-Negotiation and Parallel Detection
The RTL8201F/FL/FN supports IEEE 802.3u clause 28 Auto-negotiation for operation with other
transceivers supporting auto-negotiation. The RTL8201F/FL/FN can auto-detect the link partner’s
abilities and determine the highest speed/duplex configuration possible between the two devices. If the
link partner does not support auto-negotiation, then the RTL8201F/FL/FN will enable half-duplex mode
and enter parallel detection mode. The RTL8201F/FL/FN will default to transmitting FLP (Fast Link
Pulse) and wait for the link partner to respond. If the RTL8201F/FL/FN receives a FLP, then the auto-
negotiation process will continue. If it receives an NLP (Normal Link Pulse), then the RTL8201F/FL/FN
will change to 10Mbps and half-duplex mode. If it receives a 100Mbps IDLE pattern, it will change to
100Mbps and half-duplex mode.
8.3.1. Setting the Medium Type and Interface Mode to MAC
Table 42. Setting the Medium Type and Interface Mode to MAC
FXEN
RXDV
Operation Mode
H
H
H
L
L
L
L
H
X
L
Fiber Mode and MII Mode
Fiber Mode and RMII Mode
Fiber Mode and MII Mode
UTP Mode and MII Mode
UTP Mode and RMII Mode
UTP Mode and MII Mode
H
X
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8.4. LED Functions
The RTL8201FN supports three LED signals, and the RTL8201F and RTL8201FL support two LED
signals, in four configurable operation modes. The following sections describe the various LED actions.
8.4.1. LED and PHY Address
As the PHYAD strap options share the LED output pins, the external combinations required for strapping
and LED usage must be considered in order to avoid contention. Specifically, when the LED outputs are
used to drive LEDs directly, the active state of each output driver is dependent on the logic level sampled
by the corresponding PHYAD input upon power-up/reset. For example, as Figure 8 (left-side) shows, if a
given PHYAD input is resistively pulled high then the corresponding output will be configured as an
active low driver. On the right side, we can see that if a given PHYAD input is resistively pulled low then
the corresponding output will be configured as an active high driver. The PHY address configuration pins
should not be connected to GND or VCC directly, but must be pulled high or low through a resistor (e.g.,
4.7KΩ). If no LED indications are needed, the components of the LED path (LED+510Ω) can be
removed.
PHY Address[:] = Logical 1
LED Indication = Active low
PHY Address[:] =
Logical 0
LED Indication
Active high
=
Figure 8. LED and PHY Address Configuration
8.4.2. Link Monitor
The Link Monitor senses link integrity, such as LINK10, LINK100, LINK10/ACT, or LINK100/ACT.
Whenever link status is established, the specific link LED pin is driven low. Once a cable is disconnected,
the link LED pin is driven high, indicating that no network connection exists.
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8.4.3. RX LED
In 10/100M mode, blinking of the RX LED indicates that receive activity is occurring.
Figure 9. RX LED
8.4.4. TX LED
In 10/100M mode, blinking of the TX LED indicates that transmit activity is occurring.
Figure 10. TX LED
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8.4.5. TX/RX LED
In 10/100M mode, blinking of the TX/RX LED indicates that both transmit and receive activity is
occurring.
Figure 11. TX/RX LED
8.4.6. LINK/ACT LED
In 10/100M mode, blinking of the LINK/ACT LED indicates that the RTL8201F/FL/FN is linked and
operating properly. When this LED is high for extended periods, it indicates that a link problem exists.
Figure 12. LINK/ACT LED
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8.4.7. Customized LED
The RTL8201F/FL/FN supports programmable LEDs in 10/100Mbps mode. This function can be
enabled/disabled via page7, reg19[3] register (Figure 13).
Refer to section 7.17, page 23 for customized LED register setting.
Figure 13. Customized LED with/without LPI LED Mode
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8.4.8. EEE LED Behavior
EEE Idle mode: LED continuous slow blinking.
EEE Active mode: LED fast and slow blinking (on packet transmission and reception).
Refer to Table 29, page 23 for EEE LED enable setting.
Figure 14. EEE LED Behavior
8.5. Power Down and Link Down Power Saving Modes
Two types of Power Saving mode operation are supported. This section describes how to implement each
mode through software.
Table 43. Power Saving Mode Pin Settings
Mode
Description
PWD
Setting bit 11 of register 0 to 1 puts the RTL8201F/FL/FN into Power Down Mode (PWD). This is the
maximum power saving mode while the RTL8201F/FL/FN is still ‘live’. In PWD mode, the
RTL8201F/FL/FN will turn off all analog/digital functions except the MDC/MDIO management
interface. Therefore, if the RTL8201F/FL/FN is put into PWD mode and the MAC wants to recall the
PHY, it must create the MDC/MDIO timing by itself (this is done by software).
LDPS
Setting bit 15 of register 24 to 1 will put the RTL8201F/FL/FN into LDPS (Link Down Power Saving)
mode. In LDPS mode, the RTL8201F/FL/FN will detect the link status to decide whether or not to turn
off the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted.
However, some signals similar to NLP will be transmitted. Once the receiver detects leveled signals, it
will stop the signal and transmit FLP or 100Mbps IDLE/10Mbps NLP again. This can cut power used by
60%~80% when the link is down.
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8.6. 10M/100M Transmit and Receive
8.6.1. 100Base-TX Transmit and Receive Operation
100Base-TX Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201F/FL/FN will have different scrambler seeds and so spread the
output of the MLT-3 signals.
100Base-TX Receive
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The Phase Locked Loop (PLL) then
recovers the timing information from the signals and from the receive clock. With this, the received signal
is sampled to form NRZI (Non-Return-to-Zero Inverted) data. The next steps are the NRZI to NRZ (Non-
Return-to-Zero) process, unscrambling of the data, serial to parallel and 5B to 4B conversion, and passing
of the 4B nibble to the MII interface.
8.6.2. 100Base-FX Fiber Transmit and Receive Operation
The RTL8201F/FL/FN can be configured to 100Base-FX mode via hardware configuration. The
hardware 100Base-FX setting takes priority over NWay settings. A scrambler is not required in
100Base-FX.
100Base-FX Transmit
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pair form.
100Base-FX Receive
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
8.6.3. 10Base-T Transmit and Receive Operation
10Base-T Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a band-limited filter embedded in the RTL8201F/FL/FN and then transmitted.
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10Base-T Receive
In 10Base-T receive mode, the Manchester decoder in the RTL8201F/FL/FN converts the Manchester
encoded data stream into NRZ data by decoding the data and stripping off the SOI pulse. The serial NRZ
data stream is then converted to a parallel 4-bit nibble signal (RXD[0:3]).
8.7. Reset and Transmit Bias
There are two RTL8201F/FL/FN reset types:
1. Hardware Reset: Pull the PHYRSTB pin high for at least 150ms to access the RTL8201F/FL/FN
registers. Pull the PHYRSTB pin low for at least 10ms and then pull high. All registers will return to
default values after a hardware reset. The media interface will disconnect and restart the auto-
negotiation/parallel detection process.
2. Software Reset: Set register 0 bit 15 to 1 for at least 20ms to access the RTL8201F/FL/FN registers. A
Software reset will only partially reset the registers, and will reset the chip status to ‘initializing’.
The RSET pin must be pulled low by a 2.49KΩ resistor with 1% accuracy to establish an accurate
transmit bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from
other clock traces and transmit/receive paths to avoid signal interference.
8.8. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201F/FL/FN is fabricated in a 0.11µm process. The core circuit needs to be powered by 1.1V,
however, the digital IO and DAC circuits need a 3.3V power supply. Regulators are embedded in the
RTL8201F/FL/FN to convert 3.3V to 1.1V.
Note: The internal linear regulator output voltage is 1.1V. A 1.05V is supplied when using external core
power. The external 1.05V power supply is not suggested for the RTL8201F/FL as the internal regulators
cannot be disabled (the RTL8201F/FL does not have an EN_LDO_OUT pin to disable the internal 1.1V
power supply), and the internal and external power sources may conflict.
As with many commercial voltage conversion devices, the 1.1V output pin of this circuit requires the use
of an output capacitor (0.1µF X5R low-ESR ceramic capacitor) as part of the device frequency
compensation.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
Note: The embedded 1.1V LDO is designed for PHYceiver device internal use only. Do not provide this
power to other devices.
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8.9. Automatic Polarity Correction
The RTL8201F/FL/FN automatically corrects polarity errors on the receive pairs in 10Base-T mode
(polarity is irrelevant in 100Base-TX mode). In 10Base-T mode, polarity errors are corrected based on the
detection of validly spaced link pulses. Detection begins during the MDI crossover detection phase and
locks when the 10Base-T link is up. The polarity becomes unlocked when the link goes down.
8.10. Far End Fault Indication
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled,
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method that is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201F/FL/FN detects this pattern
three times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem.
On the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201F/FL/FN will start
sending this pattern, which in turn causes the remote side to detect a Far End Fault. This means that the
receive path has a problem from the point of view of the RTL8201F/FL/FN. The FEFI mechanism is used
only in 100Base-FX mode.
8.11. Wake-On-LAN (WOL)
8.11.1. Magic Packet and Wake-Up Frame Format
The RTL8201F/FL/FN can monitor the network for a Wake-Up Frame or a Magic Packet, and notify the
system via the PMEB (Power Management Event; ‘B’ means low active) pin when such a packet or event
occurs. The system can then be restored to a normal state to process incoming jobs. The PMEB pin must
be connected with a 4.7k-ohm resistor and pulled up to 3.3V. When the Wake-Up Frame or a Magic
Packet is sent to the PHY, the PMEB pin will be set low to notify the system to wake up. Refer to the
WOL application note for details.
Magic Packet Wake-Up occurs only when the following conditions are met:
• The destination address of the received Magic Packet is acceptable to the RTL8201F/FL/FN, e.g., a
broadcast, multicast, or unicast packet addressed to the current RTL8201F/FL/FN.
• The received Magic Packet does not contain a CRC error.
• The Magic Packet pattern matches; i.e., 6 * FFh + MISC (can be none) + 16 * DID (Destination ID)
in any part of a valid Ethernet packet.
A Wake-Up Frame event occurs only when the following conditions are met:
• The destination address of the received Wake-Up Frame is acceptable to the RTL8201F/FL/FN, e.g., a
broadcast, multicast, or unicast address to the current RTL8201F/FL/FN.
• The received Wake-Up Frame does not contain a CRC error.
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• The 16-bit CRC of the received Wake-Up Frame matches the 16-bit CRC of the sample Wake-Up
Frame pattern given by the local machine’s OS. Or, the RTL8201F/FL/FN is configured to allow
direct packet wake up, e.g., a broadcast, multicast, or unicast network packet.
Note 1: 16-bit CRC: The RTL8201F/FL/FN supports eight long-Wake-Up frames (covering 128 mask
bytes from offset 0 to 127 of any incoming network packet). CRC16 polynomial=x16+x12+x5+1.
Note 2: Refer to the WOL Application Note for detailed Wake-On-LAN register settings and waveform
timings.
8.11.2. Active Low Wake-On-LAN
When the PHY receives a Wake-Up Frame or a Magic Packet from the link partner, the PMEB pin will
go low and the MAC will wake up after a T cycle. The PMEB pin will be reset to high via the system or
MAC (Figure 15 and Figure 16).
Refer to the WOL Application Note for details.
Figure 15. Active Low When Receiving a Magic Packet
Figure 16. Active Low When Receiving a Wake-Up Frame
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8.11.3. Pulse Low Wake-On-LAN
When the PHY receives a Wake-Up Frame or a Magic Packet from the link partner, the PMEB pin will
go low for a period (84ms, 168ms (default), 336ms, or 672ms; set through the MDC/MDIO), and will
wake up after a T cycle (Figure 17 and Figure 18).
Refer to the WOL Application Note for details.
WOL Enable
From Link Partner
PMEB
Magic Packet
T
Period controlled by the PHY
Figure 17. Pulse Low When Receiving a Magic Packet
WOL Enable
From Link Partner
PMEB
Wake Up Frame
T
Period controlled by the PHY
Figure 18. Pulse Low When Receiving a Wake-Up Frame
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8.11.4. Wake-On-LAN Pin Types (MII Mode)
Table 44. Wake-On-LAN Pin Types (MII Mode)
Name
Type
Normal
WOL Enable
100M
10M
Idle
TXC
TXEN
TXD[0:3]
RXC
O/PD
I/PD
25M CLK Output
2.5M CLK Output
2.5M CLK Output
O (2.5M/25M)/L/PD1
I/PD
I
I
I
I/PD
I
I
I
I/PD
O/PD
25M CLK Output
2.5M CLK Output
2.5M CLK Output
O (2.5M/25M)/PD2
O or PD2
O or PD2
O or PD2
O or PD2
O or PD2
O or PD2
I/PU
COL
LI/O/PD
LI/O/PD
LI/O/PD
O/PD
O
O
O
O
O
O
I
O
O
O
O
O
O
I
O
O
O
O
O
O
I
CRS
RXDV
RXD[0:2]
RXD[3]
RXER
MDC
LI/O/PD
LI/O/PD
I/PU
MDIO
IO/PU
IO
IO
IO
IO/PU
Note 1: If TX Isolate=1, the TXC is halted and the pin type is ‘L’.
Set page0, register0, and bit10=1 to change the TXC pin type to ‘PD’.
Note 2: If RX Isolate=1, all the MII RX interfaces are halted and the pin types are ‘PD’.
8.11.5. Wake-On-LAN Pin Types (RMII Mode)
Table 45. Wake-On-LAN Pin Types (RMII Mode)
Name
Type
Normal
10M
WOL Enable
100M
Idle
50M CLK
Input/Output
50M CLK
Input/Output
50M CLK
Input/Output
TXC (REF_CLK)1 IO/PD
I/O (50M)2
TXEN
TXD[0:1]
CRS_DV
RXD[0:1]
RXER
I/PD
I/PD
I
I
I
I
I
I
I/PD
I/PD
O or PD3
O or PD3
O or PD3
I/PU
LI/O/PD
O/PD
O
O
O
I
O
O
O
I
O
O
O
I
LI/O/PD
I/PU
MDC
MDIO
IO/PU
IO
IO
IO
IO/PU
Note 1: If TXC (REF_CLK) is in input mode (MAC to PHY), the REF_CLK cannot halt at WOL Enable.
Note 2: When REF_CLK is in output mode (PHY to MAC), the REF_CLK cannot halt (always toggles 50MHz out). To set
the TXC pin type to ‘PD’, set page0, register0, bit10=1.
Note 3: If RX Isolate=1, all RMII RX interfaces are halted and the pin types are ‘PD’.
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8.12. Energy Efficient Ethernet (EEE)
The RTL8201F/FL/FN supports IEEE 802.3az-2010, also known as Energy Efficient Ethernet (EEE), at
10Mbps and 100Mbps. It provides a protocol to coordinate transitions to/from a lower power
consumption level (Low Power Idle mode) based on link utilization. When no packets are being
transmitted, the system goes to Low Power Idle mode to save power. When packets need to be
transmitted, the system returns to normal mode, and does this without changing the link status and
without dropping/corrupting frames.
To save power, when the system is in Low Power Idle mode, most of the circuits are disabled; however,
the transition time to/from Low Power Idle mode is kept small enough to be transparent to upper layer
protocols and applications.
EEE also specifies a negotiation method to enable link partners to determine whether EEE is supported.
Refer to http://www.ieee802.org/3/az/index.html for more details.
Refer to the ‘RTL8201(F_FL_FN)_Ethernet_Transceiver_(R)MII_EEE_App_Note’ for EEE MII/RMII
power saving mode register settings.
8.13. Spread Spectrum Clock (SSC)
The RMII REF_CLK path can be a source of EMI noise. Spread Spectrum Clock (SSC) spreads the
REF_CLK signal across a wider bandwidth, reducing the peak radiated energy at any one frequency, and
lowering unwanted EMI noise.
The SSC function is enabled by default when using RMII REF_CLK output mode (see section 7.21 Page
7 Register 24 Spread Spectrum Clock Register, page 25).
Figure 19. Spectrum Spread Clock
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9. Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 46. Absolute Maximum Ratings
Symbol
Description
Minimum
-0.4
Maximum
+3.7
Unit
V
DVDD33, AVDD33
Supply Voltage 3.3V
DVDD10, DVDD10OUT, Supply Voltage 1.05V*
AVDD10OUT
-0.1
+1.26
V
DC Input
DC Output
N/A
Input Voltage
-0.3
-0.3
-55
Corresponding Supply Voltage +0.5V
Corresponding Supply Voltage +0.5V
+125
V
V
Output Voltage
Storage Temperature
°C
Note: The internal linear regulator output voltage is 1.1V.
9.1.2. Recommended Operating Conditions
Table 47. Recommended Operating Conditions
Description
Pins
Minimum
Typical
Maximum
Unit
V
Supply Voltage VDD
DVDD33, AVDD33
2.97
3.30
3.63
DVDD10, DVDD10OUT,
AVDD10OUT
V
1.00
1.05*
1.16
Ambient Operating Temperature TA
Maximum Junction Temperature
-
-
0
-
-
-
70
°C
°C
125
Note: The internal linear regulator output voltage is 1.1V.
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9.1.3. Power On and PHY Reset Sequence
The RTL8201F/FL/FN needs 150ms power on time. After 150ms it can access the PHY register from
MDC/MDIO.
Figure 20. Power On and PHY Reset Sequence
Table 48. Power On and PHY Reset Sequence
Symbol
Rt1
Description
Minimum
100µs
Maximum
3.3V Rise Time@ Power On Sequence
1.05V Rise Time@ Power On and PHY Reset Sequence
PHYRSTB De-Assert after PHY_3.3V Stable
-
-
-
Rt2
100µs
Rt3
80µs
Note: Rt2 requires 100µs Rise Time only when using an external 1.05V power supply.
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9.1.4. RMII Input Mode Power Dissipation
The whole system power dissipation (including regulator loss) is shown in Table 49.
Table 49. RMII Input Mode Power Dissipation (Whole System)
Symbol
P10IDLE
P10F
Condition
RTL8201F
36.3
RTL8201FN
36.3
RTL8201FL
36.3
Unit
mW
mW
mW
mW
mW
mW
mW
10Base-T Idle (EEE not Enabled)
10Base-T Full Duplex
108.9
148.5
56.1
118.8
108.9
155.1
62.7
P100IDLE
100Base-T Idle (EEE not Enabled)
151.8
56.1
P100IDLEEEE 100Base-T Idle with EEE
P100F
PLDPS
100Base-T Full Duplex
Link Down Power Saving
PHY Reset
174.9
20.328
3.3
178.2
17.985
3.3
178.2
23.1
PPHYRST
3.3
Note: Setting page 4 register 21 bit12 to ‘1’will reduce power consumption when the system is idle.
9.1.5. Input Voltage: Vcc
Table 50. Input Voltage: Vcc
Symbol Condition
Minimum
0.5*Vcc
-0.5V
Maximum
Vcc+0.5V
0.7V
TTL VIH Input High Voltage
TTL VIL Input Low Voltage
TTL VOH Output High Voltage
TTL VOL Output Low Voltage
-
-
IOH=-8mA
IOL=8mA
0.65*Vcc
-
Vcc
0.7V
TTL IOZ
IIN
Tri-State Leakage
Input Current
Vout=Vcc or GND
Vin=Vcc or GND
Vin=Vcc or GND
-110µA
-1µA
10µA
10µA
IPL
Input Current with Internal Weakly Pulled
Low Resistor
-1µA
100µA
IPH
Input Current with Internal Weakly Pulled
High Resistor
Vin=Vcc or GND
-110µA
10µA
PECL VIH PECL Input High Voltage
PECL VIL PECL Input Low Voltage
PECL VOH PECL Output High Voltage
PECL VOL PECL Output Low Voltage
-
-
-
-
Vdd-1.16V
Vdd-1.81V
Vdd-1.02V
-
Vdd-0.88V
Vdd-1.47V
-
Vdd-1.62V
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9.2. AC Characteristics
All output timing assumes equivalent loading between 10pF and 25pF that includes PCB layout traces
and other connected devices (e.g., MAC).
9.2.1. MII Transmission Cycle Timing
Figure 21. MII Interface Setup/Hold Time Definitions
Figure 22 and Figure 23 and show an example of a packet transfer from MAC to PHY on the MII
interface.
t
3
VI H(min)
VI L(max)
TXCLK
t
t
2
1
t
t
5
4
VIH(min)
VI L(max)
TXD[0:3]
TXEN
Figure 22. MII Transmission Cycle Timing-1
TXCLK
TXEN
TXD[0:3]
CRS
t
t
6
7
Figure 23. MII Transmission Cycle Timing-2
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 47
Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Table 51. MII Transmission Cycle Timing
Minimum Typical Maximum Unit
Symbol Description
t1
t2
t3
t4
t5
t6
t7
TXCLK High Pulse Width
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
14
140
14
140
-
20
26
260
26
260
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
TXCLK Low Pulse Width
TXCLK Period
20
200
40
-
400
-
TXEN, TXD[0:3]
Setup to TXCLK Rising Edge
10
5
-
-
-
-
-
-
-
-
-
-
TXEN, TXD[0:3]
Hold After TXCLK Rising Edge
0
-
0
-
TXEN Sampled to CRS High
TXEN Sampled to CRS Low
-
40
400
160
2000
-
-
-
9.2.2. MII Reception Cycle Timing
Figure 24 and Figure 25 show an example of a packet transfer from PHY to MAC on the MII interface.
t
3
V
V
RXCLK
I H(min)
I L(max)
t
t
2
t
t
5
4
1
RXD[0:3]
RXDV
V
V
I H(min)
I L(max)
RXER
Figure 24. MII Reception Cycle Timing-1
RXCLK
RXDV
t9
t8
RXD[0:3]
t6
t7
CRS
TPRX+-
Figure 25. MII Reception Cycle Timing-2
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX 48
Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Table 52. MII Reception Cycle Timing
Minimum Typical Maximum Unit
Symbol Description
RXCLK High Pulse Width
t1
t2
t3
t4
t5
t6
t7
t8
t9
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
14
140
14
140
-
20
26
260
26
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
200
RXCLK Low Pulse Width
RXCLK Period
20
200
260
-
40
-
400
-
RXER, RXDV, RXD[0:3]
10
10
10
10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Setup to RXCLK Rising Edge
-
RXER, RXDV, RXD[0:3]
-
Hold After RXCLK Rising Edge
-
Receive Frame to CRS High
130
2000
240
1000
150
3200
120
1000
-
End of Receive Frame to CRS Low
Receive Frame to Sampled Edge of RXDV
-
-
-
-
End of Receive Frame to Sampled Edge of RXDV 100Mbps
10Mbps
-
-
9.2.3. RMII Transmission and Reception Cycle Timing
MAC to PHY
Setup/Hold Time
RMII TX
RTL8201F-VB/
RTL8201FL-VB/
RTL8201FN-VB
REFCLK
MAC
RMII RX
PHY to MAC
Output Delay Time
Figure 26. RMII Interface Setup, Hold Time, and Output Delay Time Definitions
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
Figure 27. RMII Transmission and Reception Cycle Timing
Table 53. RMII Transmission and Reception Cycle Timing
Symbol
Description
Minimum Typical Maximum Unit
REFCLK Frequency
REFCLK Duty Cycle
T_ipsu_tx_rmii
T_iphd_tx_rmii
T_ophd_rx_rmii
Frequency of Reference Clock
Duty Cycle of Reference Clock
TXD[1:0]/TXEN Setup Time to REFCLK
TXD[1:0]/TXEN Hold Time from REFCLK
-
35
4
50
-
-
65
-
MHz
%
-
ns
2
-
-
ns
RXD[1:0]/CRS_DV/RXER Output Delay Time
from REFCLK
2
-
-
ns
Note 1: RMII TX timing can be adjusted by setting page7, register16[11:8]; the minimum adjustable resolution is 2ns.
Any changes for these bits are not recommended as the default value is the optimum setting.
Note 2: RMII RX timing can be adjusted by setting page7, register16[7:4]; the minimum adjustable resolution is 2ns. Any
changes for these bits are not recommended as the default value is the optimum setting.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
9.2.4. MDC/MDIO Timing
Figure 28. MDC/MDIO Interface Setup, Hold Time, and Valid from MDC Rising Edge Time Definitions
Figure 29. MDC/MDIO Timing
Table 54. MDC/MDIO Timing
Symbol Description
Minimum
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
MDC High Pulse Width
160
160
400
10
-
MDC Low Pulse Width
-
ns
MDC Period
-
-
ns
MDIO Setup to MDC Rising Edge
MDIO Hold Time from MDC Rising Edge
MDIO Valid from MDC Rising Edge
ns
10
-
ns
0
300
ns
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
9.2.5. Transmission without Collision
Figure 30 shows an example of a packet transfer from MAC to PHY.
Figure 30. MAC to PHY Transmission without Collision
9.2.6. Reception without Error
Figure 31 shows an example of a packet transfer from PHY to MAC.
Figure 31. PHY to MAC Reception Without Error
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
9.3. Crystal Characteristics
Table 55. Crystal Characteristics
Symbol
Description/Condition Minimum
Typical
Maximum
Unit
Fref
Parallel Resonant Crystal Reference Frequency,
Fundamental Mode, AT-Cut Type.
-
25
-
MHz
Fref Stability
Parallel Resonant Crystal Frequency Stability,
Fundamental Mode, AT-Cut Type. Ta=0°C~70°C.
Parallel Resonant Crystal Frequency Tolerance,
-30
-50
-
-
+30
+50
ppm
ppm
Fref Tolerance
Fundamental Mode, AT-Cut Type. Ta=25°C.
Fref Duty Cycle
Reference Clock Input Duty Cycle.
Equivalent Series Resistance.
Drive Level.
40
-
-
-
-
-
60
30
%
Ω
ESR
DL
-
0.3
500
mW
ps
Jitter
Broadband Peak-to-Peak Jitter1, 2
-
Note 1: 25KHz to 25MHz RMS < 3ps.
Note 2: Broadband RMS < 9ps.
9.4. Oscillator Requirements
Table 56. Oscillator Requirements
Parameter
Condition
Minimum
Typical
Maximum
Unit
Frequency
-
-
-30
-50
40
-
25/50
-
30
MHz
ppm
ppm
%
Frequency Stability
Ta = 0°C~+70°C
-
-
Frequency Tolerance
Duty Cycle
Broadband Peak-to-Peak Jitter1, 2
Vpeak-to-peak
Ta = 25°C
50
-
-
-
-
-
-
-
60
-
500
3.45
10
ps
3.15
-
3.3
-
V
Rise Time (10%~90%)
Fall Time (10%~90%)
Operating Temperature Range
Note 1: 25KHz to 25MHz RMS < 3ps.
Note 2: Broadband RMS < 9ps.
ns
-
-
10
ns
0
-
70
°C
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
9.5. Clock Requirements
Table 57. Clock Requirements
Parameter
Minimum
Typical
Maximum
Unit
MHz
ppm
ppm
%
Frequency
-
-30
-50
40
-
25/50
-
Frequency Stability
Frequency Tolerance
Duty Cycle
Broadband Peak-to-Peak Jitter1, 2
Vpeak-to-peak
-
-
30
50
-
60
-
500
3.45
10
ps
3.15
-
3.3
-
V
Rise Time (10%~90%)
Fall Time (10%~90%)
Note 1: 25KHz to 25MHz RMS < 3ps.
Note 2: Broadband RMS < 9ps.
ns
-
-
10
ns
9.6. Transformer Characteristics
Table 58. Transformer Characteristics
Parameter
Turn Ratio
Transmit End
1:1 CT
Receive End
1:1 CT
Inductance (min.)
350µH @ 8mA
350µH @ 8mA
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
10. Mechanical Dimensions
10.1. RTL8201F (QFN-32)
Symbol
Dimension in mm
Dimension in inch
Min
0.75
0.00
Nom
0.85
Max
1.00
0.05
Min
0.030
0.000
Nom
0.034
Max
0.039
0.002
A
A1
A3
b
0.02
0.001
0.20REF
0.25
0.008REF
0.010
0.18
-
0.30
0.6
0.007
-
0.012
0.024
c
-
-
D/E
D2/E2
e
5.00BSC
3.35
0.197BSC
0.132
3.10
0.30
3.60
0.50
0.122
0.012
0.142
0.020
0.50BSC
0.40
0.020BSC
0.016
L
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
10.2. RTL8201FL (LQFP-48)
Symbol
Dimension in mm
Nom
Dimension in inch
Min
-
Max
1.60
0.15
1.45
0.27
Min
-
Nom
Max
0.063
0.006
0.057
0.011
A
A1
A2
b
-
-
0.05
1.35
0.17
-
0.002
0.053
0.007
-
1.40
0.055
0.22
0.009
D/E
D1/E1
e
9.00BSC
7.00BSC
0.50BSC
0.60
0.354BSC
0.276BSC
0.020BSC
0.024
L
0.45
0.75
0.018
0.030
L1
1.00REF
0.039REF
Note 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MS-026.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
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Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
10.3. RTL8201FN (QFN-48)
Symbol
Dimension in mm
Nom
Dimension in inch
Min
0.75
0.00
Max
1.00
0.05
Min
0.030
0.000
Nom
0.034
Max
0.039
0.002
A
A1
A3
b
0.85
0.02
0.001
0.20REF
0.20
0.008REF
0.008
0.15
4.05
0.30
0.25
4.65
0.50
0.006
0.163
0.012
0.010
0.183
0.020
D/E
D2/E2
e
6.00BSC
4.4
0.236BSC
0.173
0.40BSC
0.40
0.016BSC
0.016
L
Notes 1: CONTROLLING DIMENSION: MILLIMETER (mm).
Note 2: REFERENCE DOCUMENT: JEDEC MO-220.
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
57
Track ID: JATR-2265-11 Rev. 1.4
RTL8201F/RTL8201FL/RTL8201FN
Datasheet
11. Ordering Information
Table 59. Ordering Information
Part Number
Package
Status
RTL8201F-VB-CG
32-Pin QFN ‘Green’ Package (for details see Table 60 below)
RTL8201FL-VB-CG 48-Pin LQFP ‘Green’ Package (for details see Table 60 below)
RTL8201FN-VB-CG 48-Pin QFN ‘Green’ Package (for details see Table 60 below)
Note: See page 5, 6, and 7 for package identification.
11.1. RTL8201F Series Selection Guide
Table 60. RTL8201F Series Selection Guide
REF_CLK
Direction
H/W Strap
WOL
(PMEB Pin)
Number
of LEDs
Co-Layout
Solution
Part Number
Interface Package
EEE INTB
RMII
QFN32
MII
RTL8201F-VB-CG
RTL8201FL-VB-CG
Yes
Yes
Yes
Yes
Yes
Yes
Yes*
Yes
2
2
RTL8201E-VC
RMII
LQFP48
MII
RTL8201EL
RTL8201EL-VC
RTL8211D-VB
RTL8211E-VB
RTL8201EN-VC
RMII
QFN48
MII
RTL8201FN-VB-CG
Yes
Yes
Yes
Yes
3
Note: The RTL8201F INTB pin is used for the interrupt function only when in the RMII mode.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-578-0211 Fax: 886-3-577-6047
www.realtek.com
Single-Chip/Port 10/100M Ethernet PHYceiver with Auto MDIX
58
Track ID: JATR-2265-11 Rev. 1.4
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