RTL8201N [REALTEK]
SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX;
| 型号： | RTL8201N |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX 局域网（LAN）标准 以太网：16GBASE-T |
| 文件： | 总46页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8201N-GR
RTL8201R-GR
SINGLE-CHIP/PORT
10/100 FAST ETHERNET PHYCEIVER WITH
AUTO MDIX
DATASHEET
Rev. 1.3
17 September 2007
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8201N &RTL8201R
Datasheet
COPYRIGHT
©2007 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
REVISION HISTORY
Revision
1.0
Release Date
Summary
2006/06/29
2006/08/22
First release.
1.1
Revised pin names:
PWFBOUT18 => PWOUT18
PWFBOUT15 => PWOUT15.
Revised RTL8201N-GR (64-Pin QFN) Pin Assignments:
DVDD33 (pin 18, 34, 49) => NC
DVDD15 (pin 32, 45, 59) => NC (see Table 9 and Table 10).
Revised Table 32, Power Dissipation, page 27.
1.2
1.3
2007/02/12
2007/09/17
Revised COL/CONFIG[6] description, Table 2, MII Interface, page 6.
Added section 6.3 RMII Interface, page 7.
Revised Table 32, Power Dissipation, page 27.
Added section 9.2.3 RMII Transmission Cycle Timing, page 31.
Added RTL8201R data.
Revised Figure 1, page 3 (Added RMII Interface).
Revised Table 3 RMII Interface, page 7 (REFCLK description).
Revised Table 5 Clock Interface, page 8 (exchanged the pin numbers of
CKXTAL1 and CKXTAL2.
Revised Table 28 Auto-Negotiation Mode Pin Settings, page 22 (modified
MII/SNI description).
Modified section 9.2.3 and section 9.2.4 RMII Transmission/Reception Cycle
Timing, page 31.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
Table of Contents
1.
2.
3.
4.
5.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................2
APPLICATIONS................................................................................................................................................................2
BLOCK DIAGRAM...........................................................................................................................................................3
PIN ASSIGNMENTS .........................................................................................................................................................4
5.1.
RTL8201N-GR (64-PIN QFN) ....................................................................................................................................4
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................4
RTL8201R-GR (32-PIN QFN).....................................................................................................................................5
GREEN PACKAGE AND VERSION IDENTIFICATION ........................................................................................................5
5.2.
5.3.
5.4.
6.
PIN DESCRIPTIONS.........................................................................................................................................................6
6.1.
MANAGEMENT INTERFACE ..........................................................................................................................................6
MII INTERFACE (RTL8201N ONLY)............................................................................................................................6
RMII INTERFACE .........................................................................................................................................................7
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY. (RTL8201N ONLY) ..................................................................8
CLOCK INTERFACE.......................................................................................................................................................8
10MBPS/100MBPS NETWORK INTERFACE ...................................................................................................................8
DEVICE CONFIGURATION INTERFACE (RTL8201N ONLY)...........................................................................................9
LED INTERFACE ........................................................................................................................................................10
POWER PINS...............................................................................................................................................................10
RESET AND OTHER PINS.............................................................................................................................................10
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
6.10.
7.
REGISTER DESCRIPTIONS.........................................................................................................................................11
7.1.
REGISTER 0 BASIC MODE CONTROL REGISTER..........................................................................................................11
REGISTER 1 BASIC MODE STATUS REGISTER.............................................................................................................12
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................13
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................13
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ...................................................................13
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)....................................................14
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ............................................................................15
REGISTER 16 NWAY SETUP REGISTER (NSR)............................................................................................................15
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR).................................................15
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................16
REGISTER 19 SNR DISPLAY REGISTER ......................................................................................................................16
REGISTER 25 TEST REGISTER.....................................................................................................................................16
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
8.
FUNCTIONAL DESCRIPTION.....................................................................................................................................17
8.1.
MII/RMII MODES......................................................................................................................................................17
8.1.1. MII Data Transition (RTL8201N Only)................................................................................................................17
8.1.2. RMII Data Transition...........................................................................................................................................18
8.2.
SERIAL MANAGEMENT INTERFACE ............................................................................................................................19
8.2.1. RTL8201N ............................................................................................................................................................19
8.2.2. RTL8201R.............................................................................................................................................................20
8.3.
AUTO-NEGOTIATION AND PARALLEL DETECTION .....................................................................................................20
8.3.1. Setting the Medium Type and Interface Mode to MAC (RTL8201N Only)...........................................................20
8.3.2. UTP Mode and MII Interface (RTL8201N Only) .................................................................................................21
8.3.3. UTP Mode and SNI Interface (RTL8201N Only) .................................................................................................21
8.3.4. Fiber Mode and MII Interface (RTL8201N Only)................................................................................................21
8.4.
8.5.
FLOW CONTROL SUPPORT..........................................................................................................................................22
HARDWARE CONFIGURATION AND AUTO-NEGOTIATION (RTL8201N ONLY)...........................................................22
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
8.6.
8.7.
8.8.
SERIAL NETWORK INTERFACE (RTL8201N ONLY) ...................................................................................................23
POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES.....................................................................23
MEDIA INTERFACE.....................................................................................................................................................24
8.8.1. 100Base-TX Transmit & Receive Operation ........................................................................................................24
8.8.2. 100Base-FX Fiber Transmit & Receive Operation (RTL8201N Only) ................................................................25
8.8.3. 10Base-T Transmit & Receive Operation.............................................................................................................25
8.9.
REPEATER MODE OPERATION....................................................................................................................................26
RESET AND TRANSMIT BIAS.......................................................................................................................................26
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT......................................................................................26
FAR END FAULT INDICATION.....................................................................................................................................26
8.10.
8.11.
8.12.
9.
CHARACTERISTICS......................................................................................................................................................27
9.1.
DC CHARACTERISTICS...............................................................................................................................................27
9.1.1. Absolute Maximum Ratings..................................................................................................................................27
9.1.2. Operating Conditions...........................................................................................................................................27
9.1.3. Power Dissipation ................................................................................................................................................27
9.1.4. Input Voltage: Vcc................................................................................................................................................28
9.2.
AC CHARACTERISTICS...............................................................................................................................................29
9.2.1. MII Transmission Cycle Timing (RTL8201N Only) .............................................................................................29
9.2.2. MII Reception Cycle Timing (RTL8201N Only)...................................................................................................30
9.2.3. RMII Transmission Cycle Timing.........................................................................................................................31
9.2.4. RMII Reception Cycle Timing ..............................................................................................................................31
9.2.5. SNI Transmission Cycle Timing (RTL8201N Only) .............................................................................................32
9.2.6. SNI Reception Cycle Timing (RTL8201N Only)...................................................................................................33
9.2.7. MDC/MDIO Timing .............................................................................................................................................34
9.2.8. Transmission without Collision............................................................................................................................34
9.2.9. Reception without Error.......................................................................................................................................35
9.3.
9.4.
CRYSTAL CHARACTERISTICS .....................................................................................................................................35
TRANSFORMER CHARACTERISTICS ............................................................................................................................35
10.
MECHANICAL DIMENSIONS.................................................................................................................................36
10.1.
10.2.
RTL8201N 64-PIN QFN MECHANICAL DIMENSIONS ................................................................................................36
RTL8201R 32-PIN QFN MECHANICAL DIMENSIONS.................................................................................................37
11.
ORDERING INFORMATION...................................................................................................................................39
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
List of Tables
TABLE 1. MANAGEMENT INTERFACE.............................................................................................................................................6
TABLE 2. MII INTERFACE (RTL8201N ONLY) ..............................................................................................................................6
TABLE 3. RMII INTERFACE ...........................................................................................................................................................7
TABLE 4. SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY. (RTL8201N ONLY).....................................................................8
TABLE 5. CLOCK INTERFACE.........................................................................................................................................................8
TABLE 6. 10MBPS/100MBPS NETWORK INTERFACE......................................................................................................................8
TABLE 7. DEVICE CONFIGURATION INTERFACE (RTL8201N ONLY).............................................................................................9
TABLE 8. LED INTERFACE/PHY ADDRESS CONFIGURATION ......................................................................................................10
TABLE 9. POWER PINS .................................................................................................................................................................10
TABLE 10. RESET AND OTHER PINS ..............................................................................................................................................10
TABLE 11. REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................11
TABLE 12. REGISTER 1 BASIC MODE STATUS REGISTER...............................................................................................................12
TABLE 13. REGISTER 2 PHY IDENTIFIER REGISTER 1 ...................................................................................................................13
TABLE 14. REGISTER 3 PHY IDENTIFIER REGISTER 2 ...................................................................................................................13
TABLE 15. REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR).....................................................................13
TABLE 16. REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................14
TABLE 17. REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) ..............................................................................15
TABLE 18. REGISTER 16 NWAY SETUP REGISTER (NSR) .............................................................................................................15
TABLE 19. REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR)...................................................15
TABLE 20. REGISTER 18 RX_ER COUNTER (REC).......................................................................................................................16
TABLE 21. REGISTER 19 SNR DISPLAY REGISTER ........................................................................................................................16
TABLE 22. REGISTER 25 TEST REGISTER.......................................................................................................................................16
TABLE 23. SERIAL MANAGEMENT ................................................................................................................................................19
TABLE 24. SETTING THE MEDIUM TYPE AND INTERFACE MODE TO MAC (RTL8201N ONLY)....................................................20
TABLE 25. UTP MODE AND MII INTERFACE (RTL8201N ONLY).................................................................................................21
TABLE 26. UTP MODE AND SNI INTERFACE (RTL8201N ONLY).................................................................................................21
TABLE 27. FIBER MODE AND MII INTERFACE (RTL8201N ONLY)...............................................................................................21
TABLE 28. AUTO-NEGOTIATION MODE PIN SETTINGS ..................................................................................................................22
TABLE 29. POWER SAVING MODE PIN SETTINGS ..........................................................................................................................23
TABLE 30. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................27
TABLE 31. OPERATING CONDITIONS .............................................................................................................................................27
TABLE 32. POWER DISSIPATION....................................................................................................................................................27
TABLE 33. INPUT VOLTAGE: VCC .................................................................................................................................................28
TABLE 34. MII TRANSMISSION CYCLE TIMING (RTL8201N ONLY).............................................................................................29
TABLE 35. MII RECEPTION CYCLE TIMING (RTL8201N ONLY)...................................................................................................30
TABLE 36. RMII TRANSMISSION CYCLE TIMING ..........................................................................................................................31
TABLE 37. RMII TRANSMISSION CYCLE TIMING ..........................................................................................................................31
TABLE 38. SNI TRANSMISSION CYCLE TIMING (RTL8201N ONLY).............................................................................................32
TABLE 39. SNI RECEPTION CYCLE TIMING (RTL8201N ONLY)...................................................................................................33
TABLE 40. MDC/MDIO TIMING...................................................................................................................................................34
TABLE 41. CRYSTAL CHARACTERISTICS .......................................................................................................................................35
TABLE 42. TRANSFORMER CHARACTERISTICS ..............................................................................................................................35
TABLE 43. ORDERING INFORMATION ............................................................................................................................................39
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
vi
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
List of Figures
FIGURE 1. BLOCK DIAGRAM..........................................................................................................................................................3
FIGURE 2. RTL8201N-GR (64-PIN QFN) PIN ASSIGNMENTS .......................................................................................................4
FIGURE 3. RTL8201R-GR (32-PIN QFN) PIN ASSIGNMENTS........................................................................................................5
FIGURE 4. READ CYCLE...............................................................................................................................................................19
FIGURE 5. WRITE CYCLE .............................................................................................................................................................19
FIGURE 6. MII TRANSMISSION CYCLE TIMING-1.........................................................................................................................29
FIGURE 7. MII TRANSMISSION CYCLE TIMING-2.........................................................................................................................29
FIGURE 8. MII RECEPTION CYCLE TIMING-1...............................................................................................................................30
FIGURE 9. MII RECEPTION CYCLE TIMING-2...............................................................................................................................30
FIGURE 10. RMII TRANSMISSION CYCLE TIMING .........................................................................................................................31
FIGURE 11. RMII RECEPTION CYCLE TIMING ...............................................................................................................................31
FIGURE 12. SNI TRANSMISSION CYCLE TIMING-1 ........................................................................................................................32
FIGURE 13. SNI TRANSMISSION CYCLE TIMING-2 ........................................................................................................................32
FIGURE 14. SNI RECEPTION CYCLE TIMING-1 ..............................................................................................................................33
FIGURE 15. SNI RECEPTION CYCLE TIMING-2 ..............................................................................................................................33
FIGURE 16. MDC/MDIO TIMING..................................................................................................................................................34
FIGURE 17. MAC TO PHY TRANSMISSION WITHOUT COLLISION ..................................................................................................34
FIGURE 18. PHY TO MAC RECEPTION WITHOUT ERROR ..............................................................................................................35
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
vii
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
1. General Description
The RTL8201N (64-Pin QFN) is a single-chip/single-port PHYceiver that supports:
• MII (Media Independent Interface)
• RMII (Reduced Media Independent Interface)
• SNI (Serial Network Interface)
The RTL8201R (32-Pin QFN) is a single-chip/single-port PHYceiver that supports RMII mode only.
The chips implement all 10/100M Ethernet Physical-layer functions including the Physical Coding
Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium Dependent
Sublayer (TP-PMD), with an auto MDIX function, 10Base-Tx Encoder/Decoder, and Twisted-Pair Media
Access Unit (TPMAU).
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides
excellent performance under all operating conditions.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
1
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
2. Features
The Realtek RTL8201N & RTL8201R are Fast Ethernet PHYceivers with selectable MII, RMII, or SNI
interfaces to the MAC chip. They provide the following features:
RTL8201N-GR supports MII, RMII, and
Supports repeater mode
7-wire SNI
Adaptive Equalization
RTL8201R-GR supports RMII mode only
Network status LEDs
Supports 50MHz output for RMII mode
Flow control support
(RTL8201R only)
25MHz crystal/oscillator as clock source
IEEE 802.3/802.3u compliant
10/100Mbps operation
Full/half duplex operation
Twisted pair or fiber mode output
Auto-Negotiation
Supports IEEE 802.3u clause 28; 1.5V
operation with 3.3V IO signal tolerance
Low power supply, 1.5V, 1.8V, and 3.3V;
1.5V/1.8V is generated by an internal
regulator
Supports power down mode
Supports operation under Link Down Power
Saving mode
0.15µm CMOS process
Supports Base Line Wander (BLW)
64-pin (RTL8201N) or 32-pin (RTL8201R)
compensation
QFN packages
Supports auto MDIX
3. Applications
Network Interface Adapter
MAU (Media Access Unit)
CNR (Communication and Network Riser)
ACR (Advanced Communication Riser)
Ethernet hub
Ethernet switch
In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical
connection or Fiber PECL interface to an external 100Base-FX optical transceiver module.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
4. Block Diagram
100 M
Data
Alignment
RXD
5B
4B
Descrambler
Decoder
RXC 25M
MII
Interface
10/100
Half/Full
RMII
Interface
Switch
Logic
TXD
4B
5B
Scrambler
SNI
25M
Encoder
TXC
Interface
10/100M Auto-negotiation
Control Logic
Link Pulse
10M
TXC10
TXD10
Manchester Coded
Waveform
10M Output Waveform
Shaping
RXC10
RXD10
Data Recovery
Receive Low Pass Filter
TD+
25M
TXC
TXO+
Parrallel
to Serial
3 Level
Driver
TXO-
TXD
Variable
Current
Baseline
Wander
Correction
Peak
Detect
RXIN+
RXIN-
3 Level
MLT-3
to NRZI
Adaptive
Equalizer
Comparator
25M
RXC
ck
Master
PPL
Serial to
Parrallel
Slave
PLL
RXD
data
Control
Voltage
25M
Figure 1. Block Diagram
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
5. Pin Assignments
5.1. RTL8201N-GR (64-Pin QFN)
NC
32
NC
LED_LI NK10
DUPLEX
49
50
51
52
MDIO
31
MDC
30
29
28
27
26
I SOL ATE
CONFI G[ 4]
CONFI G[ 3]
DV DD33
TXEN
TXD[3]
TXD[2]
53
54
55
56
57
58
TXD[1]
TXD[0]
TXC
RTL8201N
CONFI G[ 2]
CONFI G[ 1]
25
24
23
22
21
DVDD 33
CONFI G[ 0]
NC
59
60
61
62
63
64
RXC
A V DD33
C K XT AL2
C K XT AL1
NC
RXD[3]
RXD[2]
LLLLLLL TXXXV
20
19
18
17
RXD[1]
NC
P WOUT15
RXD[0]
Figure 2. RTL8201N-GR (64-Pin QFN) Pin Assignments
5.2. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
5.3. RTL8201R-GR (32-Pin QFN)
Note: The RTL8201R-GR (32-Pin QFN) supports RMII mode only.
Figure 3. RTL8201R-GR (32-Pin QFN) Pin Assignments
5.4. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 3.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
6. Pin Descriptions
LI: Latched Input during Power up or Reset
IO: Bi-directional input and output
O: Output
P: Power
I: Input
6.1. Management Interface
Table 1. Management Interface
Pin No. Description
(32-pin)
Name
Type
Pin No.
(64-pin)
30
MDC
I
17
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be
asynchronous to the transmit TXC and receive RXC clocks. The clock
rate can be up to 2.5MHz. Use an internal weak pull high resistor to
prevent the bus floating.
MDIO
IO
31
18
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
6.2. MII Interface (RTL8201N Only)
Table 2. MII Interface (RTL8201N Only)
Name
Type
Pin No.
(64-pin)
24
Description
TXC
O
Transmit Clock.
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
TXEN
TXD[3:0]
RXC
I
I
29
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0]. An
internal weak pull low resistor to prevent the bus floating.
28, 27, 26, 25 Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is asserted.
An internal weak pull high resistor prevents the bus floating.
O
22
46
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3] signals.
RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
COL/
LI/O
Collision Detect.
CONFIG[6]
COL is asserted high when a collision is detected on the media.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: MII mode
1: SNI mode
This pin can be directly connected to GND or VCC.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
Name
Type
Pin No.
(64-pin)
47
Description
CRS/
LI/O
Carrier Sense.
CONFIG[5]
This pin’s signal is asserted high if the media is not in Idle state.
During power on reset, this pin set high to put the RTL8201N into repeater mode.
This pin can be directly connected to GND or VCC.
RXDV/
RMII
LI/O
16
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on the
rising edge of the RXC.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: MII mode (RTL8201N Only)
This pin can be directly connected to GND or VCC.
21, 20, 19, 17 Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
1: RMII mode
RXD[3:0]
O
driven synchronously to the RXC for reception by the external physical unit
(PHY).
RXER/
LI/O
35
Receive Error.
CONFIG[8]
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid symbol,
this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is
possible to use an external 5.1KΩ pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
6.3. RMII Interface
Table 3. RMII Interface
Pin No. Description
(32-pin)
Name
Type
Pin No.
(64-pin)
16
RXDV
RXD[1:0]
TXEN
O
O
I
9
11, 10
15
Receive Data Valid
19, 17
29
Receive Data
Transmit Enable
TXD[1:0]
RXER
I
26, 25
35
14, 13
19
Transmit Data
O
I
Receive Error
REFCLK
REFCLK
CLK_CTL
24
12
Synchronous clock reference for receive, transmit, and control interface
50MHz reference clock generated from internal PLL.
O
LI
NULL
NULL
12
16
REFCLK Control
This pin is latched to input during a power on or reset condition. It
determines the REFCLK pin type.
1: REFCLK pin is input type
0: REFCLK pin is output type
This pin can be directly connected to GND or VCC.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
7
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
6.4. SNI (Serial Network Interface) 10Mbps Only. (RTL8201N
Only)
Table 4. SNI (Serial Network Interface) 10Mbps Only. (RTL8201N Only)
Name
Type
Pin No.
(64-pin)
46
Description
COL
RXD0
CRS
O
O
O
O
Collision Detect.
17
Received Serial Data.
Carrier Sense.
47
RXC
22
Receive Clock.
Resolved from received data.
Transmit Serial Data.
Transmit Clock.
TXD0
TXC
I
25
24
O
Generated by PHY.
Transmit Enable.
TXEN
I
29
For MAC to indicate transmit operation.
6.5. Clock Interface
Table 5. Clock Interface
Pin No. Description
(32-pin)
Name
Type
Pin No.
(64-pin)
61
CKXTAL2
O
30
25MHz Crystal Output.
This pin provides the 25MHz crystal output. It must be left open when
an external 25MHz oscillator drives X1.
CKXTAL1
I
62
31
25MHz Crystal Input.
This pin provides the 25MHz crystal input. If a 25MHz oscillator is
used, connect CKXTAL1 to the oscillator’s output (see 9.3 Crystal
Characteristics, page 35, for clock source specifications).
6.6. 10Mbps/100Mbps Network Interface
Table 6. 10Mbps/100Mbps Network Interface
Name
Type
Pin No.
(64-pin)
Pin No. Description
(32-pin)
MDI+[0]
MDI-[0]
O
O
3
4
3
4
Transmit Output.
Differential transmit output pair shared by 100Base-TX, 100Base-FX,
and 10Base-T modes. When configured as 100Base-TX, output is an
MLT-3 encoded waveform. When configured as 100Base-FX, the
output is pseudo-ECL level.
RSET
I
1
1
Transmit Bias Resistor Connection.
This pin should be pulled to GND by a 2KΩ (1%) resistor to define
driving current for the transmit DAC. The resistance value may be
changed, depending on experimental results of the
RTL8201N/RTL8201R.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
Name
Type
Pin No.
(64-pin)
Pin No. Description
(32-pin)
MDI+[1]
MDI-[1]
I
I
6
7
6
7
Receive Input.
Differential receive input pair shared by 100Base-TX, 100Base-FX, and
10Base-T modes.
6.7. Device Configuration Interface (RTL8201N Only)
Table 7. Device Configuration Interface (RTL8201N Only)
Name
Type
Pin No.
(64-pin)
Description
CONFIG[4:0]
I
53, 54, 56, PHY Address.
57, 58
Set the PHY address for the device.
CONFIG[5] LI/O
CONFIG[6] LI/O
47
Repeater mode.
Set high to put the RTL8201N into repeater mode. This pin can be directly
connected to GND or VCC.
46
37
35
MII/SNI interface.
This pin is latched to input during a power on or reset condition. Pull high to set
the RTL8201N into SNI mode operation. Set low for MII mode. This pin can be
directly connected to GND or VCC.
CONFIG[7]
LI
Auto-negotiation mode.
This pin is latched to input during a power on or reset condition. Set high to enable
Auto-negotiation mode, set low to force mode. This pin can be directly connected
to GND or VCC.
CONFIG[8] LI/O
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is
possible to use an external 5.1KΩ pull high resistor to enable fiber mode.
CONFIG[9]
ISOLATE
LI
I
33
52
Speed Mode.
This pin is latched to input during a power on or reset condition. Set high to put
the RTL8201N into 100Mbps operation. This pin can be directly connected to
GND or VCC.
Set high to isolate the RTL8201N from the MAC. This will also isolate the
MDC/MDIO management interface. In this mode, the power consumption is
minimal. This pin can be directly connected to GND or VCC.
DUPLEX
LDPS
LI
I
51
44
This pin is latched to input during a power on or reset condition. Set high to enable
full duplex. This pin can be directly connected to GND or VCC.
Set high to put the RTL8201N into LDPS mode. This pin can be directly
connected to GND or VCC (see 8.7 Power Down, Link Down, Power Saving, and
Isolation Modes, page 23, for more information).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
6.8. LED Interface
Table 8. LED Interface/PHY Address Configuration
Name
Type Pin No. Pin No. Description
(64-pin) (32-pin)
LED_LINK10
LED_LINK100
LED_DUPLEX
LED_RX
O
O
O
O
O
I
50
48
43
40
39
25
24
10Mbps link indicator.
100Mbps link indicator.
NULL Duplex LED.
23
22
Receive LED.
Transmit LED.
LED_TX
CONFIG[4:0]/
CONFIG[1:0]
53, 54,
56, 57, 58
27, 28 PHY Address.
Set the PHY address for the device.
6.9. Power Pins
Table 9. Power Pins
Name
Type Pin No. Pin No. Description
(64-pin) (32-pin)
AVDD33
DVDD33
P
60
29
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well decoupled.
3.3V Digital Power Input.
P
23, 42, 55
26
3.3V power supply for digital circuit.
Analog Power. 1.8V.
AVDD18
DVDD15
P
P
5, 10
36
5, 8
20
Digital Power. 1.5V.
6.10. Reset and Other Pins
Table 10. Reset and Other Pins
Pin No. Description
(32-pin)
Name
Type
Pin No.
(64-pin)
38
PHYRSTB
I
21
RESETB.
Set low to reset the chip. For a complete reset, this pin must be
asserted low for at least 10ms.
PWOUT18
PWOUT15
O
O
2
64
2
32
Power Output.
Be sure to connect a 22µF tantalum capacitor for frequency
compensation. The connection method is outlined in 8.11 3.3V
Power Supply and Voltage Conversion Circuit, page 26.
NC
8, 9, 11~15, 18,
32, 34, 41, 45,
49, 59, 63
NULL
Not Connected.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
7. Register Descriptions
This section describes the functions and usage of the registers available in the RTL8201N/RTL8201R.
In this section the following abbreviations are used:
RO: Read Only
RW: Read/Write
7.1. Register 0 Basic Mode Control Register
Table 11. Register 0 Basic Mode Control Register
Address
Name
Description
Mode
Default
0:15
Reset
This bit sets the status and control registers of the PHY in the default
state. This bit is self-clearing.
RW
0
1: Software reset
0: Normal operation
0:14
0:13
Loopback This bit enables loopback of transmit data nibbles TXD3:0 to the
receive data path.
RW
RW
0
0
1: Enable loopback
This bit sets the network speed.
1: 100Mbps
0: Normal operation
Spd_Set
0: 10Mbps
After completing auto negotiation, this bit will reflect the Speed status.
1: 100Base-T 0: 10Base-T
When 100Base-FX mode is enabled, this bit=1 and is read only.
0:12
0:11
Auto
Negotiation
Enable
This bit enables/disables the NWay auto-negotiation function.
1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored.
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the link
speed and the data transfer mode, respectively.
RW
RW
1
0
When 100Base-FX mode is enabled, this bit=0 and is read only.
Power Down This bit turns down the power of the PHY chip, including the internal
crystal oscillator circuit. The MDC, MDIO is still alive for accessing the
MAC.
1: Power down
Reserved Reserved
Restart Auto This bits allows the NWay auto-negotiation function to be reset.
0: Normal operation
0:10
0:9
-
-
RW
0
Negotiation
1: Re-start auto-negotiation
0: Normal operation
0:8
Duplex
Mode
This bit sets the duplex mode if auto-negotiation is disabled
(bit 0:12=0).
RW
0
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex status.
1: Full duplex
0: Half duplex
0:7:1
0:0
Reserved Reserved
-
-
RMII Mode This bit sets the RMII mode.
1: RMII mode
RW
0
0: MII mode (RTL8201N Only)
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
7.2. Register 1 Basic Mode Status Register
Table 12. Register 1 Basic Mode Status Register
Address
Name
Description
Mode
Default
1:15
100Base-T4
1: Enable 100Base-T4 support
0: Suppress 100Base-T4 support
RO
0
1:14
1:13
1:12
1:11
100Base_TX_ FD 1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
RO
RO
RO
RO
1
1
1
1
100BASE_TX_HD 1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
10Base_T_FD
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
Reserved
10_Base_T_HD
1:10~7
1:6
Reserved
MF Preamble
Suppression
-
-
The RTL8201N/RTL8201R will accept management frames
with preamble suppressed.
RO
1
A minimum of 32 preamble bits are required for the first SMI
read/write transaction after reset. One idle bit is required
between any two management transactions as per IEEE 802.3u
specifications.
1:5
1:4
Auto Negotiation 1: Auto-negotiation process completed
RO
RO
0
0
Complete
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band signal
Far-End-Fault has been detected (see 8.12 Far End Fault
Indication, page 26).
1:3
1:2
1:1
1:0
Auto Negotiation 1: Link has not experienced fail state
0: Link experienced fail state
RO
RO
RO
RO
1
0
0
1
Link Status
1: Valid link established
0: No valid link established
1: Jabber condition detected
0: No jabber condition detected
Jabber Detect
Extended Capability 1: Extended register capability
0: Basic register capability only
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with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
7.3. Register 2 PHY Identifier Register 1
Table 13. Register 2 PHY Identifier Register 1
Address
Name
Description
Mode
Default
2:15~0
PHYID1
PHY identifier ID for software recognition of the
RTL8201N/RTL8201R.
RO
0000
7.4. Register 3 PHY Identifier Register 2
Table 14. Register 3 PHY Identifier Register 2
Address
Name
Description
Mode
Default
3:15~0
PHYID2
PHY identifier ID for software recognition of the
RTL8201N/RTL8201R.
RO
8201
7.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Table 15. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Address
Name
Description
Mode
Default
4:15
NP
Next Page bit.
RO
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
1: Acknowledge reception of link partner capability data word
0: Do not acknowledge reception
4:14
4:13
ACK
RF
RO
0
0
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
Reserved
RW
4:12
4:11
Reserved
TXFC
-
-
1: TX flow control is supported by local node
0: TX flow control not supported by local node
1: RX flow control is supported by local node
0: RX flow control not supported by local node
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full duplex supported by local node
0: 10Base-T full duplex not supported by local node
1: 10Base-T is supported by local node
0: 10Base-T not supported by local node
RW
0
4:10
4:9
RXFC
T4
RW
RO
RW
RW
RW
RW
RW
0
0
4:8
TXFD
TX
1
4:7
1
4:6
10FD
10
1
1
4:5
4:4~0
Selector
Binary encoded selector supported by this node. Currently only
CSMA/CD 00001 is specified. No other protocols are supported.
00001
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with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
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7.6. Register 5 Auto-Negotiation Link Partner Ability Register
(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during auto-negotiation. The
content changes after a successful auto-negotiation if Next-pages are supported.
Table 16. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Address
Name
Description
Mode
Default
5:15
NP
Next Page bit.
RO
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
5:14
5:13
ACK
RF
1: Link partner acknowledges reception of local node’s capability
data word
0: No acknowledgement
RO
RO
0
0
1: Link partner is indicating a remote fault
0: Link partner is not indicating a remote fault
Reserved
5:12
5:11
Reserved
TXFC
-
-
1: TX flow control is supported by Link partner
0: TX flow control not supported by Link partner
1: RX flow control is supported by Link partner
0: RX flow control not supported by Link partner
1: 100Base-T4 is supported by link partner
0: 100Base-T4 not supported by link partner
1: 100Base-TX full duplex is supported by link partner
0: 100Base-TX full duplex not supported by link partner
RO
0
5:10
5:9
5:8
5:7
RXFC
T4
RO
RO
RO
RO
0
0
0
0
TXFD
100BASE-TX 1: 100Base-TX is supported by link partner
0: 100Base-TX not supported by link partner
This bit will also be set if the link in 100Base is established by
parallel detection.
5:6
5:5
10FD
1: 10Base-T full duplex is supported by link partner
0: 10Base-T full duplex not supported by link partner
RO
RO
0
0
10Base-T
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
This bit will also be set if the link in 10Base-T is established by
parallel detection.
5:4~0
Selector
Link Partner’s binary encoded node selector. Currently only
CSMA/CD 00001 is specified
RO
00000
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with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
7.7. Register 6 Auto-Negotiation Expansion Register (ANER)
This register contains additional status for NWay auto-negotiation.
Table 17. Register 6 Auto-Negotiation Expansion Register (ANER)
Address
6:15~5
6:4
Name
Reserved
MLF
Description
Mode
-
Default
This bit is permanently set to 0.
Indicates whether a multiple link fault has occurred.
1: Fault occurred
-
RO
0
0: No fault occurred
6:3
LP_NP_ABLE Indicates whether the link partner supports Next Page negotiation.
RO
0
1: Supported
0: Not supported
6:2
6:1
NP_ABLE
PAGE_RX
This bit indicates whether the local node is able to send additional
Next Pages. Internal use only.
RO
RO
0
0
This bit is set when a new Link Code Word Page has been received.
It is automatically cleared when the auto-negotiation link partner’s
ability register (register 5) is read by management.
6:0
LP_NW_ABLE 1: Link partner supports NWay auto-negotiation.
RO
0
7.8. Register 16 NWay Setup Register (NSR)
Table 18. Register 16 NWay Setup Register (NSR)
Address
16:15~12
16:11
16:10
16:9
Name
Description
Mode
-
Default
Reserved
ENNWLE
Testfun
Reserved
-
1: LED4 Pin indicates link pulse
1: Auto-negotiation speeds up internal timer
1: Set NWay to loopback mode
Reserved
RW
RW
RW
-
0
0
0
-
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
16:8~3
16:2
1: Auto-negotiation experienced ability detect state
1: Auto-negotiation experienced parallel detection fault state
1: Auto-negotiation experienced link status check state
RO
RO
RO
0
0
0
16:1
16:0
7.9. Register 17 Loopback, Bypass, Receiver Error Mask Register
(LBREMR)
Table 19. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)
Address
17:15
Name
RPTR
Description
Mode
RW
Default
Set to 1 to put the RTL8201N into repeater mode.
0
0
17:14
BP_4B5B
Assertion of this bit allows bypassing of the 4B/5B & 5B/4B
encoder.
RW
17:13
17:12
17:11
17:10
BP_SCR
LDPS
Assertion of this bit allows bypassing of the scrambler/descrambler.
Set to 1 to enable Link Down Power Saving mode.
Set to 1 to power down analog function of transmitter and receiver.
Reserved
RW
RW
RW
-
0
0
0
-
AnalogOFF
Reserved
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with Auto MDIX
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Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
Address
17:9
Name
LB
Description
Mode
RW
RW
RW
RW
RW
RW
Default
Set to 1 to enable DSP Loopback.
Used to logic force good link in 10Mbps for diagnostic purposes.
0
1
1
1
0
0
17:8
F_Link_10
17:7
F_Link_100 Used to logic force good link in 100Mbps for diagnostic purposes.
17:6
JBEN
Set to 1 to enable Jabber Function in 10Base-T.
17:5
CODE_err
PME_err
Assertion of this bit causes a code error detection to be reported.
17:4
Assertion of this bit causes a premature end error detection to be
reported.
17:3
17:2
LINK_err
PKT_err
Assertion of this bit causes a link error detection to be reported.
RW
RW
0
0
Assertion of this bit causes a ‘detection of packet errors due to
722ms time-out’ to be reported.
17:1
17:0
FXMODE
SNIMODE
This bit indicates whether Fiber Mode is Enabled.
This bit indicates whether SNI mode is Enabled.
RW
RW
0
0
7.10. Register 18 RX_ER Counter (REC)
Table 20. Register 18 RX_ER Counter (REC)
Address
Name
Description
Mode
Default
18:15~0
RXERCNT
This 16-bit counter increments by 1 for each invalid packet
received. The value is valid while the link is established.
RO
H’[0000]
7.11. Register 19 SNR Display Register
Table 21. Register 19 SNR Display Register
Address
Name
Description
Mode
Default
19:15~4
Reserved
Realtek Test Mode for Internal use. Do not change this field
without Realtek’s approval.
-
-
19:3~0
SNR
These 4-bits show the Signal to Noise Ratio value.
RW
0000
7.12. Register 25 Test Register
Table 22. Register 25 Test Register
Description
Reserved for internal testing.
Address
25:15~12
25:11~7
Name
Mode
RW
Default
-
Test
PHYAD[4:0] Reflects the PHY address defined by external PHY address
configuration pins.
RO
00001
25:6~2
25:1
Test
Reserved for internal testing.
RO
RO
LINK10
1: 10Base-T link established
0
0
0: No 10Base-T link established
1: 100Base-FX or 100Base-TX link established
0: No 100Base link established
25:0
LINK100
RO
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Track ID: JATR-1076-21 Rev. 1.3
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Datasheet
8. Functional Description
The RTL8201N/RTL8201R PHYceiver is a physical layer device that integrates 10Base-T and
100Base-TX/100Base-FX functions, and some extra power management features into a 64-pin/32-pin
single chip that is used in 10/100 Fast Ethernet applications. This device supports the following functions:
• MII interface with MDC/MDIO SMI management interface to communicate with MAC (RTL8201N
only)
• RMII interface with MDC/MDIO SMI management interface to communicate with MAC
• IEEE 802.3u clause 28 Auto-Negotiation ability
• Flow control ability support to cooperate with MAC
• Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
• Flexible LED configuration
• 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode & only RTL8201N)
• Power Down mode support
• 4B/5B transform
• Scrambling/De-scrambling
• NRZ to NRZI, NRZI to MLT-3
• Manchester Encode and Decode for 10Base-T operation
• Clock and Data recovery
• Adaptive Equalization
• Far End Fault Indication (FEFI) in fiber mode
8.1. MII/RMII Modes
8.1.1.
MII Data Transition (RTL8201N Only)
To set the RTL8201N for MII mode operation, pull the MII/SNI pin low and set the ANE, SPEED, and
DUPLEX pins.
The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying
a standard interface between the PHY and MAC layer. This interface operates at two frequencies –
25MHz and 2.5MHz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions.
Transmission
The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the
PHY via TXD[0..3]. The PHY will sample TXD[0..3] synchronously with TXC – the transmit clock
signal supplied by the PHY – during the interval TXEN is asserted.
Reception
The PHY asserts the RXEN signal. It passes the received nibble data RXD[0..3] clocked by RXC. CRS
and COL signals are used for collision detection and handling.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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Datasheet
In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is
recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble
has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.
The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/
or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur, e.g., an invalid J/K,
invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the
reconciliation sublayer that an error was detected somewhere in the frame.
Note: The RTL8201N does not use a TXER signal. This does not affect the transmit function.
8.1.2.
RMII Data Transition
The RTL8201N/RTL8201R comply with the RMII requirements outlined in the RMII Consortium
specification. The main advantage introduced by RMII is pin count reduction; e.g., it operates with only
one 50MHz reference clock for both the TX and RX sides, without separate clocks needed for both paths,
as with the MII interface. However, some hardware modification is needed for this change, the most
important of which is the presence of an elastic buffer for absorption of the frequency difference between
the 50MHz reference clock and the clocking information of the incoming data stream.
Another change implemented is that MII RXDV and Carrier_Sense are merged into one signal, CRS_DV,
which is asserted high when detecting incoming packet data. When internal Carrier_Sense de-asserted,
CRS_DV is de-asserted when the first di-bit of a nibble is presented onto RXD[1..0] synchronously to
REFCLK. If there is still data in the FIFO that has not yet been presented onto RXD[1..0], then, on the
second di-bit of a nibble, CRS_DV reasserts. This pattern of assertion and de-assertion continues until all
received data in the FIFO has been presented onto RXD[1..0]
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Datasheet
8.2. Serial Management Interface
8.2.1.
RTL8201N
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 31
RTL8201N devices, configured with different PHY addresses (00001b to 11111b). During a hardware
reset, the logic levels of pins 58, 57, 56, 54, and 52 are latched into the RTL8201N to be set as the PHY
address for management communication via the serial interface. Setting the PHY address to 00000b will
put the RTL8201N into power down mode. The read and write frame structure for the management
interface is illustrated in Figure 4 and Figure 5.
MDC
Z
0
1
1
0
A4 A3 A2
A1 A0 R4 R3 R2 R1 R0
REGAD[4:0]
0
D14
D15 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA
32 1s
MDIO
Preamble
ST
OP
PHYAD[4:0]
TA
Idle
MDIO is sourced by PHY. Clock data from PHY on rising edge of MDC
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 4. Read Cycle
MDC
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHYAD[4:0] REGAD[4:0]
1
0
D14
D11 D10
D8 D7 D6 D5 D4 D3 D2
DATA
MDIO
D15
D13 D12
D9
D1 D0
32 1s
OP
Preamble
ST
TA
Idle
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 5. Write Cycle
Table 23. Serial Management
Name
Description
Preamble
32 contiguous logical ‘1’s sent by the MAC on MDIO along with 32 corresponding cycles on MDC. This
provides synchronization for the PHY.
ST
OP
Start of Frame. Indicated by a 01 pattern.
Operation Code.
Read: 10
Write: 01
PHYAD
PHY Address. Up to 31 PHYs can be connected to one MAC. This 5-bit field selects which PHY the frame
is directed to.
REGAD
TA
Register Address. This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Turnaround. This is a 2-bit time-spacing between the register address and the data field of a frame to avoid
contention during a read transaction. For a read transaction, both the STA and the PHY remain in a high-
impedance state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit
time of the turnaround of a read transaction.
DATA
IDLE
Data. These are the 16 bits of data.
Idle Condition. Not truly part of the management frame. This is a high impedance state. Electrically, the
PHY’s pull-up resistor will pull the MDIO line to a logical ‘1’.
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8.2.2.
RTL8201R
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 3
RTL8201R devices, configured with different PHY addresses (01b to 11b). During a hardware reset, the
logic levels of pins 28 and 27 are latched into the RTL8201R to be set as the PHY address for
management communication via the serial interface. Setting the PHY address to 00b will put the
RTL8201R into power down mode. The read and write frame structure for the management interface is
illustrated in Figure 4 and Figure 5.
8.3. Auto-Negotiation and Parallel Detection
The RTL8201N/RTL8201R supports IEEE 802.3u clause 28 auto-negotiation for operation with other
transceivers supporting auto-negotiation. The RTL8201N/RTL8201R can auto-detect the link partner’s
abilities and determine the highest speed/duplex configuration possible between the two devices. If the
link partner does not support auto-negotiation, then the RTL8201N/RTL8201R will enable half duplex
mode and enter parallel detection mode. The RTL8201N/RTL8201R will default to transmitting FLP
(Fast Link Pulse) and wait for the link partner to respond. If the RTL8201N/RTL8201R receives a FLP,
then the auto-negotiation process will go on. If it receives a NLP (Normal Link Pulse), then the
RTL8201N/RTL8201R will change to 10Mbps and half duplex mode. If it receives a 100Mbps IDLE
pattern, it will change to 100Mbps and half duplex mode.
To enable auto-negotiation mode operation on the RTL8201N/RTL8201R, pull the ANE (Auto-
Negotiation Enable) pin high. The SPEED and DUPLEX pins will set the ability content of the auto-
negotiation register. Auto-negotiation mode can be externally disabled by pulling the ANE pin low. In
this case, the SPEED pin and DUPLEX pin will change the media configuration of the
RTL8201N/RTL8201R.
The following is a list of all configurations of the ANE/SPEED/DUPLEX pins and their operation in
Fiber or UTP mode.
8.3.1.
Setting the Medium Type and Interface Mode to MAC
(RTL8201N Only)
Table 24. Setting the Medium Type and Interface Mode to MAC (RTL8201N Only)
FX (Pin 35)
MII/SNI (Pin 46)
Operation Mode
L
L
H
L
H
X
UTP mode and MII interface.
UTP mode and SNI interface.
Fiber mode and MII interface.
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8.3.2.
UTP Mode and MII Interface (RTL8201N Only)
Table 25. UTP Mode and MII Interface (RTL8201N Only)
ANE
(Pin 37)
SPEED
(Pin 33)
DUPLEX Operation
(Pin 51)
Auto-negotiation enabled. The ability field does not support 100Mbps or full
duplex mode operation.
H
L
L
L
Auto-negotiation enabled. The ability field does not support 100Mbps
operation.
H
H
H
L
L
L
L
H
Auto-negotiation enabled. The ability field does not support full duplex mode
operation.
H
H
L
L
Default setup, auto-negotiation enabled. The RTL8201N supports 10Base-T
/100Base-TX, half/full duplex mode operation.
H
Auto-negotiation disabled. Forces the RTL8201N into 10Base-T and half
duplex mode.
L
Auto-negotiation disabled. Forces the RTL8201N into 10Base-T and full
duplex mode.
L
H
Auto-negotiation disabled. Forces the RTL8201N into 100Base-TX and half
duplex mode.
H
H
L
Auto-negotiation disabled. Forces the RTL8201N into 100Base-TX and full
duplex mode.
H
8.3.3.
UTP Mode and SNI Interface (RTL8201N Only)
SNI interface to MAC (only operates in 10Base-T when the SNI interface is enabled)
Table 26. UTP Mode and SNI Interface (RTL8201N Only)
ANE
(Pin 37)
X
SPEED
(Pin 33)
X
DUPLEX Operation
(Pin 51)
L
The duplex pin is pulled low to support the 10Base-T half duplex function.
10Base-T half duplex is the specified default mode in the SNI interface.
X
X
H
The RTL8201N also supports full duplex in SNI mode. The duplex pin is
pulled high to support 10Base-T full duplex function.
8.3.4.
Fiber Mode and MII Interface (RTL8201N Only)
The RTL8201N only supports 100Base-FX when Fiber mode is enabled. ANE (Auto-Negotiation Enable)
and SPEED configuration is ignored when Fiber mode is enabled.
Table 27. Fiber Mode and MII Interface (RTL8201N Only)
ANE
(Pin 37)
X
SPEED
(Pin 33)
X
DUPLEX Operation
(Pin 51)
H
L
The duplex pin is pulled high to support 100Base-FX full duplex function.
The duplex pin is pulled low to support 100Base-FX half duplex function.
X
X
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8.4. Flow Control Support
The RTL8201N/RTL8201R supports flow control indications. The MAC can program the MII register to
indicate to the PHY that flow control is supported. When the MAC supports the Flow Control mechanism,
setting bit 10 of the ANAR register using the MDC/MDIO SMI interface, then the
RTL8201N/RTL8201R will add the ability to its NWay ability. If the Link partner also supports Flow
Control, then the RTL8201N/RTL8201R can recognize the Link partner’s NWay ability by examining bit
10 of ANLPAR (register 5).
8.5. Hardware Configuration and Auto-Negotiation (RTL8201N
Only)
This section describes methods to configure the RTL8201N and set the auto-negotiation mode.
Table 28 shows the various pins and their settings.
Table 28. Auto-Negotiation Mode Pin Settings
Pin Name
Description
Isolate
Set high to isolate the RTL8201N from the MAC. This will also isolate the MDC/MDIO management
interface. In this mode, power consumption is minimum (see 8.7 Power Down, Link Down, Power
Saving, and Isolation Modes, page 23).
RPTR
LDPS
Pull high to set the RTL8201N into repeater mode. This pin is pulled low by default (see 8.9 Repeater
Mode Operation, page 26).
Pull high to set the RTL8201N into LDPS mode. This pin is pulled low by default (see 8.7 Power
Down, Link Down, Power Saving, and Isolation Modes, page 23).
MII/SNI
Pull low to set the RTL8201N into MII mode operation, which is the default mode for
the RTL8201N. This pin pulled high will set the RTL8201N into SNI mode operation.
When set to SNI mode, the RTL8201N will operate at 10Mbps (see 0
Serial Network Interface, page 23).
ANE
Auto-Negotiation Enable. Pull high to enable auto-negotiation (default). Pull low to disable auto-
negotiation and activate the parallel detection mechanism (see 8.3 Auto-Negotiation and Parallel
Detection, page 20).
SPEED
DUPLEX
When ANE is pulled high, the ability to adjust speed is setup. When ANE is pulled low, pull this pin
low to force 10Mbps operation and high to force 100Mbps operation (see 8.3 Auto-Negotiation and
Parallel Detection, page 20).
When ANE is pulled high, the ability to adjust the DUPLEX pin will be setup. When ANE is pulled
low, pull this pin low to force half duplex, high to force full duplex operation (see 8.3 Auto-Negotiation
and Parallel Detection, page 20).
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8.6. Serial Network Interface (RTL8201N Only)
The RTL8201N also supports the traditional 7-wire serial interface to operate with legacy MACs or
embedded systems. To setup for this mode of operation, pull the MII/SNI pin high. By doing so, the
RTL8201N will ignore the setup of the ANE and SPEED pins. In this mode, the RTL8201N will set the
default operation to 10Mbps and half-duplex mode.
Note: The RTL8201N also supports full-duplex mode operation if the DUPLEX pin has been pulled high.
This interface consists of a 10Mbps transmit and receive clock generated by PHY, 10Mbps transmit and
receive serial data, transmit enable, collision detect, and carry sense signals.
8.7. Power Down, Link Down, Power Saving, and Isolation
Modes
Four types of Power Saving mode operation are supported. This section describes how to implement each
mode. The first three modes are configured through software, and the fourth through hardware.
Table 29. Power Saving Mode Pin Settings
Mode
Description
Analog Off
Setting bit 11 of register 17 to 1 will put the RTL8201N/RTL8201R into analog off state. In analog off
state, the RTL8201N/RTL8201R will power down all analog functions such as transmit, receive, PLL,
etc. However, the internal 25MHz crystal oscillator will not be powered down. Digital functions in this
mode are still available which allows reacquisition of analog functions
LDPS
Setting bit 12 of register 17 to 1, or pulling the LDPS pin high will put the RTL8201N/RTL8201R into
LDPS (Link Down Power Saving) mode. In LDPS mode, the RTL8201N/RTL8201R will detect the link
status to decide whether or not to turn off the transmit function. If the link is off, FLP or 100Mbps
IDLE/10Mbps NLP will not be transmitted. However, some signals similar to NLP will be transmitted.
Once the receiver detects leveled signals, it will stop the signal and transmit FLP or 100Mbps
IDLE/10Mbps NLP again. This can cut power used by 60%~80% when the link is down.
PWD
Setting bit 11 of register 0 to 1 puts the RTL8201N/RTL8201R into power down mode. This is the
maximum power saving mode while the RTL8201N/RTL8201R is still alive. In PWD mode, the
RTL8201N/RTL8201R will turn off all analog/digital functions except the MDC/MDIO management
interface. Therefore, if the RTL8201N/RTL8201R is put into PWD mode and the MAC wants to recall
the PHY, it must create the MDC/MDIO timing by itself (this is done by software).
Isolation
This mode is different from the three previous software configured power saving modes. This mode is
configured by hardware pin 52. Setting pin 52 high will isolate the RTL8201N from the Media Access
Controller (MAC) and the MDC/MDIO management interface. In this mode, power consumption is
minimal.
Note: Isolation is supported by the RTL8201N only.
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8.8. Media Interface
8.8.1.
100Base-TX Transmit & Receive Operation
100Base-TX Transmit (RTL8201N)
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201N will have different scrambler seeds and so spread the output of
the MLT-3 signals.
100Base-TX Transmit (RTL8201R)
Transmit data in 2-bit nibbles (TXD[1:0]) clocked at 50MHz (REFCLK) is transformed into 5B symbol
code (4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then
takes place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line
driver. The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/
symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-
Frame delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201R will have different scrambler seeds and so spread the output of
the MLT-3 signals.
100Base-TX Receive
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The PLL then recovers the timing
information from the signals and from the receive clock. With this, the received signal is sampled to form
NRZI data. The next steps are the NRZI to NRZ process, unscrambling of the data, serial to parallel and
5B to 4B conversion, and passing of the 4B nibble to the MII/RMII interface.
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8.8.2.
100Base-FX Fiber Transmit & Receive Operation (RTL8201N
Only)
The RTL8201N can be configured as 100Base-FX via hardware configuration. The hardware 100Base
FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.
100Base-FX Transmit
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pairs form.
100Base-FX Receive
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
8.8.3.
10Base-T Transmit & Receive Operation
10Base-T Transmit (RTL8201N)
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a band-limited filter embedded in the RTL8201N and then transmitted.
10Base-T Transmit (RTL8201R)
Transmit data in 2-bit nibbles (TXD[1:0]) clocked at 50MHz (REFCLK) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a band-limited filter embedded in the RTL8201R and then transmitted.
10Base-T Receive (RTL8201N)
In 10Base-T receive mode, the Manchester decoder in the RTL8201N converts the Manchester encoded
data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data
stream is converted to a parallel 4-bit nibble signal (RXD[3:0]).
10Base-T Receive (RTL8201R)
In 10Base-T receive mode, the Manchester decoder in the RTL8201R converts the Manchester encoded
data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data
stream is converted to a parallel 2-bit nibble signal (RXD[1:0]).
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8.9. Repeater Mode Operation
Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201N/RTL8201R into
repeater mode. In repeater mode, the RTL8201N/RTL8201R will assert CRS high only when receiving a
packet. In NIC mode, the RTL8201N/RTL8201R will assert CRS high both when transmitting and
receiving packets. If using the RTL8201N/RTL8201R in a NIC or switch application, set to the default
mode. NIC/Switch mode is the default setting and has the RPTR pin pulled low, or bit 15 of register 17 is
set to 0.
8.10. Reset and Transmit Bias
The RTL8201N/RTL8201R can be reset by pulling the RESETB pin low for about 10ms, then pulling the
pin high. It can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will
clear the registers and re-initialize them. The media interface will disconnect and restart the auto-
negotiation/parallel detection process.
The RTSET pin must be pulled low by a 2KΩ resister with 1% accuracy to establish an accurate transmit
bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock
traces and transmit/receive paths to avoid signal interference.
8.11. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201N/RTL8201R is fabricated in a 0.15µm process. The core circuit needs to be powered by
1.5V, however, the digital IO and DAC circuits need a 3.3V power supply. Two regulators are embedded
in the RTL8201N/RTL8201R to convert 3.3V to 1.5V and 1.8V. As with many commercial voltage
conversion devices, the 1.5V/1.8V output pin (PWFBOUT) of this circuit requires the use of an output
capacitor (22µF tantalum capacitor) as part of the device frequency compensation.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
8.12. Far End Fault Indication (RTL8201N Only)
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled,
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method which is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201N detects this pattern three
times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On
the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201N will start sending this
pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path
has a problem from the point of view of the RTL8201N. The FEFI mechanism is used only in
100Base-FX mode.
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9. Characteristics
9.1. DC Characteristics
9.1.1.
Absolute Maximum Ratings
Table 30. Absolute Maximum Ratings
Item
Minimum
3.0V
Typical
3.3V
-
Maximum
3.6V
Supply Voltage
Storage Temperature
-55°C
125°C
9.1.2.
Operating Conditions
Table 31. Operating Conditions
Item
Condition
Minimum
Typical
Maximum
3.6V
Vcc 3.3V
3.3V Supply Voltage
3.0V
3.3V
-
TA
Ambient Operating Temperature
0°C
70°C
9.1.3.
Power Dissipation
Test Condition: VCC=3.3V
Table 32. Power Dissipation
Symbol
PLDPS
PAnaOff
PPWD
Condition
Total Current Consumption
Link Down Power Saving Mode
Analog Off Mode
24mA
18mA
17mA
17mA
105mA
130mA
120mA
28mA
25mA
Power Down Mode
Isolate Mode
PIsolate
P100F
100Base Full Duplex
10Base-T Full Duplex
10Base-T Transmit
10Base-T Receive
10Base-T Idle
P10F
P10TX
P10RX
P10IDLE
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9.1.4.
Input Voltage: Vcc
Table 33. Input Voltage: Vcc
Symbol
TTL VIH
TTL VIL
TTL VOH
TTL VOL
TTL IOZ
IIN
Condition
Minimum
Maximum
Vcc +0.5V
0.3*Vcc
Vcc
Input High Vol.
Input Low Vol.
Output High Vol.
Output Low Vol.
Tri-state Leakage
Input Current
-
0.5*Vcc
-0.5V
-
IOH=-8mA
IOL=8mA
0.65*Vcc
0.3*Vcc
10µA
Vout=Vcc or GND
Vin=Vcc or GND
Vin=Vcc or GND
-110µA
-1µA
10µA
IPL
Input Current with internal
weak pull low resistor
-1µA
100µA
IPH
Input Current with internal
weak pull high resistor
Vin=Vcc or GND
-110µA
10µA
PECL VIH
PECL VIL
PECL VOH
PECL VOL
PECL Input High Vol.
PECL Input Low Vol.
PECL Output High Vol.
PECL Output Low Vol.
-
-
-
-
Vdd -1.16V
Vdd -1.81V
Vdd -1.02V
-
Vdd -0.88V
Vdd -1.47V
-
Vdd -1.62V
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Track ID: JATR-1076-21 Rev. 1.3
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9.2. AC Characteristics
9.2.1.
MII Transmission Cycle Timing (RTL8201N Only)
Table 34. MII Transmission Cycle Timing (RTL8201N Only)
Symbol Description
Minimum
Typical
Maximum
Unit
t1
TXCLK high pulse width
100Mbps
10Mbps
14
20
26
ns
140
200
260
ns
t2
t3
t4
TXCLK low pulse width
TXCLK period
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
14
140
-
20
200
40
26
ns
ns
ns
ns
ns
260
-
-
-
-
400
24
TXEN, TXD[0:3] setup to
TXCLK rising edge
10
10Mbps
5
0
-
-
ns
ns
t5
TXEN, TXD[0:3] hold after
TXCLK rising edge
100Mbps
10
25
10Mbps
100Mbps
10Mbps
100Mbps
5
-
-
-
-
-
-
ns
ns
ns
ns
t6
t7
TXEN sampled to CRS high
40
-
400
160
TXEN sampled to CRS low
-
10Mbps
100Mbps
10Mbps
-
-
2000
140
ns
ns
t8
t9
Transmit latency
60
70
-
-
-
-
100
-
2000
170
-
ns
ns
ns
Sampled TXEN inactive to end of 100Mbps
frame
10Mbps
Figure 6 and Figure 7 show an example of a packet transfer from MAC to PHY on the MII interface.
t
3
VIH(min)
VIL(max)
TXCLK
t
t
2
1
t
t
5
4
VIH(min)
VIL(max)
TXD[0:3]
TXEN
Figure 6. MII Transmission Cycle Timing-1
TXCLK
TXEN
TXD[0:3]
t
t
6
7
9
CRS
t
t
8
TPTX+-
Figure 7. MII Transmission Cycle Timing-2
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Datasheet
9.2.2.
MII Reception Cycle Timing (RTL8201N Only)
Table 35. MII Reception Cycle Timing (RTL8201N Only)
Symbol Description
Minimum
Typical
20
Maximum
Unit
ns
t1
t2
t3
t4
t5
RXCLK high pulse width
RXCLK low pulse width
RXCLK period
100Mbps
10Mbps
14
140
14
26
260
26
200
ns
100Mbps
20
ns
10Mbps
100Mbps
10Mbps
140
-
200
40
400
-
260
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
RXER, RXDV, RXD[0:3] setup to 100Mbps
RXCLK rising edge
10
6
10Mbps
-
RXER, RXDV, RXD[0:3] hold
after RXCLK rising edge
100Mbps
10
-
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
6
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
t6
t7
t8
t9
Receive frame to CRS high
130
2000
240
1000
150
End of receive frame to CRS low
Receive frame to sampled edge of 100Mbps
RXDV
10Mbps
-
-
-
-
-
-
3200
120
ns
ns
ns
End of receive frame to sampled
edge of RXDV
100Mbps
10Mbps
1000
Figure 8 and Figure 9 show an example of a packet transfer from PHY to MAC on the MII interface.
t3
V
RXCLK
IH(min)
IL(max)
V
t1
t2
t4
t5
RXD[0:3]
RXDV
V
V
IH(min)
IL(max)
RXER
Figure 8. MII Reception Cycle Timing-1
RXCLK
t9
t8
RXDV
RXD[0:3]
t6
t7
CRS
TPRX+-
Figure 9. MII Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
30
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
9.2.3.
RMII Transmission Cycle Timing
Table 36. RMII Transmission Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
ns
T_ipsu_txd_rmii
T_iphd_txd_rmii
TXD/TXEN setup time to REFCLK
TXD/TXEN hold time from REFCLK
2
2
-
-
-
-
ns
Figure 10. RMII Transmission Cycle Timing
9.2.4.
RMII Reception Cycle Timing
Table 37. RMII Transmission Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
ns
T_opd_rxd_rmii REFCLK rising edge to RXD/CRS_DV delay
4
-
9
Figure 11. RMII Reception Cycle Timing
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
31
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
9.2.5.
SNI Transmission Cycle Timing (RTL8201N Only)
Table 38. SNI Transmission Cycle Timing (RTL8201N Only)
Symbol Description
Minimum
Maximum
Unit
ns
t1
t2
t3
t4
t5
t8
TXCLK high pulse width
36
36
80
20
10
-
-
-
TXCLK low pulse width
ns
TXCLK period
120
-
ns
TXEN, TXD0 setup to TXCLK rising edge
TXEN, TXD0 hold after TXCLK rising edge
Transmit latency
ns
-
ns
50
ns
Figure 12 and Figure 13 show an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
TXCLK
V
IL(max)
t1
t2
t5
t4
V
V
TXD0
TXEN
IH(min)
IL(max)
Figure 12. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
t8
t9
TPTX+-
Figure 13. SNI Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
32
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
9.2.6.
SNI Reception Cycle Timing (RTL8201N Only)
Table 39. SNI Reception Cycle Timing (RTL8201N Only)
Symbol
Description
Minimum
Typical
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
t7
t8
RXCLK high pulse width
RXCLK low pulse width
RXCLK period
36
36
80
40
40
-
-
-
-
-
ns
-
120
-
ns
RXD0 setup to RXCLK rising edge
RXD0 hold after RXCLK rising edge
Receive frame to CRS high
End of receive frame to CRS low
Decoder acquisition time
-
ns
-
-
-
ns
50
160
1800
ns
-
-
ns
-
600
ns
Figure 14 and Figure 15 show an example of a packet transfer from PHY to MAC on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
RXCLK
V
IL(max)
t2
t1
t4
t5
V
V
RXD0
IH(min)
IL(max)
Figure 14. SNI Reception Cycle Timing-1
RXCLK
RXD0
t8
t6
t7
CRS
TPRX+-
Figure 15. SNI Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
33
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
9.2.7.
MDC/MDIO Timing
Table 40. MDC/MDIO Timing
Symbol Description
Minimum
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
MDC High Pulse Width
160
160
400
10
-
MDC Low Pulse Width
-
ns
MDC Period
-
-
ns
MDIO Setup To MDC Rising Edge
MDIO Hold Time From MDC Rising Edge
MDIO Valid From MDC Rising Edge
ns
10
-
ns
0
300
ns
t3
V
V
IH(min)
MDC
IL(max)
t 5
t4
t1
t2
MDIO
V
IH(min)
sourced by
V
IL(max)
STA
t6
MDIO
sourced by
RTL8201N
V
V
IH(min)
IL(max)
Figure 16. MDC/MDIO Timing
9.2.8.
Transmission without Collision
Figure 17 shows an example of a packet transfer from MAC to PHY.
Figure 17. MAC to PHY Transmission without Collision
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
34
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
9.2.9.
Reception without Error
Figure 18 shows an example of a packet transfer from PHY to MAC.
Figure 18. PHY to MAC Reception without Error
9.3. Crystal Characteristics
Table 41. Crystal Characteristics
Parameter
Range
Nominal Frequency
Oscillation Mode
25.000MHz
Base wave
±50ppm
Frequency Tolerance at 25°C
Operating Temperature Range
Equivalent Series Resistance
Drive Level
-10°C ~ +70°C
30ohm Max.
0.1mV
Load Capacitance
20pF
Shunt Capacitance
7pF Max.
Insulation Resistance
Test Impedance Meter
Aging Rate Per Year
Mega ohm Min./DC 100V
Saunders 250A
±0.0003%
9.4. Transformer Characteristics
Table 42. Transformer Characteristics
Parameter
Transmit End Receive End
Turn Ratio
1:1 CT
1:1
Inductance (min.)
350µH @ 8mA
350µH @ 8mA
Note: The auto MDIX detection function requires a transformer with symmetrical TX/RX and Choke after transformer
placement, i.e., Pulse Engineer H1251 (refer to the suggested RTL8201N/RTL8201R Schematic, which is available for
download at www.realtek.com.tw).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
35
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
10. Mechanical Dimensions
10.1. RTL8201N 64-Pin QFN Mechanical Dimensions
Note: For RTL8201N specific information, refer to line 4.
Note: Exposed Pad is Analog and Digital Ground.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
36
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
10.2. RTL8201R 32-Pin QFN Mechanical Dimensions
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
37
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
38
Track ID: JATR-1076-21 Rev. 1.3
RTL8201N &RTL8201R
Datasheet
11. Ordering Information
Table 43. Ordering Information
Package
Part Number
RTL8201N-GR
RTL8201R-GR
Status
MP
64-pin QFN with Green Package
32-pin QFN with Green Package
Sample
Note: See page 4 and 5 for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
with Auto MDIX
39
Track ID: JATR-1076-21 Rev. 1.3
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