RTL8204 [ETC]
Layout reference ; 布局参考\n
| 型号： | RTL8204 |
| 厂家： | 
ETC |
| 描述： | Layout reference
|
| 文件： | 总29页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8201BL
REALTEK SINGLE CHIP
SINGLE PORT 10/100M
FAST ETHERNET PHYCEIVER
RTL8201BL
1. Features........................................................................... 2
2. General Description....................................................... 2
3. Block Diagram................................................................ 3
4. Pin Assignments ............................................................. 4
5. Pin Description............................................................... 5
5.1 100 Mbps MII & PCS Interface ................................ 5
5.2 SNI (Serial Network Interface): 10Mbps only .......... 5
5.3 Clock Interface.......................................................... 6
5.4 100Mbps Network Interface...................................... 6
5.5 Device Configuration Interface................................. 6
5.6 LED Interface/PHY Address Config......................... 7
5.7 Reset and other pins .................................................. 7
5.8 Power and Ground pins............................................. 7
6. Register Descriptions ..................................................... 8
6.1 Register 0 Basic Mode Control Register................... 8
6.2 Register 1 Basic Mode Status Register ..................... 9
6.3. Register 2 PHY Identifier Register 1 ....................... 9
6.4. Register 3 PHY Identifier Register 2 ....................... 9
7.1 MII and Management Interface............................... 14
7.1.1 Data Transition................................................ 14
7.1.2 Serial Management.......................................... 14
7.2 Auto-negotiation and Parallel Detection................. 15
7.3 Flow control support............................................... 16
7.4 HardwareConfigurationandAuto-negotiation................. 16
7.5 LED and PHY Address Configuration.................... 17
7.6 Serial Network Interface......................................... 17
7.7 PowerDown, LinkDown, PowerSaving, andIsolationModes... 18
7.8 Media Interface....................................................... 18
7.8.1 100Base TX..................................................... 18
7.8.2 100Base-FX Fiber Mode Operation ................ 18
7.8.3 10Base Tx/Rx.................................................. 19
7.9 Repeater Mode Operation....................................... 19
7.10 Reset, and Transmit Bias(RTSET)........................ 19
7.11 3.3V power supply and voltage conversion circuit19
7.12 Far End Fault Indication (FEFI)............................ 20
8. Electrical Characteristics............................................ 21
8.1 D.C. Characteristics ................................................ 21
8.1.1. Absolute Maximum Ratings........................... 21
8.1.2. Operating Conditions ..................................... 21
8.1.3. Power Dissipation........................................... 21
8.1.4 Supply Voltage: Vcc........................................ 21
8.2 A.C. Characteristics ................................................ 22
8.2.1 MII Timing of Transmission Cycle ................. 22
8.2.2 MII Timing of Reception Cycle ...................... 23
8.2.3 SNI Timing of Transmission Cycle................. 24
8.2.4 SNI Timing of Reception Cycle ...................... 25
8.2.5 MDC/MDIO timing......................................... 26
8.2.6 Transmission Without Collision ...................... 26
8.2.7 Reception Without Error ................................. 26
8.3 Crystal and Transformer Specifications.................. 27
8.3.1 Crystal Specifications...................................... 27
8.3.2 Transformer Specifications.............................. 27
9. Mechanical Dimensions............................................... 28
10. Revision History......................................................... 29
6.5. Register
4
Auto-negotiation Advertisement
Register(ANAR) ........................................................... 10
6.6 Register 5 Auto-Negotiation Link Partner Ability
Register(ANLPAR) ....................................................... 10
6.7
Register
6
Auto-negotiation
Expansion
Register(ANER)............................................................ 11
6.8 Register 16 Nway Setup Register(NSR) ................. 11
6.9 Register 17 Loopback, Bypass, Receiver Error Mask
Register(LBREMR) ...................................................... 12
6.10 Register 18 RX_ER Counter(REC)....................... 12
6.11 Register1910MbpsNetworkInterfaceConfigurationRegister... 12
6.12 Register 20 PHY 1_1 Register .............................. 13
6.13 Register 21 PHY 1_2 Register .............................. 13
6.14 Register 22 PHY 2 Register .................................. 13
6.15 Register 23 Twister_1 Register ............................. 13
6.16 Register 24 Twister_2 Register ............................. 13
6.17 Register 25 Test Register....................................... 13
7. Functional Description ................................................ 14
2002-03-29
Rev.1.2
1
RTL8201BL
1. Features
The Realtek RTL8201BL is a Fast Ethernet Phyceiver with selectable MII or SNI interface to the MAC chip. It provides the
following features:
ꢀ
Supports MII/7-wire SNI (Serial Network
Interface) interface
ꢀ
ꢀ
ꢀ
ꢀ
Supports repeater mode
Speed/duplex/auto negotiation adjustable
3.3V operation with 5V IO signal tolerance
Low operation power consumption and only need
single supply 3.3V
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Supports 10/100Mbps operation
Supports half/full duplex operation
Support of twisted pair or Fiber mode output
IEEE 802.3/802.3u compliant
ꢀ
ꢀ
ꢀ
ꢀ
Adaptive Equalization
Supports IEEE 802.3u clause 28 auto negotiation
Supports power down mode
25MHz crystal/oscillator as clock source
Multiple network status LED support
Flow control ability support to co-work with
MAC (by MDC/MDIO)
Supports operation under Link Down Power
Saving mode
ꢀ
Supports Base Line Winder (BLW) compensation
ꢀ
48 pin LQFP package
2. General Description
The RTL8201BL is a single-port Phyceiver with an MII (Media Independent Interface)/SNI(Serial Network Interface). It
implements all 10/100M Ethernet Physical-layer functions including the Physical Coding Sublayer (PCS), Physical Medium
Attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10Base-Tx Encoder/Decoder and Twisted
Pair Media Access Unit (TPMAU). A PECL interface is supported to connect with an external 100Base-FX fiber optical
transceiver. The chip is fabricated with an advanced CMOS process to meet low voltage and low power requirements.
The RTL8201BL can be used as a Network Interface Adapter, MAU, CNR, ACR, Ethernet Hub, Ethernet Switch. Additionally,
it can be used in any embedded system with an Ethernet MAC that needs a twisted pair physical connection or fiber PECL
interface to external 100Base-FX optical transceiver module.
2002-03-29
Rev.1.2
2
RTL8201BL
3. Block Diagram
100M
5B 4B
Decoder
Data
Alignment
RXD
RXC 25M
Descrambler
MII
Interface
10/100
half/full
Switch
Logic
TXD
TXC 25M
4B 5B
Encoder
Scrambler
SNI
Interface
10/100M Auto-negotiation
Control Logic
Link pulse
10M
TXC10
TXD10
Manchester coded
waveform
10M Output waveform
shaping
RXC10
RXD10
Data Recovery
Receive low pass filter
TD+
TXC 25M
TXD
3 Level
Driver
TXO+
TXO -
Parrallel
to Serial
Variable Current
Baseline
wander
Correction
Peak
Detect
RXIN+
RXIN-
3 Level
Comparator
MLT-3
to NRZI
Adaptive
Equalizer
ck
data
RXC 25M
RXD
Serial to
Parrallel
Master
PPL
Slave
PLL
Control
Voltage
25M
2002-03-29
Rev.1.2
3
RTL8201BL
4. Pin Assignments
24. RXER
/FXEN
37. ANE
38. DUPLEX
23. CRS
39. SPEED
40. RPTR
22. RXDV
21. RXD0
20. RXD1
19. RXD2
18. RXD3
17. DGND
41. LDPS
42. RESETB
43. ISOLATE
RTL8201BL
44. MII/SNIB
/RTT3
45. DGND
46. X1
16. RXC
15. LED4/
PHYAD4
47. X2
14. DVDD33
13. LED3/
PHYAD3
48. DVDD33
2002-03-29
Rev.1.2
4
RTL8201BL
5. Pin Description
LI: Latched Input in power up or reset
I/O: Bi-directional input and output
O: Output
I: Input
P: Power
5.1 100 Mbps MII & PCS Interface
Symbol
Type
Pin No.
Description
TXC
O
7
Transmit Clock: This pin provides a continuous clock as a timing reference
for TXD[3:0] and TXEN.
TXEN
TXD[3:0]
RXC
I
I
2
3, 4, 5, 6
16
Transmit Enable: The input signal indicates the presence of a valid nibble
data on TXD[3:0].
Transmit Data: MAC will source TXD[0..3] synchronous with TXC when
TXEN is asserted.
Receive Clock: This pin provides a continuous clock reference for RXDV
and RXD[0..3] signals. RXC is 25MHz in the 100Mbps mode and 2.5Mhz in
the 10Mbps mode.
O
COL
O
O
O
1
23
22
Collision Detected: COL is asserted high when a collision is detected on the media.
Carrier Sense: This pin’s signal is asserted high if the media is not in IDEL state.
Receive Data Valid: This pin’s signal is asserted high when received data is
present on the RXD[3:0] lines; the signal is deasserted at the end of the
packet. The signal is valid on the rising of the RXC.
CRS
RXDV
RXD[3:0]
O
18, 19, 20, 21
24
Receive Data: These are the four parallel receive data lines aligned on the
nibble boundaries driven synchronously to the RXC for reception by the
external physical unit (PHY).
RXER/
FXEN
O/LI
Receive error: if any 5B decode error occurs, such as invalid J/K, T/R,
invalid symbol, this pin will go high.
Fiber/UTP Enable: During power on reset, this pin status is latched to
determine at which media mode to operate:
1: Fiber mode
0: UTP mode
An internal weak pull low resistor, sets this to the default of UTP mode. It is
possible to use an external 5.1KΩ pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
Management Data Clock: This pin provides a clock synchronous to MDIO,
which may be asynchronous to the transmit TXC and receive RXC clocks.
The clock rate can be up to 2.5MHz.
MDC
I
25
MDIO
I/O
26
Management Data Input/Output: This pin provides the bi-directional
signal used to transfer management information.
5.2 SNI (Serial Network Interface): 10Mbps only
Symbol
Type
Pin No.
Description
COL
O
1
21
23
16
6
Collision Detect
Received Serial Data
Carrier Sense
Receive Clock: Resolved from received data
Transmit Serial Data
Transmit Clock: Generate by PHY
Transmit Enable: For MAC to indicate transmit operation
RXD0
CRS
O
O
RXC
O
TXD0
TXC
I
O
7
TXEN
I
2
2002-03-29
Rev.1.2
5
RTL8201BL
5.3 Clock Interface
Symbol
Type
Pin No.
Description
X2
O
47
25MHz Crystal Output: This pin provides the 25MHz crystal output. It
must be left open when X1 is driven with an external 25MHz oscillator.
25MHz Crystal Input: This pin provides the 25MHz crystal input. If a
25MHz oscillator is used, connect X1 to the oscillator’s output. Refer to
section 8.3 to obtain clock source specifications.
X1
I
46
5.4 100Mbps Network Interface
Symbol
Type
Pin No.
Description
TPTX+
O
34
Transmit Output: Differential pair shared by 100Base-TX, 100Base-FX and
10Base-T modes. When configured as 100Base-TX, output is an MLT-3
encoded waveform. When configured as 100Base-FX, the output is
pseudo-ECL level.
TPTX-
RTSET
O
33
I
28
Transmit Bias Resistor Connection: This pin should be pulled to GND by
a 5.9KΩ (1%) resistor to define driving current for transmit DAC. The
resistance value may be changed, depending on experimental results of the
RTL8201BL.
TPRX+
TPRX-
I
I
31
30
Receive Input: Differential pair shared by 100Base-TX, 100Base-FX, and
10Base-T modes.
5.5 Device Configuration Interface
Symbol
Type
Pin No.
Description
ISOLATE
I
43
Set high to isolate the RTL8201BL from the MAC. This will also isolate the
MDC/MDIO management interface. In this mode, the power consumption is
minimum. This pin can be directly connected to GND or VCC.
RPTR
I
40
39
Set high to put the RTL8201BL into repeater mode. This pin can be directly
connected to GND or VCC.
SPEED
LI
This pin is latched to input during a power on or reset condition. Set high to
put the RTL8201BL into 100Mbps operation. This pin can be directly connected
to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable full duplex. This pin can be directly connected to GND or VCC.
This pin is latched to input during a power on or reset condition. Set high to
enable Auto-negotiation mode, set low to force mode. This pin can be directly
connected to GND or VCC.
Set high to put the RTL8201BL into LDPS mode. This pin can be directly
connected to GND or VCC. Refer to Section 7.7 for more information.
This pin is latched to input during a power on or reset condition. Pull high to
set the RTL8201BL into MII mode operation. Set low for SNI mode. This pin
can be directly connected to GND or VCC. In test mode, this pin is an output pin and
redefined as RTT3
DUPLEX
ANE
LI
LI
38
37
LDPS
I
41
44
MII/SNIB/
RTT3(test)
LI/O
2002-03-29
Rev.1.2
6
RTL8201BL
5.6 LED Interface/PHY Address Config
These five pins are latched into the RTL8201BL during power up reset to configure PHY address [0:4] used for MII
management register interface. And then, in normal operation after initial reset, they are used as driving pins for status
indication LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0]
during power-up reset. If latched status is High then it will be active low, and if latched status is Low then it will be active high.
Refer to Section 7.5 for more information.
Symbol
PHYAD0/
LED0
Type
LI/O
Pin No.
Description
9
PHY Address [0]
Link LED: Active when linked.
PAD1/
LI/O
LI/O
10
12
PHY Address [1]
LED1
PHYAD2/
LED2
Full Duplex LED: Active when in Full Duplex operation.
PHY Address [2]
Link 10/ACT LED: Active when linked in 10Base-T mode, and blinking
when transmitting or receiving data.
PHYAD3/
LED3
LI/O
LI/O
13
15
PHY Address [3]
Link 100/ACT LED: Active when linked in 100Base-TX and blinking
when transmitting or receiving data.
PHYAD4/
LED4
PHY Address [4]
Collision LED: Active when collisions occur.
5.7 Reset and other pins
Symbol
Type
Pin No.
Description
RESETB
I
42
RESETB: Set low to reset the chip. For a complete reset function, this pin
must be asserted low for at least 10ms.
PWFBOUT
O
I
32
Power Feedback Output: Be sure to connect a 22uF tantalum capacitor for
frequency compensation and a 0.1uF capacitor for noise de-coupling. Then
connect this pin through a ferrite bead to PWFBIN(pin8). The connection
method is figured in section 7.11.
Power Feedback Input: see the description of PWFBOUT.
Not connection
PWFBIN
NC
8
27
5.8 Power and Ground pins
Symbol
AVDD33
Type
P
Pin No.
Description
3.3V Analog power input: 3.3V power supply for analog circuit; should be
well decoupled.
Analog Ground: Should be connected to a larger GND plane
3.3V Digital Power input: 3.3V power supply for digital circuit.
Digital Ground: Should be connected to a larger GND plane.
36
AGND
DVDD33
DGND
P
P
P
29,35
14,48
11,17,45
2002-03-29
Rev.1.2
7
RTL8201BL
6. Register Descriptions
This section will describe definitions and usage for each of the registers available in the RTL8201BL.
6.1 Register 0 Basic Mode Control Register
Address
Name
Description/Usage
Default/Attribute
0:<15>
Reset
This bit sets the status and control registers of the
PHY in a default state. This bit is self-clearing.
1 = software reset
0, RW
0, RW
1, RW
0 = normal operation
0:<14>
0:<13>
Loopback
Spd_Set
This bit enables loopback of transmit data nibbles
TXD<3:0> to the receive data path.
1 = enable loopback
0 = normal operation
This bit sets the network speed.
1 = 100Mbps
0 = 10Mbps
When 100Base-FX mode is enabled, this bit=1 and is
read only.
0:<12>
Auto
Negotiation
Enable
This bit enables/disables the Nway auto-negotiation
function.
1, RW
1 = enable auto-negotiation; bits 0:<13> and 0:<8>
will be ignored.
0 = disable auto-negotiation; bits 0:<13> and 0:<8>
will determine the link speed and the data transfer
mode, respectively.
When 100Base-FX mode is enabled, this bit=0 and is
read only.
0:<11>
Power Down This bit turns down the power of the PHY chip
including internal crystal oscillator circuit. The MDC,
MDIO is still alive for accessing the MAC.
1 = power down
0, RW
0 = normal operation
0:<10>
0:<9>
Reserved
Restart Auto This bits allows the Nway auto-negotiation function
0, RW
1, RW
Negotiation
to be reset.
1 = re-start auto-negotiation
0 = normal operation
0:<8>
Duplex Mode This bit sets the duplex mode if auto negotiation is
disabled (bit 0:<12>=0)
1 = full duplex
0 = half duplex
After completing auto negotiation, this bit will reflect
the duplex status.(1: Full duplex, 0: Half duplex)
When 100Base-FX mode is enabled, this bit can be
set through the MDC/MDIO SMI interface or
DUPLEX pin.
0:<7:0>
Reserved
2002-03-29
Rev.1.2
8
RTL8201BL
6.2 Register 1 Basic Mode Status Register
Address
1:<15>
Name
100Base-T4
Description/Usage
1 = enable 100Base-T4 support
0 = suppress 100Base-T4 support
Default/Attribute
0, RO
1, RO
1, RO
1, RO
1, RO
1:<14>
1:<13>
1:<12>
1:<11>
100Base_TX_ 1 = enable 100Base-TX full duplex support
FD 0 = suppress 100Base-TX full duplex support
100BASE_TX_ 1 = enable 100Base-TX half duplex support
HD
0 = suppress 100Base-TX half duplex support
10Base_T_FD 1 = enable 10Base-T full duplex support
0 = suppress 10Base-T full duplex support
10_Base_T_HD 1 = enable 10Base-T half duplex support
0 = suppress 10Base-T half duplex support
Reserved
1:<10:7>
1:<6>
MF Preamble The RTL8201BL will accept management frames
1, RO
Suppression
with preamble suppressed. The RTL8201BL accepts
management frames without preamble. A Minimum
of 32 preamble bits are required for the first SMI
read/write transaction after reset. One idle bit is
required between any two management transactions
as per IEEE802.3u specifications
1:<5>
1:<4>
Auto
1 = auto-negotiation process completed
0, RO
0, RO
Negotiation
Complete
0 = auto-negotiation process not completed
Remote Fault 1 = remote fault condition detected (cleared on read)
0 = no remote fault condition detected
When in 100Base-FX mode, this bit means an
in-band signal Far-End-Fault is detected. Refer to
Section 7.11.
1:<3>
1:<2>
1:<1>
1:<0>
Auto
1 = Link had not been experienced fail state
0 = Link had been experienced fail state
1 = valid link established
1, RO
0, RO
0, RO
1, RO
Negotiation
Link Status
0 = no valid link established
Jabber Detect 1 = jabber condition detected
0 = no jabber condition detected
Extended
Capability
1 = extended register capability
0 = basic register capability only
6.3. Register 2 PHY Identifier Register 1
Address
2:<15;0>
Name
PHYID1
Description/Usage
PHY identifier ID for software recognize
RTL8201BL
Default/Attribute
0000, RO
6.4. Register 3 PHY Identifier Register 2
Address
Name
Description/Usage
Default/Attribute
3:<15;0>
PHYID2
PHY identifier ID for software recognize RTL8201
8201, RO
2002-03-29
Rev.1.2
9
RTL8201BL
6.5. Register 4 Auto-negotiation Advertisement Register(ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during
Auto-negotiation.
Address
Name
Description/Usage
Default/Attribute
4:<15>
NP
Next Page bit.
0, RO
0 = transmitting the primary capability data page
1 = transmitting the protocol specific data page
1 = acknowledge reception of link partner capability
data word
4:<14>
4:<13>
ACK
RF
0, RO
0, RW
0 = do not acknowledge reception
1 = advertise remote fault detection capability
0 = do not advertise remote fault detection capability
4:<12:11>
4:<10>
Reserved
Pause
1 = flow control is supported by local node
0 = flow control is NOT supported by local node
1 = 100Base-T4 is supported by local node
0 = 100Base-T4 not supported by local node
1 = 100Base-TX full duplex is supported by local node
0 = 100Base-TX full duplex not supported by local node
1 = 100Base-TX is supported by local node
0 = 100Base-TX not supported by local node
1 = 10Base-T full duplex supported by local node
0 = 10Base-T full duplex not supported by local node
1 = 10Base-T is supported by local node
0, RW
0, RO
4:<9>
4:<8>
4:<7>
4:<6>
4:<5>
4:<4:0>
T4
TXFD
TX
1, RW
1, RW
10FD
10
1, RW
1, RW
0 = 10Base-T not supported by local node
Selector
Binary encoded selector supported by this node.
Currently only CSMA/CD <00001> is specified. No
other protocols are supported.
<00001>, RW
6.6 Register 5 Auto-Negotiation Link Partner Ability
Register(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes
after the successful Auto-negotiation if Next-pages are supported.
Address
Name
Description/Usage
Default/Attribute
5:<15>
NP
Next Page bit.
0, RO
0 = transmitting the primary capability data page
1 = transmitting the protocol specific data page
1 = link partner acknowledges reception of local
node’s capability data word
5:<14>
5:<13>
ACK
RF
0, RO
0, RO
0 = no acknowledgement
1 = link partner is indicating a remote fault
0 = link partner does not indicate a remote fault
5:<12:11>
5:<10>
Reserved
Pause
1 = flow control is supported by Link partner
0 = flow control is NOT supported by Link partner
1 = 100Base-T4 is supported by link partner
0, RO
0, RO
0, RO
5:<9>
5:<8>
T4
0 = 100Base-T4 not supported by link partner
1 = 100Base-TX full duplex is supported by link partner
0 = 100Base-TX full duplex not supported by link partner
TXFD
2002-03-29
Rev.1.2
10
RTL8201BL
5:<7>
100BASE-TX 1 = 100Base-TX is supported by link partner
0 = 100Base-TX not supported by link partner
This bit will also be set after the link in 100Base is
established by parallel detection.
1, RO
5:<6>
5:<5>
10FD
1 = 10Base-T full duplex is supported by link partner
0 = 10Base-T full duplex not supported by link partner
1 = 10Base-T is supported by link partner
0, RO
0, RO
10Base-T
0 = 10Base-T not supported by link partner
This bit will also be set after the link in 10Base is
established by parallel detection.
5:<4:0>
Selector
Link Partner’s binary encoded node selector
Currently only CSMA/CD <00001> is specified
<00000>, RO
6.7 Register 6 Auto-negotiation Expansion Register(ANER)
This register contains additional status for NWay auto-negotiation.
Address
6:<15:5>
6:<4>
Name
Reserved
MLF
Description/Usage
Default/Attribute
This bit is always set to 0.
Status indicating if a multiple link fault has occurred.
1 = fault occurred
0, RO
0 = no fault occurred
6:<3>
LP_NP_ABLE Status indicating if the link partner supports Next
0, RO
Page negotiation.
1 = supported
0 = not supported
6:<2>
6:<1>
NP_ABLE
PAGE_RX
This bit indicates if the local node is able to send
additional Next Pages.
0, RO
0, RO
This bit is set when a new Link Code Word Page has
been received. It is automatically cleared when the
auto-negotiation link partner’s ability register
(register 5) is read by management.
6:<0>
LP_NW_ABLE 1 = link partner supports Nway auto-negotiation.
0, RO
6.8 Register 16 Nway Setup Register(NSR)
Address
16:<15:12>
16:<11>
16:<10>
16:<9>
Name
Description/Usage
Default/Attribute
Reserved
ENNWLE
Testfun
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
1 = LED4 Pin indicates linkpulse
1 = Auto-neg speeds up internal timer
1 = set Nway to loopback mode.
0, RW
0, RW
0, RW
16:<8;3>
16:<2>
1 = Auto-neg experienced ability detect state
1 = Auto-neg experienced parallel detection fault state
1 = Auto-neg experienced link status check state
0, RO
0, RO
0, RO
16:<1>
16:<0>
2002-03-29
Rev.1.2
11
RTL8201BL
6.9 Register 17 Loopback, Bypass, Receiver Error Mask
Register(LBREMR)
Address
17:<15>
17:<14>
Name
RPTR
Description/Usage
Set to 1 to put the RTL8201BL into repeater mode
Assertion of this bit allows bypassing of the 4B/5B &
5B/4B encoder.
Default/Attribute
0, RW
BP_4B5B
0, RW
17:<13>
BP_SCR
Assertion of this bit allows bypassing of the
scrambler/descrambler.
0, RW
17:<12>
17:<11>
LDPS
AnalogOFF
Set to 1 to enable Link Down Power Saving mode
Set to 1 to power down analog function of transmitter
and receiver.
0, RW
0, RW
17:<10>
17:<9:8>
DetectLength Detect length OK indication. Assert low to indicate
detect length OK.
LB<1:0>
0, RO
LB<1:0> are register bits for loopback control as
defined below:
<0, 0>, RW
1) 0 0 for normal mode;
2) 0 1 for PHY loopback;
3) 1 0 for twister loopback
17:<7>
F_Link_100
Used to logic force good link in 100Mbps for
diagnostic purposes.
1, RW
17:<6:5>
17:<4>
Reserved
CODE_err
Assertion of this bit causes a code error detection to
be reported.
0, RW
0, RW
0, RW
0, RW
0, RW
17:<3>
17:<2>
17:<1>
17:<0>
PME_err
LINK_err
PKT_err
RWPara
Assertion of this bit causes a pre-mature end error
detection to be reported.
Assertion of this bit causes a link error detection to be
reported.
Assertion of this bit causes a detection of packet
errors due to 722 ms time-out to be reported.
Parameter access enable, set 1 to access register
20~24
6.10 Register 18 RX_ER Counter(REC)
Address
18:<15:0>
Name
RXERCNT
Description/Usage
This 16-bit counter increments by 1 for each valid
packet received.
Default/Attribute
H’[0000],
RW
6.11 Register 19 10Mbps Network Interface Configuration Register
Address
19:<15:6>
19:<5>
Name
Reserved
LD
Description/Usage
Default/Attribute
This bit is the active low TPI link disable signal.
When low TPIstilltransmit link pulses and TPI stays
in good link state.
1, RW
19:<4:2>
19:<1>
19:<0>
Reserved
HBEN
JBEN
Heart beat enable
1 = enable jabber function
0 = disable jabber function
1, RW
1, RW
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6.12 Register 20 PHY 1_1 Register
Address
Name
Description/Usage
Default/Attribute
20:<15:0>
PHY1_1
PHY 1 register (functions as RTL8139C<78>)
R/W
6.13 Register 21 PHY 1_2 Register
Address
Name
Description/Usage
Default/Attribute
21:<15:0>
PHY1_2
PHY 1 register (functions as RTL8139C<78>)
R/W
6.14 Register 22 PHY 2 Register
Address
22<15:8>
Name
PHY2_76
Description/Usage
PHY2 register for cable length test (functions as
RTL8139C<76>)
PHY2 register for PLL select (functions as
RTL8139C<80>)
Default/Attribute
RO
22:<7:0>
PHY2_80
R/W
6.15 Register 23 Twister_1 Register
Address
Name
Description/Usage
Default/Attribute
23:<15:0>
TW_1
Twister register (functions as RTL8139C<7c>)
R/W
6.16 Register 24 Twister_2 Register
Address
Name
Description/Usage
Default/Attribute
24:<15:0>
TW_2
Twister register (functions as RTL8139C<7c>)
R/W
6.17 Register 25 Test Register
Address
25<15:14>
25<13>
Name
Test
Reserved
Description/Usage
Reserved for internal testing
Default/ Attribute
R/W
25:<12:8> PHYAD[4:0] Reflects the PHY address defined by external PHY
address configuration pins
RO
25<7:2>
25<1>
Test
LINK10
Reserved for internal testing
RO
RO
1: Link established in 10Base OK
0: No link established in 10Base
1: Link established in 100Base OK
0: No link established in 100Base
25<0>
LINK100
RO
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7. Functional Description
The RTL8201BL Phyceiver is a physical layer device that integrates 10Base-T and 100Base-TX functions and some extra
power manage features into a 48 pin single chip which is used in 10/100 Fast Ethernet applications. This device supports the
following functions:
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
MII interface with MDC/MDIO SMI management interface to communicate with MAC
IEEE 802.3u clause 28 Auto-Negotiation ability
Flow control ability support to cooperate with MAC
Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO.
Flexible LED configuration.
7-wire SNI(Serial Network Interface) support, works only on 10Mbps mode.
Power Down mode support
4B/5B transform
Scrambling/De-scrambling
NRZ to NRZI, NRZI to MLT3
Manchester Encode and Decode for 10 BaseT operation
Clock and Data recovery
Adaptive Equalization
Far End Fault Indication (FEFI) in fiber mode
7.1 MII and Management Interface
7.1.1 Data Transition
To set the RTL8201BL for MII mode operation, pull MII/SNIB pin high and properly set the ANE, SPEED, and DUPLEX pins.
The MII (Media Independent Interface) is an 18-signal interface which is described in IEEE 802.3u supplying a standard
interface between PHY and MAC layer. This interface operates in two frequencies – 25Mhz and 2.5Mhz to support
100Mbps/10Mbps bandwidth for both the transmit and receive function. While transmitting packets, the MAC will first assert
the TXEN signal and change byte data into 4 bits nibble and pass to the PHY by TXD[0..3]. PHY will sample TXD[0..]
synchronously with TXC — the transmit clock signal supplied by PHY – during the interval TXEN is asserted. While
receiving a packet, the PHY will assert the RXEN signal, pass the received nibble data RXD[0..3] clocked by RXC, which is
recovered from the received data. CRS and COL signals are used for collision detection and handling.
In 100Base-TX mode, when decoded signal in 5B is not IDLE, the CRS signal will assert and when 5B is recognized as IDLE
it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble been confirmed and will be de-asserted
when the IDLE pattern been confirmed.
The RXDV signal will be asserted when decoded 5B are /J/K/and will be deasserted if the 5B are /T/R/or IDLE in 100Mbps
mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur such as invalid J/K, T/R, invalid symbol, this
pin will go high for one or more clock period to indicate to the reconciliation sublayer that an error was detected somewhere in
the frame.
The RTL8201BL does not use the TXER signal and will not affect the transmit function.
7.1.2 Serial Management
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 31 RTL8201BL devices,
configured with different PHY addresses (00001b to 11111b). During a hardware reset, the logic levels of pins 9,10,12,13,15
are latched into the RTL8201BL to be set as the PHY address for serial management interface communication. Setting the
PHY address to 00000b will put the RTL8201BL into power down mode. The read and write frame structure for the
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management interface follows.
M DC
M DIO
0
1
0
1
A4
A3
A2
A1
A0
R4
R3
R2
R1
R0
1
0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
321s
Preamble
ST
OP
PHYAD[4:0]
REGAD[4:0]
TA
DATA
Idle
M DIO issourcedbyM AC.ClockdataintoPHY onrisingedgeofM DC
Write Cycle
M DC
Z
M DIO
0
1
1
0
A4
A3
A2
A1
A0
R4
R3
R2
R1
R0
0
D15 D14 D13 D12 D11 D10 D9
D8
DATA
M DIO issourcedbyPHY.Clockdatafrom PHY onrisingedgeofM DC
D7
D6
D5
D4
D3
D2
D1
D0
321s
Preamble
ST
OP
PHYAD[4:0]
REGAD[4:0]
TA
Idle
M DIO issourcedbyM AC.ClockdataintoPHY onrisingedgeofM DC
Read Cycle
Preamble 32 contiguous logic '1's sent by the MAC on MDIO along with 32 corresponding cycles on MDC. This
provides synchronization for the PHY.
ST
OP
Start of Frame. Indicated by a 01 pattern.
Operation code. Read = 10. Write = 01.
PHYAD PHY Address. Up to 31 PHYs can be connected to one MAC. This 5 bit field selects which PHY the frame is
directed to.
REGAD Register Address. This is a 5 bit field that selects which one of the 32 registers of the PHY this operation refers to.
TA
Turnaround. This is a two bit time spacing between the register address and the data field of a frame to avoid
contention during a read transaction. For a read transaction, both the STA and the PHY shall remain in a
high-impedance state for the first bit time of the turnaround. The PHY shall drive a zero bit during the second
bit time of the turnaround of a read transaction.
DATA
IDLE
Data. These are the 16 bits of Data.
Idle Condition, not actually part of the management frame. This is a high impedance state. Electrically, the
PHY's pull-up resistor will pull the MDIO line to a logic one.
7.2 Auto-negotiation and Parallel Detection
The RTL8201BL supports IEEE 802.3u clause 28 Auto-negotiation operation which can cooperate with other transceivers
supporting auto-negotiation. By this mechanism, the RTL8201BL can auto detect the link partner’s ability and determine the
highest speed/duplex configuration and transmit/receive in this configuration. If the link partner does not support
Auto-negotiation, then the RTL8201BL will enable half duplex mode and enter parallel detection. The RTL8201BL will
default to transmit FLP and wait for the link partner to respond. If the RTL8201BL receives FPL, then the auto-negotiation
process will go on. If it receives NLP, then the RTL8201BL will change to 10Mbps and half duplex mode. If it receives a
100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode.
To enable the auto-negotiation mode operation on the RTL8201BL, just pull the ANE pin high. And the SPEED pin and
DUPLEX pin will set the ability content of auto-negotiation register. The auto-negotiation mode can be externally disabled by
pulling the ANE pin low. In this case, the SPEED pin and DUX pin will change the media configuration of the RTL8201BL.
Below is a list for all configurations of the ANE/SPEED/DUPLEX pins and their operation in Fiber or UTP mode.
Select Medium type and interface mode to MAC
FX
MII/SNIB
Operation mode
(pin 24)
(pin 44)
L
L
H
H
L
UTP mode and MII interface
UTP mode and SNI interface
Fiber mode and MII interface
X
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UTP mode and MII interface
ANE
SPEED
DUPLEX
Operation
(Pin 37)
(Pin 39)
(Pin 38)
Auto-negotiation enable, the ability field does not support 100Mbps and full duplex
mode operation
Auto-negotiation enable, the ability field does not support 100Mbps operation
Auto-negotiation enable, the ability field does not support full duplex mode operation
Default setup, auto-negotiation enable, the RTL8201BL will support 10BaseT
/100BaseTX, half/full duplex mode operation
Auto-negotiation disable, force the RTL8201BL into 10BaseT and half duplex mode
Auto-negotiation disable, force the RTL8201BL into 10BaseT and full duplex mode
Auto-negotiation disable, force the RTL8201BL into 100BaseTX and half duplex mode
Auto-negotiation disable, force the RTL8201BL into 100BaseTX and full duplex mode
H
L
L
H
H
L
H
H
L
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
UTP mode and SNI interface
SNI interface to MAC. It only works in 10Base-T when the SNI interface is enabled.
ANE
(Pin 37)
X
SPEED
(Pin 39)
X
DUPLEX
(Pin 38)
L
Operation
The duplex pin is pulled low to support the 10Base-T half duplex function.10Base-T
half duplex is the specified default mode in the SNI interface.
The RTL8201BL also supports full duplex in SNI mode. The duplex pin is pulled high
to support 10Base-T full duplex function.
X
X
H
Fiber mode and MII interface
The RTL8201BL only supports 100Base-FX when Fiber mode is enabled. Ignore ANE and Speed hardwire configuration.
ANE
(Pin 37)
X
SPEED
(Pin 39)
X
DUPLEX
Operation
(Pin 38)
H
L
The duplex pin is pulled high to support 100Base-FX full duplex function.
The duplex pin is pulled low to support 100Base-FX half duplex function.
X
X
7.3 Flow control support
The RTL8201BL supports flow control indications. The MAC can program the MII register to indicate to the PHY that flow
control is supported. When MAC supports the Flow Control mechanism, setting bit 10 of the ANAR register by MDC/MDIO
SMI interface, then the RTL8201BL will add the ability to its N-Way ability. If the Link partner also supports Flow Control,
then the RTL8201BL can recognize the Link partner’s N-Way ability by examining bit 10 of ANLPAR (register 5).
7.4 Hardware Configuration and Auto-negotiation
This section describes methods to configure the RTL8201BL and set the auto-negotiation mode. This list will show the various
pins and their setting to provide the desired result.
1) Isolate pin: Set high to isolate the RTL8201BL from the MAC. This will also isolate the MDC/MDIO management
interface. In this mode, power consumption is minimum. Please refer to the section covering Isolation mode and Power
Down mode.
2) RPTR pin: Pull high to set the RTL8201BL into repeater mode. This pin is pulled low by default. Please refer to the
section covering Repeater mode operation.
3) LDPS pin: Pull high to set the RTL8201BL into LDPS mode. This pin is pulled low by default. Please refer to the section
covering Power Down mode and Link Down Power Saving.
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RTL8201BL
4) MII/SNIB: Pull high to set RTL8201BL into MII mode operation, which is the default mode for the RTL8201. This pin
pulled low will set the RTL8201BL into SNI mode operation. When set to SNI mode, the RTL8201BL will work at
10Mbps. Please refer to the section covering Serial Network Interface for more detail information.
5) ANE pin: Pull high to enable Auto-negotiation (default). Pull low to disable auto-negotiation and activate the parallel
detection mechanism. Please refer to the section covering Auto-negotiation and Parallel Detection
6) Speed pin: When ANE is pulled high, the ability to adjust speed is setup. When ANE is pulled low, pull this pin low to
force 10Mbps operation and high to force 100Mbps operation. Please refer to the section on Auto-negotiation and Parallel
Detection.
7) DUPLEX pin: When ANE is pulled high, the ability to adjust the DUPLEX pin will be setup. When ANE is pulled low,
pull this pin low to force half duplex and high to force full duplex operation. Please refer to the section covering
Auto-negotiation and Parallel Detection.
7.5 LED and PHY Address Configuration
In order to reduce the pin count on the RTL8201BL, the LED pins are duplexed with the PHY address pins. Because the
PHYAD strap options share the LED output pins, the external combinations required for strapping and LED usage must be
considered in order to avoid contention. Specifically, when the LED outputs are used to drive LEDs directly, the active state of
each output driver is dependent on the logic level sampled by the corresponding PHYAD input upon power-up/reset. For
example, as following left figure shows, if a given PHYAD input is resistively pulled high then the corresponding output will
be configured as an active low driver. As right figure shows, if a given PHYAD input is resistively pulled low then the
corresponding output will be configured as an active high driver. The PHY address configuration pins should not be connected
to GND or VCC directly, but must be pulled high or low through a resistor (ex 5.1KΩ). If no LED indications are needed, the
components of the LED path (LED+510Ω) can be removed.
VCC
PAD[0:4]/
LED[0:4]
LED
LED
5.1K ohm
510 ohm
510 ohm
5.1K ohm
PAD[0:4]/
LED[0:4]
PHY address[:] = logic 1
PHY address[:] = logic 0
LED indication = active low
LED indication = active High
LED0 Link
LED1 Full Duplex
LED2 Link 10-Activity
LED3 Link 100-Activity
LED4 Collision
LED Definitions
7.6 Serial Network Interface
The RTL8201BL also supports the traditional 7-wire serial interface to cooperate with legacy MACs or embedded systems. To
setup for this mode of operation, pull the MII/SNIB pin low and by doing so, the RTL8201BL will ignore the setup of the
ANE and SPEED pins. In this mode, the RTL8201BL will set the default to work in 10Mbps and Half-duplex mode. But the
RTL8201BL may also support full duplex mode operation if the DUPLEX pin has been pulled high.
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RTL8201BL
This interface consists of 10Mbps transmit and receive clock generated by PHY, 10Mbps transmit and receive serial data,
transmit enable, collision detect, and carry sense signals.
7.7 PowerDown,LinkDown,PowerSaving,andIsolationModes
The RTL8201BL supplies 4 kinds of Power Saving mode operation. This section will discuss all four, including how to
implement each mode. The first three modes are configured through software, and the fourth through hardware.
1) Analog off: Setting bit 11 of register 17 to 1 will put the RTL8201BL into analog off state. In analog off state, the
RTL8201BL will power down all analog functions such as transmit, receive, PLL, etc. However, the internal 25MHz
crystal oscillator will not be powered down. The digital functions in this mode are still available which allows
reacquisition of analog functions.
2) LDPS mode: Setting bit 12 of register 17 to 1 or pulling the LDPS pin high will put the RTL8201BL into LDPS (Link
Down Power Saving) mode. In LDPS mode, the RTL8201BL will detect the link status to decide whether or not to turn
off the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted. However, some
signals similar to NLP will be transmitted. Once the receiver detects any leveled signals, it will stop the signal and
transmit FLP or 100Mbps IDLE/10Mbps NLP again. This may save about 60%~80% power when the link is down.
3) PWD mode: Setting bit 11 of register 0 to 1 will put the RTL8201BL into power down mode. This is the maximum power
saving mode while the RTL8201BL is still alive. In PWD mode, the RTL8201BL will turn off all analog/digital functions
except the MDC/MDIO management interface. Therefore, if the RTL8201BL is put into PWD mode and the MAC wants
to recall the PHY, it must create the MDC/MDIO timing by itself (this is done by software).
4) Isolation mode: This mode is different from the three previous software configured power saving modes. This mode is
configured by hardware pin 43. Setting pin 43 high will isolate the RTL8201BL from the Media Access Controller (MAC)
and the MDC/MDIO management interface. In this mode, power consumption is minimum.
7.8 Media Interface
7.8.1 100Base TX
1) 100Base-TX Transmit Function: The 100Base-TX transmit function is performed as follows: First the transmit data in 4
bit nibbles (TXD[3:0]), clocked in 25MHz (TXC) will be transformed into 5B symbol code, called 4B/5B encoding.
Scrambling, serializing and conversion to 125Mhz, and NRZ to NRZI will then take place. After this process, the NRZI
signal will pass to the MLT3 encoder, then to the transmit line driver. The transmitter will first assert TXEN. Before
transmitting the data pattern, it will send a /J/K/ symbol (Start-of-frame delimiter), the data symbol, and finally a /T/R/
symbol known as the End-Of-Frame delimiter. The 4B/5B and the scramble process can be bypassed by setting the PHY
register. For better EMI performance consideration, the seed of the scrambler is related to the PHY address. Therefore in a
hub/switch environment, every RTL8201BL will be set into a different PHY address so that they will use different
scrambler seeds, which will spread the output of the MLT3 signals.
2) 100Base-TX Receive Function: The 100Base-TX receive function is performed as follows: The received signal will first
be compensated by the adaptive equalizer to make up for the signal loss due to cable attenuation and ISI. The Baseline
Wander Corrector will monitor the process and dynamically apply corrections to the process of signal equalization. The
PLL will then recover the timing information from the signals and form the receive clock. With this, the received signal
may be sampled to form NRZI data. The next steps are the NRZI to NRZ process, unscrambling of the data, serial to
parallel and 5B to 4B conversion and passing of the 4B nibble to the MII interface.
7.8.2 100Base-FX Fiber Mode Operation
RTL8201BL can be configured as 100Base-FX by hardware configuration. The priority of setting 100Base-FX is greater than
Nway. Scrambler is not needed in 100Base-FX.
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RTL8201BL
1) 100Base-FX Transmit Function: The 100Base-FX transmit function is performed as follows: Di-bits of TXD are
processed as 100Base-TX, except without scrambler before the NRZI stage. Instead of converting to MLT-3 signals, as in
100Base-TX, the serial data stream is driven out as NRZI PECL signals, which enter the fiber transceiver in
differential-pairs form.
2) In 100Base-FX Receive Function: The 100Base-FX receive function is performed as follows: The signal is received
through PECL receiver inputs from the fiber transceiver, and directly passed to the clock recovery circuit for data/clock
recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
7.8.3 10Base Tx/Rx
1) 10Base Transmit Function: The 10Base transmit function is performed as follows: The transmit 4 bits nibbles(TXD[0:3])
clocked in 2.5MHz(TXC) is first feed to parallel to serial converter, then put the 10Mbps NRZ signal to Manchester
coding. The Manchester encoder converts the 10 Mbps NRZ data into a Manchester Encoded data stream for the TP
transmitter and adds a start of idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Then, the encoded data
stream is shaped by band- limited filter embedded in RTL8201BL and then transmitted to TP line.
2) 10Base Receive function: The 10Base receive function is performed as follows: In 10Base receive mode, The
Manchester decoder in RTL8201BL converts the Manchester encoded data stream from the TP receiver into NRZ data by
decoding the data and stripping off the SOI pulse. Then, the serial NRZ data stream is converted to parallel 4 bit nibble
signal(RXD[0:3]).
7.9 Repeater Mode Operation
Setting bit 15 of register 17 to 1 or pulling the RPTR pin high will set the RTL8201BL into repeater mode. In repeater mode,
the RTL8201BL will assert CRS high only when receiving a packet. In NIC mode, the RTL8201BL will assert CRS high both
in transmitting and receiving packets. If using the RTL8201BL in a repeater, please set the RTL8201BL to Repeater mode, and
if using the RTL8201BL in a NIC or switch application, please set the default mode. NIC/Switch mode is the default setting
and has the RPTR pin pulled low or bit 15 of register 17 is set to 0.
7.10 Reset, and Transmit Bias(RTSET)
The RTL8201BL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by
setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the registers and re-initialize them, and the media
interface will first disconnect and restart the auto-negotiation/parallel detection process.
The RTSET pin must be pulled low by a 5.9KΩ resister with 1% accuracy to establish an accurate transmit bias, this will affect
the signal quality of the transmit waveform. Keep it’s circuitry away from other clock traces or transmit/receive paths to avoid
signal interference.
7.11 3.3V power supply and voltage conversion circuit
RTL8201BL is fabricated in 0.25um process. The core circuit needs to be powered by 2.5V , however, the circuit of digital IO
and DAC need 3.3V power supply. RTL8201BL has embedded a regulator to convert 3.3V to 2.5V. Just like many commercial
voltage conversion devices, The 2.5V output pin(PWFBOUT) of this circuit requires the use of an output capacitor(22uF
tantalum capacitor) as part of the device frequency compensation and another small capacitor(0.1uF) for high frequency noise
de-coupling. And PWFBIN is fed with the 2.5V power from PWFBOUT through a ferrite bead as below figure shown.
Strongly emphasize here, could not provide external 2.5V produced by any other power device for PWFBOUT and PWFBIN.
The analog and digital Ground planes should be as large and intact as possible. If the ground plane is large enough, the analog
and digital grounds can be separated, which is a more ideal configuration. However, if the total ground plane is not sufficiently
large, partition of the ground plane is not a good idea. In this case, all the ground pins can be connected together to a larger
single and intact ground plane.
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RTL8201B(L)
DVDD33(pin14)
AVDD33(pin36)
Ferrite Bead
3.3V-drived
circuit
3.3V
3.3V
0.1uF
0.1uF
DVDD33(pin48)
Error Amp
-
+
MOSFET P
0.1uF
PWFBOUT(pin32)
Ferrite Bead
1.2V
bandgap
voltage
22uF
0.1uF
PWFBIN(pin8)
2.5V-drived
circuit
0.1uF
7.12 Far End Fault Indication (FEFI)
The MII Reg.1.4 (Remote Fault) is the FEFI bit when 100FX mode is enabled which indicates that FEFI has
been detected. FEFI is an alternative in-band signaling method which is composed of 84 consecutive ‘1’
followed by one ‘0’. From the point of view of the RTL8201BL, when this pattern is detected three times,
Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On the other hand,
the incoming signal failure in causing a link OK will force the RTL8201BL to start sending this pattern, which
in turn causes the remote side to detect a Far-End-Fault. This means that the receive path has a problem from the
point of view of the RTL8201BL. The FEFI mechanism is used only in 100Base-FX mode.
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8. Electrical Characteristics
8.1 D.C. Characteristics
8.1.1. Absolute Maximum Ratings
Symbol
Supply Voltage
Storage Temp.
Conditions
Minimum
3.0V
-55°C
Typical
3.3V
Maximum
3.6V
125°C
8.1.2. Operating Conditions
Symbol
Vcc 3.3V
TA
Conditions
3.3V Supply voltage
Operating Temperature
Minimum
3.0V
Typical
3.3V
Maximum
3.6V
0°C
70°C
8.1.3. Power Dissipation
Test condition: VCC=3.3V
Symbol
Condition
Total Current Consumption
PLDPS
PAnaOff
PPWD
PIsolate
P100F
Link down power saving mode
Analog off mode
Power down mode
Isolate mode
17 mA
13 mA
3 mA
3 mA
100Base full duplex
10Base full duplex
10Base transmit
64 mA
82 mA
82 mA
25 mA
24 mA
P10F
P10TX
P10RX
P10IDLE
10Base receive
10Base idle
8.1.4 Supply Voltage: Vcc
Symbol
TTL VIH
TTL VIL
TTL VOH
TTL VOL
TTL IOZ
Conditions
Input High Vol.
Minimum
Typical
Maximum
0.5*Vcc
Vcc+0.5V
0.3*Vcc
Vcc
0.1*Vcc
10uA
Input Low Vol.
-0.5V
Output High Vol.
Output Low Vol.
Tri-state Leakage
IOH=-8mA
IOL=8mA
Vout=Vcc
GND
0.9*Vcc
or
or
-10uA
-1.0uA
IIN
Input Current
Vin=Vcc
GND
1.0uA
Icc
Average
Operating Iout=0mA
200mA
Supply Current
PECL VIH
PECL VIL
PECL VOH
PECL VOL
PECL Input High Vol
PECL Input Low Vol.
PECL Output High Vol.
PECL Output Low Vol.
Vdd-1.16V
Vdd-1.81V
Vdd-1.02V
Vdd-0.88V
Vdd-1.47V
Vdd-1.62V
2002-03-29
Rev.1.2
21
RTL8201BL
8.2 A.C. Characteristics
8.2.1 MII Timing of Transmission Cycle
Shown is an example transfer of a packet from MAC to PHY in MII interface.
Symbol
t1
Description
TXCLK high pulse width
Minimum
Typical
Maximum
Unit
ns
100Mbps
14
20
26
10Mbps
100Mbps
10Mbps
100Mbps
10Mbps
140
14
140
200
20
200
40
400
24
260
26
260
ns
ns
ns
ns
ns
ns
t2
TXCLK low pulse width
TXCLK period
t3
t4
TXEN, TXD[0:3] setup to TXCLK 100Mbps
10
5
rising edge
10Mbps
ns
ns
t5
t6
t7
TXEN, TXD[0:3] hold after 100Mbps
10
25
TXCLK rising edge
10Mbps
100Mbps
10Mbps
5
ns
ns
ns
ns
TXEN sampled to CRS high
TXEN sampled to CRS low
40
400
160
100Mbps
10Mbps
100Mbps
10Mbps
2000
140
ns
ns
t8
t9
Transmit latency
60
70
400
170
ns
ns
ns
Sampled TXEN inactive to end of 100Mbps
frame
100
10Mbps
t
3
VIH(min)
TXCLK
VIL(max)
t
t
2
1
t
t
4
5
VIH(min)
VIL(max)
TXD[0:3]
TXEN
TXCLK
TXEN
TXD[0:3]
t
t
6
7
CRS
t
t
8
9
TPTX+-
2002-03-29
Rev.1.2
22
RTL8201BL
8.2.2 MII Timing of Reception Cycle
Shown is an example of transfer of a packet from PHY to MAC in MII interface
Symbol
t1
Description
RXCLK high pulse width
Minimum
Typical
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
100Mbps
10Mbps
100Mbps
14
140
14
20
200
20
200
40
400
26
260
26
t2
t3
t4
t5
t6
t7
t8
t9
RXCLK low pulse width
RXCLK period
10Mbps
100Mbps
140
260
10Mbps
RXER, RXDV, RXD[0:3] setup to 100Mbps
10
6
RXCLK rising edge
10Mbps
RXER, RXDV, RXD[0:3] hold after 100Mbps
10
RXCLK rising edge
10Mbps
6
ns
ns
ns
ns
ns
ns
ns
ns
Receive frame to CRS high
100Mbps
130
600
240
600
150
3200
120
10Mbps
100Mbps
End of receive frame to CRS low
10Mbps
Receive frame to sampled edge of 100Mbps
RXDV
10Mbps
End of receive frame to sampled 100Mbps
edge of RXDV
10Mbps
800
ns
t
3
VIH(min)
RXCLK
VIL(max)
t
t
2
t
t
5
1
4
RXD[0:3]
RXDV
RXER
VIH(min)
VIL(max)
RXCLK
t
t
8
9
RXDV
RXD[0:3]
t
t
6
7
CRS
TPRX+-
2002-03-29
Rev.1.2
23
RTL8201BL
8.2.3 SNI Timing of Transmission Cycle
Shown is an example transfer of a packet from MAC to PHY in SNI interface. SNI mode only runs in 10Mbps.
Symbol
t1
t2
t3
t4
t5
t8
Description
Minimum
Typical
Maximum
Unit
ns
TXCLK high pulse width
36
36
80
20
10
TXCLK low pulse width
ns
TXCLK period
120
50
ns
TXEN, TXD0 setup to TXCLK rising edge
TXEN, TXD0 hold after TXCLK rising edge
Transmit latency
ns
ns
ns
t
3
VIH(min)
TXCLK
VIL(max)
t
t
2
1
t
t
4
5
VIH(min)
VIL(max)
TXD0
TXEN
TXCLK
TXEN
TXD0
t
t
8
9
TPTX+-
2002-03-29
Rev.1.2
24
RTL8201BL
8.2.4 SNI Timing of Reception Cycle
Shown is an example of transfer of a packet from PHY to MAC in SNI interface. SNI mode only runs in 10Mbps.
Symbol
t1
Description
Minimum
Typical
Maximum
Unit
ns
RXCLK high pulse width
36
36
80
40
40
t2
t3
t4
t5
t6
t7
t8
RXCLK low pulse width
ns
RXCLK period
120
ns
RXD0 setup to RXCLK rising edge
RXD0 hold after RXCLK rising edge
Receive frame to CRS high
End of receive frame to CRS low
Decoder acquisition time
ns
ns
50
ns
160
1800
ns
600
ns
t
3
VIH(min)
RXCLK
RXD0
VIL(max)
t
t
2
t
t
5
1
4
VIH(min)
VIL(max)
RXCLK
t
8
RXD0
t
t
7
6
CRS
TPRX+-
2002-03-29
Rev.1.2
25
RTL8201BL
8.2.5 MDC/MDIO timing
Symbol
t1
t2
t3
t4
t5
t6
Description
MDC high pulse width
MDC low pulse width
Minimum
Typical
Maximum
Unit
ns
160
160
400
10
10
0
ns
MDC period
ns
MDIO setup to MDC rising edge
MDIO hold time from MDC rising edge
MDIO valid from MDC rising edge
ns
ns
300
ns
t
3
VIH(min)
VIL(max)
M DC
t
t
2
t
t
5
1
4
M DIO
sourcedby
STA
VIH(min)
VIL(max)
t
6
M DIO
sourcedby
RTL8201B
VIH(min)
VIL(max)
8.2.6 Transmission Without Collision
Shown is an example transfer of a packet from MAC to PHY.
8.2.7 Reception Without Error
Shown is an example of transfer of a packet from PHY to MAC
2002-03-29
Rev.1.2
26
RTL8201BL
8.3 Crystal and Transformer Specifications
8.3.1 Crystal Specifications
Item
Parameter
Range
1
2
3
4
5
Nominal Frequency
Oscillation Mode
25.000 MHz
Base wave
±50 ppm
Frequency Tolerance at 25℃
Temperature Characteristics
Operating Temperature Range
Equivalent Series Resistance
Drive Level
±50 ppm
-10℃ ~ +70℃
30 ohm Max.
0.1 mV
20 pF
7 pF Max.
Mega ohm Min./DC 100V
Saunders 250A
±0.0003%
6
7
8
Load Capacitance
Shunt Capacitance
Insulation Resistance
Test Impedance Meter
Aging Rate A Year
9
10
11
12
8.3.2 Transformer Specifications
Parameter
Transmit End
Receive End
Turn ratio
1:1 CT
1:1
Inductance (min.)
Leakage inductance
Capacitance (max)
DC resistance (max)
350 uH @ 8mA
0.05-0.15 uH
15 pF
350 uH @ 8mA
0.05-0.15 uH
15 pF
0.4 ohm
0.4 ohm
2002-03-29
Rev.1.2
27
RTL8201BL
9. Mechanical Dimensions
Notes:
1.To be determined at seating plane -c-
2.Dimensions D1 and E1 do not include mold protrusion.
D1 and E1 are maximum plastic body size dimensions
including mold mismatch.
Symbo
l
Dimension in
Dimension in
inch
Nom
-
mm
Nom
Min
-
Max
Min
-
Max
1.70
0.20
1.50
0.29
0.25
0.20
0.16
3.Dimension b does not include dambar protrusion.
Dambar can not be located on the lower radius of the foot.
4.Exact shape of each corner is optional.
A
A1
A2
b
b1
c
c1
D
D1
E
0.067
-
0.1
1.40
0.22
0.20
-
-
0.000
0.051
0.006
0.006
0.004
0.004
0.004 0.008
0.055 0.059
0.00
1.30
0.15
0.15
0.09
0.09
5.These dimensions apply to the flat section of the lead
between 0.10 mm and 0.25 mm from the lead tip.
6. A1 is defined as the distance from the seating plane to the
lowest point of the package body.
7.Controlling dimension: millimeter.
8. Reference document: JEDEC MS-026, BBC
0.009
0.011
0.008 0.010
-
-
0.008
0.006
0.354 BSC
0.276 BSC
0.354 BSC
0.276 BSC
0.020 BSC
9.00 BSC
7.00 BSC
9.00 BSC
7.00 BSC
0.50 BSC
TITLE: 48LD LQFP ( 7x7x1.4mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
LEADFRAME MATERIAL:
E1
e
L
L1
θ
0.016
0.024 0.031
0.039 REF
0.40
0.60
1.00 REF
3.5°
0.80
APPROVE DOC. NO.
VERSION
PAGE
1
OF
0°
0°
3.5°
9°
-
0°
0°
9°
-
-
-
CHECK
DWG NO.
DATE
SS048 - P1
Sept. 25.2000
θ1
θ2
θ3
12° TYP
12° TYP
12° TYP
12° TYP
REALTEK SEMI-CONDUCTOR CORP.
2002-03-29
Rev.1.2
28
RTL8201BL
10. Revision History
Changes from Revision 1.0 to Revision 1.1 (Feb/02)
Section
8.1.3. Power Dissipation
5.4 100Mbps Network Interface
7.10 Reset, and Transmit Bias(RTSET)
Schematic Layout
Page
Change
Text
21
6
19
Modify Remove 2.5V power consumption
Modify R5 is changed from 5.6K to 5.9K
Modify R5 is changed from 5.6K to 5.9K
Modify R5 is changed from 5.6K to 5.9K
ACR; MII; SNI
Changes from Revision 1.1 to Revision 1.2 (Mar/29)
Section
Page
Change
Text
5.7 Reset and other pins
7
Modify Add pin description for pin 32 and pin 8
Modify Remove pin description of pin 32 and pin 8
Modify Modify description of bit 5:<5> and bit 5:<7>
5.8 Power and Ground pins
6.6 Register 5 Auto-Negotiation Link
Partner Ability Register
7
11
7.11 3.3V power supply and voltage
conversion circuit
19
Modify Add description: “Strongly emphasize here, could
not provide external 2.5V produced by any other
power device for PWFBOUT and PWFBIN.”
Modify 1. Modify net label:
Schematic Layout
ACR; MII; SNI
Pin32: AVDD25ꢂPWFBOUT
Pin8: DVDD25ꢂPWFBIN
2. Add pull-high resistor for MDIO
3. Modify ResetB circuit to meet wake-on-lan
application
Realtek Semiconductor Corp.
Headquarters
1F, No. 2, Industry East Road IX, Science-based
Industrial Park, Hsinchu, 300, Taiwan, R.O.C.
Tel : 886-3-5780211 Fax : 886-3-5776047
WWW: www.realtek.com.tw
2002-03-29
Rev.1.2
29
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