RTL8211B-GR [REALTEK]
INTEGRATED 10/100/1000 GIGABIT ETHERNET TRANSCEIVER;
| 型号： | RTL8211B-GR |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | INTEGRATED 10/100/1000 GIGABIT ETHERNET TRANSCEIVER 局域网（LAN）标准 以太网：16GBASE-T |
| 文件： | 总47页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8211B-GR
RTL8211BL-GR
INTEGRATED 10/100/1000 GIGABIT
ETHERNET TRANSCEIVER
DATASHEET
Rev. 1.5
10 January 2008
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8211B(L)
Datasheet
COPYRIGHT
©2008 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are
trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
Release Date Summary
1.0
2005/07/27
2006/01/19
2006/01/27
First release.
1.1
Add RTL8211BL-GR 100-Pin LQFP model.
1.2
Revised 100-pin CONFIG[0], CONFIG[1], and CONFIG[2] pin numbers (Table 6, page 6).
Revised AGND and DGND information (Table 9, page 8).
Revised Table 8, page 7, and Table 12, page 11.
Revised MDI[1]pin description (Table 1, page 4).
1.3
2006/03/24
Revised default pulse-stretch duration to 42 to 84ms (see 6.7 LED Configuration, page 20).
The default blink setting is ‘No blinking’.
Revised LED Blink Rate settings (see Table 35, page 33).
1.4
1.5
2006/12/8
Update RGMII timing diagram and RGMII timing parameters (see section 9.5.2 RGMII
Timing Modes, page 37).
2008/01/10
Revised LED control bit (Table 15, page 20).
Revised MDI/MDIX control bit (Table 29, page 31).
Removed MII timing diagram.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
Table of Contents
1.
2.
3.
4.
GENERAL DESCRIPTION..............................................................................................................................................1
FEATURES.........................................................................................................................................................................1
SYSTEM APPLICATIONS...............................................................................................................................................1
PIN ASSIGNMENTS .........................................................................................................................................................2
4.1.
RTL8211B PIN ASSIGNMENTS (64-PIN QFN) .............................................................................................................2
PACKAGE IDENTIFICATION...........................................................................................................................................2
RTL8211BL PIN ASSIGNMENTS (100-PIN LQFP) .......................................................................................................3
PACKAGE IDENTIFICATION...........................................................................................................................................3
4.2.
4.3.
4.4.
5.
PIN DESCRIPTIONS ........................................................................................................................................................4
5.1.
TRANSCEIVER INTERFACE............................................................................................................................................4
CLOCK .........................................................................................................................................................................4
RGMII/MII..................................................................................................................................................................5
MANAGEMENT INTERFACE...........................................................................................................................................6
RESET ..........................................................................................................................................................................6
MODE SELECTION ........................................................................................................................................................6
LED INDICATION .........................................................................................................................................................7
REGULATOR & REFERENCE..........................................................................................................................................7
POWER & GROUND ......................................................................................................................................................8
NOT CONNECTED .........................................................................................................................................................8
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
5.8.
5.9.
5.10.
6.
FUNCTION DESCRIPTION ............................................................................................................................................9
6.1.
TRANSMITTER..............................................................................................................................................................9
6.1.1. RGMII (1000Mbps) Mode......................................................................................................................................9
6.1.2. MII (100Mbps) Mode .............................................................................................................................................9
6.1.3. MII (10Mbps) Mode ...............................................................................................................................................9
6.2.
RECEIVER...................................................................................................................................................................10
6.2.1. RGMII (1000Mbps) Mode....................................................................................................................................10
6.2.2. MII (100Mbps) Mode ...........................................................................................................................................10
6.2.3. MII (10Mbps) Mode .............................................................................................................................................10
6.3.
6.4.
HARDWARE CONFIGURATION ....................................................................................................................................10
MAC/PHY INTERFACE..............................................................................................................................................12
6.4.1. MII........................................................................................................................................................................12
6.4.2. RGMII...................................................................................................................................................................12
6.4.3. Management Interface..........................................................................................................................................12
6.4.4. Interrupt ...............................................................................................................................................................13
6.5.
AUTO-NEGOTIATION..................................................................................................................................................14
6.5.1. Auto-Negotiation Priority Resolution...................................................................................................................17
6.5.2. Auto-Negotiation Master/Slave Resolution ..........................................................................................................18
6.5.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution ............................................................................18
6.6.
CROSSOVER DETECTION & AUTO-CORRECTION ........................................................................................................19
LED CONFIGURATION................................................................................................................................................20
POLARITY CORRECTION.............................................................................................................................................21
POWER .......................................................................................................................................................................21
6.7.
6.8.
6.9.
7.
REGISTER DESCRIPTIONS.........................................................................................................................................22
7.1. REGISTER MAPPING AND DEFINITIONS.......................................................................................................................22
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RTL8211B(L)
Datasheet
7.2.
REGISTER TABLE .......................................................................................................................................................23
7.2.1. BMCR (Basic Mode Control Register, Address 0x00) .........................................................................................23
7.2.2. BMSR (Basic Mode Status Register, Address 0x01).............................................................................................24
7.2.3. PHYID1 (PHY Identifier Register 1, Address 0x02) ............................................................................................25
7.2.4. PHYID2 (PHY Identifier Register 2, Address 0x03) ............................................................................................26
7.2.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04) ...........................................................................26
7.2.6. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05) .........................................................27
7.2.7. ANER (Auto-Negotiation Expansion Register, Address 0x06).............................................................................27
7.2.8. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07).........................................................28
7.2.9. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)...........................................................28
7.3.
GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) .....................................................................................29
7.3.1. GBSR (1000Base-T Status Register, Address 0x0A) ............................................................................................30
7.3.2. GBESR (1000Base-T Extended Status Register, Address 0x0F)..........................................................................30
7.3.3. PHYCR (PHY Specific Control Register, Address 0x10) .....................................................................................31
7.3.4. PHYSR (PHY Specific Status Register, Address 0x11).........................................................................................31
7.3.5. INER (Interrupt Enable Register, Address 0x12).................................................................................................32
7.3.6. INSR (Interrupt Status Register, Address 0x13)...................................................................................................32
7.3.7. EPHYCR (Extended PHY Specific Control Register, Address 0x14)...................................................................33
7.3.8. RXERC (Receive Error Counter, Address 0x15)..................................................................................................33
7.3.9. LEDCR (LED Control Register, Address 0x18)...................................................................................................33
8.
9.
APPLICATION DIAGRAM ...........................................................................................................................................34
CHARACTERISTICS .....................................................................................................................................................35
9.1.
ABSOLUTE MAXIMUM RATINGS.................................................................................................................................35
RECOMMENDED OPERATING CONDITIONS .................................................................................................................35
CRYSTAL REQUIREMENTS..........................................................................................................................................35
DC CHARACTERISTICS...............................................................................................................................................36
AC CHARACTERISTICS...............................................................................................................................................36
9.2.
9.3.
9.4.
9.5.
9.5.1. MII Timing............................................................................................................................................................36
9.5.2. RGMII Timing Modes...........................................................................................................................................37
10.
MECHANICAL DIMENSIONS.................................................................................................................................39
10.1.
10.2.
RTL8211B 64-PIN QFN MECHANICAL DIMENSIONS.................................................................................................39
RTL8211BL 100-PIN LQFP MECHANICAL DIMENSIONS ..........................................................................................40
11.
ORDERING INFORMATION...................................................................................................................................41
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
List of Tables
TABLE 1. TRANSCEIVER INTERFACE ..............................................................................................................................................4
TABLE 2. CLOCK............................................................................................................................................................................4
TABLE 3. RGMII/MII....................................................................................................................................................................5
TABLE 4. MANAGEMENT INTERFACE.............................................................................................................................................6
TABLE 5. RESET.............................................................................................................................................................................6
TABLE 6. MODE SELECTION ..........................................................................................................................................................6
TABLE 7. LED INDICATION ...........................................................................................................................................................7
TABLE 8. REGULATOR & REFERENCE............................................................................................................................................7
TABLE 9. POWER & GROUND ........................................................................................................................................................8
TABLE 10. NOT CONNECTED...........................................................................................................................................................8
TABLE 11. CONFIG[9:0] PINS VS. CONFIGURATION REGISTER ....................................................................................................10
TABLE 12. CONFIGURATION REGISTER DEFINITION ......................................................................................................................11
TABLE 13. TYPICAL MDIO FRAME FORMAT.................................................................................................................................12
TABLE 14. 1000BASE-T BASE AND NEXT PAGES BIT ASSIGNMENTS............................................................................................15
TABLE 15. LED CONFIGURATION .................................................................................................................................................20
TABLE 16. REGISTER MAPPING AND DEFINITIONS ........................................................................................................................22
TABLE 17. BMCR (BASIC MODE CONTROL REGISTER, ADDRESS 0X00) ......................................................................................23
TABLE 18. BMSR (BASIC MODE STATUS REGISTER) ADDRESS 0X01...........................................................................................24
TABLE 19. PHYID1 (PHY IDENTIFIER REGISTER 1, ADDRESS 0X02) ...........................................................................................25
TABLE 20. PHYID2 (PHY IDENTIFIER REGISTER 2, ADDRESS 0X03) ...........................................................................................26
TABLE 21. ANAR (AUTO-NEGOTIATION ADVERTISING REGISTER, ADDRESS 0X04)....................................................................26
TABLE 22. ANLPAR (AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER, ADDRESS 0X05) ...............................................27
TABLE 23. ANER (AUTO-NEGOTIATION EXPANSION REGISTER, ADDRESS 0X06)........................................................................27
TABLE 24. ANNPTR (AUTO-NEGOTIATION NEXT PAGE TRANSMIT REGISTER, ADDRESS 0X07).................................................28
TABLE 25. ANNPRR (AUTO-NEGOTIATION NEXT PAGE RECEIVE REGISTER, ADDRESS 0X08) ...................................................28
TABLE 26. GBCR (1000BASE-T CONTROL REGISTER, ADDRESS 0X09) .......................................................................................29
TABLE 27. GBSR (1000BASE-T STATUS REGISTER, ADDRESS 0X0A)..........................................................................................30
TABLE 28. GBESR (1000BASE-T EXTENDED STATUS REGISTER, ADDRESS 0X0F)......................................................................30
TABLE 29. PHYCR (PHY SPECIFIC CONTROL REGISTER, ADDRESS 0X10) ..................................................................................31
TABLE 30. PHYSR (PHY SPECIFIC STATUS REGISTER, ADDRESS 0X11)......................................................................................31
TABLE 31. INER (INTERRUPT ENABLE REGISTER, ADDRESS 0X12)..............................................................................................32
TABLE 32. INSR (INTERRUPT STATUS REGISTER, ADDRESS 0X13)...............................................................................................32
TABLE 33. EPHYCR (EXTENDED PHY SPECIFIC CONTROL REGISTER, ADDRESS 0X14)..............................................................33
TABLE 34. RXERC (RECEIVE ERROR COUNTER, ADDRESS 0X15)................................................................................................33
TABLE 35. LEDCR (LED CONTROL REGISTER, ADDRESS 0X18)..................................................................................................33
TABLE 36. ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................35
TABLE 37. RECOMMENDED OPERATING CONDITIONS ...................................................................................................................35
TABLE 38. CRYSTAL REQUIREMENTS............................................................................................................................................35
TABLE 39. DC CHARACTERISTICS.................................................................................................................................................36
TABLE 40. MII MANAGEMENT TIMING PARAMETERS ...................................................................................................................36
TABLE 41. RGMII TIMING PARAMETERS......................................................................................................................................38
TABLE 42. ORDERING INFORMATION ............................................................................................................................................41
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
List of Figures
FIGURE 1. RTL8211B PIN ASSIGNMENTS (64-PIN QFN)...............................................................................................................2
FIGURE 2. RTL8211BL PIN ASSIGNMENTS (100-PIN LQFP) ........................................................................................................3
FIGURE 3. TYPICAL MDC/MDIO READ TIMING..........................................................................................................................13
FIGURE 4. TYPICAL MDC/MDIO WRITE TIMING........................................................................................................................13
FIGURE 5. APPLICATION DIAGRAM..............................................................................................................................................34
FIGURE 6. MII MANAGEMENT TIMING PARAMETERS ..................................................................................................................36
FIGURE 7. RGMII TIMING MODES...............................................................................................................................................37
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
1. General Description
The Realtek RTL8211B(L) is a highly integrated Ethernet transceiver that complies with 10Base-T,
100Base-TX, and 1000Base-T IEEE 802.3 standards. It provides all the necessary physical layer functions
to transmit and receive Ethernet packets over CAT 5 UTP cable or CAT 3 UTP (10Mbps only) cable.
The RTL8211B(L) uses state-of-the-art DSP technology and an Analog Front End (AFE) to enable
high-speed data transmission and reception over UTP cable. Functions such as Crossover Detection &
Auto-Correction, polarity correction, adaptive equalization, cross-talk cancellation, echo cancellation,
timing recovery, and error correction are implemented in the RTL8211B(L) to provide robust transmission
and reception capabilities at 10Mbps, 100Mbps, or 1000Mbps.
Data transfer between MAC and PHY is via the Reduced Gigabit Media Independent Interface (RGMII) for
1000Base-T, and Media Independent Interface (MII) for 10Base-T/100Base-TX.
2. Features
1000Base-T IEEE 802.3ab Compliant
100Base-TX IEEE 802.3u Compliant
10Base-T IEEE 802.3 Compliant
IEEE 802.3 Compliant RGMII/MII
Supports Auto-Negotiation
Transmission rate up to 1Gbps over industry
standard CAT.5 UTP cable with BER less than
10-10 in 1000Base-T
The design transceiver capability target is up
to 140m for CAT.5 cable in 1000Base-T
Supports 3.3V or 2.5V signaling for RGMII
Supports power down mode
Supports Link Down Power Saving
Supports 25MHz external crystal or OSC
Provides 125MHz clock source for MAC
Provides 6 network status LEDs
64-pin QFN or 100-pin LQFP
Supports Parallel Detection
Crossover Detection & Auto-Correction
Automatic polarity correction
Transmit wave-shaping
DSP processing
Internal hybrids for 1000Base-T
Baseline Wander Correction
Supports half/full duplex operation
0.15µm process with very low power
consumption
3. System Applications
Network Interface Adapter, MAU (Media Access Unit), CNR (Communication and Network Riser), ACR
(Advanced Communication Riser), Ethernet hub, Ethernet switch. In addition, it can be used in any
embedded system with an Ethernet MAC that needs a UTP physical connection.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
4. Pin Assignments
4.1. RTL8211B Pin Assignments (64-Pin QFN)
Figure 1. RTL8211B Pin Assignments (64-Pin QFN)
4.2. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 1.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
4.3. RTL8211BL Pin Assignments (100-Pin LQFP)
LED_LINK10
DGND
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DVDD33
CONFIG[9]
DVDD15
DGND
NDIO
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TXDLY
RXDLY
CONFIG[4]
CONFIG[3]
DVDD33
CONFIG[2]
CONFIG[1]
CONFIG[0]
DGND
DGND
MDC
DGND
TXCTL
TXD[3]
TXD[2]
DGND
TXD[1]
TXD[0]
TXC
RTL8211BL
DVDD15
DGND
NC
NC
LLLLLLL
TXXXV
AVDD33
CKXTAL1
CKXTAL2
DVDD33
RXC
RXD[3]
AGND
AVDD15
CTRL15
AGND
NC
DGND
RXD[2]
RXD[1]
DVDD33
DGND
NC
RXD[0]
RXCTL
NC
Figure 2. RTL8211BL Pin Assignments (100-Pin LQFP)
4.4. Package Identification
‘Green’ package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
5. Pin Descriptions
Note that some pins have multiple functions. Refer to the Pin Assignment figures on page 2 (RTL8211B)
and on page 3 (RTL8211BL) for a graphical representation.
5.1. Transceiver Interface
Table 1. Transceiver Interface
Pin No.
Pin No.
Pin Name Type Description
(64-pin) (100-pin)
3
4
6
7
4
5
MDI+[0]
MDI−[0]
MDI+[1]
MDI−[1]
IO
IO
IO
IO
In MDI mode, this is the first pair in 1000Base-T, i.e. the BI_DA+/- pair,
and is the transmit pair in 10Base-T and 100Base-TX.
In MDI crossover mode, this pair acts as the BI_DB+/- pair, and is the
receive pair in 10Base-T and 100Base-TX.
9
In MDI mode, this is the second pair in 1000Base-T, i.e. the BI_DB+/- pair,
and is the receive pair in 10Base-T and 100Base-TX.
10
In MDI crossover mode, this pair acts as the BI_DA+/- pair, and is the
transmit pair in 10Base-T and 100Base-TX.
11
12
14
15
16
17
20
21
MDI+[2]
MDI−[2]
MDI+[3]
MDI−[3]
IO
IO
IO
IO
In MDI mode, this is the third pair in 1000Base-T, i.e. the BI_DC+/- pair.
In MDI crossover mode, this pair acts as the BI_DD+/- pair.
In MDI mode, this is the fourth pair in 1000Base-T, i.e. the BI_DD+/- pair.
In MDI crossover mode, this pair acts as the BI_DC+/- pair.
5.2. Clock
Table 2. Clock
Pin No.
Pin No.
Pin Name
Type Description
(64-pin) (100-pin)
61
62
41
92
93
60
CKXTAL1
CKXTAL2
CLK125
I
Input/Output of 25MHz Clock Reference.
125MHz reference clock generated from internal PLL.
O
O
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
5.3. RGMII/MII
Table 3. RGMII/MII
Type Description
Pin No.
Pin No.
Pin Name
(64-pin) (100-pin)
24
36
TXC
I
The transmit reference clock will be 125Mhz, 25Mhz, or 2.5Mhz +-
50ppm depending on speed.
25
26
27
28
29
37
38
40
41
42
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXCTL
I
I
I
I
I
Transmit Data. Data is transmitted from MAC to PHY via TXD[7:0].
Bits 3:0 on the rising edge of TXC, and bits7:4 on the falling edge of
TXC.
TXEN on the rising edge of TXC, and a logical derivative of TXEN
and TXERR on the falling edge of TXC.
TXEN is Transmit Enable, and TXER is Transmit Error.
When both TXER and TXEN are asserted, the transmit error symbol is
transmitted onto the cable.
When TXER is asserted with TXEN de-asserted, the carrier extension
symbol is transmitted onto the cable.
22
34
RXC
O
The continuous receive reference clock will be 125Mhz, 25Mhz, or
2.5Mhz +- 50ppm. and shall be derived from the received data stream
17
19
20
21
16
27
30
31
33
26
RXD[0]
RXD[1]
RXD[2]
RXD[3]
RXCTL
O
O
O
O
O
Receive Data. Data is transmitted from PHY to MAC via RXD[3:0].
Bits 3:0 on rising edge of RXC, and bits7:4 on falling edge of RXC
RXDV on the rising edge of RXC, and a derivative of RXDV and
RXERR on the falling edge of TXC.
RX_CTL is Receive Data Valid, and RXER is Receive Error.
When both RXER and RXDV are asserted, error symbol is received
from the cable.
When RXER is asserted with RXDV is de-asserted, it means false
carrier or carrier extension symbol is detected on the cable.
46
47
51
66
68
78
COL
CRS
O
O
I
Collision in Half Duplex Mode.
Carrier Sense in RGMII/MII Mode.
TXDLY
RGMII Transmit Clock Timing Control
1 = Add ~2 ns delay to TXC for TXD latching
RGMII Receiver Clock Timing Control
1 = Add 2 ns delay to RXC for RXD latching
52
79
RXDLY
I
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RTL8211B(L)
Datasheet
5.4. Management Interface
Table 4. Management Interface
Pin No.
Pin No.
Pin Name
Type Description
(64-pin) (100-pin)
30
31
37
44
46
56
MDC
MDIO
INTB
I
Management Data Clock.
IO
O
Input/Output of Management Data.
Interrupt. Active low.
5.5. Reset
Table 5. Reset
Pin No.
Pin No.
Pin Name
Type
Description
(64-pin) (100-pin)
38
57
PHYRSTB
I
Hardware Reset. Active low.
5.6. Mode Selection
Table 6. Mode Selection
Pin No.
Pin No.
Pin Name
Type Description
(64-pin) (100-pin)
58
57
56
54
53
47
46
37
35
33
85
84
83
81
80
68
66
56
51
49
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
CONFIG[4]
CONFIG[5]
CONFIG[6]
CONFIG[7]
CONFIG[8]
CONFIG[9]
I
I
I
I
I
I
I
I
I
I
PHY Configuration.
Note: See section 6.3 Hardware Configuration, page 10 for details.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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RTL8211B(L)
Datasheet
5.7. LED Indication
Table 7. LED Indication
Pin No.
Pin No.
Pin Name
Type Description
(64-pin) (100-pin)
50
48
44
43
40
39
76
70
63
62
59
58
LED_LINK10
LED_LINK100
LED_LINK1000
LED_DUPLEX
LED_RX
O
O
O
O
O
O
LED 1, 10Mbps link indicator.
LED 2, 100Mbps link indicator.
LED 3, 1000Mbps link indicator.
Duplex LED.
Receive LED.
LED_TX
Transmit LED.
Note: See section 7.3.9 LEDCR (LED Control Register, Address 0x18), page 33 for details.
5.8. Regulator & Reference
Table 8. Regulator & Reference
Pin No.
Pin No.
Pin Name
Type Description
(64-pin) (100-pin)
1
9
1
RSET
I
Reference.
External Resistor Reference.
Regulator Control.
13
96
CTRL18
CTRL15
O
O
Voltage control to external 1.8V regulator.
Regulator Control.
64
Voltage control to external 1.5V regulator.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
5.9. Power & Ground
Table 9. Power & Ground
Pin No.
(64-pin)
Pin No. (100-pin)
Pin Name Type Description
18, 23, 34, 42, 29, 35, 50, 61, 71, 82
49, 55
DVDD33
Power RGMII interface I/O voltage = 3.3V (2.5V tolerance).
32, 36, 45, 59
8, 60
48, 54, 65, 87
12, 91
DVDD15
AVDD33
AVDD18
AVDD15
AGND
Power Digital Power. 1.5V.
Power Analog Power. 3.3V.
Power Analog Power. 1.8V.
Power Analog Power. 1.5V.
Ground Analog Ground.
2, 5, 10, 13
63
3, 8, 15, 19
95
E-Pad
6, 11, 14, 18, 22, 94, 97
Exposed Pad (E-Pad) (64-pin package only) is Analog
and Digital Ground (see RTL8211B 64-Pin QFN
Mechanical Dimensions, page 39).
E-Pad
25, 28, 32, 39, 43, 45,
47, 52, 53, 55, 64, 67,
69, 75, 77, 86, 88
DGND
Ground Digital Ground.
Exposed Pad (E-Pad) (64-pin package only) is Analog
and Digital Ground (see RTL8211B 64-Pin QFN
Mechanical Dimensions, page 39).
5.10. Not Connected
Table 10. Not Connected
Pin No.
(64-pin)
Pin No. (100-pin)
Pin Name
Type
Description
NULL
2, 7, 23, 24, 72, 73, 74,
89, 90, 98, 99, 100
NC
NC
0: Not Connected.
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Datasheet
6. Function Description
6.1. Transmitter
Based on state-of-the-art DSP technology and mixed-mode signal processing technology, the RTL8211B(L)
is capable of operating at 10/100/1000Mbps link speed over standard CAT.5 UTP cable and CAT.3 UTP
cable (10Mbps).
6.1.1. RGMII (1000Mbps) Mode
The RTL8211B(L)’s PCS layer receives data bytes from the MAC through the RGMII interface and
performs the generation of continuous code-groups through 4D-PAM5 coding technology. Then, those
code groups are passed through a waveform-shaping filter to minimize EMI effect, and are transmitted onto
the 4-pair CAT5 cable at 125MBaud/s through a D/A converter.
6.1.2. MII (100Mbps) Mode
The transmitted 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 25Mhz (TXC), are converted into 5B
symbol code through 4B/5B coding technology, then through scrambling and serializing, are converted to
125Mhz NRZ and NRZI signals. After that, the NRZI signal are passed to the MLT3 encoder, then to the
D/A converter and transmitted onto the media.
6.1.3. MII (10Mbps) Mode
The transmit 4-bit nibbles (TXD[3:0]) from the MAC, clocked at 2.5Mhz (TXC), are serialized into
10Mbps serial data. Then, the 10Mbps serial data is converted into a Manchester-encoded data stream and
is transmitted onto the media by the D/A converter.
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Datasheet
6.2. Receiver
6.2.1. RGMII (1000Mbps) Mode
Input signals from the media first pass through the on-chip sophisticated hybrid circuit to subtract the
transmitted signal from the input signal for effective reduction of near-end echo. Afterwards, the received
signal is processed with state-of-the-art technology, such as adaptive equalization, BLW (Baseline Wander)
correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4D-PAM5
decoding. Then, the 8-bit-wide data is recovered and is sent to the RGMII interface at a clock speed of
125MHz. The Rx MAC retrieves the packet data from the receive MII/RGMII interface and sends it to the
Rx Buffer Manager.
6.2.2. MII (100Mbps) Mode
The MLT3 signal is processed with an ADC, equalizer, BLW (Baseline Wander) correction, timing
recovery, MLT3 and NRZI decoder, descrambler, 4B/5B decoder, and is then presented to the MII interface
in 4-bit-wide nibbles at a clock speed of 25MHz.
6.2.3. MII (10Mbps) Mode
The received differential signal is converted into a Manchester-encoded stream first. Next, the stream is
processed with a Manchester decoder, and is de-serialized into 4-bit-wide nibbles. The 4-bit nibbles are
presented to the MII interface at a clock speed of 2.5MHz.
6.3. Hardware Configuration
The operation speed, interface mode, and PHY address can be set by the CONFIG[9:0] pins. The respective
value mapping of CONFIG[9:0] with the configurable vector is listed in Table 11. To set the CONFIG[9:0]
pins, the externally pull-high or pull-low by resister are required.
Table 11. CONFIG[9:0] Pins vs. Configuration Register
Pin
Pin Name
PHYAD[0]
PHYAD[1]
PHYAD[2]
PHYAD[3]
PHYAD[4]
AN[0]
CONFIG[0]
CONFIG[1]
CONFIG[2]
CONFIG[3]
CONFIG[4]
CONFIG[5]
CONFIG[6]
CONFIG[7]
CONFIG[8]
CONFIG[9]
AN[1]
AN[2]
AN[3]
MODE
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RTL8211B(L)
Datasheet
Table 12. Configuration Register Definition
Configuration
Description
PHYAD[4:0]
PHY Address.
PHYAD sets the PHY address for the device.
AN[3:0]
Auto-Negotiation (NWay) Configuration.
AN[3:0] controls the setting of Auto-Negotiation enable/disable, master/slave preference, speed and
duplex setting.
register bit 16.6=0
0000: 10Base-T half duplex
0001: 10Base-T full duplex
0010: 100Base-TX half duplex
0011: 100Base-TX full duplex
0100: NWay, advertise only 1000Base-T half duplex, forced Master
0101: NWay, advertise only 1000Base-T half duplex, forced Slave
0110: NWay, advertise only 1000Base-T half duplex, preferred Master
0111: NWay, advertise only 1000Base-T half duplex, preferred Slave
1000: NWay, advertise only 1000Base-T full duplex, forced Master
1001: NWay, advertise only 1000Base-T full duplex, forced Slave
1010: NWay, advertise only 1000Base-T full duplex, preferred Master
1011: NWay, advertise only 1000Base-T full duplex, preferred Slave
1100: NWay, advertise all capabilities, forced Master
1101: NWay, advertise all capabilities, forced Slave
1110: NWay, advertise all capabilities, prefer Master
1111: NWay, advertise all capabilities, prefer Slave
For register bit 16.6=0, the AN[3:0] bits 0100-1011 will NOT have the register bit 0.12 indicate that
Auto-Negotiation is enabled.
Register bit 16.6 is Enable Crossover Detection & Auto-Correction function.
1: Enable
0: Disable
If Crossover Detection & Auto-Correction is enabled, then Auto-Negotiation is automatically
enabled. If the Crossover Detection & Auto-Correction function is disabled then the device assumes
the MDI configuration.
AN[3:0]
Auto-Negotiation (NWay) Configuration.
AN[3:0] controls the setting of Auto-Negotiation enable/disable, master/slave preference, speed and
duplex setting.
register bit 16.6=1
0000: NWay, 10Base-T half duplex
0010: NWay, 100Base-TX half duplex
0001: NWay, 10Base-T full duplex
0011: NWay, 100Base-TX full duplex
0100: NWay, advertise only 1000Base-T half duplex, forced Master
0101: NWay, advertise only 1000Base-T half duplex, forced Slave
0110: NWay, advertise only 1000Base-T half duplex, preferred Master
0111: NWay, advertise only 1000Base-T half duplex, preferred Slave
1000: NWay, advertise only 1000Base-T full duplex, forced Master
1001: NWay, advertise only 1000Base-T full duplex, forced Slave
1010: NWay, advertise only 1000Base-T full duplex, preferred Master
1011: NWay, advertise only 1000Base-T full duplex, preferred Slave
1100: NWay, advertise all capabilities, forced Master
1101: NWay, advertise all capabilities, forced Slave
1110: NWay, advertise all capabilities, prefer Master
1111: NWay, advertise all capabilities, prefer Slave
Interface Mode Select.
MODE
MODE specifies the operating mode of the RTL8211B(L).
0: Reserved
1: RGMII/MII to Copper
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Datasheet
6.4. MAC/PHY Interface
The RTL8211B(L) supports several industry standards and is suitable for most off-the-shelf MACs with an
MII/RGMII interface. They are enabled by hardware configuration bit MODE. The MII interface supports
up to 100Mbps operation, and the RGMII interface supports up to 1000Mbps operation.
6.4.1. MII
In 100Base-TX and 10Base-T modes (MII mode is selected), TXC and RXC sources are 25MHz and
2.5MHz, respectively. TXC will always be generated by the MAC and RXC will always be generated by
the PHY. TXD[3:0] and RXD[3:0] signals are used for date transitions.
6.4.2. RGMII
In 1000Base-T mode (RGMII interface is selected), TXC and RXC sources are 125MHz. TXC will always
be generated by the MAC and RXC will always be generated by the PHY. TXD[3:0] and RXD[3:0] signals
are used for date transitions on rising edge and on falling edge of clock.
6.4.3. Management Interface
The management interface provides access to the internal registers through the MDC and MDIO pins as
described in IEEE 802.3u section 22. The MDC signal, provided by the MAC, is the management data
clock reference to the MDIO signal. The MDIO is the management data input/output and is a bi-directional
signal that runs synchronously to MDC. The MDIO pin needs a 10k Ohm pull-up resistor to maintain the
MDIO high during idle and turnaround.
Preamble suppression (register bit 1.6 = 1) is the default setting of the RTL8211B(L) after power-on.
However, there still must be at least one idle bit between operations.
Up to 32 RTL8211B(L)s can share the same MDIO line. In switch/router applications, each port should be
assigned a unique address during the hardware reset sequence, and it can only be addressed via that unique
PHY address. For detailed information on the RTL8211B(L) management registers, see section 7. Register
Descriptions, page 22.
Table 13. Typical MDIO Frame Format
<idle><start><op code><PHY addr.><reg. addr.><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
MII Management Serial Protocol
Read
Write
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RTL8211B(L)
Datasheet
MDC
z
z
MDIO(MAC)
MDIO(PHY)
z
z
z
z
1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
Read
(OP
Code)
Idle Start
PHY Address
0x01
Reg. Address
0x00 (BMCR)
Turn
Around
Reg. Data
0x1140
Idle
Figure 3. Typical MDC/MDIO Read Timing
MDC
z
z
MDIO(MAC)
z
z
0
1
0
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
1
0 0 0 0 0 0
Write
(OP
Code)
PHY Address
0x01
Reg. Address
0x00 (BMCR)
Turn
Around
Reg. Data
0x1340
Idle
Start
Idle
Figure 4. Typical MDC/MDIO Write Timing
6.4.4. Interrupt
Whenever there is a status change on the media that the RTL8211B(L) detected, the RTL8211B(L) will
drive the interrupt pin (INTB) low to issue an interrupt event. The MAC senses the status change and
accesses the registers through the MDC/MDIO interface in response. Register 18 (Table 31, page 32)
controls the mask to enable which events will assert the interrupt (INTB) signal, and register 19 (Table 32,
page 32) is the interrupt status register and reflects which interrupt events have occurred, even though the
corresponding bits in register 18 are not set.
The value of register 19 is cleared automatically when register 19 is read through MDC/MDIO, and the
INTB is de-asserted at the same time. The RTL8211B(L) interrupt function removes the need for
continuous polling through the MDC/MDIO management interface.
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Datasheet
6.5. Auto-Negotiation
Auto-Negotiation is a mechanism to determine the fastest connection between two link partners. For copper
media applications, it was introduced in IEEE 802.3u for Ethernet and Fast Ethernet, and then in
IEEE 802.3ab to address extended functions for Gigabit Ethernet. It performs the following:
• Auto-Negotiation Priority Resolution
• Auto-Negotiation Master/Slave Resolution
• Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution
• Crossover Detection & Auto-Correction Resolution
Upon de-assertion of a hardware reset, the RTL8211B(L) can be configured to have auto-negotiation
enabled, or be forced to operate in 10Base-T, 100Base-TX, or 1000Base-T mode via the CONFIG[4:0] pins
(see section 6.3 Hardware Configuration, page 10). If the RTL8211B(L) is configured to operate only in
1000Base-T mode, then auto-negotiation is still enabled with only 1000Base-T mode advertised.
The auto-negotiation process is initiated automatically upon any of the following:
• Power-up
• Hardware reset
• Software reset (register 0.15)
• Restart auto-negotiation (register 0.9)
• Transition from power down to power up (register 0.11)
• Entering the link fail state
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Datasheet
Table 14. 1000Base-T Base and Next Pages Bit Assignments
Bit
Name
Bit Description
Register Location
Base Page
D15
NP
Next Page.
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
D14
D13
Ack
RF
Acknowledge.
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Remote Fault.
1: Indicates to its link partner that a device has encountered a
fault condition
D[12:5]
D[4:0]
A[7:0]
S[4:0]
Technology Ability Field.
Indicates to its link partner the supported technologies specific
to the selector field value.
Register 4.[12:5]
Table 21, page 26.
Selector Field.
Always 00001.
Register 4.[4:0]
Table 21, page 26.
Indicates to its link partner that it is an IEEE Std 802.3 device.
PAGE 0 (Message Next Page)
M15
NP
Next Page.
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
M14
M13
M12
M11
Ack
MP
Ack2
T
Acknowledge.
-
-
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Message Page.
1: Indicates to its link partner that this is a message page, not an
unformatted page.
Acknowledge 2.
1: Indicates to its link partner that a device has the ability to
comply with the message.
Toggle.
Used by the NWay arbitration function to ensure
synchronization with its link partner during Next Page
exchange.
M[10:0]
U15
-
1000Base-T Message Code.
Always 8.
-
-
PAGE 1 (Unformatted Next Page)
NP
Next Page.
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
U14
U13
Ack
MP
Acknowledge.
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Message Page.
1: Indicates to its link partner that this is a message page, not an
unformatted page.
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RTL8211B(L)
Datasheet
Bit
Name
Bit Description
Register Location
U12
Ack2
Acknowledge 2.
-
1: Indicates to its link partner that a device has the ability to
comply with the message.
U11
T
Toggle.
-
Used by the NWay arbitration function to ensure
synchronization with its link partner during Next Page
exchange.
U[10:5]
U4
-
-
Reserved. Transmit as 0
-
1000Base-T Half Duplex.
1: Half duplex
RGMII register 9.8 (GBCR)
Table 26, page 29.
0: No half duplex
U3
U2
U1
-
-
-
1000Base-T Full Duplex.
1: Full duplex
RGMII register 9.9 (GBCR)
Table 26, page 29.
0: No full duplex
1000Base-T Port Type Bit.
1: Multi-port device
RGMII register 9.10 (GBCR)
Table 26, page 29.
0: Single-port device
1000Base-T Master-Slave Manual Configuration Value.
1: Master
RGMII register 9.11 (GBCR)
Table 26, page 29.
0: Salve
This bit is ignored if bit 9.12 = 0
U0
-
1000Base-T Master-Slave Manual Configuration Enable.
1: Manual Configuration Enable
RGMII register 9.12 (GBCR)
Table 26, page 29.
This bit is intended to be used for manual selection in
Master-Slave mode, and is to be used in conjunction with bit
9.11
PAGE 2 (Unformatted Next Page)
U15
NP
Next Page.
-
1: Indicates that Next Pages follow
0: Indicates that no Next Pages follow
U14
U13
U12
U11
Ack
MP
Ack2
T
Acknowledge.
-
-
-
-
1: Indicates that a device has successfully received its link
partner’s Link Code Word (LCW)
Message Page.
1: Indicates to its link partner that this is a message page, not an
unformatted page.
Acknowledge 2.
1: Indicates to its link partner that a device has the ability to
comply with the message.
Toggle.
Used by the NWay arbitration function to ensure
synchronization with its link partner during Next Page
exchange.
U[10:0]
-
1000Base-T Master-Slave Seed Bit[10:0]
Master-Slave Seed Value
SB[10:0]
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Datasheet
6.5.1. Auto-Negotiation Priority Resolution
Upon the start of auto-negotiation, to advertise its capabilities, each station transmits a 16-bit packet called
a Link Code Word (LCW), within a burst of 17 to 33 Fast Link Pulses (FLP). A device capable of
auto-negotiation transmits and receives the FLPs. The receiver must identify three identical LCWs before
the information is authenticated and used in the arbitration process. The devices decode the base LCW and
select capabilities with the highest common denominator supported by both devices.
To advertise 1000Base-T capability, both link partners, sharing the same link medium, should engage in
Next Page (1000Base-T Message Page, Unformatted Page 1, and Unformatted Page 2) exchange.
Auto-negotiation ensures that the highest priority protocol will be selected as the link speed based on the
following priority advertised through the Link Code Word (LCW) exchange. Refer to IEEE 802.3 Clause
28 for detailed information.
1. 1000Base-T full duplex (highest priority)
2. 1000Base-T half duplex
3. 100Base-TX full duplex
4. 100Base-TX half duplex
5. 10Base-T full duplex
6. 10Base-T half duplex (lowest priority)
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Datasheet
6.5.2. Auto-Negotiation Master/Slave Resolution
To establish a valid 1000Base-T link, the Master/Slave mode of both link partners should be resolved
through the auto-negotiation process:
• Master Priority:
Multi-port > Single port
Manual > Non-manual
• Determination of Master/Slave configuration from LCW:
Manual_MASTER = U0 * U1
Manual_SLAVE = U0 * !U1
Single-port device = !U0 * !U2
Multi-port device = !U0 * U2
Where:
U0 is bit 0 of the Unformatted Page 1
U1 is bit 1 of the Unformatted Page 1
U2 is bit 2 of the Unformatted Page 1
• Where there are two stations with the same configuration, the one with higher Master-Slave seed
SB[10:0] in the unformatted page 2 shall become Master.
• Master-Slave configuration process resolution:
Successful: Bit 10.15 Master-Slave Configuration Fault is set to logical 0, and bit 10.14 is set to
logical 1 for Master resolution, or set to logical 0 for Slave resolution.
Unsuccessful: Auto-Negotiation restarts.
Fault detect: Bit 10.15 is set to logical 1 to indicate that a configuration fault has been detected.
Auto-Negotiation restarts automatically. This happens when both stations are set to manual
Master mode or manual Slave mode, or after seven attempts to configure the Master-Slave
relationship through the seed method has failed.
6.5.3. Auto-Negotiation PAUSE/ASYMMETRIC PAUSE Resolution
Auto-negotiation is also used to determine the flow control capability between link partners. Flow control
is a mechanism that can force a busy transmitting link partner to stop transmitting in a full duplex
environment by sending special MAC control frames. In IEEE 802.3u, a PAUSE control frame had already
been defined. However, in IEEE 802.3ab, a new ASY-PAUSE control frame was defined; if the MAC can
only generate PAUSE frames but is not able to respond to PAUSE frames generated by the link partner,
then it is called Asymmetric PAUSE.
PAUSE/ASYMMETRIC PAUSE capability can be configured by setting the ANAR bits 10 and 11 (Table
21). Link partner PAUSE capabilities can be determined from ANLPAR bits 10 and 11 (Table 22). A PHY
layer device such as the RTL8211B(L) is not directly involved in PAUSE resolution, but simply advertises
and reports PAUSE capabilities during the Auto-Negotiation process. The MAC is responsible for final
PAUSE/ASYMMETRIC PAUSE resolution after a link is established, and is responsible for correct flow
control actions thereafter.
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Datasheet
6.6. Crossover Detection & Auto-Correction
Ethernet needs a crossover mechanism between both link partners to cross the transmit signal to the
receiver when the medium is twisted-pair cable (e.g. CAT.3 or CAT.5 UTP). Crossover Detection &
Auto-Correction Configuration eliminates the need for crossover cables between devices, such as two PC’s
connected to each other with a CAT.3 or CAT.5 Ethernet cable. The basic concept is to assume the initial
default setting is MDI mode, and then check the link status. If no link is established after a certain time,
change to MDI Crossover mode and repeat the process until a link is established. An 11-bit pseudo-random
timer is applied to decide the mode change time interval.
Crossover Detection & Auto-Correction is not a part of the Auto-Negotiation process, but it utilizes the
process to exchange the MDI/MDI Crossover configuration. If the RTL8211B(L) is configured to only
operate in 100Base-TX or only in 10Base-T mode, then Auto-Negotiation is disabled only if the Crossover
Detection & Auto-Correction function is also disabled. If Crossover Detection & Auto-Correction are
enabled, then Auto-Negotiation is enabled and the RTL8211B(L) advertises only 100Base-TX mode or
10Base-T mode. If the speed of operation is configured manually and Auto-Negotiation is still enabled
because the Crossover Detection & Auto-Correction function is enabled, then the duplex advertised is as
follows:
1. If CONFIG is set to half duplex, then only half duplex is advertised.
2. If CONFIG is set to full duplex, then both full and half duplex are advertised.
If the user wishes to advertise only full duplex at a particular speed with the Crossover Detection &
Auto-Correction function enabled, then Auto-Negotiation should be enabled (register 0.12) with the
appropriate advertising capabilities set in registers 4 or 9. The Crossover Detection & Auto-Correction
function may be enabled/disabled by setting (register 16.6) manually.
After initial configuration following a hardware reset, Auto-Negotiation can be enabled and disabled via
register 0.12, speed via registers 0.13, 0.6, and duplex via register 0.8. The abilities that are advertised can
be changed via registers 4 and 9. Changes to registers 0.12, 0.13, 0.6, and 0.8 do not take effect unless at
least one of the following events occurs:
• Software reset (register 0.15)
• Restart of Auto-Negotiation (register 0.9)
• Transition from power-down to power-up (register 0.11)
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Datasheet
Registers 4 and 9 are internally latched once each time Auto-Negotiation enters the ABILITY DETECT
state in the arbitration state machine (IEEE 802.3). Hence a write into register 4 or 9 has no effect once the
RTL8211B(L) begins to transmit Fast Link Pulses.
Register 7 is treated in a similar manner as 4 and 9 during additional Next Page exchanges. Once the
RTL8211B(L) completes Auto-Negotiation, it updates the various statuses in registers 1, 5, 6, and 10. The
speed, duplex, page received, and Auto-Negotiation completed statuses are also available in registers 17
and 19.
6.7. LED Configuration
The RTL8211B(L) supports six LED pins, suitable for multiple types of applications, that can directly drive
the LEDs. These pins are LED10, LED100, LED1000, LEDDUP, LEDRX, and LEDTX. The output of
these pins is determined by setting the corresponding bits in register 24. The functionality of the LED pins
is shown in Table 15.
Table 15. LED Configuration
Pin
Register 24
Control Bit
Register 24 Control Bit = 0 (default)
Register 24 Control Bit = 1
LED_LINK10
24.3
Low = 10 Link Up
LED10, LED100:
High = 10 Link Down
Low, Low = 1000Mbps
High, Low = 100Mbps
Low, High = 10Mbps
High, High = Link Down
Low = Link Up (Any speed)
High = Link Down (Any speed)
Low = Full Duplex
LED_LINK100
24.3
Low = 100 Link Up
High = 100 Link Down
LED_LINK1000
LED_DUPLEX
24.3
24.2
Low = 1000 Link Up
High = 1000 Link Down
Low = Full Duplex
High = Half Duplex
Blink = Collision
High = Half Duplex
LED_RX
LED_TX
24.1
24.1
Low = Receiving
Low = Link Up
High = Not Receiving
High = Link Down
Blinking = Receiving
Low = Link Up
Low = Transmitting
High = Not Transmitting
High = Link Down
Blinking = Transmitting or Receiving
Some of the statuses can be pulse-stretched. Pulse-stretching is necessary because the duration of these
status events may be too short to be observable on the LEDs. The pulse-stretch duration can be programmed
via register 24.14:12. The default pulse-stretch duration is 42 to 84ms. The pulse-stretch duration applies to
all applicable LEDs. Some of the statuses indicate multiple events by blinking LEDs. The blink period can
be programmed via register 24.10:8. The default blink setting is ‘No blinking’. The blink rate applies to all
applicable LEDs.
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Datasheet
6.8. Polarity Correction
The RTL8211B(L) automatically corrects polarity errors on the receive pairs in 1000Base-T and 10Base-T
modes. In 100Base-TX polarity is irrelevant. In 1000Base-T mode, receive polarity errors are automatically
corrected based on the sequence of idle symbols. Once the descrambler is locked, the polarity is also locked
on all pairs. The polarity becomes unlocked only when the receiver loses lock. In 10Base-T mode, polarity
errors are corrected based on the detection of validly spaced link pulses. The detection begins during the
MDI crossover detection phase and locks when the 10Base-T link is up. The polarity becomes unlocked
when the link is down.
6.9. Power
The RTL8211B(L) implements two voltage regulators to generate operating power. The system vendor
needs to supply a 3.3V, 1A steady power source. The RTL8211B(L) converts the 3.3V steady power source
to 1.8V and 1.5V with two separate transistors. The transistor should have a beta value large enough to
supply sufficient current for internal logic. A transistor with beta value larger than 100 is recommended.
Another implementation is using three regulators to generate 3.3V, 1.8V, and 1.5V. Note that the regulators
need to meet the required rate current.
The RTL8211B(L) implements an option for the DVDD33 power pins. The I/O voltage of the RGMII
interface=3.3V (2.5V tolerance).
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7. Register Descriptions
7.1. Register Mapping and Definitions
Table 16. Register Mapping and Definitions
Offset
0
Access
RW
RO
Name
Description
BMCR
Basic Mode Control Register.
Basic Mode Status Register.
PHY Identifier Register 1.
PHY Identifier Register 2.
Auto-Negotiation Advertising Register.
1
BMSR
2
RO
PHYID1
PHYID2
ANAR
3
RO
4
RW
RW
RW
RW
RW
RW
RO
5
ANLPAR
ANER
Auto-Negotiation Link Partner Ability Register.
Auto-Negotiation Expansion Register.
Auto-Negotiation Next Page Transmit Register.
Auto-Negotiation Next Page Receive Register.
1000Base-T Control Register.
1000Base-T Status Register.
Reserved.
6
7
ANNPTR
ANNPRR
GBCR
8
9
10
11-14
15
16
17
18
19
20
21
24
25-31
GBSR
RO
Reserved
GBESR
PHYCR
PHYSR
INER
RO
1000Base-T Extended Status Register.
PHY Specific Control Register.
PHY Specific Status Register.
Interrupt Enable Register.
RW
RO
RW
RO
INSR
Interrupt Status Register.
RW
RO
EPHYCR
RXERC
LEDCR
Reserved
Extended PHY specific Control Register.
Receive Error Counter.
RW
RO
LED Control Register.
Reserved.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.2. Register Table
7.2.1. BMCR (Basic Mode Control Register, Address 0x00)
Table 17. BMCR (Basic Mode Control Register, Address 0x00)
Bit
Name
RW
Default Description
0.15
Reset
RW, SC
0
Reset.
1: PHY reset
0: Normal operation
Loopback.
0.14
0.13
Loopback
Speed[0]
RW
RW
0
1: Enable loopback mode
0: Disable loopback mode
The loopback function enables MII/RGMII transmit data to be
routed to the MII/RGMII receive data path.
0
Speed Select bit 0.
In forced mode, i.e. when Auto-Negotiation is disabled, bits 6 and 13
determine device speed selection.
Speed[1]
Speed[0]
Speed Enabled
Reserved
1
1
0
0
1
0
1
0
1000Mbps
100Mbps
10Mbps
0.12
0.11
ANE
PWD
RW
RW
1
0
Auto-Negotiation Enable.
1: Enable Auto-Negotiation
0: Disable Auto-Negotiation
Power Down.
1: Power down (only Management Interface and logic active, link is
down)
0: Normal operation
Isolate.
0.10
Isolate
RW
0
1: MII interface is isolated; the serial management interface (MDC,
MDIO) is still active. When this bit is asserted, the RTL8211B(L)
ignores TXD[3:0], and TXCLT inputs, and presents a high
impedance on TXC, RXC, RXCLT, RXD[3:0], COL and CRS
outputs.
0: Normal operation
0.9
0.8
Restart_AN
Duplex
RW, SC
RW
0
-
Restart Auto-Negotiation.
1: Restart Auto-Negotiation
0: Normal operation
Duplex Mode.
1: Full Duplex operation
0: Half Duplex operation
This bit is valid only in force mode, i.e., NWay is disabled.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
Bit
Name
RW
Default Description
0.7
Collision test
RW
0
Collision Test.
1: Collision test enabled
0: Normal operation
When set, this bit will cause the COL signal to be asserted in
response to the assertion of TXEN within 512-bit times. The COL
signal will be de-asserted within 4-bit times in response to the
de-assertion of TXEN.
0.6
Speed[1]
RSVD
RW
RO
0
Speed Select bit 1.
Refer to bit 0.13.
0.5:0
000000 Reserved.
Note 1: The power-on duplex, speed, and ANE values take on the values set by external pins AN[3:0] on hardware reset
only. A write to these registers has no effect unless any one of the following also occurs: Software reset (0.15) is asserted,
Restart_AN (0.9) is asserted, or PWD (0.11) transitions from power down to normal operation.
Note 2: When the RTL8211B(L) is switched from power down to normal operation, software reset and restart
auto-negotiation are performed even if bits Reset (0.15) and Restart_AN (0.9) are not set by the user.
Note 3: Auto-Negotiation is enabled when speed is set to 1000Base-T. Crossover Detection & Auto-Correction takes
precedence over Auto-Negotiation disable (0.12=0). If ANE is disabled, speed and duplex capabilities are advertised by
0.13, 0.6, and 0.8. Otherwise, register 4.8:5 and 9.9:8 take effect.
Note 4: Auto-Negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit
(0.9) is set.
7.2.2. BMSR (Basic Mode Status Register, Address 0x01)
Table 18. BMSR (Basic Mode Status Register) Address 0x01
Bit
Name
RW
Default
Description
1.15
100Base-T4
RO
0
100Base-T4 Capability.
The RTL8211B(L) does not support 100Base-T4 mode. This bit
should always be 0.
1.14
1.13
1.12
1.11
1.10
100Base-TX (full)
100Base-TX (half)
10Base-T (full)
RO
RO
RO
RO
RO
1
1
1
1
0
100Base-TX Full Duplex Capability.
1: Device is able to perform 100Base-TX in full duplex mode
0: Device is not able to perform 100Base-TX in full duplex mode
100Base-TX Half Duplex Capability.
1: Device is able to perform 100Base-TX in half duplex mode
0: Device is not able to perform 100Base-TX in half duplex mode
10Base-T Full Duplex Capability.
1: Device is able to perform 10Base-T in full duplex mode.
0: Device is not able to perform 10Base-T in full duplex mode.
10Base-T Half Duplex Capability.
10Base-T (half)
100Base-T2 (full)
1: Device is able to perform 10Base-T in half duplex mode
0: Device is not able to perform 10Base-T in half duplex mode
100Base-T2 Full Duplex Capability.
The RTL8211B(L) does not support 100Base-T2 mode and this bit
should always be 0.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
Bit
Name
RW
Default
Description
1.9
100Base-T2 (half)
RO
0
100Base-T2 Half Duplex Capability.
The RTL8211B(L) does not support 100Base-T2 mode. This bit
should always be 0.
1.8
1000Base-T
RO
1
1000Base-T Extended Status Register.
Extended status
1: Device supports Extended Status Register 0x0F (15)
0: Device does not support Extended Status Register 0x0F
This register is read-only and is always set to 1.
Reserved.
1.7
1.6
RSVD
RO
RO
0
1
Preamble
Preamble Suppression Capability (permanently on).
Suppression
The RTL8211B(L) always accepts transactions with preamble
suppressed.
1.5
1.4
Auto-Negotiation
Complete
RO
RO
0
0
Auto-Negotiation Complete.
1: Auto-Negotiation process complete, and contents of registers
5, 6, 8, and 10 are valid
0: Auto-Negotiation process not complete
Remote Fault.
Remote Fault
1: Remote fault condition detected (cleared on read or by reset).
Indication or notification of remote fault from Link Partner
0: No remote fault condition detected
Auto Configured Link.
1.3
1.2
Auto-Negotiation
Ability
RO
RO
1
0
1: Device is able to perform Auto-Negotiation
0: Device is not able to perform Auto-Negotiation
Link Status.
Link Status
1: Linked
0: Not Linked
This register indicates whether the link was lost since the last read.
For the current link status, either read this register twice or read
register bit 17.10 Link Real Time.
1.1
1.0
Jabber detect
RO
RO
0
1
Jabber Detect.
1: Jabber condition detected
0: No Jabber occurred
Extended
Capability
1: Extended register capabilities, always 1
7.2.3. PHYID1 (PHY Identifier Register 1, Address 0x02)
Table 19. PHYID1 (PHY Identifier Register 1, Address 0x02)
Bit
Name
RW
Default
Description
2.15:0 OUI_MSB
RO
0000000000011100
Organizationally Unique Identifier Bit 3:18.
Always 0000000000011100.
Note: Realtek OUI is 0x000732.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.2.4. PHYID2 (PHY Identifier Register 2, Address 0x03)
Table 20. PHYID2 (PHY Identifier Register 2, Address 0x03)
Bit
Name
RW
Default
Description
3.15:10 OUI_LSB
RO
110010
Organizationally Unique Identifier Bit 19:24.
Always 110010.
3.9:4
3.3:0
Model Number
Revision Number
RO
RO
010001
0010
Model Number
Always 010001.
Revision Number
7.2.5. ANAR (Auto-Negotiation Advertising Register, Address 0x04)
Table 21. ANAR (Auto-Negotiation Advertising Register, Address 0x04)
Bit
Name
RW
Default
Description
4.15
NextPage
RW
0
1: Additional next pages exchange desired
0: No additional next pages exchange desired
Reserved.
4.14
4.13
RSVD
RO
0
0
Remote fault
RW
1: Set Remote Fault bit
0: No remote fault detected
4.12
4.11
RSVD
RO
0
0
Reserved.
Asymmetric
PAUSE
RW
1: Advertise support of asymmetric pause
0: No support of asymmetric pause
1: Advertise support of pause frames
0: No support of pause frames
0: Not capable of 100Base-T4
1: Advertise support of 100Base-TX full-duplex mode
0: Not advertised
4.10
PAUSE
RW
0
4.9
4.8
100Base-T4
RO
0
1
100Base-TX(full)
RW
4.7
4.6
100Base-TX(half)
10Base-T(full)
10Base-T(half)
Selector field
RW
RW
RW
RO
1
1: Advertise support of 100Base-TX half-duplex mode
0: Not advertised
1
1
1: Advertise support of 10Base-TX full-duplex mode
0: Not advertised
4.5
1: Advertise support of 10Base-TX full-duplex mode
0: Not advertised
4.4:0
00001
Indicates the RTL8211B(L) supports IEEE 802.3
Note 1: The setting of Register 4 has no effect unless NWay is restarted or the link goes down.
Note 2: If 1000Base-T is advertised, then the required next pages are automatically transmitted. Register 4.15 should be set
to 0 if no additional next pages are needed.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.2.6. ANLPAR (Auto-Negotiation Link Partner Ability Register,
Address 0x05)
Table 22. ANLPAR (Auto-Negotiation Link Partner Ability Register, Address 0x05)
Bit
Name
RW
Default
Description
5.15
Next Page
RO
0
Next Page Indication.
Received Code Word Bit 15.
Acknowledge.
5.14
5.13
ACK
RO
RO
0
0
Received Code Word Bit 14.
Remote Fault indicated by Link Partner.
Received Code Word Bit 13.
Remote Fault
5.12:5 Technology Ability
Field
RO
RO
00000000 Received Code Word Bit 12:5.
5.4:0
Selector Field
00000 Received Code Word Bit 4:0.
Note: Register 5 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
7.2.7. ANER (Auto-Negotiation Expansion Register, Address 0x06)
Table 23. ANER (Auto-Negotiation Expansion Register, Address 0x06)
Bit
Name
RW
RO
RO
Default
0x000
0
Description
6.15:5 RSVD
Reserved.
6.4
6.3
6.2
6.1
6.0
Parallel Detection
Fault
1: A fault has been detected via the Parallel Detection function
0: A fault has not been detected via the Parallel Detection function
1: Link Partner supports Next Page exchange
0: Link Partner does not support Next Page exchange
1: Local Device is able to send Next Page
Always 1.
Link Partner Next
Pageable
RO
RO
RO
RO
0
1
0
0
Local Next
Pageable
Page Received
1: A New Page (new LCW) has been received
0: A New Page has not been received
1: Link Partner supports Auto-Negotiation
0: Link Partner does not support Auto-Negotiation
Link Partner
Auto-Negotiation
capable
Note: Register 6 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.2.8. ANNPTR (Auto-Negotiation Next Page Transmit Register,
Address 0x07)
Table 24. ANNPTR (Auto-Negotiation Next Page Transmit Register, Address 0x07)
Bit
Name
RW
Default
Description
7.15
Next Page
RW
0
Next Page Indication.
0: No more next pages to send
1: More next pages to send
Transmit Code Word Bit 15.
Transmit Code Word Bit 14.
Message Page.
7.14
7.13
RSVD
RO
0
1
Message Page
RW
0: Unformatted Page
1: Message Page
Transmit Code Word Bit 13.
Acknowledge2.
7.12
7.11
Acknowledge 2
Toggle
RW
0
0: Local device has no ability to comply with the message received
1: Local device has the ability to comply with the message received
Transmit Code Word Bit 12.
Toggle bit.
RO
0
Transmit Code Word Bit 11.
Content of message/unformatted page.
Transmit Code Word Bit 10:0.
7.10:0 Message/
Unformatted Field
RW
0x001
7.2.9. ANNPRR (Auto-Negotiation Next Page Receive Register,
Address 0x08)
Table 25. ANNPRR (Auto-Negotiation Next Page Receive Register, Address 0x08)
Bit
8.15
8.14
8.13
8.12
8.11
Name
RW
RO
RO
RO
RO
RO
RO
Default
Description
Next Page
Acknowledge
Message Page
Acknowledge 2
Toggle
0
Received Link Code Word Bit 15.
Received Link Code Word Bit 14.
Received Link Code Word Bit 13.
Received Link Code Word Bit 12.
Received Link Code Word Bit 11.
Received Link Code Word Bit 10:0.
0
0
0
0
8.10:0 Message/
Unformatted Field
Note: Register 8 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
0x00
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.3. GBCR (1000Base-T Control Register, Address 0x09)
Table 26. GBCR (1000Base-T Control Register, Address 0x09)
Bit
Name
RW
Default
Description
9.15:13 Test Mode
RW
0
Test Mode Select.
000 = Normal Mode
001 = Test Mode 1 - Transmit Jitter Test
010 = Test Mode 2 - Transmit Jitter Test (MASTER mode)
011 = Test Mode 3 - Transmit Jitter Test (SLAVE mode)
100 = Test Mode 4 - Transmit Distortion Test
101, 110, 111 = Reserved
9.12
MASTER/SLAVE
Manual
Configuration
Enable
RW
AN[3:0] Enable Manual Master/Slave Configuration.
1: Manual MASTER/SLAVE configuration
0: Automatic MASTER/SLAVE
9.11
9.10
9.9
MASTER/SLAVE
Configuration
Value
RW
RW
RW
RW
RW
AN[3:0] Advertise Master/Slave Configuration Value.
1: Manual configure as MASTER
0: Manual configure as SLAVE
Port Type
AN[3:0] Advertise Device Type Preference.
1: Prefer multi-port device (MASTER)
0: Prefer single port device (SLAVE)
AN[3:0] Advertise 1000Base-T Full-Duplex Capability.
1: Advertise
1000Base-T Full
Duplex
0: Do not advertise
9.8
1000Base-T Half
Duplex
AN[3:0] Advertise 1000Base-T Half-Duplex Capability.
1: Advertise
0: Do not advertise
9.7:0
RSVD
0
Reserved.
Note 1: Values set in register 9.12:8 have no effect unless Auto-Negotiation is restarted (Reg0.9) or the link goes down.
Note 2: Bits 9.11 and 9.10 are ignored when bit 9.12 = 0.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.3.1. GBSR (1000Base-T Status Register, Address 0x0A)
Table 27. GBSR (1000Base-T Status Register, Address 0x0A)
Bit
Name
RW
Default
Description
10.15 MASTER/SLAVE RO, SC
Configuration Fault
0
Master/Slave Manual Configuration Fault Detected.
1: MASTER/SLAVE configuration fault detected
0: No MASTER/SLAVE configuration fault detected
Master/Slave Configuration Result.
10.14 MASTER/SLAVE
Configuration
RO
RO
RO
RO
RO
0
0
0
0
0
1: Local PHY configuration resolved to MASTER
0: Local PHY configuration resolved to SLAVE
Local Receiver Status.
Resolution
10.13 Local Receiver
Status
1: Local Receiver OK
0: Local Receiver Not OK
10.12 Remote Receiver
Status
Remote Receiver Status.
1: Remote Receiver OK
0: Remote Receiver Not OK
10.11 Link Partner
1000Base-T Full
Link Partner 1000Base-T Full Duplex Capability.
1: Link Partner is capable of 1000Base-T full duplex
0: Link Partner is not capable of 1000Base-T full duplex
Link Partner 1000Base-T Half Duplex Capability.
1: Link Partner is capable of 1000Base-T half duplex
0: Link Partner is not capable of 1000Base-T half duplex
Reserved.
Duplex Capability
10.10 Link Partner
1000Base-T Half
Duplex Capability
10.9:8 RSVD
RO
00
10.7:0 Idle Error Count
RO, SC
0x00
MSB of Idle Error Counter.
The counter stops automatically when it reaches 0xff.
Note 1: Values set in register 10.11:10 are not valid until register 6.1 is set to 1.
Note 2: SC: Self-cleared after read.
Note 3: Register 10 is not valid until the Auto-Negotiation complete bit 1.5 indicates completed.
7.3.2. GBESR (1000Base-T Extended Status Register, Address 0x0F)
Table 28. GBESR (1000Base-T Extended Status Register, Address 0x0F)
Bit
Name
RW
RO
RO
RO
RO
RO
Default
Description
15.15 1000Base-X FD
15.14 1000Base-X HD
15.13 1000Base-T FD
15.12 1000Base-T HD
15.11:0 RSVD
0
0: Not 1000Base-X full duplex capable
0: Not 1000Base-X half duplex capable
1: 1000Base-T full duplex capable
1: 1000Base-T half duplex capable
Reserved.
0
1
1
0x000
Integrated 10/100/1000 Gigabit Ethernet Transceiver
30
Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.3.3. PHYCR (PHY Specific Control Register, Address 0x10)
Table 29. PHYCR (PHY Specific Control Register, Address 0x10)
Bit
Name
RW
Default
Description
16.15:12 RSVD
RW
0000
Reserved.
16.11 Assert CRS on
Transmit
RW
0
1: Assert CRS on transmit
0: Never assert CRS on transmit
1: Force link good
16.10 Force Link Good
RW
0
0: Normal operation
16.9:7 RSVD
RW
RW
000
10
Reserved.
16.6:5 MDI Crossover
Mode
01: Manual MDI configuration
00: Manual MDI Crossover configuration
Note: After setting the register, a PHY reset is required.
1: CLK125 remains at logic High
0: CLK125 Toggling
16.4
Disable CLK125
RW
0
16.3:1 RSVD
16.0 Disable Jabber
RW
RW
000
0
Reserved.
1: Disable jabber function
0: Enable jabber function
7.3.4. PHYSR (PHY Specific Status Register, Address 0x11)
Table 30. PHYSR (PHY Specific Status Register, Address 0x11)
Bit
Name
RW
Default
Description
17.15:14 Speed
RO
00
Link Speed.
11: Reserved
10: 1000Mbps
00: 10Mbps
01: 100Mbps
17.13 Duplex
RO
RO
RO
RO
0
0
0
0
Full/Half Duplex Mode.
1: Full duplex
0: Half duplex
17.12 Page received
New Page Received.
1: Page received
0: Page not received
17.11 Speed and duplex
resolved
Speed and Duplex Mode Resolved.
1: Resolved
0: Not resolved
17.10 Link (real time)
Real Time Link Status.
1: Link OK
0: Link not OK
0: MDI
17.9:7 Reserved
RO
RO
000
0
Reserved.
17.6
MDI crossover
status
MDI/MDI Crossover Status.
1: MDI Crossover
Reserved
17.5:1 RSVD
17.0 Jabber (real time)
RO
RO
00000
0
Real Time Jabber Indication.
1: Jabber Indication
0: No jabber Indication
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.3.5. INER (Interrupt Enable Register, Address 0x12)
Table 31. INER (Interrupt Enable Register, Address 0x12)
Bit
Name
RW
Default Description
18.15 Auto-Negotiation Error
Interrupt
RW
0
1: Interrupt enable
0: Interrupt disable
18.14 Speed Change Interrupt
RW
RW
0
0
1: Interrupt enable
1: Interrupt enable
0: Interrupt disable
0: Interrupt disable
18.13 Duplex Mode Change
Interrupt
18.12 Page Received Interrupt
RW
RW
0
0
1: Interrupt enable
1: Interrupt enable
0: Interrupt disable
0: Interrupt disable
18.11 Auto-Negotiation
Completed Interrupt
18.10 Link Status Change
Interrupt
RW
0
1: Interrupt enable
0: Interrupt disable
18.9
18.8
18.7
18.6
Symbol Error Interrupt
False Carrier Interrupt
Reserved
RW
RW
RW
RW
0
0
0
0
1: Interrupt enable
1: Interrupt enable
Reserved.
0: Interrupt disable
0: Interrupt disable
MDI Crossover Change
Interrupt
1: Interrupt enable
0: Interrupt disable
18.5:2 Reserved
RW
RW
RW
0
0
0
Reserved.
18.1
18.0
Polarity Change Interrupt
Jabber Interrupt
1: Interrupt enable
1: Interrupt enable
0: Interrupt disable
0: Interrupt disable
7.3.6. INSR (Interrupt Status Register, Address 0x13)
Table 32. INSR (Interrupt Status Register, Address 0x13)
Bit
Name
RW Default Description
19.15 Auto-Negotiation Error
19.14 Speed Change
RO
RO
RO
RO
RO
0
0
0
0
0
1: Auto-Negotiation Error
1: Link speed changed
0: No Auto-Negotiation Error
0: Link speed not changed
0: Duplex mode not changed
0: Page not received
19.13 Duplex Mode Change
19.12 Page Received
1: Duplex mode changed
1: Page (a new LCW) received
1: Auto-Negotiation completed
0: Auto-Negotiation not completed
1: Link status changed
19.11 Auto-Negotiation
Completed
19.10 Link Status Change
RO
RO
RO
RO
0
0
0
0
0
0: Link status not changed
0: No symbol error detected
0: No false carrier detected
19.9
19.8
19.7
19.6
Symbol Error
False Carrier
RSVD
1: Symbol error detected
1: False carrier
Reserved.
MDI Crossover Change RO
1: Crossover status changed
0: Crossover status not changed
19.5:2 RSVD
RO
RO
0000 Reserved.
19.1
Polarity Change
0
1: Polarity Changed
0: Polarity not changed
Note: This bit is valid only when 1000Base-T is enabled.
19.0
Jabber
RO
0
1: Jabber detected
0: No jabber detected
Integrated 10/100/1000 Gigabit Ethernet Transceiver
32
Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
7.3.7. EPHYCR (Extended PHY Specific Control Register, Address
0x14)
Table 33. EPHYCR (Extended PHY Specific Control Register, Address 0x14)
Name RW Default Description
RW 0 0000 0000 Reserved.
Bit
20.15:7 Reserved
20.6:4 TXC speed
RW
100
0xx: 0MHz
110: 2.5MHz
Reserved
10x: 125MHz
111: 25MHz
20.3:0 Reserved
RW
000
Note: Bits 20.6:4 specify TXC speed.
7.3.8. RXERC (Receive Error Counter, Address 0x15)
Table 34. RXERC (Receive Error Counter, Address 0x15)
Bit
Name
RW
Default
Description
21.15:0 Receive Error Count
RO
0x0000
Receive Error Count.
Note: The RXERC register is self-cleared after a read.
7.3.9. LEDCR (LED Control Register, Address 0x18)
Table 35. LEDCR (LED Control Register, Address 0x18)
Bit
Name
RW
RW
RW
Default
0
Description
24.15 Disable LED
0: Enable
1: Disable
24.14:12 LED Pulse Stretch
Duration
010
000: No pulse stretching
010: 42ms to 84ms
100: 170ms to 340ms
110: 670ms to 1.3s
Reserved.
001: 21ms to 42ms
011: 84ms to 170ms
101: 340ms to 670ms
111: 1.3s to 2.7s
24.11 RSVD
RW
RW
0
24.10:8 LED Blink Rate
111
000: 42ms
001: 84ms
010: 170ms
011: 340ms
101: 21ms
100: 670ms
110: 10ms
111: No blinking
24.7:4 RSVD
RW
RW
0100
0
Reserved.
24.3
LEDLINK Control
1: Link and Speed Indication by combination of LEDs
0: Link and Speed Indication by specific LED
Refer to section 6.7 LED Configuration, page 20.
1: Full Duplex Indication
24.2
24.1
24.0
LEDDUP Control
LEDRX Control
LEDTX Control
RW
RW
RW
0
0
0
0: Full Duplex/Collision Indication
1: Rx Activity/Link Indication
0: Rx Activity Indication only
1: Tx or Rx Activity/Link Indication
0: Tx Activity Indication only
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
8. Application Diagram
Figure 5. Application Diagram
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
9. Characteristics
9.1. Absolute Maximum Ratings
Table 36. Absolute Maximum Ratings
Minimum Maximum
-0.5
Description/Symbol
Unit
V
Supply Voltage (DVDD33, AVDD33)
Supply Voltage (AVDD18)
Supply Voltage (AVDD15, DVDD15)
Input Voltage (DC input)
4
-0.5
-0.5
-0.5
-0.5
-55
2.5
2
V
V
AVDD33 + 0.5
AVDD33 + 0.5
+125
V
Output Voltage (DC output)
Storage Temperature
V
°C
9.2. Recommended Operating Conditions
Table 37. Recommended Operating Conditions
Description
Pins
Minimum
Typical
Maximum
Unit
V
Supply Voltage VDD
DVDD33, AVDD33
3.14
1.68
1.33
0
3.3
1.8
1.5
-
3.46
2.13
1.68
70
AVDD18
V
AVDD15, DVDD15
V
Ambient Operating Temperature TA
Maximum Junction Temperature
-
-
°C
°C
-
-
125
9.3. Crystal Requirements
Table 38. Crystal Requirements
Symbol
Description/Condition
Minimum Typical
Maximum
Unit
Fref
Parallel resonant crystal reference frequency,
fundamental mode, AT-cut type.
-
25
-
-
MHz
Fref Stability
Parallel resonant crystal frequency stability,
fundamental mode, AT-cut type. Ta=25°C.
Parallel resonant crystal frequency tolerance,
-50
-30
+50
+30
ppm
ppm
Fref Tolerance
-
fundamental mode, AT-cut type. Ta=-20°C~+70°C.
Fref Duty Cycle Reference Clock Input Duty Cycle.
DL Drive Level.
40
-
-
-
60
%
0.5
mW
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
9.4. DC Characteristics
Table 39. DC Characteristics
Symbol Description
Pins Condition
Minimum Typical Maximum Unit
VIH
VIL
VOH
VOL
IIH
Input High Voltage
I
I
-
-
0.5*VDD
-
-
-
-
-
-
-
-
V
V
Input Low Voltage
Output High Voltage
Output Low Voltage
Input High Current
Input Low Current
-
0.3*VDD
O, IO VDD=Min, IOH=-8mA
0.9*VDD
-
V
O, IO VDD=Min, IOL=8mA
-
-
0.1*VDD
V
I, IO VIN=VDD, VDD=VDD (max)
I, IO VIN=GND, VDD=VDD (max)
1
-
µA
µA
µA
IIL
-1
-
IOZ
Tri-State Output
Leakage Current
IO
VOUT=VDD
10
IOZ
Tri-State Output
Leakage Current
IO
VOUT=GND
-10
-
-
µA
9.5. AC Characteristics
9.5.1. MII Timing
MII Timing – MII Management Port
tMCC
tMCH
Vih(min)
Vil(max)
MDC
tMCL
tMSU
tMRV
tMHT
Vih(min)
Vil(max)
MDIO
Figure 6. MII Management Timing Parameters
Table 40. MII Management Timing Parameters
Symbol
tMCC
tMCH
tMCL
tMSU
tMHT
tMRV
Description
Min
80
30
30
10
10
-
Max
Units
ns
MDC Cycle Time.
-
-
MDC High Time.
ns
MDC Low Time.
-
ns
MDIO Setup Time.
MDIO Hold Time.
-
ns
-
ns
MDC Clock Rise to MDIO valid.
40
ns
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
9.5.2. RGMII Timing Modes
Figure 7. RGMII Timing Modes
Integrated 10/100/1000 Gigabit Ethernet Transceiver 37
Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
Table 41. RGMII Timing Parameters
Symbol
TXC/RXC
tGCC
Description
Min
Typical
Max
Units
MHz
ns
TXC, RXC Frequency.
125~100ppm
125
8
-
125+100ppm
TXC, RXC Cycle Time.
-
-
-
tR
RXC Rise Time (20%~80%).
0.75
ns
tF
RXC Fall Time (20%~80%).
-
-
0.75
ns
TsetupT
TholdT
Tsetup
Thold
TxD, TXCLT Setup to TXC.
1
2
2
-
-
-
ns
TxD, TXCLT Hold from TXC.
TXDLY=1; TxD, TXCLT Setup to TXC.
TXDLY=1; TxD, TXCLT Hold from TXC.
Data to Clock Output Skew
0.8
-0.9
2.7
-0.5
1.2
1
ns
-
ns
-
-
ns
Tskew
TsetupR
TholdR
0
2
2
0.5
-
ns
RXDLY=1; RxD, RXCLT Setup to RXC.
RXDLY=1; RxD, RXCLT Hold from RXC.
ns
-
ns
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
10. Mechanical Dimensions
10.1. RTL8211B 64-Pin QFN Mechanical Dimensions
Note: For RTL8211B-GR specific information,
refer to line 3.
Note: Exposed Pad is Analog and Digital
Ground.
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
10.2. RTL8211BL 100-Pin LQFP Mechanical Dimensions
Notes:
1. To be determined at seating plane -c-
2. Dimensions D1 and E1 do not include mold protrusion. D1 and
E1 maximum plastic body size dimensions are maximum plastic
body size dimensions, including mold mismatch.
Symbol Dimension in inch Dimension in mm
Min Nom Max Min Nom Max
-
-
0.067
-
-
1.70
0.20
1.50
0.29
0.25
0.20
0.16
3. Dimension b does not include dambar protrusion.
Dambar can not be located on the lower radius of the foot.
4. Exact shape of each corner is optional.
5. These dimensions apply to the flat section of the lead between
0.10mm and 0.25mm from the lead tip.
6. A1 is defined as the distance from the seating plane to the lowest
point of the package body.
7. Controlling dimension: millimeter.
A
A1
A2
B
b1
C
c1
D
D1
E
0.000 0.004 0.008 0.00
0.051 0.055 0.059 1.30
0.006 0.009 0.011 0.15
0.006 0.008 0.010 0.15
0.004
0.004
0.1
1.40
0.22
0.20
-
-
-
0.008 0.09
0.006 0.09
-
0.630 BSC
0.551 BSC
0.630 BSC
0.551 BSC
0.020 BSC
16.00 BSC
14.00 BSC
16.00 BSC
14.00 BSC
0.50 BSC
8. Reference document: JEDEC MS-026, BED.
TITLE: 100LD LQFP (14x14x1.4mm)
PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm
LEADFRAME MATERIAL:
E1
0.016 0.024 0.031 0.40 0.60 0.80
APPROVE
CHECK
DOC. NO.
VERSION
PAGE
DWG NO. LQ100 - P1
DATE
L
L1
θ
θ1
θ2
θ3
0.039 REF
3.5°
1.00 REF
3.5°
1
OF
0°
0°
9°
-
0°
0°
9°
-
-
-
12°TYP
12°TYP
12°TYP
12°TYP
REALTEK SEMICONDUCTOR CORP.
Integrated 10/100/1000 Gigabit Ethernet Transceiver
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Track ID: JATR-1076-21 Rev. 1.5
RTL8211B(L)
Datasheet
11. Ordering Information
Table 42. Ordering Information
Part Number
RTL8211B-GR
RTL8211BL-GR
Package
Status
MP
64-Pin QFN with Green Package.
100-Pin LQFP with Green Package.
MP
Note: See page 2 (RTL8211B-GR) and page 3 (RTL8211BL-GR) for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
Integrated 10/100/1000 Gigabit Ethernet Transceiver
41
Track ID: JATR-1076-21 Rev. 1.5
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