RTL8201N-GR_07 [REALTEK]
SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX;
| 型号： | RTL8201N-GR_07 |
| 厂家： | 
Realtek Semiconductor Corp. |
| 描述： | SINGLE-CHIP/PORT 10/100 FAST ETHERNET PHYCEIVER WITH AUTO MDIX 局域网（LAN）标准 以太网：16GBASE-T |
| 文件： | 总39页 (文件大小：616K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RTL8201N-GR
SINGLE-CHIP/PORT
10/100M FAST ETHERNET PHYCEIVER
WITH AUTO MDIX
DATASHEET
Rev. 1.1
22 August 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw
RTL8201N
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
Release Date
2006/06/29
2006/08/22
Summary
First release.
1.1
Revised pin names:
PWFBOUT18 => PWOUT18
PWFBOUT15 => PWOUT15.
Revised Pin Assignments:
DVDD33 (pin 18, 34, 49) => NC
DVDD15 (pin 32, 45, 59) => NC (see Table 7 and Table 8).
Revised Table 30, Power Dissipation, page 24.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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Rev. 1.1
RTL8201N
Datasheet
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................2
3. APPLICATIONS..................................................................................................................................................................2
4. BLOCK DIAGRAM.............................................................................................................................................................3
5. PIN ASSIGNMENTS ...........................................................................................................................................................4
5.1.
GREEN PACKAGE AND VERSION IDENTIFICATION.........................................................................................................4
6. PIN DESCRIPTIONS ..........................................................................................................................................................5
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
MII INTERFACE ............................................................................................................................................................5
SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY ....................................................................................................6
CLOCK INTERFACE .......................................................................................................................................................6
10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................7
DEVICE CONFIGURATION INTERFACE ...........................................................................................................................7
LED INTERFACE...........................................................................................................................................................8
POWER PINS.................................................................................................................................................................8
RESET AND OTHER PINS...............................................................................................................................................8
7. REGISTER DESCRIPTIONS ............................................................................................................................................9
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
REGISTER 0 BASIC MODE CONTROL REGISTER............................................................................................................9
REGISTER 1 BASIC MODE STATUS REGISTER .............................................................................................................10
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................11
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................11
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ....................................................................11
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................12
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) .............................................................................13
REGISTER 16 NWAY SETUP REGISTER (NSR).............................................................................................................13
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR).................................................13
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................14
REGISTER 19 SNR DISPLAY REGISTER.......................................................................................................................14
REGISTER 25 TEST REGISTER.....................................................................................................................................14
8. FUNCTIONAL DESCRIPTION.......................................................................................................................................15
8.1.
8.1.1.
8.1.2.
8.2.
8.2.1.
8.2.2.
8.2.3.
8.2.4.
MII AND MANAGEMENT INTERFACE ..........................................................................................................................15
Data Transition.....................................................................................................................................................15
Serial Management...............................................................................................................................................16
AUTO-NEGOTIATION AND PARALLEL DETECTION ......................................................................................................17
Setting the Medium Type and Interface Mode to MAC.........................................................................................17
UTP Mode and MII Interface ...............................................................................................................................18
UTP Mode and SNI Interface ...............................................................................................................................18
Fiber Mode and MII Interface..............................................................................................................................18
FLOW CONTROL SUPPORT ..........................................................................................................................................19
HARDWARE CONFIGURATION AND AUTO-NEGOTIATION ............................................................................................19
SERIAL NETWORK INTERFACE....................................................................................................................................20
POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES ......................................................................20
MEDIA INTERFACE .....................................................................................................................................................21
100Base-TX Transmit & Receive Operation ........................................................................................................21
100Base-FX Fiber Transmit & Receive Operation ..............................................................................................21
10Base-T Transmit & Receive Operation.............................................................................................................22
REPEATER MODE OPERATION.....................................................................................................................................22
RESET, AND TRANSMIT BIAS ......................................................................................................................................22
8.3.
8.4.
8.5.
8.6.
8.7.
8.7.1.
8.7.2.
8.7.3.
8.8.
8.9.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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RTL8201N
Datasheet
8.10.
8.11.
3.3V POWER SUPPLY AND VOLTAGE CONVERSION CIRCUIT.......................................................................................23
FAR END FAULT INDICATION ......................................................................................................................................23
9. CHARACTERISTICS.......................................................................................................................................................24
9.1.
9.1.1.
9.1.2.
9.1.3.
9.1.4.
DC CHARACTERISTICS...............................................................................................................................................24
Absolute Maximum Ratings..................................................................................................................................24
Operating Conditions...........................................................................................................................................24
Power Dissipation ................................................................................................................................................24
Input Voltage: Vcc ................................................................................................................................................25
AC CHARACTERISTICS...............................................................................................................................................26
MII Transmission Cycle Timing............................................................................................................................26
MII Reception Cycle Timing.................................................................................................................................27
SNI Transmission Cycle Timing............................................................................................................................28
SNI Reception Cycle Timing.................................................................................................................................29
MDC/MDIO Timing..............................................................................................................................................30
CRYSTAL CHARACTERISTICS......................................................................................................................................31
TRANSFORMER CHARACTERISTICS ............................................................................................................................31
9.2.
9.2.1.
9.2.2.
9.2.3.
9.2.4.
9.2.5.
9.3.
9.4.
10.
11.
MECHANICAL DIMENSIONS ...................................................................................................................................32
ORDERING INFORMATION......................................................................................................................................33
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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Rev. 1.1
RTL8201N
Datasheet
List of Tables
Table 1. MII Interface..................................................................................................................................5
Table 2. SNI (Serial Network Interface) 10Mbps Only ..............................................................................6
Table 3. Clock Interface ..............................................................................................................................6
Table 4. 10Mbps/100Mbps Network Interface............................................................................................7
Table 5. Device Configuration Interface .....................................................................................................7
Table 6. LED Interface/PHY Address Configuration..................................................................................8
Table 7. Power Pins .....................................................................................................................................8
Table 8. Reset and Other Pins......................................................................................................................8
Table 9. Register 0 Basic Mode Control Register .......................................................................................9
Table 10. Register 1 Basic Mode Status Register........................................................................................10
Table 11. Register 2 PHY Identifier Register 1...........................................................................................11
Table 12. Register 3 PHY Identifier Register 2...........................................................................................11
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)..................................................11
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR) ....................................12
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER).........................................................13
Table 16. Register 16 NWay Setup Register (NSR)....................................................................................13
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR) ..............................13
Table 18. Register 18 RX_ER Counter (REC)............................................................................................14
Table 19. Register 19 SNR Display Register ..............................................................................................14
Table 20. Register 25 Test Register.............................................................................................................14
Table 21. Serial Management......................................................................................................................16
Table 22. Setting the Medium Type and Interface Mode to MAC..............................................................17
Table 23. UTP Mode and MII Interface ......................................................................................................18
Table 24. UTP Mode and SNI Interface......................................................................................................18
Table 25. Fiber Mode and MII Interface .....................................................................................................18
Table 26. Auto-Negotiation Mode Pin Settings ..........................................................................................19
Table 27. Power Saving Mode Pin Settings ................................................................................................20
Table 28. Absolute Maximum Ratings........................................................................................................24
Table 29. Operating Conditions...................................................................................................................24
Table 30. Power Dissipation........................................................................................................................24
Table 31. Input Voltage: Vcc.......................................................................................................................25
Table 32. MII Transmission Cycle Timing .................................................................................................26
Table 33. MII Reception Cycle Timing.......................................................................................................27
Table 34. SNI Transmission Cycle Timing .................................................................................................28
Table 35. SNI Reception Cycle Timing ......................................................................................................29
Table 36. MDC/MDIO Timing....................................................................................................................30
Table 37. Crystal Characteristics.................................................................................................................31
Table 38. Transformer Characteristics ........................................................................................................31
Table 39. Ordering Information...................................................................................................................33
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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Rev. 1.1
RTL8201N
Datasheet
List of Figures
Figure 1. Block Diagram .............................................................................................................................3
Figure 2. Pin Assignments...........................................................................................................................4
Figure 3. Read Cycle .................................................................................................................................16
Figure 4. Write Cycle ................................................................................................................................16
Figure 5. MII Transmission Cycle Timing-1.............................................................................................26
Figure 6. MII Transmission Cycle Timing-2.............................................................................................26
Figure 7. MII Reception Cycle Timing-1..................................................................................................27
Figure 8. MII Reception Cycle Timing-2..................................................................................................27
Figure 9. SNI Transmission Cycle Timing-1 ............................................................................................28
Figure 10. SNI Transmission Cycle Timing-2 ............................................................................................28
Figure 11. SNI Reception Cycle Timing-1..................................................................................................29
Figure 12. SNI Reception Cycle Timing-2..................................................................................................29
Figure 13. MDC/MDIO Timing ..................................................................................................................30
Figure 14. MDC/MDIO MAC to PHY Transmission Without Collision ...................................................30
Figure 15. MDC/MDIO PHY to MAC Reception Without Error...............................................................31
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
vi
Rev. 1.1
RTL8201N
Datasheet
1. General Description
The RTL8201N is a single-chip/single-port PHYceiver with an MII (Media Independent Interface)/SNI
(Serial Network Interface). It implements all 10/100M Ethernet Physical-layer functions including the
Physical Coding Sublayer (PCS), Physical Medium Attachment (PMA), Twisted Pair Physical Medium
Dependent Sublayer (TP-PMD), with an auto MDIX function, 10Base-Tx Encoder/Decoder, and
Twisted-Pair Media Access Unit (TPMAU).
A PECL (Pseudo Emitter Coupled Logic) interface is supported to connect with an external 100Base-FX
fiber optical transceiver. The chip utilizes an advanced CMOS process to meet low voltage and low
power requirements. With on-chip DSP (Digital Signal Processing) technology, the chip provides
excellent performance under all operating conditions.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
1
Rev. 1.1
RTL8201N
Datasheet
2. Features
The Realtek RTL8201N is a Fast Ethernet PHYceiver with selectable MII, RMII, or SNI interface to the
MAC chip. It provides the following features:
Supports auto MDIX
Pin-to-pin compatible with the RTL8211B
Supports repeater mode
Supports MII and 7-wire SNI (Serial Network
Interface)
Adaptive Equalization
Supports RMII mode (new RTL8201N
Network status LEDs
function)
Flow control support
10/100Mbps operation
25MHz crystal/oscillator as clock source
IEEE 802.3/802.3u compliant
Full/half duplex operation
Twisted pair or fiber mode output
Auto-Negotiation
Supports IEEE 802.3u clause 28; 1.5V
operation with 3.3V IO signal tolerance
Supports power down mode
Low power supply, 1.5V, 1.8V and 3.3V;
1.5V/1.8V is generated by an internal
regulator
Supports operation under Link Down Power
Saving mode
0.15µm CMOS process
64-pin QFN package
Supports Base Line Wander (BLW)
compensation
3. Applications
Network Interface Adapter
MAU (Media Access Unit)
CNR (Communication and Network Riser)
ACR (Advanced Communication Riser)
Ethernet hub
Ethernet switch
In addition, it can be used in any embedded system with an Ethernet MAC that needs a UTP physical
connection or Fiber PECL interface to an external 100Base-FX optical transceiver module.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
2
Rev. 1.1
RTL8201N
Datasheet
4. Block Diagram
Figure 1. Block Diagram
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
3
Rev. 1.1
RTL8201N
Datasheet
5. Pin Assignments
Figure 2. Pin Assignments
5.1. Green Package and Version Identification
Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 2.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
4
Rev. 1.1
RTL8201N
Datasheet
6. Pin Descriptions
LI: Latched Input during Power up or Reset
IO: Bi-directional input and output
O: Output
P: Power
I: Input
6.1. MII Interface
Table 1. MII Interface
Description
Transmit Clock.
Name
Type
Pin No.
TXC
O
24
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
TXEN
TXD[3:0]
RXC
I
I
29
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0]. An
internal weak pull low resistor to prevent the bus floating.
28, 27, 26, 25 Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is
asserted. An internal weak pull high resistor prevents the bus floating.
O
22
46
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3]
signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
COL/
LI/O
Collision Detect.
CONFIG[6]
COL is asserted high when a collision is detected on the media.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: SNI mode
1: MII mode
This pin can be directly connected to GND or VCC.
CRS/
CONFIG[5]
LI/O
LI/O
47
16
Carrier Sense.
This pin’s signal is asserted high if the media is not in Idle state.
During power on reset, this pin set high to put the RTL8201N into repeater
mode. This pin can be directly connected to GND or VCC.
RXDV/
RMII
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the RXD[3:0]
lines. The signal is de-asserted at the end of the packet. The signal is valid on the
rising edge of the RXC.
During power on reset, this pin status is latched to determine at which interface
mode to operate:
0: MII mode
1: RMII mode
This pin can be directly connected to GND or VCC.
RXD[3:0]
O
21, 20, 19, 17 Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
5
Rev. 1.1
RTL8201N
Datasheet
Name
RXER/
Type
Pin No.
Description
LI/O
35
Receive Error.
CONFIG[8]
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid
symbol, this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is possible to
use an external 5.1KΩ pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
MDC
I
30
31
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be asynchronous to
the transmit TXC and receive RXC clocks. The clock rate can be up to 2.5MHz.
Use an internal weak pull high resistor to prevent the bus floating.
MDIO
IO
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.
6.2. SNI (Serial Network Interface) 10Mbps Only
Table 2. SNI (Serial Network Interface) 10Mbps Only
Name
COL
Type
O
Pin No.
46
Description
Collision Detect.
RXD0
CRS
O
17
Received Serial Data.
Carrier Sense.
O
47
RXC
O
22
Receive Clock.
Resolved from received data.
Transmit Serial Data.
Transmit Clock.
TXD0
TXC
I
25
24
O
Generated by PHY.
Transmit Enable.
TXEN
I
29
For MAC to indicate transmit operation.
6.3. Clock Interface
Table 3. Clock Interface
Name
Type
Pin No.
Description
CKXTAL2
O
62
25MHz Crystal Output.
This pin provides the 25MHz crystal output. It must be left open when an external
25MHz oscillator drives X1.
CKXTAL1
I
61
25MHz Crystal Input.
This pin provides the 25MHz crystal input. If a 25MHz oscillator is used, connect
X1 to the oscillator’s output (see 9.3 Crystal Characteristics, page 31, for clock
source specifications).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
6
Rev. 1.1
RTL8201N
Datasheet
6.4. 10Mbps/100Mbps Network Interface
Table 4. 10Mbps/100Mbps Network Interface
Name
MDI+[0]
MDI-[0]
Type
O
O
Pin No.
Description
3
4
Transmit Output.
Differential transmit output pair shared by 100Base-TX, 100Base-FX and 10Base-
T modes. When configured as 100Base-TX, output is an MLT-3 encoded
waveform. When configured as 100Base-FX, the output is pseudo-ECL level.
RSET
I
1
Transmit Bias Resistor Connection.
This pin should be pulled to GND by a 2KΩ (1%) resistor to define driving current
for the transmit DAC. The resistance value may be changed, depending on
experimental results of the RTL8201N.
MDI+[1]
MDI-[1]
I
I
6
7
Receive Input.
Differential receive input pair shared by 100Base-TX, 100Base-FX, and 10Base-T
modes.
6.5. Device Configuration Interface
Table 5. Device Configuration Interface
Description
53, 54, 56, PHYAddress.
Name
Type
Pin No.
CONFIG[4:0]
I
57, 58
Set the PHY address for the device.
CONFIG[5] LI/O
CONFIG[6] LI/O
47
Repeater mode.
Set high to put the RTL8201N into repeater mode. Thispincan bedirectlyconnected
to GND or VCC.
46
37
35
MII/SNI interface.
This pin is latched to input during a power on or reset condition. Pull high to set
the RTL8201N into SNI mode operation. Set low for MII mode. Thispin canbe
directly connected to GND or VCC.
CONFIG[7]
LI
Auto-negotiation mode.
This pin is latched to input during a power on or reset condition. Set high to enable
Auto-negotiation mode, set low to force mode. Thispin canbe directlyconnected to
GND or VCC.
CONFIG[8] LI/O
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor sets this to the default of UTP mode. It is possible to
use an external 5.1KΩ pull high resistor to enable fiber mode.
CONFIG[9]
ISOLATE
LI
I
33
52
Speed mode.
This pin is latched to input during a power on or reset condition. Set high to put
the RTL8201N into 100Mbps operation. This pin can be directly connected to GND or
VCC.
Set high to isolate the RTL8201N from the MAC. This will also isolate the MDC/MDIO
management interface. In this mode, the power consumption is minimal. This pin can be
directly connected to GND or VCC.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
7
Rev. 1.1
RTL8201N
Datasheet
Name
Type
Pin No.
Description
DUPLEX
LI
51
This pin is latched to input during a power on or reset condition. Set high to enable
full duplex. This pin can be directly connected to GND or VCC.
LDPS
I
44
Set high to put the RTL8201N into LDPS mode. Thispin can bedirectlyconnected to
GND or VCC (see 8.6 Power Down, Link Down, Power Saving, and Isolation
Modes, page 20, for more information).
6.6. LED Interface
Table 6. LED Interface/PHY Address Configuration
Name
Type Pin No. Description
LED_LINK10
LED_LINK100
LED_DUPLEX
LED_RX
O
O
O
O
O
50
48
43
40
39
10Mbps link indicator.
100Mbps link indicator.
Duplex LED.
Receive LED.
LED_TX
Transmit LED.
6.7. Power Pins
Table 7. Power Pins
Name
Type
Pin No.
Description
AVDD33
P
60
3.3V Analog Power Input.
3.3V power supply for analog circuit; should be well decoupled.
3.3V Digital Power Input.
DVDD33
P
23, 42, 55
3.3V power supply for digital circuit.
Analog Power. 1.8V.
AVDD18
DVDD15
P
P
5, 10
36
Digital Power. 1.5V.
6.8. Reset and Other Pins
Table 8. Reset and Other Pins
Name
Type
Pin No.
Description
PHYRSTB
I
38
RESETB.
Set low to reset the chip. For a complete reset, this pin must be asserted low
for at least 10ms.
PWOUT18
PWOUT15
O
O
2
64
Power Output.
Be sure to connect a 22uF tantalum capacitor for frequency compensation.
The connection method is outlined in 8.10 3.3V Power Supply and Voltage
Conversion Circuit, page 23.
NC
8, 9, 11~15, 18, Not Connected.
32, 34, 41, 45, 49,
59, 63
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
8
Rev. 1.1
RTL8201N
Datasheet
7. Register Descriptions
This section describes the functions and usage of the registers available in the RTL8201N.
In this section the following abbreviations are used:
RO: Read Only
RW: Read/Write
7.1. Register 0 Basic Mode Control Register
Table 9. Register 0 Basic Mode Control Register
Address
Name
Description
Mode
Default
0:15
Reset
This bit sets the status and control registers of the PHY in the default
state. This bit is self-clearing.
1: Software reset
RW
RW
RW
0
0: Normal operation
0:14
0:13
Loopback This bit enables loopback of transmit data nibbles TXD3:0 to the
0
0
receive data path.
1: Enable loopback
0: Normal operation
Spd_Set
This bit sets the network speed.
1: 100Mbps
0: 10Mbps
After completing auto negotiation, this bit will reflect the Speed status.
1: 100Base-T
0: 10Base-T
When 100Base-FX mode is enabled, this bit=1 and is read only.
0:12
0:11
Auto
Negotiation
Enable
This bit enables/disables the NWay auto-negotiation function.
1: Enable auto-negotiation; bits 0:13 and 0:8 will be ignored.
0: Disable auto-negotiation; bits 0:13 and 0:8 will determine the link
speed and the data transfer mode, respectively.
RW
RW
1
0
When 100Base-FX mode is enabled, this bit=0 and is read only.
Power Down This bit turns down the power of the PHY chip, including the internal
crystal oscillator circuit. The MDC, MDIO is still alive for accessing
the MAC.
1: Power down
0: Normal operation
0:10
0:9
Reserved
Restart Auto This bits allows the NWay auto-negotiation function to be reset.
Negotiation
RW
RW
0
0
1: Re-start auto-negotiation
0: Normal operation
0:8
Duplex
Mode
This bit sets the duplex mode if auto-negotiation is disabled
(bit 0:12=0).
1: Full duplex
0: Half duplex
After completing auto-negotiation, this bit will reflect the duplex status.
1: Full duplex
0: Half duplex
0:7:1
Reserved
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
9
Rev. 1.1
RTL8201N
Datasheet
Address
Name
Description
Mode
Default
0:0
RMII Mode This bit sets the RMII mode.
1: RMII mode
RW
0
0: MII mode
7.2. Register 1 Basic Mode Status Register
Table 10. Register 1 Basic Mode Status Register
Address
Name
Description
Mode
Default
1:15
100Base-T4
1: Enable 100Base-T4 support
0: Suppress 100Base-T4 support
RO
0
1:14
1:13
1:12
1:11
100Base_TX_ FD 1: Enable 100Base-TX full duplex support
0: Suppress 100Base-TX full duplex support
RO
RO
RO
RO
1
1
1
1
100BASE_TX_HD 1: Enable 100Base-TX half duplex support
0: Suppress 100Base-TX half duplex support
10Base_T_FD
1: Enable 10Base-T full duplex support
0: Suppress 10Base-T full duplex support
1: Enable 10Base-T half duplex support
0: Suppress 10Base-T half duplex support
10_Base_T_HD
1:10~7
1:6
Reserved
MF Preamble
Suppression
The RTL8201N will accept management frames with preamble
suppressed.
RO
1
A minimum of 32 preamble bits are required for the first SMI
read/write transaction after reset. One idle bit is required
between any two management transactions as per IEEE 802.3u
specifications.
1:5
1:4
Auto Negotiation 1: Auto-negotiation process completed
RO
RO
0
0
Complete
0: Auto-negotiation process not completed
Remote Fault
1: Remote fault condition detected (cleared on read)
0: No remote fault condition detected
When in 100Base-FX mode, this bit means an in-band signal
Far-End-Fault has been detected (see 8.11 Far End Fault
Indication, page 23).
1:3
1:2
1:1
1:0
Auto Negotiation 1: Link has not experienced fail state
0: Link experienced fail state
RO
RO
RO
RO
1
0
0
1
Link Status
1: Valid link established
0: No valid link established
1: Jabber condition detected
0: No jabber condition detected
Jabber Detect
Extended Capability 1: Extended register capability
0: Basic register capability only
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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RTL8201N
Datasheet
7.3. Register 2 PHY Identifier Register 1
Table 11. Register 2 PHY Identifier Register 1
Address
Name
Description
Mode
Default
2:15~0
PHYID1
PHY identifier ID for software recognition of the RTL8201N.
RO
0000
7.4. Register 3 PHY Identifier Register 2
Table 12. Register 3 PHY Identifier Register 2
Address
Name
Description
Mode
Default
3:15~0
PHYID2
PHY identifier ID for software recognition of the RTL8201N.
RO
8201
7.5. Register 4 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner
during auto-negotiation.
Table 13. Register 4 Auto-Negotiation Advertisement Register (ANAR)
Address
Name
Description
Mode
Default
4:15
NP
Next Page bit.
RO
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
1: Acknowledge reception of link partner capability data word
0: Do not acknowledge reception
4:14
4:13
ACK
RF
RO
0
0
1: Advertise remote fault detection capability
0: Do not advertise remote fault detection capability
RW
4:12
4:11
Reserved
TXFC
1: TX flow control is supported by local node
0: TX flow control not supported by local node
1: RX flow control is supported by local node
0: RX flow control not supported by local node
1: 100Base-T4 is supported by local node
0: 100Base-T4 not supported by local node
1: 100Base-TX full duplex is supported by local node
0: 100Base-TX full duplex not supported by local node
1: 100Base-TX is supported by local node
0: 100Base-TX not supported by local node
1: 10Base-T full duplex supported by local node
0: 10Base-T full duplex not supported by local node
1: 10Base-T is supported by local node
RW
RW
RO
0
4:10
4:9
RXFC
T4
0
0
4:8
TXFD
TX
RW
RW
RW
RW
RW
1
4:7
1
4:6
10FD
10
1
1
4:5
0: 10Base-T not supported by local node
4:4~0
Selector
Binary encoded selector supported by this node. Currently only
CSMA/CD 00001 is specified. No other protocols are supported.
00001
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RTL8201N
Datasheet
7.6. Register 5 Auto-Negotiation Link Partner Ability Register
(ANLPAR)
This register contains the advertised abilities of the Link Partner as received during auto-negotiation. The
content changes after a successful auto-negotiation if Next-pages are supported.
Table 14. Register 5 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Address
Name
Description
Mode
Default
5:15
NP
Next Page bit.
RO
0
0: Transmitting the primary capability data page
1: Transmitting the protocol specific data page
5:14
5:13
ACK
RF
1: Link partner acknowledges reception of local node’s capability
data word
0: No acknowledgement
RO
RO
0
0
1: Link partner is indicating a remote fault
0: Link partner is not indicating a remote fault
5:12
5:11
Reserved
TXFC
1: TX flow control is supported by Link partner
0: TX flow control not supported by Link partner
1: RX flow control is supported by Link partner
0: RX flow control not supported by Link partner
1: 100Base-T4 is supported by link partner
0: 100Base-T4 not supported by link partner
1: 100Base-TX full duplex is supported by link partner
0: 100Base-TX full duplex not supported by link partner
RO
RO
RO
RO
RO
0
0
0
0
0
5:10
5:9
5:8
5:7
RXFC
T4
TXFD
100BASE-TX 1: 100Base-TX is supported by link partner
0: 100Base-TX not supported by link partner
This bit will also be set if the link in 100Base is established by
parallel detection.
5:6
5:5
10FD
1: 10Base-T full duplex is supported by link partner
0: 10Base-T full duplex not supported by link partner
RO
RO
0
0
10Base-T
1: 10Base-T is supported by link partner
0: 10Base-T not supported by link partner
This bit will also be set if the link in 10Base-T is established by
parallel detection.
5:4~0
Selector
Link Partner’s binary encoded node selector. Currently only
CSMA/CD 00001 is specified
RO
00000
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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RTL8201N
Datasheet
7.7. Register 6 Auto-Negotiation Expansion Register (ANER)
This register contains additional status for NWay auto-negotiation.
Table 15. Register 6 Auto-Negotiation Expansion Register (ANER)
Name Description
Address
6:15~5
6:4
Mode
Default
Reserved
MLF
This bit is permanently set to 0.
Indicates whether a multiple link fault has occurred.
1: Fault occurred
RO
0
0: No fault occurred
6:3
LP_NP_ABLE Indicates whether the link partner supports Next Page negotiation.
RO
0
1: Supported
0: Not supported
6:2
6:1
NP_ABLE
PAGE_RX
This bit indicates whether the local node is able to send additional
Next Pages. Internal use only.
RO
RO
0
0
This bit is set when a new Link Code Word Page has been
received. It is automatically cleared when the auto-negotiation link
partner’s ability register (register 5) is read by management.
6:0
LP_NW_ABLE 1: Link partner supports NWay auto-negotiation.
RO
0
7.8. Register 16 NWay Setup Register (NSR)
Table 16. Register 16 NWay Setup Register (NSR)
Address
16:15~12
16:11
16:10
16:9
Name
Reserved
ENNWLE
Testfun
Description
Mode
Default
1: LED4 Pin indicates link pulse
RW
RW
RW
0
0
0
1: Auto-negotiation speeds up internal timer
1: Set NWay to loopback mode
NWLPBK
Reserved
FLAGABD
FLAGPDF
FLAGLSC
16:8~3
16:2
1: Auto-negotiation experienced ability detect state
1: Auto-negotiation experienced parallel detection fault state
1: Auto-negotiation experienced link status check state
RO
RO
RO
0
0
0
16:1
16:0
7.9. Register 17 Loopback, Bypass, Receiver Error Mask Register
(LBREMR)
Table 17. Register 17 Loopback, Bypass, Receiver Error Mask Register (LBREMR)
Address
17:15
Name
RPTR
Description
Mode
RW
Default
Set to 1 to put the RTL8201N into repeater mode.
0
0
17:14
BP_4B5B
Assertion of this bit allows bypassing of the 4B/5B & 5B/4B
encoder.
RW
17:13
BP_SCR
Assertion of this bit allows bypassing of the
scrambler/descrambler.
RW
0
17:12
17:11
LDPS
Set to 1 to enable Link Down Power Saving mode.
RW
RW
0
0
AnalogOFF
Set to 1 to power down analog function of transmitter and receiver.
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Datasheet
Address
17:10
17:9
Name
Reserved
LB
Description
Mode
Default
Reserved.
Set to 1 to enable DSP Loopback.
RW
RW
RW
RW
RW
RW
0
1
1
1
0
0
17:8
F_Link_10
F_Link_100
JBEN
Used to logic force good link in 10Mbps for diagnostic purposes.
Used to logic force good link in 100Mbps for diagnostic purposes.
Set to 1 to enable Jabber Function in 10Base-T.
Assertion of this bit causes a code error detection to be reported.
17:7
17:6
17:5
CODE_err
PME_err
17:4
Assertion of this bit causes a pre-mature end error detection to be
reported.
17:3
17:2
LINK_err
PKT_err
Assertion of this bit causes a link error detection to be reported.
RW
RW
0
0
Assertion of this bit causes a ‘detection of packet errors due to
722 ms time-out’ to be reported.
17:1
17:0
FXMODE
This bit indicates whether Fiber Mode is Enabled.
RW
RW
0
0
SNIBMODE This bit indicates whether SNI mode is Enabled.
7.10. Register 18 RX_ER Counter (REC)
Table 18. Register 18 RX_ER Counter (REC)
Address
Name
Description
Mode
Default
18:15~0
RXERCNT
This 16-bit counter increments by 1 for each invalid packet
received. The value is valid while the link is established.
RO
H’[0000]
7.11. Register 19 SNR Display Register
Table 19. Register 19 SNR Display Register
Address
Name
Description
Mode
Default
19:15~4
Reserved
Realtek Test Mode Internal use. Do not change this field without
Realtek’s approval.
19:3~0
SNR
These 4-bits show the Signal to Noise Ratio value.
RW
0000
7.12. Register 25 Test Register
Table 20. Register 25 Test Register
Description
Reserved for internal testing.
Address
25:15~12
25:11~7
Name
Mode
RW
Default
Test
PHYAD[4:0] Reflects the PHY address defined by external PHY address
configuration pins.
RO
00001
25:6~2
25:1
Test
Reserved for internal testing.
RO
RO
LINK10
1: 10Base-T link established
0
0
0: No 10Base-T link established
1: 100Base-FX or 100Base-TX link established
0: No 100Base link established
25:0
LINK100
RO
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Rev. 1.1
RTL8201N
Datasheet
8. Functional Description
The RTL8201N PHYceiver is a physical layer device that integrates 10Base-T and
100Base-TX/100Base-FX functions, and some extra power management features into a 64-pin single chip
that is used in 10/100 Fast Ethernet applications. This device supports the following functions:
• MII interface with MDC/MDIO SMI management interface to communicate with MAC
• IEEE 802.3u clause 28 Auto-Negotiation ability
• Flow control ability support to cooperate with MAC
• Speed, duplex, auto-negotiation ability configurable by hard wire or MDC/MDIO
• Flexible LED configuration
• 7-wire SNI (Serial Network Interface) support (only in 10Mbps mode)
• Power Down mode support
• 4B/5B transform
• Scrambling/De-scrambling
• NRZ to NRZI, NRZI to MLT-3
• Manchester Encode and Decode for 10Base-T operation
• Clock and Data recovery
• Adaptive Equalization
• Far End Fault Indication (FEFI) in fiber mode
8.1. MII and Management Interface
8.1.1. Data Transition
To set the RTL8201N for MII mode operation, pull the MII/SNIB pin high and set the ANE, SPEED, and
DUPLEX pins.
The MII (Media Independent Interface) is an 18-signal interface (as described in IEEE 802.3u) supplying
a standard interface between the PHY and MAC layer. This interface operates at two frequencies –
25MHz and 2.5MHz to support 100Mbps/10Mbps bandwidth for both transmit and receive functions.
Transmission
The MAC asserts the TXEN signal. It then changes byte data into 4-bit nibbles and passes them to the
PHY via TXD[0..3]. The PHY will sample TXD[0..3] synchronously with TXC – the transmit clock
signal supplied by PHY – during the interval TXEN is asserted.
Reception
The PHY asserts the RXEN signal. It passes the received nibble data RXD[0..3] clocked by RXC. CRS
and COL signals are used for collision detection and handling.
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RTL8201N
Datasheet
In 100Base-TX mode, when the decoded signal in 5B is not IDLE, the CRS signal will assert. When 5B is
recognized as IDLE it will be de-asserted. In 10Base-T mode, CRS will assert when the 10M preamble
has been confirmed and will be de-asserted when the IDLE pattern has been confirmed.
The RXDV signal will be asserted when decoded 5B are /J/K/ and will be de-asserted if the 5B are /T/R/
or IDLE in 100Mbps mode. In 10Mbps mode, the RXDV signal is the same as the CRS signal.
The RXER (Receive Error) signal will be asserted if any 5B decode errors occur, e.g., an invalid J/K,
invalid T/R, or invalid symbol. This pin will go high for one or more clock periods to indicate to the
reconciliation sublayer that an error was detected somewhere in the frame.
Note: The RTL8201N does not use a TXER signal. This does not affect the transmit function.
8.1.2. Serial Management
The MAC layer device can use the MDC/MDIO management interface to control a maximum of 31
RTL8201N devices, configured with different PHY addresses (00001b to 11111b). During a hardware
reset, the logic levels of pins 58, 57, 56, 54, and 52 are latched into the RTL8201N to be set as the PHY
address for management communication via the serial interface. Setting the PHY address to 00000b will
put the RTL8201N into power down mode. The read and write frame structure for the management
interface is illustrated in Figure 3 and Figure 4.
MDC
Z
0
1
1
0
A4 A3 A2
A1 A0 R4 R3 R2 R1 R0
REGAD[4:0]
0
D14
D15 D13 D12
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATA
32 1s
MDIO
Preamble
ST
OP
PHYAD[4:0]
TA
Idle
MDIO is sourced by PHY. Clock data from PHY on rising edge of MDC
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 3. Read Cycle
MDC
0
1
0
1
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHYAD[4:0] REGAD[4:0]
1
0
D14
D11 D10
D8 D7 D6 D5 D4 D3 D2
DATA
MDIO
D15
D13 D12
D9
D1 D0
32 1s
OP
Preamble
ST
TA
Idle
MDIO is sourced by MAC. Clock data into PHY on rising edge of MDC
Figure 4. Write Cycle
Table 21. Serial Management
Name
Description
Preamble
32 contiguous logical ‘1’s sent by the MAC on MDIO along with 32 corresponding cycles on MDC. This
provides synchronization for the PHY.
ST
OP
Start of Frame. Indicated by a 01 pattern.
Operation Code.
Read: 10
Write: 01
PHYAD
REGAD
PHY Address. Up to 31 PHYs can be connected to one MAC. This 5-bit field selects which PHY the frame
is directed to.
Register Address. This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
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RTL8201N
Datasheet
Name
Description
TA
Turnaround. This is a 2-bit time-spacing between the register address and the data field of a frame to avoid
contention during a read transaction. For a read transaction, both the STA and the PHY remain in a high-
impedance state for the first bit time of the turnaround. The PHY drives a zero bit during the second bit
time of the turnaround of a read transaction.
DATA
IDLE
Data. These are the 16 bits of data.
Idle Condition. Not truly part of the management frame. This is a high impedance state. Electrically, the
PHY’s pull-up resistor will pull the MDIO line to a logical ‘1’.
8.2. Auto-Negotiation and Parallel Detection
The RTL8201N supports IEEE 802.3u clause 28 Auto-negotiation for operation with other transceivers
supporting auto-negotiation. The RTL8201N can auto-detect the link partner’s abilities and determine the
highest speed/duplex configuration possible between the two devices. If the link partner does not support
auto-negotiation, then the RTL8201N will enable half duplex mode and enter parallel detection mode.
The RTL8201N will default to transmitting FLP (Fast Link Pulse) and wait for the link partner to
respond. If the RTL8201N receives a FLP, then the auto-negotiation process will go on. If it receives
NLP (Normal Link Pulse), then the RTL8201N will change to 10Mbps and half duplex mode. If it
receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode.
To enable auto-negotiation mode operation on the RTL8201N, pull the ANE (Auto-Negotiation Enable)
pin high. The SPEED and DUPLEX pins will set the ability content of the auto-negotiation register.
Auto-negotiation mode can be externally disabled by pulling the ANE pin low. In this case, the SPEED
pin and DUPLEX pin will change the media configuration of the RTL8201N.
The following is a list of all configurations of the ANE/SPEED/DUPLEX pins and their operation in
Fiber or UTP mode.
8.2.1. Setting the Medium Type and Interface Mode to MAC
Table 22. Setting the Medium Type and Interface Mode to MAC
FX (Pin 35)
MII/SNIB (Pin 46) Operation Mode
L
L
H
H
L
UTP mode and MII interface.
UTP mode and SNI interface.
Fiber mode and MII interface.
X
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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RTL8201N
Datasheet
8.2.2. UTP Mode and MII Interface
Table 23. UTP Mode and MII Interface
ANE
(Pin 37)
SPEED
(Pin 33)
DUPLEX Operation
(Pin 51)
Auto-negotiation enabled. The ability field does not support 100Mbps or full
duplex mode operation.
H
H
H
H
L
L
L
L
L
L
L
Auto-negotiation enabled. The ability field does not support 100Mbps
operation.
H
L
Auto-negotiation enabled. The ability field does not support full duplex mode
operation.
H
H
L
Default setup, auto-negotiation enabled. The RTL8201N supports 10Base-T
/100Base-TX, half/full duplex mode operation.
H
L
Auto-negotiation disabled. Forces the RTL8201N into 10Base-T and half
duplex mode.
Auto-negotiation disabled. Forces the RTL8201N into 10Base-T and full
duplex mode.
L
H
L
Auto-negotiation disabled. Forces the RTL8201N into 100Base-TX and half
duplex mode.
H
H
Auto-negotiation disabled. Forces the RTL8201N into 100Base-TX and full
duplex mode.
H
8.2.3. UTP Mode and SNI Interface
SNI interface to MAC (only operates in 10Base-T when the SNI interface is enabled)
Table 24. UTP Mode and SNI Interface
ANE
(Pin 37)
X
SPEED
(Pin 33)
X
DUPLEX
(Pin 51)
L
Operation
The duplex pin is pulled low to support the 10Base-T half duplex function.
10Base-T half duplex is the specified default mode in the SNI interface.
X
X
H
The RTL8201N also supports full duplex in SNI mode. The duplex pin is
pulled high to support 10Base-T full duplex function.
8.2.4. Fiber Mode and MII Interface
The RTL8201N only supports 100Base-FX when Fiber mode is enabled. ANE (Auto-Negotiation Enable)
and SPEED configuration is ignored when Fiber mode is enabled.
Table 25. Fiber Mode and MII Interface
ANE
(Pin 37)
X
SPEED
(Pin 33)
X
DUPLEX
(Pin 51)
Operation
H
L
The duplex pin is pulled high to support 100Base-FX full duplex function.
The duplex pin is pulled low to support 100Base-FX half duplex function.
X
X
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Datasheet
8.3. Flow Control Support
The RTL8201N supports flow control indications. The MAC can program the MII register to indicate to
the PHY that flow control is supported. When the MAC supports the Flow Control mechanism, setting
bit 10 of the ANAR register using the MDC/MDIO SMI interface, then the RTL8201N will add the
ability to its NWay ability. If the Link partner also supports Flow Control, then the RTL8201N can
recognize the Link partner’s NWay ability by examining bit 10 of ANLPAR (register 5).
8.4. Hardware Configuration and Auto-Negotiation
This section describes methods to configure the RTL8201N and set the auto-negotiation mode. Table 26
shows the various pins and their settings.
Table 26. Auto-Negotiation Mode Pin Settings
Pin Name
Description
Isolate
Set high to isolate the RTL8201N from the MAC. This will also isolate the MDC/MDIO management
interface. In this mode, power consumption is minimum (see 8.6 Power Down, Link Down, Power
Saving, and Isolation Modes, page 20).
RPTR
Pull high to set the RTL8201N into repeater mode. This pin is pulled low by default (see 8.8 Repeater
Mode Operation, page 22).
LDPS
Pull high to set the RTL8201N into LDPS mode. This pin is pulled low by default (see 8.6 Power
Down, Link Down, Power Saving, and Isolation Modes, page 20).
MII/SNIB
Pull high to set RTL8201N into MII mode operation, which is the default mode for the RTL8201.
This pin pulled low will set the RTL8201N into SNI mode operation. When set to SNI mode, the
RTL8201N will operate at 10Mbps (see 8.5 Serial Network Interface, page 20).
ANE
Auto-Negotiation Enable. Pull high to enable auto-negotiation (default). Pull low to
disable auto-negotiation and activate the parallel detection mechanism (see 0
Auto-Negotiation and Parallel Detection, page 17).
SPEED
When ANE is pulled high, the ability to adjust speed is setup. When ANE is pulled
low, pull this pin low to force 10Mbps operation and high to force 100Mbps operation
(see 0
Auto-Negotiation and Parallel Detection, page 17).
DUPLEX
When ANE is pulled high, the ability to adjust the DUPLEX pin will be setup. When
ANE is pulled low, pull this pin low to force half duplex, high to force full duplex
operation (see 0
Auto-Negotiation and Parallel Detection, page 17).
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Datasheet
8.5. Serial Network Interface
The RTL8201N also supports the traditional 7-wire serial interface to operate with legacy MACs or
embedded systems. To setup for this mode of operation, pull the MII/SNIB pin low. By doing so, the
RTL8201N will ignore the setup of the ANE and SPEED pins. In this mode, the RTL8201N will set the
default operation to 10Mbps and half-duplex mode.
Note: The RTL8201N also supports full-duplex mode operation if the DUPLEX pin has been pulled high.
This interface consists of a 10Mbps transmit and receive clock generated by PHY, 10Mbps transmit and
receive serial data, transmit enable, collision detect, and carry sense signals.
8.6. Power Down, Link Down, Power Saving, and Isolation Modes
Four types of Power Saving mode operation are supported. This section describes how to implement each
mode. The first three modes are configured through software, and the fourth through hardware.
Table 27. Power Saving Mode Pin Settings
Mode
Description
Analog Off
Setting bit 11 of register 17 to 1 will put the RTL8201N into analog off state. In analog off state, the
RTL8201N will power down all analog functions such as transmit, receive, PLL, etc. However, the
internal 25MHz crystal oscillator will not be powered down. Digital functions in this mode are still
available which allows reacquisition of analog functions
LDPS
Setting bit 12 of register 17 to 1, or pulling the LDPS pin high will put the RTL8201N into LDPS
(Link Down Power Saving) mode. In LDPS mode, the RTL8201N will detect the link status to decide
whether or not to turn off the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps
NLP will not be transmitted. However, some signals similar to NLP will be transmitted. Once the
receiver detects leveled signals, it will stop the signal and transmit FLP or 100Mbps IDLE/10Mbps
NLP again. This can cut power used by 60%~80% when the link is down.
PWD
Setting bit 11 of register 0 to 1 puts the RTL8201N into power down mode. This is the maximum
power saving mode while the RTL8201N is still alive. In PWD mode, the RTL8201N will turn off all
analog/digital functions except the MDC/MDIO management interface. Therefore, if the RTL8201N
is put into PWD mode and the MAC wants to recall the PHY, it must create the MDC/MDIO timing
by itself (this is done by software).
Isolation
This mode is different from the three previous software configured power saving modes. This mode is
configured by hardware pin 52. Setting pin 52 high will isolate the RTL8201N from the Media Access
Controller (MAC) and the MDC/MDIO management interface. In this mode, power consumption is
minimal.
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Datasheet
8.7. Media Interface
8.7.1. 100Base-TX Transmit & Receive Operation
100Base-TX Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 25MHz (TXC) is transformed into 5B symbol code
(4B/5B encoding). Scrambling, serializing, and conversion to 125MHz, and NRZ to NRZI then takes
place. After this process, the NRZI signal is passed to the MLT-3 encoder, then to the transmit line driver.
The transmitter will first assert TXEN. Before transmitting the data pattern, it will send a /J/K/ symbol
(Start-of-frame delimiter), the data symbol, and finally a /T/R/ symbol known as the End-Of-Frame
delimiter. For better EMI performance, the seed of the scrambler is based on the PHY address. In a
hub/switch environment, each RTL8201N will have different scrambler seeds and so spread the output of
the MLT-3 signals.
100Base-TX Receive
The received signal is compensated by the adaptive equalizer to make up for signal loss due to cable
attenuation and Inter Symbol Interference (ISI). Baseline Wander Correction monitors the process and
dynamically applies corrections to the process of signal equalization. The PLL then recovers the timing
information from the signals and from the receive clock. With this, the received signal is sampled to form
NRZI data. The next steps are the NRZI to NRZ process, unscrambling of the data, serial to parallel and
5B to 4B conversion, and passing of the 4B nibble to the MII interface.
8.7.2. 100Base-FX Fiber Transmit & Receive Operation
The RTL8201N can be configured as 100Base-FX via hardware configuration. The hardware
100Base-FX setting takes priority over NWay settings. A scrambler is not required in 100Base-FX.
100Base-FX Transmit
Di-bits of TXD are processed as 100Base-TX except without a scrambler before the NRZI stage. Instead
of converting to MLT-3 signals, as in 100Base-TX, the serial data stream is driven out as NRZI PECL
signals, which enter the fiber transceiver in differential-pairs form.
100Base-FX Receive
The signal is received through PECL receiver inputs from the fiber transceiver and directly passed to the
clock recovery circuit for data/clock recovery. The scrambler/de-scrambler is bypassed in 100Base-FX.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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RTL8201N
Datasheet
8.7.3. 10Base-T Transmit & Receive Operation
10Base-T Transmit
Transmit data in 4-bit nibbles (TXD[3:0]) clocked at 2.5MHz (TXC) is first fed to a parallel-to-serial
converter, then the 10Mbps NRZ signal is sent to a Manchester encoder. The Manchester encoder
converts the 10Mbps NRZ data into a Manchester Encoded data stream for the TP transmitter and adds a
Start of Idle pulse (SOI) at the end of the packet as specified in IEEE 802.3. Finally, the encoded data
stream is shaped by a band-limited filter embedded in the RTL8201N and then transmitted.
10Base-T Receive
In 10Base-T receive mode, the Manchester decoder in the RTL8201N converts the Manchester encoded
data stream into NRZ data by decoding the data and stripping off the SOI pulse. Then the serial NRZ data
stream is converted to a parallel 4-bit nibble signal (RXD[0:3]).
8.8. Repeater Mode Operation
Setting bit 15 of register 17 to 1, or pulling the RPTR pin high, sets the RTL8201N into repeater mode. In
repeater mode, the RTL8201N will assert CRS high only when receiving a packet. In NIC mode, the
RTL8201N will assert CRS high both when transmitting and receiving packets. If using the RTL8201N in
a NIC or switch application, set to the default mode. NIC/Switch mode is the default setting and has the
RPTR pin pulled low, or bit 15 of register 17 is set to 0.
8.9. Reset, and Transmit Bias
The RTL8201N can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It
can also be reset by setting bit 15 of register 0 to 1, and then setting it back to 0. Reset will clear the
registers and re-initialize them. The media interface will disconnect and restart the auto-
negotiation/parallel detection process.
The RTSET pin must be pulled low by a 2KΩ resister with 1% accuracy to establish an accurate transmit
bias. This will affect the signal quality of the transmit waveform. Keep its circuitry away from other clock
traces and transmit/receive paths to avoid signal interference.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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Rev. 1.1
RTL8201N
Datasheet
8.10. 3.3V Power Supply and Voltage Conversion Circuit
The RTL8201N is fabricated in a 0.15µm process. The core circuit needs to be powered by 1.5V,
however, the digital IO and DAC circuits need a 3.3V power supply. Two regulators are embedded in the
RTL8201N to convert 3.3V to 1.5V and 1.8V. As with many commercial voltage conversion devices, the
1.5V/1.8V output pin (PWFBOUT) of this circuit requires the use of an output capacitor (22uF tantalum
capacitor) as part of the device frequency compensation.
The analog and digital ground planes should be as large and intact as possible. If the ground plane is large
enough, the analog and digital grounds can be separated, which is the ideal configuration. However, if the
total ground plane is not sufficiently large, partition of the ground plane is not a good idea. In this case,
all the ground pins can be connected together to a larger single and intact ground plane.
8.11. Far End Fault Indication
The MII Reg.1.4 (Remote Fault) is the Far End Fault Indication (FEFI) bit when 100FX mode is enabled,
and indicates when a FEFI has been detected. FEFI is an alternative in-band signaling method which is
composed of 84 consecutive ‘1’s followed by one ‘0’. When the RTL8201N detects this pattern three
times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On
the other hand, if an incoming signal fails to cause a ‘Link OK’, the RTL8201N will start sending this
pattern, which in turn causes the remote side to detect a Far End Fault. This means that the receive path
has a problem from the point of view of the RTL8201N. The FEFI mechanism is used only in
100Base-FX mode.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
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Rev. 1.1
RTL8201N
Datasheet
9. Characteristics
9.1. DC Characteristics
9.1.1. Absolute Maximum Ratings
Table 28. Absolute Maximum Ratings
Item
Minimum
3.0V
Typical
Maximum
3.6V
Supply Voltage
Storage Temperature
3.3V
-55°C
125°C
9.1.2. Operating Conditions
Table 29. Operating Conditions
Item
Condition
Minimum
Typical
Maximum
3.6V
Vcc 3.3V
TA
3.3V Supply voltage
3.0V
3.3V
Ambient Operating Temperature
0°C
70°C
9.1.3. Power Dissipation
Test Condition: VCC=3.3V
Table 30. Power Dissipation
Symbol
PLDPS
PAnaOff
PPWD
Condition
Total Current Consumption
Link down power saving mode
Analog off mode
22mA
21mA
20mA
19mA
116mA
151mA
134mA
46mA
27mA
Power down mode
Isolate mode
PIsolate
P100F
100Base full duplex
10Base-T full duplex
10Base-T transmit
10Base-T receive
10Base-T idle
P10F
P10TX
P10RX
P10IDLE
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With Auto MDIX
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Rev. 1.1
RTL8201N
Datasheet
9.1.4. Input Voltage: Vcc
Table 31. Input Voltage: Vcc
Symbol
TTL VIH
TTL VIL
TTL VOH
TTL VOL
TTL IOZ
IIN
Condition
Minimum
0.5*Vcc
-0.5V
Maximum
Input High Vol.
Input Low Vol.
Output High Vol.
Output Low Vol.
Tri-state Leakage
Input Current
Vcc +0.5V
0.3*Vcc
Vcc
IOH=-8mA
0.65*Vcc
IOL=8mA
0.3*Vcc
10µA
Vout=Vcc or GND
Vin=Vcc or GND
Vin=Vcc or GND
-110µA
-1µA
10µA
IPL
Input Current with internal
weak pull low resistor
-1µA
100µA
IPH
Input Current with internal
weak pull high resistor
Vin=Vcc or GND
-110µA
10µA
PECL VIH
PECL VIL
PECL VOH
PECL VOL
PECL Input High Vol.
PECL Input Low Vol.
PECL Output High Vol.
PECL Output Low Vol.
Vdd -1.16V
Vdd -1.81V
Vdd -1.02V
Vdd -0.88V
Vdd -1.47V
Vdd -1.62V
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
25
Rev. 1.1
RTL8201N
Datasheet
9.2. AC Characteristics
9.2.1. MII Transmission Cycle Timing
Table 32. MII Transmission Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
t1
TXCLK high pulse width
100Mbps
10Mbps
14
20
26
ns
140
14
200
260
26
ns
t2
t3
t4
TXCLK low pulse width
TXCLK period
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
20
200
40
ns
ns
ns
ns
ns
140
260
400
24
TXEN, TXD[0:3] setup to
TXCLK rising edge
10
5
10Mbps
ns
ns
t5
TXEN, TXD[0:3] hold after
TXCLK rising edge
100Mbps
10
25
10Mbps
100Mbps
10Mbps
100Mbps
5
ns
ns
ns
ns
t6
t7
TXEN sampled to CRS high
40
400
160
TXEN sampled to CRS low
10Mbps
2000
140
ns
ns
t8
t9
Transmit latency
100Mbps
60
70
10Mbps
100Mbps
10Mbps
2000
170
ns
ns
ns
Sampled TXEN inactive to end
of frame
100
Figure 5 and Figure 6 show an example of a packet transfer from MAC to PHY on the MII interface.
t
3
VIH(min)
VIL(max)
TXCLK
t
t
2
1
t
t
5
4
VIH(min)
VIL(max)
TXD[0:3]
TXEN
Figure 5. MII Transmission Cycle Timing-1
TXCLK
TXEN
TXD[0:3]
t
t
6
7
9
CRS
t
t
8
TPTX+-
Figure 6. MII Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
26
Rev. 1.1
RTL8201N
Datasheet
9.2.2. MII Reception Cycle Timing
Table 33. MII Reception Cycle Timing
Symbol
Description
Minimum
Typical
20
Maximum
Unit
ns
t1
RXCLK high pulse width
100Mbps
10Mbps
100Mbps
10Mbps
100Mbps
14
140
14
26
260
26
200
ns
t2
t3
t4
t5
RXCLK low pulse width
RXCLK period
20
ns
140
200
40
260
ns
ns
10Mbps
400
ns
ns
ns
ns
RXER, RXDV, RXD[0:3] setup to 100Mbps
RXCLK rising edge
10
6
10Mbps
RXER, RXDV, RXD[0:3] hold
after RXCLK rising edge
100Mbps
10
10Mbps
6
ns
ns
t6
t7
t8
t9
Receive frame to CRS high
100Mbps
130
10Mbps
100Mbps
10Mbps
2000
240
ns
ns
ns
ns
End of receive frame to CRS low
1000
150
Receive frame to sampled edge of 100Mbps
RXDV
10Mbps
3200
120
ns
ns
End of receive frame to sampled
edge of RXDV
100Mbps
10Mbps
1000
ns
Figure 7 and Figure 8 show an example of a packet transfer from PHY to MAC on the MII interface.
t3
V
RXCLK
IH(min)
IL(max)
V
t1
t2
t4
t5
RXD[0:3]
RXDV
V
V
IH(min)
IL(max)
RXER
Figure 7. MII Reception Cycle Timing-1
RXCLK
RXDV
t9
t8
RXD[0:3]
t6
t7
CRS
TPRX+-
Figure 8. MII Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
27
Rev. 1.1
RTL8201N
Datasheet
9.2.3. SNI Transmission Cycle Timing
Table 34. SNI Transmission Cycle Timing
Symbol Description
Minimum
Maximum
Unit
t1
t2
t3
t4
t5
t8
TXCLK high pulse width
36
36
80
20
10
ns
ns
ns
ns
ns
ns
TXCLK low pulse width
TXCLK period
120
50
TXEN, TXD0 setup to TXCLK rising edge
TXEN, TXD0 hold after TXCLK rising edge
Transmit latency
Figure 9 and Figure 10 show an example of a packet transfer from MAC to PHY on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
TXCLK
V
IL(max)
t1
t2
t5
t4
V
V
TXD0
TXEN
IH(min)
IL(max)
Figure 9. SNI Transmission Cycle Timing-1
TXCLK
TXEN
TXD0
t8
t9
TPTX+-
Figure 10. SNI Transmission Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
28
Rev. 1.1
RTL8201N
Datasheet
9.2.4. SNI Reception Cycle Timing
Table 35. SNI Reception Cycle Timing
Symbol
Description
Minimum
Typical
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
t7
t8
RXCLK high pulse width
RXCLK low pulse width
RXCLK period
36
36
80
40
40
ns
120
ns
RXD0 setup to RXCLK rising edge
RXD0 hold after RXCLK rising edge
Receive frame to CRS high
End of receive frame to CRS low
Decoder acquisition time
ns
ns
50
ns
160
ns
600
1800
ns
Figure 11 and Figure 12 show an example of a packet transfer from PHY to MAC on the SNI interface.
Note: SNI mode only runs at 10Mbps.
t3
V
IH(min)
RXCLK
V
IL(max)
t2
t1
t4
t5
V
V
RXD0
IH(min)
IL(max)
Figure 11. SNI Reception Cycle Timing-1
RXCLK
RXD0
t8
t6
t7
CRS
TPRX+-
Figure 12. SNI Reception Cycle Timing-2
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
29
Rev. 1.1
RTL8201N
Datasheet
9.2.5. MDC/MDIO Timing
Table 36. MDC/MDIO Timing
Symbol Description
Minimum
160
Maximum
Unit
ns
t1
t2
t3
t4
t5
t6
MDC high pulse width
MDC low pulse width
MDC period
160
ns
400
ns
MDIO setup to MDC rising edge
10
ns
MDIO hold time from MDC rising edge
MDIO valid from MDC rising edge
10
0
ns
300
ns
t3
V
IH(min)
MDC
V
IL(max)
t 5
t4
t1
t2
MDIO
sourced by
STA
V
IH(min)
V
IL(max)
t6
MDIO
sourced by
RTL8201CN
V
V
IH(min)
IL(max)
Figure 13. MDC/MDIO Timing
Transmission Without Collision
Figure 14 shows an example of a packet transfer from MAC to PHY.
Figure 14. MDC/MDIO MAC to PHY Transmission Without Collision
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
30
Rev. 1.1
RTL8201N
Datasheet
Reception Without Error
Figure 15 shows an example of a packet transfer from PHY to MAC.
Figure 15. MDC/MDIO PHY to MAC Reception Without Error
9.3. Crystal Characteristics
Table 37. Crystal Characteristics
Parameter
Range
Nominal Frequency
Oscillation Mode
25.000MHz
Base wave
±50 ppm
Frequency Tolerance at 25°C
Operating Temperature Range
Equivalent Series Resistance
Drive Level
-10°C ~ +70°C
30 ohm Max.
0.1 mV
Load Capacitance
20 pF
Shunt Capacitance
7 pF Max.
Insulation Resistance
Test Impedance Meter
Aging Rate Per Year
Mega ohm Min./DC 100V
Saunders 250A
±0.0003%
9.4. Transformer Characteristics
Table 38. Transformer Characteristics
Parameter
Transmit End
1:1 CT
Receive End
1:1
Turn Ratio
Inductance (min.)
350 uH @ 8mA
350 uH @ 8mA
Note: The auto MDIX detection function requires a transformer with symmetrical TX/RX and Choke after transformer
placement, i.e. Pulse Engineer H1251 (refer to the suggested RTL8201N Schematic, which is available for download at
www.realtek.com.tw).
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
31
Rev. 1.1
RTL8201N
Datasheet
10. Mechanical Dimensions
Note: For RTL8201N specific information, refer to line 4.
Note: Exposed Pad is Analog and Digital Ground.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
32
Rev. 1.1
RTL8201N
Datasheet
11. Ordering Information
Table 39. Ordering Information
Package
64-pin QFN with Green Package
Part Number
Status
RTL8201N-GR
Note: See page 4 for package identification.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II, Hsinchu Science Park,
Hsinchu 300, Taiwan.
Tel: 886-3-5780211 Fax: 886-3-5776047
www.realtek.com.tw
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
33
Rev. 1.1
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