EK42520-02 [PSEMI]
UltraCMOS SPDT RF Switch 9 kHz - 13 GHz; 的UltraCMOS RF SPDT开关在9 kHz - 13 GHz的
| 型号： | EK42520-02 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | UltraCMOS SPDT RF Switch 9 kHz - 13 GHz |
| 文件： | 总16页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE42520
UltraCMOS® SPDT RF Switch
9 kHz - 13 GHz
Product Description
Features
The PE42520 SPDT absorptive RF switch is designed for
use in Test/ATE and other high performance wireless
applications. This broadband general purpose switch
maintains excellent RF performance and linearity from 9
kHz through 13 GHz. This switch is a pin-compatible
upgraded version of PE42552 with higher power handling
of 36 dBm continuous wave (CW) and 38 dBm
instantaneous power in 50Ω @ 8 GHz. The PE42520
exhibits high isolation, fast settling time, and is offered in a
3x3 mm QFN package.
HaRP™ technology enhanced
Fast settling time
No gate and phase lag
No drift in insertion loss and phase
High power handling @ 8 GHz in 50Ω
36 dBm CW
38 dBm instantaneous power
26 dBm terminated port
The PE42520 is manufactured on Peregrine’s
UltraCMOS® process, a patented variation of silicon-on-
insulator (SOI) technology on a sapphire substrate,
offering the performance of GaAs with the economy and
integration of conventional CMOS.
High linearity
66 dBm IIP3
Low insertion loss
0.8 dB @ 3 GHz
0.9 dB @ 10 GHz
2.0 dB @ 13 GHz
Figure 1. Functional Diagram
High isolation
45 dB @ 3 GHz
31 dB @ 10 GHz
18 dB @ 13 GHz
ESD performance
4kV HBM on RF pins to GND
2.5kV HBM on all pins
1kV CDM on all pins
Figure 2. Package Type
16-lead 3x3 mm QFN
DOC-50572
Document No. DOC-12714-3 |
www.psemi.com
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 16
PE42520
Product Specification
Table 1. Electrical Specifications @ 25°C, VDD = 3.3V, VssEXT = 0V or VDD = 3.4V, VssEXT = -3.4V,
(ZS = ZL = 50Ω) unless otherwise noted
Parameter
Path
Condition
Min
Typ
Max
Unit
As
shown
Operation frequency
9 kHz
13 GHz
9 kHz –10 MHz
0.60
0.80
0.85
0.90
1.20
2.00
0.80
1.00
1.05
1.10
1.65
2.70
dB
dB
dB
dB
dB
dB
10 MHz – 3 GHz
3 GHz – 7.5 GHz
7.5 GHz – 10 GHz
10 GHz – 12 GHz
12 GHz –13 GHz
Insertion loss
RFC–RFX
RFX–RFX
RFC–RFX
RFC-RFX
RFC-RFX
RFX
9 kHz –10 MHz
70
46
35
24
16
13
90
54
38
27
19
17
dB
dB
dB
dB
dB
dB
10 MHz – 3 GHz
3 GHz – 7.5 GHz
7.5 GHz – 10 GHz
10 GHz – 12 GHz
12 GHz –13 GHz
Isolation
9 kHz –10 MHz
80
42
41
26
16
13
90
45
44
31
20
18
dB
dB
dB
dB
dB
dB
10 MHz – 3 GHz
3 GHz – 7.5 GHz
7.5 GHz – 10 GHz
10 GHz – 12 GHz
12 GHz –13 GHz
Isolation
9 kHz –10 MHz
23
17
15
18
20
10
dB
dB
dB
dB
dB
dB
10 MHz – 3 GHz
3 GHz – 7.5 GHz
7.5 GHz – 10 GHz
10 GHz – 12 GHz
12 GHz –13 GHz
Return loss (active port)
Return loss (common port)
Return loss (terminated port)
9 kHz –10 MHz
23
17
15
18
18
10
dB
dB
dB
dB
dB
dB
10 MHz – 3 GHz
3 GHz – 7.5 GHz
7.5 GHz – 10 GHz
10 GHz – 12 GHz
12 GHz –13 GHz
9 kHz –10 MHz
32
24
21
13
8
dB
dB
dB
dB
dB
dB
10 MHz – 3 GHz
3 GHz – 7.5 GHz
7.5 GHz – 10 GHz
10 GHz – 12 GHz
12 GHz –13 GHz
5
Input 0.1 dB compression point1
Input IP2
RFC–RFX
RFC–RFX
RFC–RFX
10 MHz – 13 GHz
Fig. 5
120
66
dBm
dBm
dBm
834 MHz, 1950 MHz
Input IP3
834 MHz, 1950 MHz, and 2700 MHz
Settling time
50% CTRL to 0.05 dB final value
15
20
μs
μs
Switching time
50% CTRL to 90% or 10% of final value
5.5
9.5
Note 1: The input 0.1 dB compression point is a linearity figure of merit. Refer to Table 3 for the RF input power PIN (50Ω)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 2 of 16
PE42520
Product Specification
Figure 3. Pin Configuration (Top View)
Table 3. Operating Ranges
Symbol
Min
Typ
Max
Unit
Parameter
Supply voltage (normal
mode, VssEXT = 0V)1
VDD
2.3
5.5
V
Supply voltage (bypass
mode, VssEXT = -3.4V,
VDD
2.7
3.4
5.5
V
V
DD ≥3.4V for full spec.
compliance)2
Negative supply voltage
(bypass mode)2
VssEXT
-3.6
-3.2
200
80
V
Supply current (normal
mode, VssEXT = 0V)1
IDD
120
50
µA
µA
Supply current (bypass
mode, VssEXT = -3.4V)2
IDD
Negative supply current
(bypass mode, VssEXT
=
ISS
-40
-16
µA
V
-3.4V)2
Digital input high
(CTRL)
Table 2. Pin Descripion
VIH
1.17
-0.3
3.6
Pin #
Pin Name
Description
Digital input low (CTRL)
Digital input current
VIL
0.6
10
V
2
RF11
RF port 1
Ground
ICTRL
µA
1, 3, 4, 5,
6, 8, 9, 10,
12
GND
RF input power, CW
(RFC-RFX)3
9 kHz ≤10 MHz
10 MHz ≤8 GHz
8 GHz ≤13 GHz
PIN-CW
Fig. 4
36
Fig. 5
dBm
dBm
dBm
7
RFC1
RF21
RF common
RF port 2
11
13
14
2
VssEXT
External Vss negative voltage control
Digital control logic input
RF input power, pulsed
(RFC-RFX)4
CTRL
LS
PIN-PULSED
9 kHz ≤10 MHz
10 MHz ≤13 GHz
Fig. 4
Fig. 5
dBm
dBm
Logic Select - used to determine the
definition for the CTRL pin (see Table 5)
15
RF input power, hot
switch, CW3
16
VDD
Supply voltage
PIN-HOT
9 kHz ≤300 kHz
300 kHz ≤13 GHz
Fig. 4
20
dBm
dBm
Pad
GND
Exposed pad: ground for proper operation
Notes: 1. RF pins 2, 7, and 11 must be at 0V DC. The RF pins do not require
DC blocking capacitors for proper operation if the 0V DC requirement
is met
RF input power into
terminated ports, CW
(RFX)3
PIN,TERM
2. Use VssEXT (pin 13) to bypass and disable internal negative voltage
generator. Connect VssEXT (pin 13) to GND (VssEXT = 0V) to enable
internal negative voltage generator
9 kHz ≤600 kHz
600 kHz ≤13 GHz
Fig. 4
26
dBm
dBm
Operating temperature
range
TOP
-40
+25
+85
°C
Notes: 1. Normal mode: connect VssEXT (pin 13) to GND (VssEXT = 0V) to
enable internal negative voltage generator
2. Bypass mode: use VssEXT (pin 13) to bypass and disable internal
negative voltage generator
3. 100% duty cycle, all bands, 50Ω
4. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
Document No. DOC-12714-3 |
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 16
PE42520
Product Specification
Table 4. Absolute Maximum Ratings
Switching Frequency
The PE42520 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 13 = GND). The rate at which the
PE42520 can be switched is only limited to the
switching time (Table 1) if an external negative
supply is provided (pin 13 = VssEXT).
Symbol
Min
Max
Unit
Parameter/Condition
Supply voltage
VDD
VCTRL
VLS
-0.3
-0.3
-0.3
5.5
3.6
3.6
V
V
V
Digital input voltage (CTRL)
LS input voltage
RF input power, CW
(RFC-RFX)1
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
9 kHz ≤10 MHz
10 MHz ≤8 GHz
8 GHz ≤13 GHz
PIN-CW
Fig. 4 dBm
36 dBm
Fig. 5 dBm
RF input power, pulsed
(RFC-RFX)2
PIN-PULSED
9 kHz ≤10 MHz
10 MHz ≤13 GHz
Fig. 4 dBm
Fig. 5 dBm
RF input power into terminated
ports, CW (RFX)1
Optional External Vss Control (VssEXT
)
PIN,TERM
9 kHz ≤10 MHz
Fig. 4 dBm
For proper operation, the VssEXT control pin must
be grounded or tied to the Vss voltage specified in
Table 3. When the VssEXT control pin is grounded,
FETs in the switch are biased with an internal
negative voltage generator. For applications that
require the lowest possible spur performance,
VssEXT can be applied externally to bypass the
internal negative voltage generator.
10 MHz ≤13 GHz
26
dBm
Storage temperature range
TST
-65
150
°C
ESD voltage HBM3
RF pins to GND
All pins
VESD,HBM
4000
2500
V
V
ESD voltage MM4, all pins
ESD voltage CDM5, all pins
VESD,MM
200
V
V
VESD,CDM
1000
Spurious Performance
Notes: 1. 100% duty cycle, all bands, 50Ω
2. Pulsed, 5% duty cycle of 4620 µs period, 50Ω
3. Human Body Model (MIL-STD 883 Method 3015)
4. Machine Model (JEDEC JESD22-A115)
The typical spurious performance of the PE42520
is -152 dBm when VssEXT = 0V (pin 13 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting VssEXT = -3.4V.
5. Charged Device Model (JEDEC JESD22-C101)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Table 5. Control Logic Truth Table
LS
0
CTRL
RFC-RF1
RFC-RF2
0
1
0
1
off
on
on
off
on
off
off
on
Electrostatic Discharge (ESD) Precautions
0
When handling this UltraCMOS® device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
1
1
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42520 in the 16-lead 3x3 mm QFN package is
MSL3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS®
devices are immune to latch-up.
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 4 of 16
PE42520
Product Specification
Figure 4. Power De-rating Curve for 9 kHz – 10 MHz (50Ω)
40
35
30
Max. RF Input Power, CW and Pulsed, (‐40°C to +85°C Ambient)
25
20
15
10
5
0
‐5
1
10
100
1000
10000
Frequency (kHz)
Document No. DOC-12714-3 |
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 16
PE42520
Product Specification
Figure 5a. Power De-rating Curve for 10 MHz – 13 GHz @ 25°C Ambient (50Ω)
40
P0.1dB Compression @ 25°C Ambient
Max. RF Input Power, Pulsed @ 25°C Ambient
Max. RF Input Power, CW @ 25°C Ambient
39.5
39
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
0.01
1
2
3
4
5
6
7
8
9
10
11
12
13
Frequency (GHz)
Figure 5b. Power De-rating Curve for 10 MHz – 13 GHz @ 85°C Ambient (50Ω)
40
P0.1dB Compression @ 85°C Ambient
39.5
39
Max. RF Input Power, Pulsed @ 85°C Ambient
Max. RF Input Power, CW @ 85°C Ambient
38.5
38
37.5
37
36.5
36
35.5
35
34.5
34
33.5
33
0.01
1
2
3
4
5
6
7
8
9
10
11
12
13
Frequency (GHz)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 6 of 16
PE42520
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 6. Insertion Loss vs. Temp (RFC–RF1)
Figure 7. Insertion Loss vs. VDD (RFC–RF1)
Figure 8. Insertion Loss vs. Temp (RFC–RF2)
Figure 9. Insertion Loss vs. VDD (RFC–RF2)
Document No. DOC-12714-3 |
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 16
PE42520
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 10. RFC Port Return Loss vs. Temp
(RF1 Active)
Figure 11. RFC Port Return Loss vs. VDD
(RF1 Active)
Figure 12. RFC Port Return Loss vs. Temp
(RF2 Active)
Figure 13. RFC Port Return Loss vs. VDD
(RF2 Active)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 8 of 16
PE42520
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 14. Active Port Return Loss vs. Temp
(RF1 Active)
Figure 15. Active Port Return Loss vs. VDD
(RF1 Active)
Figure 16. Active Port Return Loss vs. Temp
(RF2 Active)
Figure 17. Active Port Return Loss vs. VDD
(RF2 Active)
Document No. DOC-12714-3 |
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 16
PE42520
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 18. Terminated Port Return Loss vs. Temp
(RF1 Active)
Figure 19. Terminated Port Return Loss vs. VDD
(RF1 Active)
Figure 20. Terminated Port Return Loss vs. Temp
(RF2 Active)
Figure 21. Terminated Port Return Loss vs. VDD
(RF2 Active)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 10 of 16
PE42520
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 22. Isolation vs. Temp
(RF1–RF2, RF1 Active)
Figure 23. Isolation vs. VDD
(RF1–RF2, RF1 Active)
Figure 24. Isolation vs. Temp
(RF2–RF1, RF2 Active)
Figure 25. Isolation vs. VDD
(RF2–RF1, RF2 Active)
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 16
PE42520
Product Specification
Typical Performance Data @ 25°C and VDD = 3.4V unless otherwise specified
Figure 26. Isolation vs. Temp
(RFC–RF2, RF1 Active)
Figure 27. Isolation vs. VDD
(RFC–RF2, RF1 Active)
Figure 28. Isolation vs. Temp
(RFC–RF1, RF2 Active)
Figure 29. Isolation vs. VDD
(RFC–RF1, RF2 Active)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 12 of 16
PE42520
Product Specification
Evaluation Kit
Figure 30. Evaluation Kit Layout
The SPDT switch evaluation board was designed
to ease customer evaluation of Peregrine’s
PE42520. The RF common port is connected
through a 50Ω transmission line via the SMA
connector, J1. RF1 and RF2 ports are connected
through 50Ω transmission lines via SMA
connectors J2 and J3, respectively. A 50Ω
through transmission line is available via SMA
connectors J5 and J6, which can be used to
de-embed the loss of the PCB. J4 provides DC
and digital inputs to the device.
For the true performance of the PE42520 to be
realized, the PCB should be designed in such a
way that RF transmission lines and sensitive DC
I/O traces are heavily isolated from one another.
PRT-30186
Document No. DOC-12714-3 |
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 13 of 16
PE42520
Product Specification
Figure 31. Evaluation Board Schematic
DOC-12726
Notes: 1. Use PRT-30186-02 PCB
2. CAUTION: Contains parts and assemblies susceptible
to damage by electrostatic discharge (ESD)
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 14 of 16
PE42520
Product Specification
Figure 32. Package Drawing
16-lead 3x3 mm QFN
0.10
(2X)
C
A
3.00
0.28
(X16)
1.70±0.05
0.50
B
9
12
0.575
(X16)
0.50
13
(X12)
8
1.70±0.05
1.75
3.40
3.00
16
5
0.23±0.05
(X16)
0.10
(2X)
C
4
1
0.375±0.05
(X16)
1.50
1.75
3.40
Pin #1 Corner
TOP VIEW
BOTTOM VIEW
RECOMMENDED LAND PATTERN
DOC-01881
0.10
0.05
C
C
0.10
0.05
C
C
A B
0.80 MAX
ALL FEATURES
SEATING PLANE
0.203
0.05
C
SIDE VIEW
Figure 33. Top Marking Specifications
42520
YYWW
ZZZZZ
= Pin 1 designator
YYWW = Date code
ZZZZZ = Last five digits of lot number
17-0009
Document No. DOC-12714-3 |
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©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 15 of 16
PE42520
Product Specification
Figure 34. Tape and Reel Specifications
Tape Feed Direction
Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber in compliance with EIA 481
Pin 1
Ao = 3.30
Bo = 3.30
Ko = 1.10
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
Top of
Device
Device Orientation in Tape
Table 6. Ordering Information
Order Code
PE42520MLBA-Z
EK42520-02
Description
Package
Shipping Method
3000 units / T&R
1 / Box
PE42520 SPDT RF switch
PE42520 Evaluation kit
Green 16-lead 3x3 mm QFN
Evaluation kit
Sales Contact and Information
For sales and contact information please visit www.psemi.com.
Advance Information: The product is in a formative or design stage. The datasheet contains design target No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.
specifications for product development. Specifications and features may change in any manner without notice. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant,
or in other applications intended to support or sustain life, or in any application in which the failure of the
Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no
liability for damages, including consequential or incidental damages, arising out of the use of its products in
such applications.
The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE
are trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of
the following U.S. Patents: http://patents.psemi.com.
Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later
date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best
possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to
change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer
Notification Form).
The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use
of this information. Use shall be entirely at the user’s own risk.
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-12714-3 |
UltraCMOS® RFIC Solutions
Page 16 of 16
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PSEMI
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