EK42552-02 [PSEMI]
SPDT UltraCMOS RF Switch DC - 7500 MHz; 单刀双掷的UltraCMOS RF开关直流 - 7500兆赫
| 型号： | EK42552-02 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | SPDT UltraCMOS RF Switch DC - 7500 MHz |
| 文件： | 总9页 (文件大小：398K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE42552
SPDT UltraCMOS™ RF Switch
DC - 7500 MHz
Product Description
Features
The PE42552 RF Switch is designed for use in Test/ATE,
cellular and other wireless applications. This broadband general
purpose switch maintains excellent RF performance and
linearity from DC through 7500 MHz. The PE42552 integrates
on-board CMOS control logic driven by a single-pin, low voltage
CMOS control input. It also has a logic select pin which enables
changing the logic definition of the control pin. Additional
features include a novel user defined logic table, enabled by the
on-board CMOS circuitry. The PE42552 also exhibits
•
HaRP™-Technology-Enhanced
•
•
•
Eliminates Gate and Phase Lag
No insertion loss or phase drift
Fast settling time
•
•
High linearity: 65 dBm IIP3
Low insertion loss: 0.65 dB at 3.0 GHz,
0.85 dB at 6.0 GHz, 1.0 at 7.5 GHz
High isolation of 47 dB at 3.0 GHz,
44 dB at 7.5 GHz
•
outstanding isolation of 44 dB at 7500 MHz, fast settling time,
and is offered in a tiny 3x3 mm QFN package.
•
•
•
•
•
1 dB compression point: +34.5 dBm typ.
The PE42552 is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance of
GaAs with the economy and integration of conventional CMOS.
Logic Select pin to invert logic control
High ESD: 1000 V HBM
Absorptive switch design
Standard 3x3 mm QFN package
Figure 1. Functional Diagram
RFC
Figure 2. Package Type
16-lead 3x3 mm QFN
RF1
RF2
ESD
ESD
50Ω
50Ω
CMOS
Control
Driver
LS CTRL
Table 1. Target Electrical Specifications Temp = 25°C, VDD = 3.3V, VSS = 0V / -3.3V
Parameter
Conditions
Min
Typical
Max
Units
Operation Frequency MHz
9 kHz
7.5 GHz
9 KHz
0.6
0.65
0.85
1.0
0.7
0.8
1.0
dB
dB
dB
dB
3000 MHz
6000 MHz
7500 MHz
Insertion Loss
1.22
3000 MHz
6000 MHz
7500 MHz
45
32
25
47
34
28
dB
dB
dB
Isolation – RF1 to RF2
Isolation – RFC to RFX
Return Loss
3000 MHz
6000 MHz
7500 MHz
44
49
37
47
55
44
dB
dB
dB
3000 MHz
6000 MHz
7500 MHz
20
25
15
dB
dB
dB
50% CTRL to 0.05 dB final value (-40 to +85 °C) Rising Edge
50% CTRL to 0.05 dB final value (-40 to +85 °C) Falling Edge
9
15
11
45
µs
µs
Settling Time
Switching Time
50% CTRL to 90% or 10% of final value (-40 to +85 °C)
5
7
µs
dBm
dBm
800 MHz
7500 MHz
32
34.5
34
Input 1 dB Compression
Input IP3
Input IP2
7500 MHz
7500 MHz
65
100
dBm
dBm
Document No. 70-0246-03 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 9
PE42552
Product Specification
Figure 3. Pin Configuration (Top View)
Table 4. Absolute Maximum Ratings
Symbol
Parameter/Conditions
Power supply voltage
Voltage on any input except for
CTRL and LS inputs
Voltage on CTRL input
Voltage on LS input
Min
-0.3
Max Units
VDD
4.0
V
VDD
0.3
4.0
4.0
150
+
VI
-0.3
-65
V
1
2
3
4
12
11
10
9
GND
RF1
GND
RF2
VCTRL
VLS
TST
V
V
°C
Storage temperature range
Input Power:
GND
GND
GND
GND
PIN
9 kHz ≤ 1 MHz
1 MHz ≤ 7.5 GHz
ESD voltage (HBM)1
ESD voltage (Machine Model)
fig. 4,5 dBm
30
dBm
1000
100
V
V
VESD
Note: 1. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Table 2. Pin Descriptions
Pin No.
Pin Name
Description
2
RF1
RF Port 1
Ground
1, 3, 4, 5, 6,
8, 9, 10, 12
GND
Electrostatic Discharge (ESD) Precautions
7
RFC
RF2
RF Common
RF Port 2
11
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
Negative supply voltage or GND
connection (Note 1)
13
14
VSS
CTRL
CMOS level:
Logic Select - Used to determine
the definition for the CTRL pin (see
Table 5)
15
LS
16
VDD
Nominal 3.3 V supply connection
Latch-Up Avoidance
Note: 1. Use VSS (pin 13, VSS = -VDD) to bypass and disable
internal negative voltage generator. Connect VSS (pin 13) to GND
(VSS = 0V) to enable internal negative voltage generator.
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Table 3. Operating Ranges
LS
0
0
1
1
CTRL
RFC-RF1
RFC-RF2
Parameter
Min Typ Max Units
0
1
0
1
off
on
on
off
on
off
off
on
VDD Positive Power Supply Voltage
3.0
3.3
3.6
V
VSS Negative Power Supply Voltage
(external power supply used)
-3.6
-3.3
-3.0
V
VSS Negative Power Supply Voltage
(internal power supply used)
-0.1
0.0
15
0.0
120
-40
V
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
I
DD Power Supply Current
(VSS = 0V, Temp = +85 °C)
µA
µA
ISS Negative Supply
-10
(VSS = -VDD, Temp = 25 °C)
Spurious Performance
Control Voltage High
Control Voltage Low
0.7xVDD
-40
V
V
The typical spurious performance of the PE42552 is
-116 dBm when VSS=0V (pin 13 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
0.3xVDD
85
TOP Operating temperature range
25
°C
RF Power In1(PIN):
9 kHz ≤ 1 MHz
fig. 4,5 dBm
30 dBm
1 MHz ≤ 7.5 GHz
Switching Frequency
Note: 1. Please consult low frequency graphs on page 3 for
recommended operating power level.
The PE42552 has a maximum 25 kHz switching rate
when the internal negative voltage generator is used
(pin 13=GND). The rate at which the PE42552 can be
switched is only limited to the switching time (Table 1) if
an external negative supply is provided at
(pin13=VSS).
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the PE42552 in
the 16-lead 3x3mm QFN package is MSL1.
©2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
Page 2 of 9
PE42552
Product Specification
Low Frequency Power Handling: ZL = 50Ω
Figure 4 provides guidelines of how to adjust the Vdd
and input Power to the 42552 device. The upper limit
curve represents the maximum Input Power vs Vdd
recommended for this part.
Figure 5 shows how the power limit in Figure 4 will
increase with frequency. As the frequency increases,
the contours and Maximum Power Limit Curve will
increase with the increase in power handling shown on
the curve.
Figure 4. Maximum Operating Power Limit
vs. Vdd and Input Power @ 9 KHz
Figure 5. Operating Power Offset vs.
Frequency (Normalized to 9kHz)
Upper Power Limit
30
25
20
15
10
5
8
6
4
2
0
-2
-4
-6
-8
-10
-12
0
1
10
100
1000
Freq (kHz)
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Power Handling Examples
Vdd (V)
Example 1: Maximum power handling at 100kHz, Z=50
ohms, VSWR 1:1, and Vdd=3V
To allow for sustained operation under any load VSWR condition,
max power should be kept 6dB lower than max power in 50 Ohm.
•
The power handling offset for 100kHz from Fig. 5 is
10dB
•
The max power handling at Vdd = 3V is 5.5dB from
Fig. 4
•
•
Derate power under mismatch conditions
Total maximum power handling for this example is
10dB + 5.5dB = 15.5dBm
Document No. 70-0246-03 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 9
PE42552
Product Specification
Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated
Figure 6. Nominal Insertion Loss: RF1, RF2
Figure 7. Insertion Loss: RFX @ 3.3 V
0
-0.2
-0.4
-0.6
-0.8
-1
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.2
-1.4
-1.6
-1.8
-2
RF1 Path
RF2 Path
+25deg C
+85deg C
-40deg C
-1.4
-1.6
-1.8
-2
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Frequency [GHz]
Frequency [GHz]
Figure 8. Insertion Loss: RFX @ 25 °C
Figure 9. Isolation: Active Port to
Isolated Port @ 3.3 V
0
0
-0.2
-0.4
-0.6
-0.8
-10
+25deg C
+85deg C
-40deg C
-20
-30
-40
-50
-60
-70
-80
-90
-100
3.0 V
3.3 V
3.6 V
-1
-1.2
-1.4
-1.6
-1.8
-2
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Frequency [GHz]
Frequency [GHz]
Figure 10. Isolation: Active Port to
Isolated Port @ 25 °C
Figure 11. Isolation: RFC to Isolated Port @ 3.3 V
0
0
-10
-10
3.0 V
3.3 V
3.6 V
+25deg C
+85deg C
-40deg C
-20
-30
-40
-50
-60
-70
-80
-90
-100
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Frequency [GHz]
Frequency [GHz]
©2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
Page 4 of 9
PE42552
Product Specification
Performance Plots: Temperature = 25 °C, VDD = 3.3 V unless otherwise indicated
Figure 12. Isolation: RFC to Isolated Port @ 25 °C
Figure 13. IIP3: Third Order Distortion from
10kHz - 7.5GHz
0
70
60
50
40
30
20
10
0
-10
3.0 V
3.3 V
3.6 V
-20
-30
-40
-50
-60
-70
-80
-90
-100
3.0 V
3.3 V
3.6 V
0
1
2
3
4
5
6
7
8
9
Frequency [GHz]
Frequency [Hz]
Figure 14. Return Loss at active port @ 25 °C
Figure 15. Return Loss at active port @ 3.3 V
0
0
-5
-5
3.0 V
+25deg C
3.3 V
3.6 V
+85deg C
-40deg C
-10
-15
-20
-25
-30
-35
-10
-15
-20
-25
-30
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
Frequency [GHz]
Frequency [GHz]
Document No. 70-0246-03 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 9
PE42552
Product Specification
Figure 16. Evaluation Board Layouts
Peregrine Specification 101/0334
Evaluation Kit
The SPDT switch EK Board was designed to ease
customer evaluation of Peregrine’s PE42552. The
RF common port is connected through a 50 Ω
transmission line via the top SMA connector, J1.
RF1, RF2, RF3 and RF4 are connected through
50 Ω transmission lines via SMA connectors J3,
J5, J2 and J4, respectively. A through 50 Ω
transmission is available via SMA connectors J6
and J7. This transmission line can be used to
estimate the loss of the PCB over the
environmental conditions being evaluated.
The evaluation kit board is constructed of four
metal layers. The dual clad top RF layer is
Rogers RO4003 material with an 8 mil RF core
and er = 3.55. The other two dielectric layers are
FR4 for DC control and overall board strength with
an cumulative board thickness of 60 mils. The RF
transmission lines were designed using a
Grounded co-planar waveguide with a linewidth of
15 mils and gap of 10 mils.
Figure 17. Evaluation Board Schematic
Peregrine Specification 102/0404
J1
142-0761-881/891
2
9
10
11
12
4
3
2
1
GND
GND
RF2
GND
GND
RF1
J2
J3
142-0761-881/891
U1
142-0761-881/891
QFN50P3X3-16P
RF2
1
RF1
1
GND
GND
J4
R1 DNI
R2 DNI
HEADER 14
CTRL
2
4
6
1
3
5
7
9
11
13
2
4
6
8
10
12
14
1
3
5
7
9
LS
L1
VDD
VSS
8
10
12
14
0 OHM
L1 WAS INDUCTOR
R4 0 OHM
11
13
R3
DNI
C4
C3
22pF
C2
C1
68pF
22pF
22pF
J5
J6
142-0761-881/891
142-0761-881/891
Through Line
1
1
©2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
Page 6 of 9
PE42552
Product Specification
Figure 18. Package Drawing (mm)
16-lead 3x3 mm QFN
QFN 3x3 mm
MAX
NOM
MIN
0.800
0.750
0.700
A
Document No. 70-0246-03 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 9
PE42552
Product Specification
Figure 19. Tape and Reel Specifications
16-lead 3x3 mm QFN
Tape Feed Direction
Pin 1
Top of
Device
Device Orientation in Tape
Table 6. Ordering Information
Order Code Part Marking
Description
Package
Shipping Method
Bulk or tape cut from reel
3000 units / T&R
PE42552MLIB
PE42552MLIB-Z
EK42552-02
42552
PE42552G-16QFN 3x3mm-75A
PE42552G-16QFN 3x3mm-3000C
PE42552-16QFN 3x3mm-EK
Green 16-lead 3x3mm QFN
Green 16-lead 3x3mm QFN
Evaluation Kit
42552
PE42552-EK
1 / Box
©2008 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0246-03 │ UltraCMOS™ RFIC Solutions
Page 8 of 9
PE42552
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
Fax: +82-31-728-3940
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
Hi-Rel and Defense Products
Americas:
Tel: 858-731-9453
Europe, Asia Pacific:
180 Rue Jean de Guiramand
13852 Aix-En-Provence Cedex 3, France
Tel: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Document No. 70-0246-03 │ www.psemi.com
©2008 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 9
相关型号：
EK42750-01
75 Terminated 5 - 2200 MHz SPDT CATV UltraCMOS? Switch Featuring Unpowered Operation
PSEMI
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