EK45361-01 [ETC]
PE45361 EVALUATION KIT;
| 型号： | EK45361-01 |
| 厂家： | 
ETC |
| 描述： | PE45361 EVALUATION KIT |
| 文件： | 总15页 (文件大小：2274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PE45361
Document Category: Product Specification
UltraCMOS® Power Limiter, 10 MHz–8 GHz
Features
• Monolithic drop-in solution with no external bias
components
Figure 1 • PE45361 Functional Diagram
• Adjustable low power limiting threshold from
+7 dBm to +13 dBm
POUT
• High maximum power handling of 50 dBm,
100W pulsed
P1dB
RF1
RF2
• Positive threshold control from +0V to +0.3V
• Fast response time of less than 1 ns
• Packaging – 12-lead 3 × 3 × 0.5 mm QFN
PIN
Voltage Control and ESD
Applications
• Wireless infrastructure transceivers and antennas
• Test and measurement (T&M)
VCTRL
Product Description
The PE45361 is a HaRP™ technology-enhanced power limiter designed for use in high performance power
limiting applications in test and measurement equipment and wireless infrastructure transceivers and antennas.
Unlike traditional PIN diode solutions, the PE45361 achieves an adjustable input 1dB compression point or
limiting threshold via a low current control voltage (VCTRL), eliminating the need for external bias components
such as DC blocking capacitors, RF choke inductors and bias resistors.
It delivers low insertion loss and high linearity under non-limiting power levels and extremely fast response time
in a limiting event, ensuring protection of sensitive circuitry. It also offers excellent ESD rating and ESD
protection.
The PE45361 is manufactured on pSemi’s UltraCMOS® process, a patented advanced form of silicon-on-
insulator (SOI) technology, offering the performance of GaAs with the economy and integration of conventional
CMOS.
©2016-2020, pSemi Corporation. All rights reserved. • Headquarters: 9369 Carroll Park Drive, San Diego, CA, 92121
Product Specification
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Absolute Maximum Ratings
Exceeding absolute maximum ratings listed in Table 1 may cause permanent damage. Operation should be
restricted to the limits in Table 2. Operation between operating range maximum and absolute maximum for
extended periods may reduce reliability.
ESD Precautions
When handling this UltraCMOS device, observe the same precautions as with any other ESD-sensitive devices.
Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to
avoid exceeding the rating specified in Table 1.
Latch-up Immunity
Unlike conventional CMOS devices, UltraCMOS devices are immune to latch-up.
Table 1 • Absolute Maximum Ratings for PE45361
Parameter/Condition
Min
Max
Unit
Control voltage, VCTRL
Power limiting mode
0
3.6
50
V
dBm
°C
V
RF input power, Pulsed(1)
Storage temperature range
–65
+150
7000
2000
ESD voltage HBM, all pins(2)
ESD voltage CDM, all pins(3)
V
Notes:
1) Pulsed, 1.0% duty cycle of 10 µs pulse width in 1 ms period, 50Ω at +25 °C.
2) Human body model (MIL-STD 883 Method 3015).
3) Charged device model (JEDEC JESD22-C101).
Page 2 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Recommended Operating Conditions
Table 2 lists the recommended operating conditions for the PE45361. Devices should not be operated outside
the operating conditions listed below.
Table 2 • Recommended Operating Conditions for PE45361
Parameter
Min
Typ
Max
Unit
Control voltage, VCTRL
0
0
+0.3
+3.0
V
V
Power limiting mode
Power reflecting mode
RF input power, CW(*)
Fig. 2
+105
+150
dBm
°C
Operating temperature range
Operating max junction temperature
Note: * See Fig. 2.
–55
+25
°C
DOC-75388-6 – (10/2020)
Page 3 of 15
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PE45361
UltraCMOS® Power Limiter
Electrical Specifications
Table 3 provides the PE45361 key electrical specifications at +25 °C (ZS = ZL = 50Ω), unless otherwise
specified.
Table 3 • PE45361 Electrical Specifications
Parameter
Condition
Min
Typ
Max
Unit
As
shown
Operation frequency
10 MHz
8 GHz
Power Limiting Mode
10 MHz–3000 MHz
3001–6000 MHz
6001–8000 MHz
0.40
0.95
1.32
0.50
1.20
1.70
dB
dB
dB
Insertion loss
Return loss
10 MHz–3000 MHz
3001–6000 MHz
6001–8000 MHz
22
12
dB
dB
dB
9.5
VCTRL = 0V @ 915 MHz
13
10
7
dBm
dBm
dBm
VCTRL = +0.15V @ 915 MHz
VCTRL = +0.3V @ 915 MHz
P1dB/limiting threshold
VCTRL = 0V @ 8 GHz
9
8
7
dBm
dBm
dBm
VCTRL = +0.15V @ 8 GHz
VCTRL = +0.3V @ 8 GHz
VCTRL = 0V @ 915 MHz, PCW = 30 dBm
VCTRL = +0.15V @ 915 MHz, PCW = 30 dBm
VCTRL = +0.3V @ 915 MHz, PCW = 30 dBm
16
15
13
16.8
15.9
14.7
dBm
dBm
dBm
Leakage power(1)
Input IP2
VCTRL = 0V @ 915 MHz
VCTRL = 0V @ 6 GHz
VCTRL = 0V @ 8 GHz
88
70
70
dBm
dBm
dBm
VCTRL = 0V @ 915 MHz
VCTRL = 0V @ 6 GHz
VCTRL = 0V @ 8 GHz
37
31
30
dBm
dBm
dBm
Input IP3
Response time
1 GHz
1
1
ns
ns
Recovery time(4)
1 GHz, PIN, pulse = 30 dBm
Power Reflecting Mode(2)
VCTRL = +3.0V @ 915 MHz, PCW = 30 dBm
VCTRL = +3.0V @ 8 GHz, PCW = 30 dBm
–41
–20
–39
–19
dBm
dBm
Leakage power(1)
Switching time(3)
State change to 10% RF
3
µs
Page 4 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Table 3 • PE45361 Electrical Specifications (Cont.)
Parameter Condition
Min
Typ
Max
Unit
Notes:
1) Measured with +30 dBm CW applied at input.
2) This mode requires the control voltage to toggle between +3.0V and 0V. At +3.0V, the limiter equivalent circuit is a low impedance to ground,
reflecting most of the incident power back to the source.
3) State change is V
toggle from 0V to +3.0V.
CTRL
4) Pulsed, 1% duty cycle of 10 µs pulse width in 1 ms period, 50Ω @ +25 °C.
DOC-75388-6 – (10/2020)
www.psemi.com
Page 5 of 15
PE45361
UltraCMOS® Power Limiter
Thermal Data
Psi-JT (JT), junction top-of-package, is a thermal
metric to estimate junction temperature of a device on
the customer application PCB (JEDEC JESD51-2).
Table 4 • Thermal Data for PE45361
Parameter
Typ Unit
JT
35
73
°C/W
°C/W
JT = (TJ – TT)/P
JA, junction-to-ambient thermal resistance
where
JT = junction-to-top of package characterization
parameter, °C/W
TJ = die junction temperature, °C
TT = package temperature (top surface, in the
center), °C
P = power dissipated by device, Watts
Power De-rating Curve
Figure 2 shows the power de-rating curve indicating maximum allowable operating RF input power (CW) up to
the part’s maximum operating ambient temperature of +105 °C. This RF input power maintains the maximum
operating junction temperature requirement of +150 °C.
Figure 2 • Power De-rating Curve, 10 MHz–8 GHz, +25 °C to +105 °C Ambient, CW, 50Ω
25 C
85 C
105 C
37
36
35
34
33
32
31
30
29
28
27
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
1.00E+10
Frequency (Hz)
Page 6 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Power Reflecting Mode
Dual Mode Operation
Power reflecting mode requires a power detector to
sample the RF input power and a microcontroller to
toggle the limiter control voltage between +3.0V and
0V based on the system protection requirements. At
+3.0V, the limiter impedance to ground is less than 1Ω
and most of the incident power will be reflected back
to the source. At 0V, the device operates as in power
limiting mode.
Power Limiting Mode
The PE45361 performs as a linear power limiter with
adjustable P1dB/limiting threshold. The P1dB/limiting
threshold can be adjusted by changing the control
voltage between 0V and +0.3V. If unbiased, or if
VCTRL = 0V, the PE45361 still offers power limiting
protection.
DOC-75388-6 – (10/2020)
Page 7 of 15
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Typical Performance Data
Fig. 3–Figure 16 show the typical performance data at +25 °C (ZS = ZL = 50Ω), unless otherwise specified.
Figure 3 • Insertion Loss vs Temp
-55 °C
+25 °C
+85 °C
+105 °C
0
-0.5
-1
-1.5
-2
-2.5
-3
-3.5
-4
-4.5
-5
0
1
2
3
4
5
6
Frequency (GHz)
Figure 5 • Output Return Loss vs Temp
Figure 4 • Input Return Loss vs Temp
-55 °C
+25 °C
+85 °C
+105 °C
-55 °C
+25 °C
+85 °C
+105 °C
0
-5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-10
-15
-20
-25
-30
-35
-40
-45
0
1
2
3
4
5
6
0
1
2
3
4
5
6
Frequency (GHz)
Frequency (GHz)
Page 8 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Figure 9 • POUT vs PIN Over VCTRL (Reflecting Mode @ 915
MHz)
Figure 6 • POUT vs PIN Over VCTRL (Limiting Mode @
915 MHz)
1 V
2 V
3 V
0 V
0.15 V
0.3 V
0
-10
-20
-30
-40
-50
-60
-70
-80
20
18
16
14
12
10
8
6
4
2
0
-2
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
Pin (dBm)
Pin (dBm)
Figure 10 • POUT vs PIN Over VCTRL (Reflecting Mode @
6 GHz)
Figure 7 • POUT vs PIN Over VCTRL (Limiting Mode @
6 GHz)
1 V
2 V
3 V
0 V
0.15 V
0.3 V
0
-10
-20
-30
-40
-50
-60
20
18
16
14
12
10
8
6
4
2
0
-2
0
5
10
15
20
25
30
35
0
5
10
15
20
25
30
35
Pin (dBm)
Pin (dBm)
Figure 11 • P1dB vs VCTRL Over Temp @ 6 GHz
Figure 8 • P1dB vs VCTRL Over Temp @ 915 MHz
-55 °C
+25 °C
+85 °C
+105 °C
-55 °C
+25 °C
+85 °C
+105 °C
14
12
10
8
14
12
10
8
6
6
4
4
2
2
0
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0
0.05
0.1
0.15
0.2
0.25
0.3
VCTRL (V)
VCTRL (V)
DOC-75388-6 – (10/2020)
Page 9 of 15
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Figure 12 • Leakage Power @ PMAX vs VCTRL Over Temp @
915 MHz
Figure 15 • Leakage Power @ PMAX vs VCTRL Over Temp @
6 GHz
-55 °C
+25 °C
+85 °C
+105 °C
-55 °C
+25 °C
+85 °C
+105 °C
18
16
14
12
10
8
6
4
2
0
18
16
14
12
10
8
6
4
2
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0
0.05
0.1
0.15
0.2
0.25
0.3
VCTRL (V)
V CTRL(V)
Figure 13 • IIP2/IIP3 vs PIN Over VCTRL @ 915 MHz
Figure 16 • IIP2/IIP3 vs PIN Over VCTRL @ 6 GHz
IIP2 @ VCTRL = 0V
IIP2 @ VCTRL = 0.3V
IIP2 @ VCTRL = 0.15V
IIP3 @ VCTRL = 0V
IIP2 @ VCTRL = 0V
IIP2 @ VCTRL = 0.3V
IIP2 @ VCTRL = 0.15V
IIP3 @ VCTRL = 0V
IIP3 @ VCTRL = 0.3V
IIP3 @ VCTRL = 0.15V
IIP3 @ VCTRL = 0.3V
IIP3 @ VCTRL = 0.15V
80
60
40
20
0
100
80
60
40
20
0
-10
0
10
20
-10
-5
0
5
10
15
20
25
PIN (dBm)
PIN (dBm)
Figure 14 • IIP2/IIP3 vs VCTRL Over PIN @ 915 MHz
Figure 17 • IIP2/IIP3 vs VCTRL Over PIN @ 6 GHz
IIP2 @ Pin = -5dBm
IIP2 @ Pin = 0dBm
IIP2 @ Pin = 5dBm
IIP3 @ Pin = -5dBm
IIP2 @ Pin = -5dBm
IIP2 @ Pin = 0dBm
IIP2 @ Pin = 5dBm
IIP3 @ Pin = -5dBm
IIP3 @ Pin = 0dBm
IIP3 @ Pin = 5dBm
IIP3 @ Pin = 0dBm
IIP3 @ Pin = 5dBm
100
80
60
40
20
0
80
60
40
20
0
0
0.1
0.2
0.3
0
0.1
0.2
0.3
VCTRL
VCTRL
Page 10 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Evaluation Kit
The power limiter evaluation kit board (EVB) was designed to ease customer evaluation of pSemi’s PE45361.
The uni-directional RF input and output are connected to the RF1 and RF2 port through a 50Ω transmission line
via SMA connectors J2 and J3. A through 50Ω transmission line is available via SMA connectors J5 and J6. This
transmission line can be used to estimate the loss of the PCB over the environmental conditions being
evaluated. The 2-pin connector J4 is connected to the external bias VCTRL
.
The board is constructed of a four metal layer material with a total thickness of 62 mils. The top RF layer is
Rogers RO4350B material with a 6.6 mil RF core and ƐR = 3.66. The middle layers provide ground for the trans-
mission lines. The transmission lines were designed using a coplanar wavequide with ground plane model using
a trace width of 13.5 mils, trace gaps of 10 mils, and metal thickness of 2.1 mils.
Figure 18 • Evaluation Kit Layout for PE45361
DOC-75388-6 – (10/2020)
Page 11 of 15
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Pin Information
This section provides pinout information for the
PE45361. Figure 19 shows the pin map of this device
for the available package. Table 5 provides a
description for each pin.
Table 5 • Pin Descriptions for PE45361
Pin
Pin No.
Description
Name
Figure 19 • Pin Configuration (Top View)
1, 3, 4, 6, 7,
9
GND
Ground
Pin 1 Dot
Marking
RF1(1)(3)
VCTRL
2
RF port 1
5
8
Control voltage
RF port 2
RF2(1)(3)
N/C(2)
10–12
No connect
1
2
3
9
8
7
GND
RF1
GND
RF2
Exposed pad: ground for proper oper-
ation
Pad
GND
Exposed
Ground Pad
Notes:
1) RF pins 2 and 8 must be at 0 VDC. The RF pins do not require DC
blocking capacitors for proper operation if the 0 VDC requirement
is met.
GND
GND
2) Pins 10–12 can be grounded if deemed necessary by the cus-
tomer.
3) The limiter is not bi-directional. RF1 is the RF input and RF2 is the
RF output.
Page 12 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Packaging Information
This section provides packaging data including the moisture sensitivity level, package drawing, package
marking and tape-and-reel information.
Moisture Sensitivity Level
The moisture sensitivity level rating for the PE45361 in the 12-lead 3 × 3 × 0.5 mm QFN package is MSL1.
Package Drawing
Figure 20 • Package Mechanical Drawing for 12-lead 3 × 3 × 0.5 mm QFN
0.30
0.10
(2X)
C
(x12)
3.00
0.50
(x8)
A
1.80 0.10
0.30 0.05
(x12)
B
0.70
(x12)
0.50
(x8)
3.00
1.80 0.10 1.90
3.10
0.25 0.05
(x12)
0.10
(2X)
C
1.00
Ref.
1.90
3.80
TOP VIEW
SIDE VIEW
BOTTOM VIEW
RECOMMENDED LAND PATTERN
PIN #1 CORNER
0.10
0.05
C
C
A B
0.10
0.05
C
C
0.50 0.05
C
ALL FEATURES
SEATING PLANE
0.02
0.152
Ref.
Top-Marking Specification
Figure 21 • Package Marking Specifications for PE45361
45361
= Pin 1 indicator
YY = Last two digits of assembly year
WW = Assembly work week
YYWW
ZZZZZZ
ZZZZZZ = Assembly lot code (maximum six characters)
DOC-75388-6 – (10/2020)
Page 13 of 15
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Tape and Reel Specification
Figure 22 • Tape and Reel Specifications for 12-lead 3 × 3 × 0.5 mm QFN
.
Direction of Feed
Section A-A
P1
P0
see
D0
D1
P2
T
A
A
see note 3
note 1
E
F
see note 3
B0
K0
A0
W0
A0
B0
K0
D0
D1
E
3.3
3.3
1.10
Pin 1
1.50 + 0.10/ -0.00
1.50 min
Notes:
1. 10 Sprocket hole pitch cumulative tolerance 0.2
2. Camber in compliance with EIA 481
3. Pocket position relative to sprocket hole measured
as true position of pocket, not pocket hole
1.75 0.10
5.50 0.05
4.00
F
P0
P1
P2
T
8.00
2.00 0.05
0.30 0.05
12.00 0.30
W0
Dimensions are in milimeters unless otherwise specified
Device Orientation in Tape
Page 14 of 15
DOC-75388-6 – (10/2020)
www.psemi.com
PE45361
UltraCMOS® Power Limiter
Ordering Information
Table 6 lists the available ordering codes for the PE45361 as well as available shipping methods.
Table 6 • Order Codes for PE45361
Order Codes
Description
Packaging
Shipping Method
PE45361A–X
EK45361–01
PE45361 Power limiter
PE45361 Evaluation kit
12-lead 3 × 3 × 0.5 mm QFN
Evaluation kit
500 units/T&R
1/box
Document Categories
Advance Information
The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and
features may change in any manner without notice.
Preliminary Specification
The datasheet contains preliminary data. Additional data may be added at a later date. pSemi reserves the right to change specifications at any
time without notice in order to supply the best possible product.
Product Specification
The datasheet contains final data. In the event pSemi decides to change the specifications, pSemi will notify customers of the intended changes by
issuing a CNF (Customer Notification Form).
Product Brief
This document contains a shortened version of the datasheet. For the full datasheet, contact sales@psemi.com.
Sales Contact
For additional information, contact Sales at sales@psemi.com.
Disclaimers
The information in this document is believed to be reliable. However, pSemi assumes no liability for the use of this information. Use shall be entirely
at the user’s own risk. No patent rights or licenses to any circuits described in this document are implied or granted to any third party. pSemi’s
products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or
sustain life, or in any application in which the failure of the pSemi product could create a situation in which personal injury or death might occur.
pSemi assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications.
Patent Statement
pSemi products are protected under one or more of the following U.S. patents: patents.psemi.com
Copyright and Trademark
©2016-2020, pSemi Corporation. All rights reserved. The Peregrine Semiconductor name, Peregrine Semiconductor logo and UltraCMOS are
registered trademarks and the pSemi name, pSemi logo, HaRP and DuNE are trademarks of pSemi Corporation in the U.S. and other countries.
Product Specification
www.psemi.com
DOC-75388-6 – (10/2020)
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