EK42650A-01 [PSEMI]
SP3T High Power UltraCMOS RF Switch 30 MHz - 1000 MHz; SP3T高功率的UltraCMOS RF开关30兆赫 - 1000兆赫
| 型号： | EK42650A-01 |
| 厂家： | 
Peregrine Semiconductor |
| 描述： | SP3T High Power UltraCMOS RF Switch 30 MHz - 1000 MHz |
| 文件： | 总11页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Product Specification
PE42650A
SP3T High Power UltraCMOS™
RF Switch 30 MHz - 1000 MHz
Product Description
Features
The following specification defines an SP3T (single pole three
throw) switch for use in cellular and other wireless applications.
It has both a standard and attenuated RX mode. The
PE42650A uses Peregrine’s UltraCMOS™ process and also
features HaRP™ technology enhancements to deliver high
linearity and exceptional harmonics performance. HaRP™
technology is an innovative feature of the UltraCMOS™
process providing upgraded linearity performance.
•
•
50 Watt P1dB compression point
10 Watts <8:1 VSWR (Normal
Operation)
•
•
•
•
•
38 dB TX-RX Isolation
2fo and 3fo < -81 dBc @10 Watts
ESD rugged to 2.0 kV HBM
No blocking capacitors required
32-lead 5x5 mm QFN package
The PE42650A is manufactured on Peregrine’s UltraCMOS™
process, a patented variation of silicon-on-insulator (SOI)
technology on a sapphire substrate, offering the performance
of GaAs with the economy and integration of conventional
CMOS.
Figure 1. Functional Diagram
Figure 2. Package Type
32-lead 5x5 mm QFN
TX1
ESD
TX2
RX
ANT
ESD
ESD
CMOS
Control Driver
and ESD
CTRL
Document No. 70-0267-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 1 of 11
PE42650A
Product Specification
Table 1: Electrical Specifications @ +25 °C, VDD = 3.3 V (ZS = ZL = 50 Ω) unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Units
TX Insertion Loss1
0.3
0.5
0.5
0.9
16
dB
dB
30 MHz ≤ 1 GHz
RX Insertion Loss (Un-Attenuated State)1 30 MHz ≤ 1 GHz
RX Insertion Loss (Attenuated State)1
800 MHz
13
14.5
45.4
dB
0.1 dB Input Compression Point
800 MHz, 50% duty cycle
dBm
Isolation (Supply Biased): TX-TX
Isolation (Supply Biased): TX-RX
800 MHz
800 MHz
30
35
33
38
dB
dB
Unbiased Isolation: ANT - TX, VDD, V1,
V2, V3=0 V
800 MHz, +27 dBm
800 MHz, +27 dBm
6
10
22
dB
dB
Unbiased Isolation: ANT - RX, VDD, V1,
V2, V3=0 V
14
Un-Attenuated State, 800 MHz
18
12
20
22
18
dB
dB
RX Port Return Loss1
Attenuated State, with external matching inductor optimized without
attenuator engaged, 800 MHz
TX and ANT Port Return Loss1
800 MHz
23
dB
TX, 2nd Harmonic
TX, 3rd Harmonic
800 MHz @ 42.5 dBm
800 MHz @ 42.5 dBm
-81
-81
-79
-79
dBc
dBc
RX IIP3
Un-Attenuated State, 800 MHz, 150 kHz tone separation
50% of CTRL to 10/90% of RF
30
dBm
ms
Switching Time
0.1
0.5
Note: 1. The device was matched with ~4 nH inductance per RF port. RX port may not need matching inductor.
Table 3. Absolute Maximum Ratings
Table 2. Operating Ranges
Symbol
Parameter/Conditions
Min Max Units
Parameter
Min
Typ
Max Units
Power supply voltage
-0.3
4
V
VDD
Frequency Range
30
1000
40
MHz
dBm
dBm
V
VDD
0.3
+
TX Input Power1 (VSWR ≤ 8:1)
RX Input Power2 (VSWR ≤ 8:1)
VDD Power Supply Voltage
IDD Power Supply Current
Control Voltage High
Voltage on any DC input
-0.3
V
VI
Storage temperature range
Maximum case temperature
-65
150
°C
°C
27
TST
85
TCASE
3.2
1.4
3.3
90
3.4
170
Peak maximum junction
temperature (10 seconds max)
TX Input Power1
(VSWR 20:1, 10 seconds)
TX Input Power1 (50 Ω)
RX Input Power at ANT pin2
(VSWR 20:1)
uA
200
°C
Tj
V
40
45
dBm
dBm
Control Voltage Low
0.4
85
V
TOP Operating temperature
range (Case)
PIN
-40
°C
°C
27
27
dBm
dBm
W
RF Input Power on inactive ports or
supply unbiased
Tj Operating junction
temperature
140
Maximum Power Dissipation from
RF Insertion Loss
Notes: 1. Supply biased
PD
2.8
2. Supply biased or unbiased
ESD Voltage (HBM, MIL_STD 883
Method 3015.7)
2000
V
VESD
Moisture Sensitivity Level
Notes: 1. Supply biased
2. Supply biased or unbiased
The Moisture Sensitivity Level rating for the PE42650A
in the 5x5 QFN package is MSL3.
Absolute Maximum Ratings
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0267-02 │ UltraCMOS™ RFIC Solutions
Page 2 of 11
PE42650A
Product Specification
Figure 3. Pin Configuration (Top View)
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
TX1
GND
TX2
GND
TX2
GND
TX1
Latch-Up Avoidance
Exposed
Ground
Paddle
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
GND
GND
GND
GND
GND
GND
RX
GND
Table 5. Control Logic Truth Table
Path
ANT – RX Attenuated
Unsupported mode
Unsupported mode
ANT – TX1
V3
L
V2
L
V1
L
L
L
H
L
Table 4. Pin Descriptions
L
H
H
L
Pin No.
Pin Name
Description
L
H
L
1
2
GND
TX1
Ground
TX1 port
Ground
TX1 port
Ground
RX port
ANT – RX
H
H
H
H
Unsupported mode
Unsupported mode
ANT – TX2
L
H
L
3
GND
TX11
GND
RX
H
H
4
H
5-7
8
9-10
11
GND
N/C
VDD
Ground
No Connect
12
Nominal 3.3 V supply connection
Control
13
V3
14
V2
Control
15
V12
Control
16
N/C
GND
TX2
GND
TX23
GND
ANT
GND
GND
Do not connect
Ground
17-20
21
TX2 port
22
Ground
23
TX2 port
24-27
28
Ground
Antenna Port
Ground
29-32
Paddle
Exposed ground paddle
Note: 1. Must be tied to pin 2
2. Must be tied to V2
3. Must be tied to pin 21
Document No. 70-0267-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 11
PE42650A
Product Specification
Evaluation Kit
The PE42650A Evaluation Kit board was designed
to ease customer evaluation of the PE42650A RF
switch.
Figure 4. Evaluation Board Layout
Peregrine Specification 101-0315
DC power is supplied through J10, with VDD on pin 9,
and GND on the entire lower row of even numbered
pins. To evaluate a switch path, add or remove
jumpers on V1 (pin 3), V2 (pin 5), and V3 (pin
7) using Table 5 (adding a jumper pulls the CMOS
control pin low and removing it allows the on-board
pull-up resistor to set the CMOS control pin
high). J10 pins 1, 11, and 13 are N/C.
The RF common port (ANT) is connected through
a 50 Ohm transmission line via the top SMA
connector, J1. RX and TX paths are also
connected through 50 Ohm transmission lines via
SMA connectors. A 50 Ohm through transmission
line is available via SMA connectors J8 and J9.
This transmission line can be used to estimate the
loss of the PCB over the environmental conditions
being evaluated. An open-ended 50 Ohm
transmission line is also provided at J7 for calibration
if needed.
Narrow trace widths are used near each part to
improve impedance matching.
Figure 5. Evaluation Board Schematic
Peregrine Specification 102-0535
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0267-02 │ UltraCMOS™ RFIC Solutions
Page 4 of 11
PE42650A
Product Specification
Performance Plots
Figure 6. Isolation, Tx-Tx, VDD=3.3V
Figure 8. Isolation, Tx-Tx, +25°C
Figure 9. Isolation, Tx-Rx, +25°C
Figure 7. Isolation, Tx-Rx, VDD=3.3V
Document No. 70-0267-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
PE42650A
Product Specification
Figure 10. Tx Insertion Loss, VDD=3.3V
Figure 13. Tx Insertion Loss, +25°C
Figure 11. Rx Insertion Loss
Un-Attenuated, VDD=3.3V
Figure 14. Rx Insertion Loss
Un-Attenuated, +25°C
Figure 12. Rx Insertion Loss
Attenuated, VDD=3.3V
Figure 15. Rx Insertion Loss
Attenuated, +25°C
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0267-02 │ UltraCMOS™ RFIC Solutions
Page 6 of 11
PE42650A
Product Specification
Figure 16. Return Loss, VDD=3.3V
Figure 18. Return Loss, +25°C
Figure 19. Tx Return Loss, +25°C
Figure 17. Tx Return Loss, VDD=3.3V
Document No. 70-0267-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
PE42650A
Product Specification
Figure 22. Rx Return Loss
Attenuated, +25°C
Figure 20. Rx Return Loss
Attenuated, VDD=3.3V
Figure 21. Rx Return Loss
Un-Attenuated, VDD=3.3V
Figure 23. Rx Return Loss
Un-Attenuated, +25°C
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0267-02 │ UltraCMOS™ RFIC Solutions
Page 8 of 11
PE42650A
Product Specification
Thermal Data
Though the insertion loss for this part is very low,
when handling high power RF signals, the part can
get quite hot.
Figure 24. Power Dissipation
3.0
1: 1VSWR(50OhmLoad)
2: 1VSWR(25OhmLoad)
8:1VSWR(6.25OhmLoad)
20:1VSWR(2.5OhmLoad)
INF:1VSWR(0OhmLoad)
Rel i abi l i ty Li mi t
2.5
2.0
1.5
Figure 24 shows the estimated power dissipation for
a given incident RF power level. Multiple curves are
presented to show the effect of poor VSWR
conditions. VSWR conditions that present short
circuit loads to the part can cause significantly more
power dissipation than with proper matching.
1.0
Figure 25 shows the estimated maximum junction
temperature of the part for similar conditions.
0.5
0.0
Note that both of these charts assume that the case
(GND slug) temperature is held at 85C. Special
consideration needs to be made in the design of the
PCB to properly dissipate the heat away from the
part and maintain the 85C maximum case
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
RF Power (dBm)
temperature. It is recommended to use best design
practices for high power QFN packages: multi-layer
PCBs with thermal vias in a thermal pad soldered to
the slug of the package. Special care also needs to
be made to alleviate solder voiding under the part.
Figure 25. Maximum Junction Temperature
14 5
14 0
13 5
13 0
12 5
12 0
115
110
10 5
10 0
95
1:1VSWR(50OhmLoad)
2:1VSWR(25OhmLoad)
8:1VSWR(6.25OhmLoad)
20:1VSWR(2.5OhmLoad)
INF:1 VSWR (0 OhmLoad)
Reliability Li mi t
Table 6. Theta JC
Parameter
Min
Typ
Max Units
Theta JC (+85°C)
15
C/W
90
85
30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
RF Power (dBm)
Document No. 70-0267-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 11
PE42650A
Product Specification
Figure 26. Package Drawing
See Note
below
Note: Not for electrical connection.
Corner detail is tied to paddle and
should not be isolated on PCB board.
Figure 27. Tape and Reel Specs
Pin 1
Top of
Device
Tape Feed Direction
Device Orientation in Tape
Table 7. Ordering Information
Order Code
Part Marking
Description
Package
Shipping Method
PE42650AMLI-Z
42650A
Parts on Tape and Reel
Green 32-lead 5x5mm QFN
3000 units / T&R
PE42650AMLI
EK42650A-01
42650A
42650A
Parts in Tubes or Cut Tape
Evaluation Kit
Green 32-lead 5x5mm QFN
Evaluation Kit
73 units / Tube
1 / Box
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Document No. 70-0267-02 │ UltraCMOS™ RFIC Solutions
Page 10 of 11
PE42650A
Product Specification
Sales Offices
The Americas
Peregrine Semiconductor Corporation
Peregrine Semiconductor, Asia Pacific (APAC)
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
9380 Carroll Park Drive
San Diego, CA 92121
Tel: 858-731-9400
Fax: 858-731-9499
Peregrine Semiconductor, Korea
#B-2607, Kolon Tripolis, 210
Geumgok-dong, Bundang-gu, Seongnam-si
Gyeonggi-do, 463-943 South Korea
Tel: +82-31-728-3939
Europe
Peregrine Semiconductor Europe
Bâtiment Maine
Fax: +82-31-728-3940
13-15 rue des Quatre Vents
F-92380 Garches, France
Tel: +33-1-4741-9173
Fax : +33-1-4741-9173
Peregrine Semiconductor K.K., Japan
Teikoku Hotel Tower 10B-6
1-1-1 Uchisaiwai-cho, Chiyoda-ku
Tokyo 100-0011 Japan
Tel: +81-3-3502-5211
Fax: +81-3-3502-5213
High-Reliability and Defense Products
Americas
San Diego, CA, USA
Phone: 858-731-9475
Fax: 848-731-9499
Europe/Asia-Pacific
Aix-En-Provence Cedex 3, France
Phone: +33-4-4239-3361
Fax: +33-4-4239-7227
For a list of representatives in your area, please refer to our Web site at: www.psemi.com
Data Sheet Identification
Advance Information
The information in this data sheet is believed to be reliable.
However, Peregrine assumes no liability for the use of this
information. Use shall be entirely at the user’s own risk.
The product is in a formative or design stage. The data
sheet contains design target specifications for product
development. Specifications and features may change in
any manner without notice.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted to any third party.
Preliminary Specification
Peregrine’s products are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Peregrine product could
create a situation in which personal injury or death might occur.
Peregrine assumes no liability for damages, including
consequential or incidental damages, arising out of the use of
its products in such applications.
The data sheet contains preliminary data. Additional data
may be added at a later date. Peregrine reserves the right
to change specifications at any time without notice in order
to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine
decides to change the specifications, Peregrine will notify
customers of the intended changes by issuing a DCN
(Document Change Notice).
The Peregrine name, logo, and UTSi are registered trademarks
and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks
of Peregrine Semiconductor Corp.
Document No. 70-0267-02 │ www.psemi.com
©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 11 of 11
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PSEMI
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