BUK9225-55A,118 [NXP]

N-channel TrenchMOS logic level FET DPAK 3-Pin;
BUK9225-55A,118
型号: BUK9225-55A,118
厂家: NXP    NXP
描述:

N-channel TrenchMOS logic level FET DPAK 3-Pin

开关 脉冲 晶体管
文件: 总13页 (文件大小:110K)
中文:  中文翻译
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BUK9225-55A  
TrenchMOS™ logic level FET  
Rev. 01 — 17 April 2001  
Product specification  
M3D300  
1. Description  
N-channel enhancement mode field-effect power transistor in a plastic package using  
TrenchMOS™1 technology, featuring very low on-state resistance.  
Product availability:  
BUK9225-55A in SOT428 (D-PAK).  
2. Features  
TrenchMOS™ technology  
Q101 compliant  
175 °C rated  
Logic level compatible.  
3. Applications  
Automotive and general purpose power switching:  
12 V and 24 V loads  
c
c
Motors, lamps and solenoids.  
4. Pinning information  
Table 1: Pinning - SOT428 (D-PAK), simplified outline and symbol  
Pin  
1
Description  
gate (g)  
Simplified outline  
Symbol  
d
s
mb  
2
drain (d)  
3
source (s)  
g
mb  
mounting base;  
connected to  
drain (d)  
MBB076  
2
1
3
Top view  
MBK091  
SOT428 (D-PAK)  
1. TrenchMOS is a trademark of Royal Philips Electronics.  
 
 
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
5. Quick reference data  
Table 2: Quick reference data  
Symbol Parameter  
Conditions  
Typ  
Max  
55  
Unit  
V
VDS  
ID  
drain-source voltage (DC)  
drain current (DC)  
Tmb = 25 °C; VGS = 5 V  
Tmb = 25 °C  
43  
A
Ptot  
Tj  
total power dissipation  
junction temperature  
94  
W
175  
25  
°C  
RDSon  
drain-source on-state resistance  
Tj = 25 °C; VGS = 5 V; ID = 25 A  
Tj = 25 °C; VGS = 4.5 V; ID = 25 A  
Tj = 25 °C; VGS = 10 V; ID = 25 A  
21  
mΩ  
mΩ  
mΩ  
27  
19  
22  
6. Limiting values  
Table 3: Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
55  
Unit  
V
VDS  
VDGR  
VGS  
ID  
drain-source voltage (DC)  
drain-gate voltage (DC)  
gate-source voltage (DC)  
drain current (DC)  
RGS = 20 kΩ  
55  
V
±15  
43  
V
Tmb = 25 °C; VGS = 5 V;  
A
Figure 2 and 3  
T
mb = 100 °C; VGS = 5 V; Figure 2  
30  
A
A
[1]  
IDM  
peak drain current  
Tmb = 25 °C; pulsed; tp 10 µs;  
173  
Figure 3  
Ptot  
Tstg  
Tj  
total power dissipation  
storage temperature  
Tmb = 25 °C; Figure 1  
94  
W
55  
55  
+175  
+175  
°C  
°C  
operating junction temperature  
Source-drain diode  
IDR  
reverse drain current (DC)  
pulsed reverse drain current  
Tmb = 25 °C  
43  
A
A
IDRM  
Tmb = 25 °C; pulsed; tp 10 µs  
173  
Avalanche ruggedness  
WDSS  
non-repetitive avalanche energy  
unclamped inductive load; ID = 43 A;  
123  
mJ  
VDS 55 V; VGS = 5 V; RGS = 50 ;  
starting Tj = 25 °C  
[1] IDM is limited by chip, not package.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
2 of 13  
 
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
03aa24  
120  
100  
80  
60  
40  
20  
0
I
03aa16  
der  
(%)  
120  
der  
P
(%)  
100  
80  
60  
40  
20  
0
0
25  
50  
75 100 125 150 175 200  
o
0
50  
100  
150  
200  
(oC)  
T
( C)  
T
mb  
mb  
V
GS 4.5 V  
Ptot  
Pder  
=
× 100%  
----------------------  
P
ID  
°
tot(25 C)  
Ider  
=
× 100%  
------------------  
I
°
D(25 C)  
Fig 1. Normalized total power dissipation as a  
function of mounting base temperature.  
Fig 2. Normalized continuous drain current as a  
function of mounting base temperature.  
3
10  
I
D
(A)  
R
= V / I  
DS D  
DSon  
2
10  
t
= 10 us  
p
100 us  
1 ms  
10  
t
p
P
δ =  
T
D.C.  
10 ms  
t
t
p
100 ms  
T
1
2
10  
1
10  
V
(V)  
DS  
Tmb = 25 °C; IDM is single pulse.  
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
3 of 13  
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
7. Thermal characteristics  
Table 4: Thermal characteristics  
Symbol  
Rth(j-a)  
Parameter  
Conditions  
Value  
71.4  
1.6  
Unit  
K/W  
K/W  
thermal resistance from junction to ambient  
Rth(j-mb)  
thermal resistance from junction to mounting Figure 4  
base  
7.1 Transient thermal impedance  
10  
Z
th(j-mb)  
(K/W)  
1
δ = 0.5  
0.2  
0.1  
-1  
10  
0.05  
t
p
P
δ =  
T
0.02  
Single Shot  
t
t
p
T
-2  
10  
10  
-6  
-5  
-4  
10  
-3  
10  
-2  
10  
-1  
10  
10  
1
t
(s)  
p
Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
4 of 13  
 
 
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
8. Characteristics  
Table 5: Characteristics  
Tj = 25 °C unless otherwise specified  
Symbol  
Static characteristics  
V(BR)DSS drain-source breakdown  
voltage  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
ID = 0.25 mA; VGS = 0 V  
Tj = 25 °C  
55  
50  
V
V
Tj = 55 °C  
VGS(th)  
gate-source threshold voltage ID = 1 mA; VDS = VGS  
Figure 9  
Tj = 25 °C  
;
1
1.5  
2
V
V
V
Tj = 175 °C  
Tj = 55 °C  
0.5  
2.3  
IDSS  
drain-source leakage current VDS = 55 V; VGS = 0 V  
Tj = 25 °C  
Tj = 175 °C  
0.05  
10  
µA  
µA  
nA  
500  
100  
IGSS  
gate-source leakage current VGS = ±10 V; VDS = 0 V  
2
RDSon  
drain-source on-state  
resistance  
VGS = 5 V; ID = 25 A;  
Figure 7 and 8  
Tj = 25 °C  
21  
25  
50  
27  
22  
mΩ  
mΩ  
mΩ  
mΩ  
Tj = 175 °C  
VGS = 4.5 V; ID = 25 A;  
VGS = 10 V; ID =25 A;  
19  
Dynamic characteristics  
Ciss  
Coss  
Crss  
td(on)  
tr  
input capacitance  
output capacitance  
reverse transfer capacitance  
turn-on delay time  
rise time  
VGS = 0 V; VDS = 25 V;  
f = 1 MHz; Figure 12  
1360  
240  
160  
17  
1724  
287  
222  
pF  
pF  
pF  
ns  
ns  
ns  
ns  
nH  
VDD = 30 V; RL = 1.2 ;  
VGS = 5 V; RG = 10 ;  
104  
82  
td(off)  
tf  
turn-off delay time  
fall time  
80  
Ld  
internal drain inductance  
measured from drain to  
centre of die  
2.5  
Ls  
internal source inductance  
measured from source lead  
to source bond pad  
7.5  
nH  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
5 of 13  
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
Table 5: Characteristics…continued  
Tj = 25 °C unless otherwise specified  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Source-drain diode  
VSD  
source-drain (diode forward) IS = 15 A; VGS = 0 V;  
0.85  
1.2  
V
voltage  
Figure 15  
trr  
reverse recovery time  
recovered charge  
IS = 20 A; dIS/dt = 100 A/µs  
VGS = 10 V; VDS = 30 V  
50  
85  
ns  
Qr  
nC  
V
(V) = 9  
GS  
8
03na05  
03na03  
180  
160  
140  
120  
100  
80  
45  
40  
35  
30  
25  
20  
15  
10  
I
D
(A)  
R
10  
7
DSon  
(m)  
6
5
4
60  
40  
3
20  
2.2  
0
0
2
4
6
8
10  
(V)  
2
4
6
8
10  
V
V
(V)  
GS  
DS  
Tj = 25 °C  
Tj = 25 °C; ID = 25 A  
Fig 5. Output characteristics: drain current as a  
function of drain-source voltage; typical values.  
Fig 6. Drain-source on-state resistance as a function  
of gate-source voltage; typical values.  
03ne89  
03na06  
2.2  
50  
R
(m)  
DSon  
3.8  
a
2
3.6  
3.4  
3.2  
45  
40  
35  
30  
25  
20  
15  
10  
1.8  
1.6  
1.4  
1.2  
1
V
(V)= 3  
GS  
4
0.8  
0.6  
0.4  
0.2  
0
5
10  
30  
50  
70  
90  
-60  
-20  
20  
60  
100  
140  
180  
I
(A)  
D
o
T ( C)  
j
Tj = 25 °C  
RDSon  
a =  
---------------------------  
RDSon(25 C)  
°
Fig 7. Drain-source on-state resistance as a function  
of drain current; typical values.  
Fig 8. Normalized drain-source on-state resistance  
factor as a function of junction temperature.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
6 of 13  
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
03aa36  
-1  
03aa33  
10  
I
2.5  
D
V
GS(th)  
(V)  
2
(A)  
-2  
10  
10  
10  
10  
10  
-3  
-4  
-5  
-6  
1.5  
1
min  
typ  
max  
0.5  
0
-60  
0
60  
120  
180  
0
0.5  
1
1.5  
2
2.5  
V
3
(V)  
T
(oC)  
j
GS  
ID = 1 mA; VDS = VGS  
Tj = 25 °C; VDS = VGS  
Fig 9. Gate-source threshold voltage as a function of  
junction temperature.  
Fig 10. Sub-threshold drain current as a function of  
gate-source voltage.  
03na04  
4000  
C
40  
g
fs  
(pF)  
(S)  
3500  
35  
3000  
2500  
2000  
30  
25  
20  
15  
10  
5
1500  
Ciss  
1000  
500  
Coss  
Crss  
2
0
0
-2  
-1  
10  
10  
1
10  
10  
(V)  
0
20  
40  
60  
80  
I
(A)  
V
DS  
D
Tj = 25 °C; VDS = 25 V  
VGS = 0 V; f = 1 MHz  
Fig 11. Forward transconductance as a function of  
drain current; typical values.  
Fig 12. Input, output and reverse transfer capacitances  
as a function of drain-source voltage; typical  
values.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
7 of 13  
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
03na02  
03na00  
100  
6
5
4
3
2
1
0
V
I
GS  
(V)  
D
(A)  
80  
V
= 14 V  
DD  
60  
40  
V
= 44 V  
DD  
20  
o
o
T = 25  
C
T = 175  
C
j
j
0
0
10  
20  
30  
40  
0
2
4
6
Q
(nC)  
V
(V)  
G
GS  
VDS = 25 V  
Tj = 25 °C; ID = 25 A  
Fig 13. Transfer characteristics: drain current as a  
function of gate-source voltage; typical values.  
Fig 14. Gate-source voltage as a function of turn-on  
gate charge; typical values.  
03na01  
100  
I
S
(A)  
80  
60  
o
T = 175  
C
o
j
T = 25  
C
j
40  
20  
0
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6  
(V)  
V
SD  
VGS = 0 V  
Fig 15. Reverse diode current as a function of reverse diode voltage; typical values.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
8 of 13  
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
9. Package outline  
Plastic single-ended surface mounted package (Philips version of D-PAK); 3 leads  
(one lead cropped)  
SOT428  
seating plane  
y
A
A
E
A
2
A
b
D
1
1
2
mounting  
base  
E
1
D
H
E
L
2
2
L
1
L
1
3
b
b
w
M
A
c
1
e
e
1
0
10  
20 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
b
E
H
E
max.  
D
L
1
min.  
A
max.  
E
max.  
y
D
max.  
1
1
(1)  
1
A
A
b
2
UNIT  
mm  
b
c
e
e
1
L
L
w
2
1
2
max.  
max.  
min.  
max.  
0.65 0.89  
0.45 0.71  
0.7  
0.5  
2.38  
2.22  
0.89 1.1  
0.71 0.9  
5.36  
5.26  
0.4 6.22  
0.2 5.98  
6.73  
6.47  
10.4 2.95  
9.6  
2.55  
4.81  
4.45  
4.57  
0.2  
0.2  
4.0 2.285  
0.5  
Note  
1. Measured from heatsink back to lead.  
REFERENCES  
EUROPEAN  
PROJECTION  
OUTLINE  
VERSION  
ISSUE DATE  
IEC  
JEDEC  
EIAJ  
98-04-07  
99-09-13  
SOT428  
TO-252  
SC-63  
Fig 16. SOT428 (D-PAK).  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
9 of 13  
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
10. Revision history  
Table 6: Revision history  
Rev Date  
CPCN  
-
Description  
01 20010417  
Product specification; initial version.  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
10 of 13  
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
11. Data sheet status  
[1]  
[2]  
Data sheet status  
Product status  
Definition  
Objective data  
Development  
This data sheet contains data from the objective specification for product development. Philips Semiconductors  
reserves the right to change the specification in any manner without notice.  
Preliminary data  
Product data  
Qualification  
Production  
This data sheet contains data from the preliminary specification. Supplementary data will be published at a  
later date. Philips Semiconductors reserves the right to change the specification without notice, in order to  
improve the design and supply the best possible product.  
This data sheet contains data from the product specification. Philips Semiconductors reserves the right to  
make changes at any time in order to improve the design, manufacturing and supply. Changes will be  
communicated according to the Customer Product/Process Change Notification (CPCN) procedure  
SNW-SQ-650A.  
[1]  
[2]  
Please consult the most recently issued data sheet before initiating or completing a design.  
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at  
URL http://www.semiconductors.philips.com.  
12. Definitions  
13. Disclaimers  
Short-form specification The data in  
extracted from a full data sheet with the same type number and title. For  
detailed information see the relevant data sheet or data handbook.  
a
short-form specification is  
Life support — These products are not designed for use in life support  
appliances, devices, or systems where malfunction of these products can  
reasonably be expected to result in personal injury. Philips Semiconductors  
customers using or selling these products for use in such applications do so  
at their own risk and agree to fully indemnify Philips Semiconductors for any  
damages resulting from such application.  
Limiting values definition Limiting values given are in accordance with  
the Absolute Maximum Rating System (IEC 60134). Stress above one or  
more of the limiting values may cause permanent damage to the device.  
These are stress ratings only and operation of the device at these or at any  
other conditions above those given in the Characteristics sections of the  
specification is not implied. Exposure to limiting values for extended periods  
may affect device reliability.  
Right to make changes — Philips Semiconductors reserves the right to  
make changes, without notice, in the products, including circuits, standard  
cells, and/or software, described or contained herein in order to improve  
design and/or performance. Philips Semiconductors assumes no  
responsibility or liability for the use of any of these products, conveys no  
licence or title under any patent, copyright, or mask work right to these  
products, and makes no representations or warranties that these products  
are free from patent, copyright, or mask work right infringement, unless  
otherwise specified.  
Application information Applications that are described herein for any  
of these products are for illustrative purposes only. Philips Semiconductors  
make no representation or warranty that such applications will be suitable for  
the specified use without further testing or modification.  
9397 750 08134  
© Philips Electronics N.V. 2001 All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
11 of 13  
 
 
 
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
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Marketing Communications,  
Internet: http://www.semiconductors.philips.com  
Building BE, P.O. Box 218, 5600 MD EINDHOVEN,  
The Netherlands, Fax. +31 40 272 4825  
(SCA72)  
9397 750 08134  
© Philips Electronics N.V. 2001. All rights reserved.  
Product specification  
Rev. 01 — 17 April 2001  
12 of 13  
BUK9225-55A  
TrenchMOS™ logic level FET  
Philips Semiconductors  
Contents  
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Thermal characteristics. . . . . . . . . . . . . . . . . . . 4  
Transient thermal impedance . . . . . . . . . . . . . . 4  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
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7.1  
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© Philips Electronics N.V. 2001.  
Printed in The Netherlands  
All rights are reserved. Reproduction in whole or in part is prohibited without the prior  
written consent of the copyright owner.  
The information presented in this document does not form part of any quotation or  
contract, is believed to be accurate and reliable and may be changed without notice. No  
liability will be accepted by the publisher for any consequence of its use. Publication  
thereof does not convey nor imply any license under patent- or other industrial or  
intellectual property rights.  
Date of release: 17 April 2001  
Document order number: 9397 750 08134  

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