935325849518 [NXP]

RISC Microcontroller;


型号：	935325849518
厂家：	NXP
描述：	RISC Microcontroller 微控制器外围集成电路
文件：	总131页 (文件大小：2650K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5674F

Rev. 10.1, 06/2015

MPC5674F

TEPBGA–416

27mm x 27mm

TEPBGA–516

27mm x 27mm

MPC5674F Microcontroller

Data Sheet

TEPBGA–324

23mm x 23mm

Covers: MPC5674F and MPC5673F

• Dual issue, 32-bit CPU core complex (e200z7)

single action, double action, pulse width modulation

(PWM) and modulus counter operation

• Four enhanced queued analog-to-digital converters

(eQADC)

– Compliant with the Power Architecture embedded

category

– 16 KB I-Cache and 16 KB D-Cache

– Includes an instruction set enhancement allowing

variable length encoding (VLE), optional encoding of

mixed 16-bit and 32-bit instructions, for code size

footprint reduction

– Support for 64 analog channels

– Includes one absolute reference ADC channel

– Includes eight decimation filters

• Four deserial serial peripheral interface (DSPI) modules

• Three enhanced serial communication interface (eSCI)

modules

• Four controller area network (FlexCAN) modules

• Dual-channel FlexRay controller

– Includes signal processing extension (SPE2) instruction

support for digital signal processing (DSP) and

single-precision floating point operations

• 4 MB on-chip flash

– Supports read during program and erase operations, and

multiple blocks allowing EEPROM emulation

• 256 KB on-chip general-purpose SRAM including 32 KB

of standby RAM

• Nexus development interface (NDI) per IEEE-ISTO

5001-2003/5001-2008 standard

• Device and board test support per Joint Test Action Group

(JTAG) (IEEE 1149.1)

• Two direct memory access controller (eDMA2) blocks

– One supporting 64 channels

• On-chip voltage regulator controller regulates supply

voltage down to 1.2 V for core logic

– One supporting 32 channels

• Interrupt controller (INTC)

• Frequency modulated phase-locked loop (FMPLL)

• Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus masters

• External bus interface (EBI) for calibration and application

development (not available on all packages)

• System integration unit (SIU)

• Error correction status module (ECSM)

• Boot assist module (BAM) supports serial bootload via

CAN or SCI

• Two second-generation enhanced time processor units

(eTPU2) that share code and data RAM.

– 32 standard channels per eTPU2

– 24 KB code RAM

– 6 KB parameter (data) RAM

• Enhanced modular input output system supporting 32

unified channels (eMIOS) with each channel capable of

Table of Contents

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

4.7.3 LVDS Pad Specifications . . . . . . . . . . . . . . . . . 35

4.8 Oscillator and FMPLL Electrical Characteristics . . . . . 35

4.9 eQADC Electrical Characteristics . . . . . . . . . . . . . . . . 37

4.9.1 ADC Internal Resource Measurements . . . . . . 39

4.10 C90 Flash Memory Electrical Characteristics . . . . . . . 40

4.11 AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.11.1 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4.11.2 Pad AC Specifications . . . . . . . . . . . . . . . . . . . 44

4.12 AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

4.12.1 Generic Timing Diagrams. . . . . . . . . . . . . . . . . 45

4.12.2 Reset and Configuration Pin Timing. . . . . . . . . 46

4.12.3 IEEE 1149.1 Interface Timing. . . . . . . . . . . . . . 47

4.12.4 Nexus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.12.5 External Bus Interface (EBI) Timing. . . . . . . . . 53

4.12.6 External Interrupt Timing (IRQ Pin) . . . . . . . . . 57

4.12.7 eTPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 57

4.12.8 eMIOS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 58

4.12.9 DSPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.1 324-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.2 416-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.3 516-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

1.1 Orderable Parts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

1.2 MPC567xF Family Differences . . . . . . . . . . . . . . . . . . . .4

MPC5674F Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

2.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

3.1 324-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .6

3.2 416-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . . .9

3.3 516-ball TEPBGA Pin Assignments . . . . . . . . . . . . . . .14

3.4 Signal Properties and Muxing. . . . . . . . . . . . . . . . . . . .19

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .21

4.2.1 General Notes for Specifications at

Maximum Junction Temperature . . . . . . . . . . . .23

4.3 EMI (Electromagnetic Interference) Characteristics . . .24

4.4 ESD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25

4.5 PMC/POR/LVI Electrical Specifications . . . . . . . . . . . .25

4.6 Power Up/Down Sequencing . . . . . . . . . . . . . . . . . . . .29

4.6.1 Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.6.2 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.6.3 Power Sequencing and POR Dependent on V_DDA

4.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30

4.7.1 I/O Pad Current Specifications . . . . . . . . . . . . .33

4.7.2 I/O Pad V_DD33Current Specifications . . . . . . . .34

Appendix ASignal Properties and Muxing . . . . . . . . . . . . . . . . . . 73

Appendix BRevision History . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Ordering Information

1.1

Orderable Parts

Figure 1 and Table 1 describe and list the orderable part numbers for the MPC5674F.

M PC 5674F F 3 M VR 3

Qualification status

Core code

Note: Not all options are

Device number

available on all

Fab Revision ID

devices. Refer to

Revision of Silicon

Table 1.

Temperature range

Package identifier

Operating frequency (MHz)

Tape and reel status

Temperature Range

M = –40 °C to 125 °C

Package Identifier

Operating Frequency

2 = 200 MHz

3 = 264 MHz

Tape and Reel Status

R = Tape and reel

(blank) = Trays

VZ = 324 BGA Pb-free

VR = 416 BGA Pb-free

VY = 516 BGA Pb-free

VV = 516 BGA SnPb

Qualification Status

P = Pre qualification

Revision of Silicon

3 = Rev 3 (ATMC)

Fab Revision ID

F = ATMC

M = Fully spec. qualified, general market flow

S = Fully spec. qualified, automotive flow

0 = Rev 0 (TSMC14)

K = TSMC14

Figure 1. MPC5674F Orderable Part Number Description

Table 1. Orderable Part Numbers

Speed (MHz)¹

Operating Temperature²

Freescale Part Number

Package Description

Nominal

Max³(f_MAX

)

Min (T_L)

Max (T_H)

SPC5674FK0MVR3

SPC5674FK0MVY3

SPC5674FK0MVV3R

SPC5674FK0MVV3

SPC5674FK0MVY3R

SPC5674FK0MVY3

SPC5673FK0MVR2R

SPC5673FK0MVR2

SPC5673FK0MVV2R

SPC5673FK0MVV2

416 PBGA, no EBI, Pb-free

516 PBGA, w/EBI, Pb-free

516 PBGA, w/EBI, SnPb

516 PBGA, w/EBI, Pb-free

416 PBGA, no EBI, Pb-free

324 PBGA, no EBI, Pb-free

264

200

270

200

270

200

–40 °C

125 °C

For the operating mode frequency of various blocks on the device, see Table 28.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Ordering Information

The lowest ambient operating temperature is referenced by T_L; the highest ambient operating temperature is referenced by T_H.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

270 MHz parts allow for 264 MHz system clock + 2% FM.

1.2

MPC567xF Family Differences

Table 2 lists the differences between the MPC567xF devices. Refer to the MPC5674F Reference Manual for a full feature list

and comparison.

Table 2. MPC567xF Family Differences

Feature

Package

MPC5674F

416 BGA

MPC5674F

324 BGA

MPC5673F

416 BGA

MPC5673F

324 BGA

516 BGA

Flash

4 MB

256 KB

3 MB

192 KB

SRAM

256 KB

192 KB

External bus

Yes

(516 BGA only)

Serial

eSCI_A

eSCI_B

eSCI_C

SPI

Yes

DSPI_A

DSPI_B

DSPI_C

DSPI_D

eMIOS

eTPU2

eTPU_A

eTPU_B

Yes

32 channel

64 channel

Yes (32 ch)

22 channel

47 channel

Yes (26 ch)

32 channel

64 channel

Yes

22 channel

47 channel

Yes (26 ch)

Yes (21 ch, no

TCRCLK)

Yes

Yes (21 ch, no

TCRCLK)

ADC

64 channel

48 channel

Yes (24 ch)

64 channel

48 channel

Yes (24 ch)

eQADC_A

eQADC_B

Yes (64 ch)¹

There are are two pairs of 24 channels plus 16 shared channels. This gives 64 channels total: 40 per

ADC (since 16 are shared).

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

MPC5674F Blocks

2.1

Block Diagram

Figure 2 shows a top-level block diagram of the MPC5674F device.

Power™

e200z7 Core

MPC5674F

SPE2

VLE

Interrupt

Controller

Nexus

JTAG

MMU

eDMA2

64 Channel

eDMA2

32 Channel

16K

FlexRay

I-Cache D-Cache

EBI

(Calibration

Development

Use)

Crossbar Switch

MPU

4MB

Flash

I/O

Bridge

256KB SRAM Boot Assist

(32K S/B) Module

I/O

Bridge

ECSM

SIU

eQADC eQADC

ADCi ADCi

6KB

Data

RAM

eMIOS

eTPU2

Channel Channel

Channel

24KB

Code

RAM

AMux

LEGEND

eSCI

ADC

ADCi

– Analog to digital convertor

– ADC interface

– Enhanced serial communications interface

eTPU2 – Enhanced time processing unit 2

FlexCAN– Controller area network

MMU

MPU

S/B

AMux – Analog multiplexer

DECFIL – Decimation filter

DSPI

EBI

– Memory management unit

– Memory protection unit

– Stand-by

– Deserial/serial peripheral interface

– External bus interface

ECSM – Error correction status module

eDMA2 – Enhanced direct memory access

eMIOS – Enhanced modular I/O system

SIU

SPE2

– System integration unit

– Signal processing engine 2

SRAM – General-purpose static RAM

VLE – Variable length instruction encoding

eQADC – Enhanced queued A/D converter module

Figure 2. Block Diagram

Pin Assignments

The figures in this section show the primary pin function. For the full signal properties and muxing table, see Appendix A,

Signal Properties and Muxing.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

3.1

324-ball TEPBGA Pin Assignments

Figure 3 shows the 324-ball TEPBGA pin assignments. The same information is shown in Figure 4 through Figure 5.

REF–

BYPCB1

REF–

BYPCB1

VRH_A

VSS

VDD

RSTOUT ANA0

ANA1

ANA4

ANA5

ANA15 VDDA_A0

VRL_A

VDDA_ B0

VRL_B VRH_B

ANB2

ANB3

ANB6

ANB7

ANB22

VSS

REF–

BYPCB

REF–

BYPCA

VDDEH1

VSS

VDD

TEST

VDD

ANA2

ANA8

VDD

ANA3

ANA10

ANA11

ANA6

ANA9

ANA7

VDDA_ B1 VSSA_ B0

ANB1

ANB4

ANB5

ANB19 ANB23

VSS TCRCLKC

VDDA_A0 VSSA_A1

ANB0

ETPUA21 ETPUA26 VSS

ANA13 ANA17 ANA19 ANA21 ANA23 ANB10

ANB9

ANB11

ANB12 ANB14 ANB16 ANB20

VSS

ETPUC0

VDDEH7

ETPUA23 ETPUA25 ETPUA31 VSS

ETPUA20 ETPUA22 ETPUA24 ETPUA30

ETPUA13 ETPUA14 ETPUA15 ETPUA27

ETPUA10 ETPUA11 ETPUA12 ETPUA17

ETPUA5 ETPUA6 ETPUA9 ETPUA16

ETPUA1 ETPUA2 ETPUA3 ETPUA4

ANA12 ANA14 ANA16 ANA18 ANA20 ANA22

ANB8

ANB13 ANB15 ANB17 ANB18 ANB21

VSS

ETPUC3 ETPUC2

ETPUC1

ETPUC10 ETPUC11 ETPUC4

ETPUC5

ETPUC12 ETPUC14 ETPUC13 ETPUC9

ETPUC20 ETPUC18 ETPUC19 ETPUC17

MPC5674F 324 TEPBGA

(as viewed from top through the package)

ETPUC23 ETPUC22 ETPUC21

VDDEH7

VSS

ETPUC27 ETPUC28 ETPUC26ETPUC24

ETPUC31ETPUC30ETPUC29ETPUC25

ETPUB12 ETPUB13 ETPUB14 VDDEH7

ETPUB7 ETPUB10 ETPUB11 ETPUB9

ETPUB0 VDDEH6 ETPUB8 ETPUB6

TCRCLKB ETPUB16 ETPUB5 ETPUB4

ETPUB1 ETPUB17 ETPUB3 ETPUB2

ETPUB19 ETPUB18 VDDEH6 REGCTL

ETPUB31 ETPUB30 VDDREG VSSSYN

TCRCLKA

VDD

VSTBY

ETPUA0

BOOT-

CFG1

PLLCFG1 PLLCFG2 VDDEH1

VSS

JCOMP RESET PLLCFG0 RDY

VDDE2

VDDE2 MCKO MSEO1

EVTI

MDO1

MDO5

VDDE2

VDDE2 VDDE2

EVTO

MDO2

MDO6

MSEO0 MDO0

MDO3

MDO7

MDO4

MDO8

MDO9 MDO10 MDO11 MDO15

MDO12 VDDE2 MDO14 VDD33_2

VDD

VSS

REGSEL VSSFL

EXTAL

TDO

TCK

MDO13

TDI

TMS

VSS

VDD

VSS

VDD

VDDE2 PCSB2 VDDEH4

FR_B_

VDD

EMIOS8 EMIOS9 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNTXC CNRXC CNRXB

VDD VDD33_3 XTAL

FR_A_

SCKA

SCKB

PCSB0 EMIOS2 EMIOS5 EMIOS14 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNRXD

EMIOS0 EMIOS3 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS28 EMIOS29 CNRXA SCKC

VSS

VDD VDDSYN

FR_A_

FR_B_

AA ENGCLK

VSS

PCSA5

SINA

SINB

SINC

VSS

VDD

FR_B_

TX_EN

FR_A_

TX_EN

VSS

VDD

PCSA0 SOUTA SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 CNTXA SOUTC PCSC0 VDDEH4 CNTXD

VSS

VDDE2

Figure 3. MPC5674F 324-ball TEPBGA (full diagram)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

VRH_A

VSS

VDD

RSTOUT ANA0

ANA1

ANA4

ANA5

ANA15 VDDA_A0

VRL_A

REF–

BYPCA

VDDEH1

VSS

VDD

TEST

VDD

ANA2

ANA8

VDD

ANA3

ANA10

ANA11

ANA6

ANA9

ANA7

VDDA_A0 VSSA_A1

ETPUA21 ETPUA26 VSS

ANA13 ANA17 ANA19 ANA21

ETPUA23 ETPUA25 ETPUA31 VSS

ETPUA20 ETPUA22 ETPUA24 ETPUA30

ETPUA13 ETPUA14 ETPUA15 ETPUA27

ETPUA10 ETPUA11 ETPUA12 ETPUA17

ETPUA5 ETPUA6 ETPUA9 ETPUA16

ETPUA1 ETPUA2 ETPUA3 ETPUA4

ANA12 ANA14 ANA16 ANA18 ANA20

MPC5674F 324 TEPBGA

(as viewed from top through the package)

VSS

TCRCLKA

VDD

VSTBY

VSS

ETPUA0

BOOT-

CFG1

PLLCFG1 PLLCFG2 VDDEH1

VSS

JCOMP RESET PLLCFG0 RDY

VDDE2

VDDE2 MCKO MSEO1

EVTI

MDO1

MDO5

VDDE2

VDDE2 VDDE2

EVTO

MDO2

MDO6

MSEO0 MDO0

MDO3

MDO7

MDO4

MDO8

MDO9 MDO10 MDO11 MDO15

MDO12 VDDE2 MDO14 VDD33_2

TDO

TCK

MDO13

TDI

TMS

VSS

VDD

VSS

VDD

VDDE2 PCSB2 VDDEH4

FR_B_

VDD

EMIOS8 EMIOS9

FR_A_

SCKA

SCKB

PCSB0 EMIOS2 EMIOS5

FR_A_

FR_B_

AA ENGCLK

VSS

PCSA5

SINA

SINB

EMIOS0 EMIOS3 EMIOS10 AA

FR_B_

TX_EN

FR_A_

TX_EN

VSS

VDD

PCSA0 SOUTA SOUTB EMIOS1 EMIOS4 EMIOS7 AB

VDDE2

Figure 4. MPC5674F 324-ball TEPBGA (1 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

REF–

BYPCB1

REF–

BYPCB1

VDDA_ B0

VRL_B VRH_B

ANB2

ANB3

ANB6

ANB7

ANB22

VSS

REF–

BYPCB

VDDA_ B1VSSA_ B0

ANB1

ANB4

ANB5

ANB19 ANB23

VSS TCRCLKC

ANB0

ANA23 ANB10

ANB9

ANB11

ANB12 ANB14 ANB16 ANB20

VSS

ETPUC0

VDDEH7

ETPUC3 ETPUC2

ANA22

ANB8

ANB13 ANB15 ANB17 ANB18 ANB21

VSS

ETPUC1

ETPUC10 ETPUC11 ETPUC4

ETPUC5

ETPUC12 ETPUC14 ETPUC13 ETPUC9

ETPUC20 ETPUC18 ETPUC19 ETPUC17

MPC5674F 324 TEPBGA

(as viewed from top through the package)

ETPUC23 ETPUC22 ETPUC21

VDDEH7

ETPUC27

VSS

ETPUC26ETPUC24

ETPUC28

ETPUC31ETPUC30ETPUC29ETPUC25

ETPUB12 ETPUB13 ETPUB14 VDDEH7

ETPUB7 ETPUB10 ETPUB11 ETPUB9

ETPUB0 VDDEH6 ETPUB8 ETPUB6

TCRCLKB ETPUB16 ETPUB5 ETPUB4

ETPUB1 ETPUB17 ETPUB3 ETPUB2

ETPUB19 ETPUB18 VDDEH6 REGCTL

ETPUB31 ETPUB30 VDDREG VSSSYN

VDD

VSS

REGSEL VSSFL

EXTAL

EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNTXC CNRXC CNRXB

VDD VDD33_3 XTAL

EMIOS14 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB CNRXD

SCKC

VSS

VDD VDDSYN

AA EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS28 EMIOS29 CNRXA

SINC

VSS

VDD

AB EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 CNTXA SOUTC PCSC0 VDDEH4 CNTXD

VSS

Figure 5. MPC5674F 324-ball TEPBGA (2 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

3.2

416-ball TEPBGA Pin Assignments

Figure 6 shows the 416-ball TEPBGA pin assignments in one figure. The same information is shown in Figure 7 through

Figure 10.

REF–

ANA4

ANA8

ANA11

ANA15 VDDA_A0

VRL_A VRH_A

AN28

AN32

AN36 VDDA_B0

AN33 VDDA_B1

VRL_B VRH_B

ANB7

ANB11

ANB14 ANB17 ANB21 ANB23

VSS

VDD

RSTOUT ANA0

BYPCA1

BYPCB1

REF–

AN24

REF–

ANB6

ANA14 VDDA_A1 VSSA_A1

AN27

AN26

AN25

AN29

AN30

AN31

ANB8

ANB5

ANB9

ANB10 ANB15 ANB18 ANB22

VSS

TCRCLKC

VDDEH1

VSS

VDD

TEST

VDD

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

ANA10

ANA9

ANA7

VSSA_B0

AN38

BYPCA

BYPCB

ANA13 ANA17 ANA19 ANA21 ANA23

ANA12 ANA16 ANA18 ANA20 ANA22

AN34

AN35

AN37

AN39

ANB0

ANB2

ANB4

ANB3

ANB12 ANB16 ANB19

VSS

ETPUC0 ETPUC1

ETPUC2 ETPUC3

ETPUA30 ETPUA31 VSS

ANB1

ANB13 ANB20

VSS

VDDEH7

ETPUA27 ETPUA28 ETPUA29 VSS

ETPUA23 ETPUA24 ETPUA25 ETPUA26

ETPUA19 ETPUA20 ETPUA21 ETPUA22

ETPUA15 ETPUA16 ETPUA17 ETPUA18

ETPUA11 ETPUA12 ETPUA14 ETPUA13

ETPUA7 ETPUA8 ETPUA9 ETPUA10

ETPUA3 ETPUA4 ETPUA5 ETPUA6

TCRCLKA ETPUA0 ETPUA1 ETPUA2

VDDEH7 ETPUC4 ETPUC5 ETPUC6

ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14

ETPUC15 ETPUC16 ETPUC17 ETPUC18

ETPUC19 ETPUC20 ETPUC21ETPUC22

ETPUC23 ETPUC24ETPUC25ETPUC26

ETPUC27ETPUC28ETPUC29ETPUC30

ETPUC31ETPUB15 ETPUB14 VDDEH7

VDDEH6 ETPUB11 ETPUB12 ETPUB13

ETPUB7 ETPUB8 ETPUB9 ETPUB10

ETPUB3 ETPUB4 ETPUB5 ETPUB6

TCRCLKB ETPUB0 ETPUB1 ETPUB2

ETPUB19 ETPUB18 ETPUB17 ETPUB16

ETPUB26 ETPUB22 ETPUB21 ETPUB20

REGSEL ETPUB25 ETPUB24 ETPUB23

ETPUB29 ETPUB28 ETPUB27 REGCTL

VDD33_3 ETPUB30 VDDREG VSSSYN

MPC5674F 416-ball TEPBGA

(as viewed from top through the package)

VSS

VDD33_1 TXDA

BOOT–

RXDA

VSTBY

VSS

VDDE2

RXDB

CFG1

WKPCFG VDD

VDDE2 VDDE2

TXDB

PLLCFG2 VDDEH1

PLLCFG1

JCOMP RESET PLLCFG0 RDY

VDDE2 MCKO MSEO1

EVTO MSEO0 MDO0

EVTI

MDO1

MDO5

VDDE2 VDDE2 VDDE2

MDO2

MDO6

MDO3

MDO7

MDO4

MDO8 VDDE2

MDO9 MDO10 MDO11 MDO15

MDO12 MDO13 MDO14 VDD33_2

VSSFL

TDO

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDD ETPUB31

EXTAL

PCSA1 PCSA2 PCSB4 PCSB1 VDDEH3 VDDEH4

VDD

EMIOS8 EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1

VSS

VDD

VSS

VDDEH6 XTAL

VDD VDDSYN

AC VDDE2

VDDE2

FR_A_ FR_B_

TX TX

EMIOS5 EMIOS9 EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30

RXDC

SINC

PCSC3

AD ENGCLK VDD

PCSA5 SOUTA

SCKA

SCKB

PCSB0 PCSB3 EMIOS2

CNTXB CNTXD

SCKC

FR_A_ FR_B_

RX RX

PCSA4 PCSA0 PCSA3

SINB

EMIOS0 EMIOS3 EMIOS6 EMIOS10 EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0

PCSC2 PCSC5

VSS

VDD

VSS

FR_A_ FR_B_

TX_EN TX_EN

EMIOS7 EMIOS11 EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28

VDDEH4 TXDC

PCSC4 VDDEH5

VSS

VDDE2

VDDEH3 PCSB5

SINA

PCSB2 SOUTB EMIOS1 EMIOS4

10 11

CNTXA CNTXC SOUTC

19 20 21

Figure 6. MPC5674F 416-ball TEPBGA (full diagram)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

REFBYP-

CA1

VSS

VDD

VSS

RSTOUT

ANA0

ANA4

ANA8

ANA11

ANA15 VDDA_A0

VRL_A

VRH_A

AN28

VDDEH1

VDD

VSS

TEST

VDD

VSS

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

ANA10

ANA9

ANA7

ANA14 VDDA_A1 VSSA_A1 REFBYPCA AN24

AN27

AN26

AN25

ETPUA30 ETPUA31

ANA13

ANA12

ANA17

ANA16

ANA19

ANA18

ANA21

ANA20

ANA23

ANA22

ETPUA27 ETPUA28 ETPUA29

ETPUA23 ETPUA24 ETPUA25 ETPUA26

ETPUA19 ETPUA20 ETPUA21 ETPUA22

ETPUA15 ETPUA16 ETPUA17 ETPUA18

ETPUA11 ETPUA12 ETPUA14 ETPUA13

ETPUA7 ETPUA8 ETPUA9 ETPUA10

ETPUA3 ETPUA4 ETPUA5 ETPUA6

TCRCLKA ETPUA0 ETPUA1 ETPUA2

MPC5674F 416-ball TEPBGA

(as viewed from top through the package)

(1 of 4)

VSS

VDD33_1 TXDA

RXDA

VSTBY

RXDB BOOTCFG1 WKPCFG

VDD

VDDE2

VSS

Figure 7. MPC5674F 416-ball TEPBGA (1 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

REFBYP-

CB1

AN32

AN36 VDDA_B0

VRL_B

VRH_B

ANB7

ANB11

ANB14

ANB17

ANB21

ANB23

VSS

AN29

AN30

AN31

AN33 VDDA_B1 VSSA_B0 REFBYPCB ANB6

ANB8

ANB5

ANB9

ANB10

ANB12

ANB13

ANB15

ANB16

ANB20

ANB18

ANB19

VSS

ANB22

VSS

TCRCLKC

AN34

AN35

AN37

AN39

AN38

ANB1

ANB0

ANB2

ANB4

ANB3

ETPUC0 ETPUC1

VDDEH7 ETPUC2 ETPUC3

VDDEH7 ETPUC4 ETPUC5 ETPUC6

ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14

ETPUC15 ETPUC16 ETPUC17 ETPUC18

ETPUC19 ETPUC20 ETPUC21 ETPUC22

ETPUC23 ETPUC24 ETPUC25 ETPUC26

ETPUC27 ETPUC28 ETPUC29 ETPUC30

ETPUC31 ETPUB15 ETPUB14 VDDEH7

VDDEH6 ETPUB11 ETPUB12 ETPUB13

MPC5674F 416-ball TEPBGA

(as viewed from top through the package)

(2 of 4)

VSS

Figure 8. MPC5674F 416-ball TEPBGA (2 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

TXDB

JCOMP

VDDE2

EVTO

PLLCFG1 PLLCFG2 VDDEH1

VDDE2

VSS

RESET PLLCFG0

RDY

EVTI

VDDE2

VSS

MCKO

MSEO0

MDO3

MDO7

MSEO1

MDO0

MDO4

MDO8

VDDE2

MDO1

MDO5

VDDE2

MDO15

VDDE2

VSS

MDO2

MDO6

MDO9

MPC5674F 416-ball TEPBGA

(as viewed from top through the package)

(3 of 4)

MDO10 MDO11

AA MDO12 MDO13 MDO14 VDD33_2

TDO

VDDE2

ENGCLK

VDD

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDDE2

PCSA1

PCSA2

SOUTA

PCSA3

PCSB4

SCKA

SCKB

PCSB1 VDDEH3 VDDEH4

VDD

EMIOS8

VDD

VSS

FR_A_TX FR_B_TX PCSA5

PCSB0

PCSB3 EMIOS2 EMIOS5 EMIOS9

FR_A_RX FR_B_RX PCSA4

PCSA0

SINB

EMIOS0 EMIOS3 EMIOS6 EMIOS10 AE

FR_A_

TX_EN

FR_B_

TX_EN

VSS

VDDE2

VDDEH3 PCSB5

SINA

PCSB2

SOUTB EMIOS1 EMIOS4 EMIOS7 EMIOS11

Figure 9. MPC5674F 416-ball TEPBGA (3 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

VSS

ETPUB7 ETPUB8 ETPUB9 ETPUB10

ETPUB3 ETPUB4 ETPUB5 ETPUB6

TCRCLKB ETPUB0 ETPUB1 ETPUB2

ETPUB19 ETPUB18 ETPUB17 ETPUB16

ETPUB26 ETPUB22 ETPUB21 ETPUB20

REGSEL ETPUB25 ETPUB24 ETPUB23

ETPUB29 ETPUB28 ETPUB27 REGCTL

VDD33_3 ETPUB30 VDDREG VSSSYN

VSS

MPC5674F 416-ball TEPBGA

(as viewed from top through the package)

(4 of 4)

VDD

VSS

ETPUB31 VSSFL

EXTAL

XTAL

EMIOS14 EMIOS18 EMIOS22 EMIOS27 EMIOS31 CNRXB CNRXD VDDEH5 PCSC1

VDD

VSS

VDDEH6

VDD

EMIOS15 EMIOS19 EMIOS23 EMIOS26 EMIOS30 CNTXB

CNTXD

SCKC

RXDC

SINC

PCSC3

PCSC2

VDDSYN

VDD

AE EMIOS13 EMIOS17 EMIOS21 EMIOS25 EMIOS29 CNRXA CNRXC PCSC0

PCSC5

VSS

EMIOS12 EMIOS16 EMIOS20 EMIOS24 EMIOS28 CNTXA

CNTXC SOUTC VDDEH4

TXDC

PCSC4 VDDEH5

VSS

Figure 10. MPC5674F 416-ball TEPBGA (4 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

3.3

516-ball TEPBGA Pin Assignments

Figure 11 shows the 516-ball TEPBGA pin assignments in one figure. The same information is shown split into four quadrants

in Figure 12 through Figure 15.

REF–

VDD

RSTOUT ANA0

ANA4

ANA9

ANA11

ANA15 VDDA_A0

VRL_A VRH_A

AN28

AN29

AN36 VDDA_B0

VRL_B VRH_B

ANB5

ANB9

ANB12 ANB18 ANB21

VSS

BYPCA1

BYPCB1

REF–

AN24

REF–

ANB4

VDDEH1

VSS

VDD

TEST

VDD

ANA1

ANA2

VDD

ANA5

ANA6

ANA3

VDD

ANA10 ANA14 VDDA_A1 VSSA_A1

AN27

AN25

AN26

VSS

AN30

AN31

AN33

VSS

AN32 VDDA_B1 VSSA_B0

ANB8

ANB6

ANB10 ANB13 ANB19 ANB22

VSS

BYPCA

BYPCB

ETPUA30 ETPUA31 VSS

ANA7

ANA8

VSS

ANA13 ANA17 ANA19 ANA21 ANA22

ANA12 ANA16 ANA18 ANA20 ANA23

AN34

AN35

VSS

AN39

AN38

VSS

AN37

ANB1

VSS

ANB0

ANB2

VSS

ANB7

ANB3

ANB11

ANB15 ANB20

VSS

ETPUC0 ETPUC1

ETPUA27 ETPUA28 ETPUA29 VSS

ANB14 ANB16 ANB17

VSS

VDDEH7 ETPUC2 ETPUC3

ETPUA23 ETPUA24 ETPUA25 ETPUA26 VSS

ETPUA19 ETPUA20 ETPUA21 ETPUA22 VSS

ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18

VSS

ANB23

VSS

VDDEH7 ETPUC4 ETPUC5 ETPUC6

VDDE8

VDDE8 VDDE8

VSS

VDDE10 VDDE10

VDDE10

VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15

MPC5674F 516-ball TEPBGA

ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16

ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12

ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21

ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27

(as viewed from top through the package)

TXDB

TXDA

RXDA TCRCLKA ETPUA6 ETPUA10

VSS

ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15

VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10

D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7

BOOT– BOOT–

RXDB ETPUA0

PLLCFG1 PLLCFG2

CFG1

CFG0

VSS

VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG

D_WE0 D_WE2 D_WE3

VDD

RESET VDDE8

VDDE2

VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4

D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1

D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16

VDDE2 VDDE2

VDDE10 ETPUB13 D_OE

D_ALE D_DAT0 D_DAT1

D_RD_

ETPUB9 ETPUB12 ETPUB14 ETPUB15

VDDE2

D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3

VDDE2

VDDE2 VDDE2

ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11

ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6

ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0

D_CS2 JCOMP

RDY

MCKO MSEO1 MSEO0

VDDE2 VDDE2 VDDE2

EVTI

MDO4

MDO7

EVTO

MDO5

MDO0

MDO2

MDO3

MDO6 VDDE2 MDO8

MDO1

VSS

ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18

ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL

MDO9 MDO10 MDO11 MDO12

AA MDO13 MDO14 MDO15 VDD33_1 VDDE8

PCSA5

SCKA

SCKB

SOUTB VDD33_4

VDDE9 VDD33_4

EMIOS23 EMIOS31

CNRXB

VSS

VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA

TDO

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDDE9 VDDE9

SINB

D_CS1 D_ADD21 D_ADD29 EMIOS1 EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9 VDDE9 VDDE9 VDDE9

VSS

VDD ETPUB30 VSSFL

EXTAL AB

EMIOS0 EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1

VSS

VDD

VSS

VDDEH6 XTAL

AC VDDE2

VDDE2 PCSA1 SOUTA

PCSB3 VDDEH3 VDDEH4

VDD

FR_A_ FR_B_

TX TX

AD ENGCLK VDD

PCSA0 PCSA3 PCSB2 D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD

SCKC

RXDC

SINC

PCSC3

VDD VDDSYN AD

FR_A_ FR_B_

RX RX

VDD

VSS

PCSA4 PCSB5

SINA

PCSB1

D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0

PCSC2 PCSC5

VSS

VDD

CLKOUT

FR_A_ FR_B_

TX_EN TX_EN

VDDE2

VDDEH3 PCSA2 PCSB4 PCSB0

D_TA D_ADD24 D_ADD27

EMIOS4 EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4 TXDC

PCSC4 VDDEH5

Figure 11. MPC5674F 516-ball TEPBGA (full diagram)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

REF-

BYPCA1

VDD

RSTOUT

ANA0

ANA4

ANA9

ANA11

ANA15 VDDA_A0

VRL_A

VRH_A

AN28

VDDEH1

VSS

VDD

VSS

TEST

VDD

VSS

ANA1

ANA2

VDD

VSS

ANA5

ANA6

ANA3

VDD

ANA10

ANA7

ANA8

VSS

ANA14 VDDA_A1 VSSA_A1 REFBYPCA AN24

AN27

AN25

AN26

VSS

ETPUA30 ETPUA31

ANA13

ANA12

VSS

ANA17

ANA16

VSS

ANA19

ANA18

VSS

ANA21

ANA20

VSS

ANA22

ANA23

VSS

ETPUA27 ETPUA28 ETPUA29

ETPUA23 ETPUA24 ETPUA25 ETPUA26

ETPUA19 ETPUA20 ETPUA21 ETPUA22

VSS

VDDE8

VSS

MPC5674F 516-ball TEPBGA

(as viewed from top through the package)

(1 of 4)

ETPUA11 ETPUA13 ETPUA15 ETPUA17 ETPUA18

ETPUA5 ETPUA7 ETPUA8 ETPUA3 ETPUA14 ETPUA16

ETPUA1 ETPUA2 ETPUA9 ETPUA4 ETPUA12

TXDB

TXDA

RXDA TCRCLKA ETPUA6 ETPUA10

VSS

PLLCFG1 PLLCFG2 BOOTCFG1 BOOTCFG0 RXDB

VDD33_1 D_BDIP PLLCFG0 VSTBY WKPCFG

ETPUA0

D_WE0 D_WE2 D_WE3

VDD

RESET

VDDE8

VDDE2

VSS

Figure 12. MPC5674F 516-ball TEPBGA (1 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

REF-

BYPCB1

AN29

AN36

AN32

AN34

AN35

VSS

VDDA_B0

VRL_B

VRH_B

ANB5

ANB9

ANB12

ANB18

ANB21

VSS

AN30

AN31

AN33

VSS

VDDA_B1 VSSA_B0 REFBYPCB ANB4

ANB8

ANB6

ANB10

ANB11

ANB16

VSS

ANB13

ANB15

ANB17

VSS

ANB19

ANB20

VSS

ANB22

VSS

AN39

AN38

VSS

AN37

ANB1

VSS

ANB0

ANB2

VSS

ANB7

ANB3

ETPUC0 ETPUC1

ANB14

ANB23

VDDEH7 ETPUC2 ETPUC3

VSS

VDDEH7 ETPUC4 ETPUC5 ETPUC6

VSS

VDDE10 VDDE10

VDDE10

VDDE10 TCRCLKC ETPUC7 ETPUC8 ETPUC9 ETPUC10

ETPUC11 ETPUC12 ETPUC13 ETPUC14 ETPUC15

MPC5674F 516-ball TEPBGA

(as viewed from top through the package)

(2 of 4)

ETPUC19 ETPUC16 ETPUC17 ETPUC18 ETPUC20 ETPUC21

ETPUC22 ETPUC23 ETPUC24 ETPUC26 ETPUC27

VSS

ETPUC25 ETPUC28 ETPUC29 ETPUC30 ETPUC31 D_DAT15

VDD33_6 D_DAT14 D_DAT13 D_DAT12 D_DAT11 D_DAT10

D_DAT9 D_DAT8 D_DAT7 D_DAT5 VDDEH7

VSS

VDDE10 D_DAT6 VDDEH6 D_DAT2 D_DAT3 D_DAT4

Figure 13. MPC5674F 516-ball TEPBGA (2 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

D_ADD9 D_ADD10 D_ADD11 VDDEH1 D_WE1 VDD33_1

D_ADD12 D_ADD13 D_ADD14 D_ADD15 D_ADD16

VDDE2

VSS

VDDE2

VSS

VDDE2 D_ADD18 D_ADD19 D_ADD20 D_ADD17 D_CS3

VDDE2

D_CS2

EVTI

JCOMP

EVTO

RDY

MDO0

MDO6

MCKO

MDO2

VDDE2

MSEO1 MSEO0

MDO3

MPC5674F 516-ball TEPBGA

(as viewed from top through the package)

(3 of 4)

MDO4

MDO7

MDO5

MDO9

MDO8

MDO1

MDO10 MDO11

MDO12

AA MDO13 MDO14 MDO15 VDD33_1 VDDE8

VSS

PCSA5

SCKA

SOUTB VDD33_4

VDDE9 AA

TDO

TCK

TDI

TMS

VDD

VSS

VDD

VSS

VDDE9

PCSA1

SINB

D_CS1

D_ADD29 EMIOS1 AB

D_ADD21

VDDE9

SOUTA

AC VDDE2

AD ENGCLK

VDDE2

SCKB

PCSB3 VDDEH3 VDDEH4

VDD

EMIOS0 AC

VDD

VSS

FR_A_TX FR_B_TX PCSA0

PCSA3

SINA

PCSB2

PCSB1

D_CS0 D_ADD22 D_ADD25 D_ADD28 EMIOS2 AD

D_TS D_ADD23 D_ADD26 D_ADD30 EMIOS3 AE

D_TA D_ADD24 D_ADD27 D_CLKOUT EMIOS4 AF

VDD

FR_A_RX FR_B_RX PCSA4

PCSB5

FR_A_

TX_EN

FR_B_

TX_EN

VDDE2

VDDEH3 PCSA2

PCSB4

PCSB0

Figure 14. MPC5674F 516-ball TEPBGA (3 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

VSS

VDDE10 ETPUB13 D_OE

D_ALE

D_DAT0 D_DAT1

VSS

ETPUB9 ETPUB12 ETPUB14 ETPUB15 D_RD_WR

ETPUB17 ETPUB3 ETPUB7 ETPUB8 ETPUB10 ETPUB11

ETPUB23 ETPUB1 ETPUB2 ETPUB4 ETPUB5 ETPUB6

ETPUB21 ETPUB22 ETPUB16 TCRCLKB ETPUB0

MPC5674F 516-ball TEPBGA

(as viewed from top through the package)

(4 of 4)

ETPUB25 ETPUB29 REGSEL ETPUB20 ETPUB19 ETPUB18

ETPUB31 ETPUB26 ETPUB27 ETPUB24 REGCTL

AA VDD33_4

EMIOS23 EMIOS31

CNRXB

VDDE9

VSS

VDDE10 VDD33_3 ETPUB28 VDDREG VSSSYN AA

AB EMIOS11 EMIOS17 EMIOS19 EMIOS29 VDDE9

VDDE9

VSS

VDD

VSS

ETPUB30 VSSSFL EXTAL

EMIOS8 EMIOS13 EMIOS22 EMIOS24 EMIOS28 CNTXB CNRXD VDDEH5 PCSC1

VDD

VSS

VDDEH6

VDD

XTAL

EMIOS7 EMIOS12 EMIOS16 EMIOS18 EMIOS27 CNRXA CNTXD

SCKC

RXDC

SINC

PCSC3

PCSC2

VDDSYN AD

EMIOS6 EMIOS10 EMIOS15 EMIOS21 EMIOS26 CNTXA CNRXC PCSC0

PCSC5

VSS

VDD

EMIOS5 EMIOS9 EMIOS20 EMIOS14 EMIOS25 EMIOS30 CNTXC SOUTC VDDEH4

TXDC

PCSC4 VDDEH5

Figure 15. MPC5674F 516-ball TEPBGA (4 of 4)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Pin Assignments

3.4

Signal Properties and Muxing

See Appendix A, Signal Properties and Muxing, for a listing and description of the pin functions and properties.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications for the MPC5674F.

The electrical specifications are preliminary and are from previous designs, design simulations, or initial evaluation. These

specifications may not be fully tested or guaranteed at this stage of the product life cycle, however for production silicon these

specifications will be met. Finalized specifications will be published after complete characterization and device qualifications

have been completed.

4.1

Maximum Ratings

Table 3. Absolute Maximum Ratings

Spec

Characteristic

1.2 V Core Supply Voltage

Symbol

Min

Max

Unit

V_DD

V_STBY

V_DDSYN

V_DD33

–0.3

–0.1

–0.3

–0.1

–3 ¹¹

2.0 ²

3,4

SRAM Standby Voltage

6.4

Clock Synthesizer Voltage

5.3 ^4,5

6.4 ^3,4

5.3 ^4,5

6.4 ^3,4

0.1

I/O Supply Voltage (I/O buffers and predrivers)

Analog Supply Voltage (reference to V_SSA

)

V_DDA

I/O Supply Voltage (fast I/O pads)

V_DDE

V_DDEH

V_DDREG

I/O Supply Voltage (medium I/O pads)

Voltage Regulator Input Supply Voltage

Analog Reference High Voltage (reference to V_RL

V_SSto V_SSA⁸Differential Voltage

)

V_RH

V_SS– V_SSA

V_RH– V_RL

_REFDifferential Voltage

6.4 ^3,4

0.3

V_RLto V_SSADifferential Voltage

V_RL– V_SSA

V_DD33– V_DDSYN

V_SSSYN– V_SS

I_MAXD

V_DD33to V_DDSYNDifferential Voltage

_SSSYNto V_SSDifferential Voltage

0.1

Maximum Digital Input Current ¹⁰(per pin, applies to all

digital pins)

3 ¹¹

Maximum Analog Input Current ¹²(per pin, applies to all

analog pins)

I_MAXA

– 3 ⁷

–40.0

–55.0

3 ^7,11

150.0

^oC

Maximum Operating Temperature Range ¹³– Die Junction

Temperature

T_J

Storage Temperature Range

T_stg

T_sdr

^oC

Maximum Solder Temperature ¹⁴

Pb-free package

—

260.0

245.0

SnPb package

Moisture Sensitivity Level ¹⁵

MSL

—

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings only,

and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device reliability or

cause permanent damage to the device.

2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.

6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.

Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.

MPC5674F has two analog power supply pins on the pinout: VDDA_A and VDDA_B.

MPC5674F has two analog ground supply pins on the pinout: VSSA_A and VSSA_B.

MPC5674F has two analog low reference voltage pins on the pinout: VRL_A and VRL_B.

MPC5674F has two analog high reference voltage pins on the pinout: VRH_A and VRH_B.

¹⁰Total injection current for all pins must not exceed 25 mA at maximum operating voltage.

¹¹Injection current of ±5 mA allowed for limited duration for analog (ADC) pads and digital 5 V pads. The maximum accumulated

time at this current shall be 60 hours. This includes an assumption of a 5.25 V maximum analog or V_DDEHsupply when under

this stress condition.

¹²Total injection current for all analog input pins must not exceed 15 mA.

¹³Lifetime operation at these specification limits is not guaranteed.

¹⁴Solder profile per CDF-AEC-Q100.

¹⁵Moisture sensitivity per JEDEC test method A112.

4.2

Thermal Characteristics

Table 4. Thermal Characteristics, 416-pin TEPBGA Package

Characteristic

Symbol

Value

Unit

Junction to Ambient ^2,3Natural Convection (Single layer board)

Junction to Ambient ^2,4Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁵

R_θJA

R_θJMA

R_θJB

R_θJC

Ψ_JT

°C/W

Junction to Case ⁶

Junction to Package Top ⁷Natural Convection

Thermal characteristics are targets based on simulation that are subject to change per device

characterization. This data is PRELIMINARY based on similar package used on other devices.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the

board, and board thermal resistance.

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case

temperature.

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 5. Thermal Characteristics, 516-pin TEPBGA Package

Characteristic

Symbol

Value

Unit

Junction to Ambient ^2,3Natural Convection (Single layer board)

Junction to Ambient ^2,4Natural Convection (Four layer board 2s2p)

Junction to Ambient (@200 ft./min., Single layer board)

Junction to Ambient (@200 ft./min., Four layer board 2s2p)

Junction to Board ⁵

R_θJA

R_θJMA

R_θJB

R_θJC

Ψ_JT

°C/W

Junction to Case ⁶

Junction to Package Top ⁷Natural Convection

Thermal characteristics are targets based on simulation that are subject to change per device

characterization. This data is PRELIMINARY based on similar package used on other devices.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the

board, and board thermal resistance.

Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case

temperature.

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

Table 6. Thermal Characteristics, 324-pin Package

MPC5674F Thermal Characteristic

Symbol

Value

Unit

Junction to ambient ^{2, 3}, natural convection (one-layer board)

Junction to ambient ^{1, 4}, natural convection (four-layer board 2s2p)

Junction to ambient (@200 ft./min., one-layer board)

Junction to ambient (@200 ft./min., four-layer board 2s2p)

Junction to board ⁵(four-layer board 2s2p)

R_θJA

R_θJMA

R_θJB

R_θJC

Ψ_JT

°C/W

Junction to case ⁶

Junction to package top ⁷, natural convection

Thermal characteristics are targets based on simulation that are subject to change per device

characterization. This data is PRELIMINARY based on similar package used on other devices.

Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting

site (board) temperature, ambient temperature, air flow, power dissipation of other components on the

board, and board thermal resistance.

Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board

temperature is measured on the top surface of the board near the package.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Indicates the average thermal resistance between the die and the case top surface as measured by the

cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case

temperature.

Thermal characterization parameter indicating the temperature difference between package top and the

junction temperature per JEDEC JESD51-2.

4.2.1

General Notes for Specifications at Maximum Junction Temperature

An estimation of the chip junction temperature, T , can be obtained from the equation:

T = T + (R

* P )

Eqn. 1

θJA

where:

T = ambient temperature for the package ( C)

= junction to ambient thermal resistance ( C/W)

θJA

P = power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal

performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value

obtained on a board with two planes. For packages such as the TEPBGA, these values can be different by a factor of two. Which

value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a

single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal

planes is usually appropriate if the board has low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed as the sum of a junction to case thermal resistance and a case to

ambient thermal resistance:

= R

+ R

θCA

Eqn. 2

θJA

θJC

where:

= junction to ambient thermal resistance ( C/W)

θJA

θJC

θCA

= junction to case thermal resistance ( C/W)

= case to ambient thermal resistance ( C/W)

is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to

θJC

ambient thermal resistance, R

. For instance, the user can change the size of the heat sink, the air flow around the device, the

θCA

interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit

board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal

Characterization Parameter (Ψ ) can be used to determine the junction temperature with a measurement of the temperature at

the top center of the package case using the following equation:

T = T + (Ψ x P )

Eqn. 3

where:

T = thermocouple temperature on top of the package ( C)

= thermal characterization parameter ( C/W)

P = power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied

to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm. of wire extending from the

junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects

of the thermocouple wire.

References:

Semiconductor Equipment and Materials International

3081 Zanker Road

San Jose, CA 95134

(408) 943-6900

MIL-SPEC and EIA/JESD (JEDEC) specifications are available from Global Engineering Documents at 800-854-7179 or

303-397-7956.

JEDEC specifications are available on the WEB at http://www.jedec.org.

•

C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an Automotive Engine

Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47-54.

G. Kromann, S. Shidore, and S. Addison, “Thermal Modeling of a PBGA for Air-Cooled Applications,” Electronic

Packaging and Production, pp. 53-58, March 1998.

B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance and Its Application

in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp. 212-220.

4.3

EMI (Electromagnetic Interference) Characteristics

To find application notes that provide guidance on designing your system to minimize interference from radiated emissions, go

to www.freescale.com and perform a keyword search for “radiated emissions.” The following tables list the values of the

device's radiated emissions operating behaviors.

Table 7. EMC Radiated Emissions Operating Behaviors: 416 BGA

f_OSC

f_SYS

Frequency

band (MHz)

Level

(max.)

Symbol

Description

Conditions

Unit Notes

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

416 BGA

EBI off

40 MHz crystal

264 MHz

(f_{EBI_CAL}= 66

MHz)

0.15–50

50–150

I²

dBμV

150–500

500–1000

1, 3

CLK on

FM off

IEC and SAE level

—

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

416 BGA

EBI off

40 MHz crystal

264 MHz

(f_{EBI_CAL}= 66

MHz)

0.15–50

50–150

K⁵

dBμV

150–500

500–1000

1,3

CLK off

IEC and SAE level

—

FM on⁴

Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell

Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM

(GTEM) Cell Method.

I = 36 dBμV

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated

Circuits—TEM/Wideband TEM (GTEM) Cell Method.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

“FM on” = FM depth of ±2%

K = 30 dBμV

Table 8. EMC Radiated Emissions Operating Behaviors: 516 BGA

f_OSC

f_SYS

Frequency

band (MHz)

Level

(max.)

Symbol

V_{RE_TEM}

Description

Conditions

Unit Notes

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

40 MHz crystal

264 MHz

(f_{EBI_CAL}= 66

MHz)

0.15–50

50–150

G²

dBμV

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

516 BGA

EBI on

150–500

500–1000

1, 3

CLK on

FM off

IEC and SAE level

—

V_{RE_TEM}

Radiated emissions,

electric field and

magnetic field

V_DD= 1.2 V

V_DDE= 3.3 V

V_DDEH= 5 V

T_A= 25 °C

516 BGA

EBI on

40 MHz crystal

264 MHz

(f_{EBI_CAL}= 66

MHz)

0.15–50

50–150

G²

dBμV

150–500

500–1000

1, 3

CLK on

IEC and SAE level

—

FM on⁴

Determined according to IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband TEM Cell

Method, and SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated Circuits—TEM/Wideband TEM

(GTEM) Cell Method.

G = 48 dBμV

Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method, and Appendix D of SAE Standard J1752-3, Measurement of Radiated Emissions from Integrated

Circuits—TEM/Wideband TEM (GTEM) Cell Method.

“FM on” = FM depth of ±2%

4.4

ESD Characteristics

1,2

Table 9. ESD Ratings

Spec

Characteristic

ESD for Human Body Model (HBM)

ESD for Charged Device Model (CDM)

Symbol

Value

Unit

V_HBM

V_CDM

2000

750 (corners)

500 (other)

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade

Integrated Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the

device specification.

4.5

PMC/POR/LVI Electrical Specifications

Note: For ADC internal resource measurements, see Table 21 in Section 4.9.1, “ADC Internal Resource Measurements.”

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 10. PMC Operating conditions

Name

Parameter

Condition

Min

Typ

Max

Unit Note

V_DDREG

V_DD33

V_DD

Supply voltage VDDREG LDO5V / SMPS5V mode

5V nominal

4.5

5.5

Supply voltage VDDREG LDO3V mode

3V nominal

3.0

3.3

1.2

3.6

Supply voltage VDDSYN / LDO3V mode

V_DD333.3V nominal

Core supply voltage

—

1.14

1.32

Voltage should be higher than maximum V_LVDREGto avoid LVD event

Applies to both V_DD33(flash supply) and VDDSYN (PLL supply) pads. Voltage should be higher than maximum V_LVD33

to avoid LVD event

Voltage should be higher than maximum V_LVD12to avoid LVD event

NOTE

In the following table, "untrimmed” means “at reset" and "trimmed” means “after reset".

Table 11. PMC Electrical Specifications

Name

V_BG

Parameter

Min

Typ

Max

Unit

Nominal bandgap reference voltage

Untrimmed bandgap reference voltage

Nominal VRC regulated 1.2V output VDD

0.608

V_BG– 5%

—

0.620

V_BG

0.632

V_BG+ 5%

—

V_DD12OUT

1.27

—

Untrimmed VRC 1.2V output variation before band

gap trim (unloaded)

Note: Voltage should be higher than maximum

V_LVD12to avoid LVD event

_DD12OUT– 14% V_DD12OUTV_DD12OUT+ 10%

Trimmed VRC 1.2V output variation after band gap V_DD12OUT– 10% V_DD12OUTV_DD12OUT+ 5%

trim (REGCTL load max. 20mA, VDD load max.

1A)¹

2c V_STEPV12

Trimming step V_DD12OUT

POR rising VDD 1.2V

POR VDD 1.2V variation

POR 1.2V hysteresis

—

0.7

—

V_PORC

—

V_PORC– 30%

V_PORC

V_PORC+ 30%

—

V_LVD12

Nominal rising LVD 1.2V

1.100

Note: ~V_DD12OUT× 0.87

—

Untrimmed LVD 1.2V variation before band gap trim V_LVD12– 6%

Note: Rising VDD

V_LVD12

V_LVD12+ 6%

V_LVD12+ 3%

Trimmed LVD 1.2V variation after band gap trim

Rising VDD

V_LVD12– 3%

V_LVD12

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 11. PMC Electrical Specifications (continued)

Name

Parameter

LVD 1.2V Hysteresis

Min

Typ

Max

Unit

—

4d V_LVDSTEP12

Trimming step LVD 1.2V

I_REGCTL

—

VRC DC current output on REGCTL

Voltage regulator 1.2V current consumption

VDDREG

V_DD33OUT

—

Nominal V_REG3.3V output

—

3.3

—

Untrimmed V_REG3.3V output variation before band

gap trim (unloaded)

V_DD33OUT– 6% V_DD33OUTV_DD33OUT+ 10%

Note: Rising VDDSYN

—

Trimmed V_REG3.3V output variation after band gap V_DD33OUT– 5% V_DD33OUTV_DD33OUT+ 10%

trim (max. load 80mA)

7c V_STEPV33

Trimming step VDDSYN

—

V_LVD33

Nominal rising LVD 3.3V

2.950

Note: ~V_DD33OUT× 0.872

—

Untrimmed LVD 3.3V variation before band gap trim

Note: Rising VDDSYN

V_LVD33– 5%

V_LVD33– 3%

V_LVD33

V_LVD33+ 5%

V_LVD33+ 3%

—

Trimmed LVD 3.3V variation after bad gap trim

Note: Rising VDDSYN

V_LVD33

—

LVD 3.3V Hysteresis

—

8d V_LVDSTEP33

Trimming step LVD 3.3V

I_DD33

V_{REG =}4.5 V, max DC output current

V_REG= 4.25 V, max DC output current, crank

condition

—

Note: Max current supplied by VDDSYN that does

not cause it to drop below V_LVD33

—

Voltage regulator 3.3V current consumption

VDDREG

Note: Except I_DD33

—

11 V_PORREG

11a —

POR rising on VDDREG

POR VDDREG variation

POR VDDREG hysteresis

2.00

V_PORREG– 30% V_PORREGV_PORREG+ 30%

11b —

—

250

—

12 V_LVDREG

Nominal rising LVD VDDREG

(LDO3V / LDO5V mode)

2.950

12a —

12b —

Untrimmed LVD VDDREG variation before band

gap trim

Note: Rising VDDREG

_LVDREG– 5% V_LVDREGV_LVDREG+ 5%

Trimmed LVD VDDREG variation after band gap

V_LVDREG– 3% V_LVDREGV_LVDREG+ 3%

trim

Note: Rising VDDREG

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 11. PMC Electrical Specifications (continued)

Name

Parameter

Min

Typ

Max

Unit

12c —

LVD VDDREG Hysteresis

(LDO3V / LDO5V mode)

—

12d V_LVDSTEPREGTrimming step LVD VDDREG

(LDO3V / LDO5V mode)

—

13 V_LVDREG

Nominal rising LVD VDDREG

(SMPS5V mode)

4.360

13a —

Untrimmed LVD VDDREG variation before band

gap trim

V_LVDREG– 5% V_LVDREGV_LVDREG+ 5%

Note: Rising VDDREG

13b —

13c —

Trimmed LVD VDDREG variation after band gap

trim

Note: Rising VDDREG

_LVDREG– 3% V_LVDREGV_LVDREG+ 3%

LVD VDDREG Hysteresis

(SMPS5V mode)

—

13d V_LVDSTEPREGTrimming step LVD VDDREG

(SMPS5V mode)

14 V_LVDA

14a —

Nominal rising LVD VDDA

4.60

—

Untrimmed LVD VDDA variation before band gap

trim

V_LVDA– 5%

V_LVDA

V_LVDA+ 5%

14b —

Trimmed LVD VDDA variation after band gap trim

LVD VDDA Hysteresis

V_LVDA– 3%

V_LVDA

150

V_LVDA+ 3%

14c —

—

Ohm

14d V_LVDASTEP

Trimming step LVD VDDA

—

SMPS regulator output resistance

Note: Pulup to VDDREG when high, pulldown to

VSSREG when low.

—

SMPS regulator clock frequency (after reset)

SMPS regulator overshoot at start-up²

SMPS maximum output current

1.0

—

1.5

1.32

1.0

—

2.4

1.4

—

MHz

Voltage variation on current step²(20% to 80% of

maximum current with 4 usec constant time)

0.1

VRC linear regulator is capable of sourcing a current up to 20 mA and sinking a current up to 500 uA. When using the

recommended ballast transistor the maximum output current provided by the voltage regulator VRC/ballast to the VDD core

voltage is up to 1A.

Parameter cannot be tested; this value is based on simulation and characterization.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.6

Power Up/Down Sequencing

There is no power sequencing required among power sources during power up and power down in order to operate within

specification as long as the following two rules are met:

•

When VDDREG is tied to a nominal 3.3V supply, VDD33 and VDDSYN must be both shorted to VDDREG.

When VDDREG is tied to a 5V supply, VDD33 and VDDSYN must be tied together and shall be powered by the

internal 3.3V regulator.

The recommended power supply behavior is as follows: Use 25 V/millisecond or slower rise time for all supplies. Power up

each V /V first and then power up V . For power down, drop V to 0 V first, and then drop all V /V

DDE DDEH

supplies. There is no limit on the fall time for the power supplies.

Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive current spikes, etc.,

the state of the I/O pins during power up/down varies according to Table 12 and Table 13.

Table 12. Power Sequence Pin States for MH and AE pads

VDD

VDD33

VDDE

MH Pad

MH+LVDS Pads¹

AE/up-down Pads

High

—

High

Low

High

Normal operation

Outputs disabled

Normal operation

Pin is tri-stated (output buffer,

input buffer, and weak pulls

disabled)

Pull-ups enabled,

pull-downs disabled

Low

High

Low

Output low,

pin unpowered

Outputs disabled

Output low,

pin unpowered

High

Pin is tri-stated (output buffer,

input buffer, and weak pulls

disabled)

Pull-ups enabled,

pull-downs disabled

MH+LVDS pads are output-only.

Table 13. Power Sequence Pin States for F and FS pads

VDD

VDD33

VDDE

F and FS pads

low

high

low

high

—

Outputs Disabled

high

low

high

low

high

Normal operation - except no drive current

and input buffer output is unknown.¹

high

Normal Operation

The pad pre-drive circuitry will function normally but since VDDE is unpowered

the outputs will not drive high even though the output pmos can be enabled.

4.6.1

Power-Up

If V

is powered up first, then a threshold detector tristates all drivers connected to V

. There is no limit

DDE DDEH

to how long after V

powers up before V must power up. If there are multiple V

supplies, they can

DDE DDEH

be powered up in any order. For each V

supply not powered up, the drivers in that V

segment exhibit

DDE DDEH

the characteristics described in the next paragraph.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

If V is powered up first, then all pads are loaded through the drain diodes to V

/V . This presents a heavy load that

DDE DDEH

pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the current

injection specification. There is no limit to how long after V powers up before V

must power up.

DDE DDEH

The rise times on the power supplies are to be no faster than 25 V/millisecond.

4.6.2

Power-Down

If V is powered down first, then all drivers are tristated. There is no limit to how long after V powers down before

must power down.

DDE DDEH

If V

is powered down first, then all pads are loaded through the drain diodes to V

. This presents a heavy

DDE DDEH

load that pulls the pad down to a diode above V . Current injected by external devices connected to the pads must meet the

current injection specification. There is no limit to how long after V

powers down before V must power down.

DDE DDEH DD

There are no limits on the fall times for the power supplies.

4.6.3

Power Sequencing and POR Dependent on V_DDA

During power up or down, V

can lag other supplies (of magnitude greater than V

/2) within 1 V to prevent any

DDA

DDEH

forward-biasing of device diodes that causes leakage current and/or POR. If the voltage difference between V

is more than 1 V, the following will result:

and V

DDEH

DDA

•

Triggers POR (ADC monitors on V

segment which powers the RESET pin) if the leakage current path created,

DDEH1

when V

level.

is sufficiently low, causes sufficient voltage drop on V

node monitored crosses low-voltage detect

DDA

DDEH1

•

If V

out of reset.

is between 0–2 V, powering all the other segments (especially V

) will not be sufficient to get the part

DDEH1

DDA

Each V

up to (V

will have a leakage current to V

of a magnitude of ((V

– V

– 1 V(diode drop)/200 KOhms)

DDA

DDEH

DDA

DDEH

/2 = V

+ 1 V).

DDEH

DDA

Each V has the same behavior; however, the leakage will be small even though there is no current limiting resistor

since V = 1.32 V max.

4.7

DC Electrical Specifications

Table 14. DC Electrical Specifications

Spec

Characteristic

Symbol

Min

Max

Unit

Core Supply Voltage (External Regulation)

Core Supply Voltage (Internal Regulation)³

I/O Supply Voltage (fast I/O pads)

I/O Supply Voltage (medium I/O pads)

3.3 V I/O Buffer Voltage

V_DD

1.14

1.08

3.0

1.32^1,2

1.32

V_DDE

3.6^1,4

5.25^1,5

3.6^1,4

5.25^1,5

1.2

V_DDEH

V_DD33

V_DDA

3.0

Analog Supply Voltage

4.75

0.95⁶

SRAM Standby Voltage

V_{STBY_LOW}

Keep-out Range: 1.2V–2V

SRAM Standby Voltage

V_{STBY_HIGH}

V_DDREG

Keep-out Range: 1.2V–2V

Voltage Regulator Control Input Voltage⁷

2.7⁸

5.5^1,5

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 14. DC Electrical Specifications (continued)

Spec

Characteristic

Symbol

Min

Max

Unit

Clock Synthesizer Operating Voltage⁹

V_DDSYN

V_{IH_F}

3.0

3.6^1,4

Fast I/O Input High Voltage

Hysteresis enabled

_DDE+ 0.3

0.65 × V_DDE

0.55 × V_DDE

Hysteresis disabled

Fast I/O Input Low Voltage

Hysteresis enabled

V_{IL_F}

V_{IH_S}

V_{IL_S}

V_SS– 0.3

0.35 × V_DDE

0.40 × V_DDE

Hysteresis disabled

Medium I/O Input High Voltage

Hysteresis enabled

V_DDEH+ 0.3

0.65 × V_DDEH

Hysteresis disabled

0.55 × V

DDEH

Medium I/O Input Low Voltage

Hysteresis enabled

V_SS– 0.3

0.35 × V_DDEH

0.40 × V_DDEH

Hysteresis disabled

Fast I/O Input Hysteresis

V_{HYS_F}

V_{HYS_S}

V_INDC

V_{OH_F}

V_{OH_S}

V_{OL_F}

V_{OL_S}

C_L

0.1 × V_DDE

0.1 × V_DDEH

V_SSA– 0.1

0.8 × V_DDE

0.8 × V_DDEH

—

Medium I/O Input Hysteresis

Analog Input Voltage

V_DDA+ 0.1

—

Fast I/O Output High Voltage¹⁰

Medium I/O Output High Voltage¹¹

Fast I/O Output Low Voltage¹⁰

Medium I/O Output Low Voltage¹¹

—

0.2 × V_DDE

0.2 × V_DDEH

—

Load Capacitance (Fast I/O)¹²

DSC(PCR[8:9]) = 0b00

DSC(PCR[8:9]) = 0b01

DSC(PCR[8:9]) = 0b10

DSC(PCR[8:9]) = 0b11

—

Input Capacitance (Digital Pins)

Input Capacitance (Analog Pins)

C_IN

—

C_{IN_A}

Operating Current 1.2 V Supplies @ f_sys= 264 MHz

V_DD@1.32 V

I_DD

I_DDSTBY

I_DDSTBY6

—

850

0.10

0.15

V_STBY¹³@1.2 V and 85^oC

V_STBY@6.0 V and 85^oC

Operating Current 3.3 V Supplies @ f_sys= 264 MHz

V_DD33

V_DDSYN

I_DD33

I_DDSYN

—

note¹⁴

7¹⁵

Operating Current 5.0 V Supplies @ f_sys= 264 MHz

V_DDA

I_DDA

I_REF

I_REG

—

50¹⁶

1.0

Analog Reference Supply Current (Transient)

V_DDREG

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Spec

Table 14. DC Electrical Specifications (continued)

Characteristic

Symbol

Min

Max

Unit

Operating Current V_DDE/V_DDEH¹⁷Supplies

V_DDE2

I_DD2

I_DD1

I_DD3

I_DD4

I_DD5

I_DD6

I_DD7

—

V_DDEH1

V_DDEH3

V_DDEH4

V_DDEH5

V_DDEH6

V_DDEH7

note¹⁷

Fast I/O Weak Pull Up/Down Current¹⁸

3.0 V–3.6 V

I_{ACT_F}

I_{ACT_S}

158

μA

Medium I/O Weak Pull Up/Down Current¹⁹

3.0 V–3.6 V

4.5 V–5.5 V

200

μA

I/O Input Leakage Current²⁰

I_{INACT_D}

I_IC

–2.5

–1.0

–250

2.5

1.0

μA

DC Injection Current (per pin)

Analog Input Current, Channel Off²¹, AN[0:7], AN38,

I_{INACT_A}

250

AN39

Analog Input Current, Channel Off, all other analog

inputs AN[x]

–150

150

V_SSDifferential Voltage

V_SS– V_SSA

V_RL

V_RL– V_SSA

V_RH

–100

V_SSA

–100

V_DDA– 100

4.75

100

V_SSA+ 100

100

Analog Reference Low Voltage

V_RLDifferential Voltage

Analog Reference High Voltage

V_DDA

5.25

V_REFDifferential Voltage

V_RH– V_RL

V_SSSYN– V_SS

T_A(T_Lto T_H)

—

V_SSSYNto V_SSDifferential Voltage

Operating Temperature Range—Ambient (Packaged)

Slew rate on power supply pins

–100

–40.0

—

100

^οC

125.0

V/ms

kΩ

Weak Pull-Up/Down Resistance²², 200 K Option

Weak Pull-Up/Down Resistance²², 100 K Option

Weak Pull-Up/Down Resistance²², 5 K Option

R_PUPD200K

R_PUPD100K

R_PUPD5K

R_PUPDMTCH

130

280

140

1.4

7.5

Pull-Up/Down Resistance Matching Ratios²³

(100K/200K)

–2.5

+2.5

Voltage overshoots during a high-to-low or low-to-high transition must not exceed 10 seconds per instance.

2.0 V for 10 hours cumulative time, 1.2 V +10% for time remaining.

Assumed with DC load.

5.3 V for 10 hours cumulative time, 3.3 V +10% for time remaining.

6.4 V for 10 hours cumulative time, 5.0 V +10% for time remaining.

V_STBYbelow 0.95 V the RAM will not retain states, but will be operational. V_STBYcan be 0 V when bypass standby mode.

Regulator is functional with derated performance, with supply voltage down to 4.0 V for system with V_DDREG= 4.5 V (min).

2.7 V minimum operating voltage allowed during vehicle crank for system with V_DDREG= 3.0 V (min). Normal operating voltage

should be either V_DDREG= 3.0 V (min) or 4.5 V (min) depending on the user regulation voltage system selected.

Required to be supplied when 3.3 V regulator is disabled. See Section 4.5, “PMC/POR/LVI Electrical Specifications.”

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

= {16,32,47,77} mA and I_{OL_F}= {24,48,71,115} mA for {00,01,10,11} drive mode with V_DDE= 3.0 V. This spec is for

OH_F

characterization only.

= {11.6} mA and IOL_S = {17.7} mA for {medium} I/O with V_DDE= 4.5 V;

OH_S

_{OH_S}= {5.4} mA and IOL_S = {8.1} mA for {medium} I/O with V_DDE= 3.0 V. These specs are for characterization only.

¹²Applies to D_CLKOUT, external bus pins, and Nexus pins.

current specified at 1.0 V at a junction temperature of 85 ^oC. V_STBYcurrent is 700 µA maximum at a junction

STBY

temperature of 150 ^oC.

¹⁴Power requirements for the V_DD33supply depend on the frequency of operation and load of all I/O pins, and the voltages on

the I/O segments. See Section 4.7.2, “I/O Pad V_DD33Current Specifications,” for information on both fast (F, FS) and medium

(MH) pads. Also refer to Table 16 for values to calculate power dissipation for specific operation.

¹⁵This value is a target that is subject to change.

¹⁶This value allows a 5 V reference to supply ADC + REF.

¹⁷Power requirements for each I/O segment depend on the frequency of operation and load of the I/O pins on a particular I/O

segment, and the voltage of the I/O segment. See Section 4.7.1, “I/O Pad Current Specifications,” for information on I/O pad

power. Also refer to Table 15 for values to calculate power dissipation for specific operation. The total power consumption of

an I/O segment is the sum of the individual power consumptions for each pin on the segment.

¹⁸Absolute value of current, measured at V_ILand V_IH.

¹⁹Absolute value of current, measured at V_ILand V_IH.

²⁰Weak pull up/down inactive. Measured at V_DDE= 3.6 V and V_DDEH= 5.25 V. Applies to pad types F and MH.

²¹Maximum leakage occurs at maximum operating temperature. Leakage current decreases by approximately one-half for each

8 to 12 ^oC, in the ambient temperature range of 50 to 125 ^oC. Applies to pad types AE and AE/up-down. See Appendix A,

Signal Properties and Muxing.

²²This programmable option applies only to eQADC differential input channels and is used for biasing and sensor diagnostics

²³Pull-up and pull-down resistances are both enabled and settings are equal.

4.7.1

I/O Pad Current Specifications

The power consumption of an I/O segment is dependent on the usage of the pins on a particular segment. The power

consumption is the sum of all output pin currents for a particular segment. The output pin current can be calculated from

Table 15 based on the voltage, frequency, and load on the pin. Use linear scaling to calculate pin currents for voltage, frequency,

and load parameters that fall outside the values given in Table 15.

The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”

Table 15. V

I/O Pad Average DC Current

DDE DDEH

Frequency

(MHz)

Load²

(pF)

Voltage

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

Medium

I_{DRV_MH}

3.0

2.0

200

5.25

3.6

16.0

6.3

1.1

2.4

Fast

I_{DRV_FC}

7.4

3.6

10.5

12.3

35.2

3.6

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 15. V

I/O Pad Average DC Current (continued)

DDE DDEH

Frequency

Load²

(pF)

Voltage

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

(MHz)

Fast w/ Slew

Control

I_{DRV_FSR}

3.6

12.7

6.7

4.2

2.6

9.1

33.33

200

These are average IDDE numbers for worst case PVT from simulation. Currents apply to output pins only.

All loads are lumped.

4.7.2

I/O Pad V_DD33Current Specifications

The power consumption of the V_DD33supply is dependent on the usage of the pins on all I/O segments. The power consumption

is the sum of all input and output pin V_DD33currents for all I/O segments. The V_DD33current draw on fast speed pads can be

calculated from Table 16 dependent on the voltage, frequency, and load on all F type pins. The V_DD33current draw on medium

pads can be calculated from Table 16 dependent on voltage and independent on the frequency and load on all MH type pins.

Use linear scaling to calculate pin currents for voltage, frequency, and load parameters that fall outside the values given in

Table 16.

The AC timing of these pads are described in the Section 4.11.2, “Pad AC Specifications.”

Table 16. V

Pad Average DC Current

DD33

Frequency

(MHz)

Load²

(pF)

V_DD33

(V)

V_DDE

(V)

Drive/Slew

Rate Select

Spec

Pad Type

Symbol

Current (mA)

Medium

Fast

I_{33_MH}

I_{33_FC}

—

200

3.6

5.5

3.6

—

0.0007

0.92

1.14

1.50

2.19

0.74

0.52

0.19

Fast w/ Slew

Control

I_{33_FSR}

33.33

These are average IDDE for worst case PVT from simulation. Currents apply to output pins only for the fast pads and to input

pins only for the medium pads.

All loads are lumped.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.7.3

LVDS Pad Specifications

LVDS pads are implemented to support the MSC (Microsecond Channel) protocol, which is an enhanced feature of the DSPI

module.

Table 17. DSPI LVDS pad specification

Min.

Value

Typ.

Value

Max.

Value

Characteristic

Symbol

Condition

Data Rate

Unit

Data Frequency

f_LVDSCLK

—

MHz

Driver Specs

Differential output voltage

V_OD

SRC=0b00 or 0b11

SRC=0b01

SRC=0b10

—

150

—

400

320

480

1.39

160

1.06

—

Common mode voltage (LVDS),

VOS

V_OS

1.2

Rise/Fall time

T_R/T_F

T_PLH

—

0.5

Propagation delay (Low to High)

Propagation delay (High to Low)

Delay (H/L), sync Mode

T_PHL

t_PDSYNC

T_DZ

Delay, Z to Normal (High/Low)

500

—

Diff Skew Itphla-tplhbI or

Itplhb-tphlaI

T_SKEW

Termination

10 Trans. Line (differential Zo)

11 Temperature

—

100

—

105

150

ohms

–40

°C

4.8

Oscillator and FMPLL Electrical Characteristics

Table 18. FMPLL Electrical Specifications

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Max

Unit

PLL Reference Frequency Range²(Normal Mode)

Crystal Reference (PLLCFG2 = 0b0)

Crystal Reference (PLLCFG2 = 0b1)

External Reference (PLLCFG2 = 0b0)

External Reference (PLLCFG2 = 0b1)

MHz

f_{ref_crystal}

f_{ref_ext}

40³

f_{ref_ext}

Loss of Reference Frequency⁴

Self Clocked Mode Frequency⁵

PLL Lock Time⁶

f_LOR

f_SCM

t_LPLL

100

1000

kHz

MHz

μs

—

< 400

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 18. FMPLL Electrical Specifications (continued)

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Duty Cycle of Reference ⁷

Frequency un-LOCK Range

Symbol

Min

Max

Unit

t_DC

f_UL

f_LCK

C_Jitter

–4.0

–2.0

–5

4.0

2.0

% f_sys

%f_clkout

Frequency LOCK Range

D_CLKOUT Period Jitter^{8, 9}Measured at f_SYSMax

Cycle-to-cycle Jitter

10,11

Peak-to-Peak Frequency Modulation Range Limit

C_mod

%f_sys

(f_sysMax must not be exceeded)

FM Depth Tolerance¹²

C_{mod_err}

f_VCO

–0.25

192

0.400

0.25

600

%f_sys

MHz

VCO Frequency

Modulation Rate Limits¹³

Predivider output frequency range¹⁴

f_mod

f_prediv

All values given are initial design targets and subject to change.

Crystal and External reference frequency limits depend on device relying on PLL to lock prior to release of reset, default

PREDIV/EPREDIV, MFD/EMFD default settings, and VCO frequency range. Absolute minimum loop frequency is 4 MHz.

Upper tolerance of less than 1% is allowed on 40MHz crystal.

“Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f_LOR. This

frequency is measured at D_CLKOUT. A default RFD value of (0x05) is used in SCM mode, and the programmed MFD and

RFD values have no effect

This specification applies to the period required for the PLL to re-lock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, lock time will be additive with crystal

startup time.

For Flexray operation, duty cycle requirements are higher.

Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f_sys

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via V_DDSYNand V_SSSYNand variation in crystal oscillator frequency increase the Cjitter

percentage for a given interval. D_CLKOUT divider set to divide-by-2.

Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C_jitter+ C_mod

¹⁰Modulation depth selected must not result in f_pllvalue greater than the f_pllmaximum specified value.

¹¹Maximum and minimum variation from programmed modulation depth is pending characterization. Depth settings available in

control register are: 2%, 3%, and 4% peak-to-peak.

¹²Depth tolerance is the programmed modulation depth ±0.25% of F_sys. Violating the VCO min/max range may prevent the

system from exiting reset.

¹³Modulation rates less than 400 kHz will result in exceedingly long FM calibration durations. Modulation rates greater than 1 MHz

will result in reduced calibration accuracy.

¹⁴Violating this range will cause the VCO max/min range to be violated with the default MFD settings out of reset.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 19. Oscillator Electrical Specifications

(V_DDSYN= 3.0 V to 3.6 V, V_SS= V_SSSYN= 0 V, T_A= T_Lto T_H)

Spec

Characteristic

Symbol

Min

Max

Unit

Crystal Mode Differential Amplitude²

—

| V_extal– V_xtal| > 0.4 V

crystal_diff_amp

(Min differential voltage between EXTAL and XTAL)

Crystal Mode: Internal Differential Amplifier Noise

Rejection

V_{crystal_diff_amp_nr}

V_IHEXT

—

| V_extal– V_xtal| < 0.2 V

EXTAL Input High Voltage

((V

/2) + 0.4 V)

—

DD33

Bypass mode, External Reference

—

EXTAL Input Low Voltage

V_ILEXT

/2) – 0.4 V

DD33

Bypass mode, External Reference

XTAL Current³

I_XTAL

C_{S_XTAL}

C_{S_EXTAL}

C_L

—

Total On-chip stray capacitance on XTAL

Total On-chip stray capacitance on EXTAL

Crystal manufacturer’s recommended capacitive load

Discrete load capacitance to be connected to EXTAL

1.5

See crystal spec

—

See crystal spec

C_{L_EXTAL}

(2 × C – C

S_EXTAL

– C

PCB_EXTAL )

—

Discrete load capacitance to be connected to XTAL

C_{L_XTAL}

(2 × C – C

S_XTAL

– C

PCB_XTAL )

All values given are initial design targets and subject to change.

This parameter is meant for those who do not use quartz crystals or resonators, but instead use CAN oscillators in crystal mode.

In that case, V_extal– V_xtal≥ 400 mV criterion has to be met for oscillator’s comparator to produce output clock.

I_xtalis the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

C_{PCB_EXTAL}and C_{PCB_XTAL}are the measured PCB stray capacitances on EXTAL and XTAL, respectively.

4.9

eQADC Electrical Characteristics

Table 20. eQADC Conversion Specifications (Operating)

Spec

Characteristic

Symbol

Min

Max

Unit

ADC Clock (ADCLK) Frequency

f_ADCLK

MHz

Conversion Cycles

ADCLK cycles

Single Ended Conversion Cycles 12 bit resolution

Single Ended Conversion Cycles 10 bit resolution

Single Ended Conversion Cycles 8 bit resolution

Note: Differential conversion (min) is one clock

cycle less than the single-ended

2 + 14

2 + 12

2 + 10

128 + 14

128 + 12

128 + 10

conversion values listed here.

Stop Mode Recovery Time¹

Resolution²

T_SR

—

1.25

–4⁴

–8⁴

–3⁴

—

4⁴

8⁴

3⁴

μs

INL: 8 MHz ADC Clock³

INL: 16 MHz ADC Clock³

DNL: 8 MHz ADC Clock³

DNL: 16 MHz ADC Clock³

INL8

INL16

DNL8

DNL16

LSB⁵

LSB

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 20. eQADC Conversion Specifications (Operating) (continued)

Spec

Characteristic

Symbol

Min

Max

Unit

Offset Error without Calibration

OFFNC

OFFWC

GAINNC

GAINWC

I_INJ

0⁴

–4⁴

100⁴

4⁴

LSB

Offset Error with Calibration

Full Scale Gain Error without Calibration

Full Scale Gain Error with Calibration

Non-Disruptive Input Injection Current ^{7, 8, 9, 10}

Incremental Error due to injection current^{11, 12}

TUE value at 8 MHz ^{13, 14}(with calibration)

TUE value at 16 MHz ^{13, 14}(with calibration)

–120⁴

–4^4,6

–3

0⁴

LSB

4^4,6

LSB

mΑ

E_INJ

–4⁴

4⁴

Counts

TUE8

–4^4,6

4^4,6

TUE16

–8

Maximum differential voltage¹⁵

(DANx+ - DANx-) or (DANx- - DANx+)

PREGAIN set to 1X setting

DIFF_max

DIFF_max2

DIFF_max4

—

(V_RH– V_RL)/2

(V_RH– V_RL)/4

(V_RH- V_RL)/8

PREGAIN set to 2X setting

PREGAIN set to 4X setting

Differential input Common mode voltage¹⁵

(DANx- + DANx+)/2

DIFF_cmv

(V_RH– V_RL)/2

– 5%

(V_RH– V_RL)/2

+ 5%

Stop mode recovery time is the time from the setting of either of the enable bits in the ADC Control Register to the time that

the ADC is ready to perform conversions. Delay from power up to full accuracy = 8 ms.

At V_RH– V_RL= 5.12 V, one count = 1.25 mV without using pregain.

INL and DNL are tested from V_RL+ 50 LSB to V_RH– 50 LSB. The eQADC is guaranteed to be monotonic at 10 bit accuracy

(12 bit resolution selected).

New design target. Actual specification will change following characterization. Margin for manufacturing has not been fully

included.

At V_RH– V_RL= 5.12 V, one LSB = 1.25 mV.

The value is valid at 8 MHz, it is ±8 counts at 16 Mhz.

Below disruptive current conditions, the channel being stressed has conversion values of $3FF for analog inputs greater than

V_RHand $000 for values less than V_RL. Other channels are not affected by non-disruptive conditions.

Exceeding limit may cause conversion error on stressed channels and on unstressed channels. Transitions within the limit do

not affect device reliability or cause permanent damage.

Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate

resistance values using V_POSCLAMP= V_DDA+ 0.5 V and V_NEGCLAMP= –0.3 V, then use the larger of the calculated values.

¹⁰Condition applies to two adjacent pins at injection limits.

¹¹Performance expected with production silicon.

¹²All channels have same 10 kΩ < Rs < 100 kΩ Channel under test has Rs = 10 kΩ, I_INJ=I_{INJMAX INJMIN}

¹³The TUE specification is always less than the sum of the INL, DNL, offset, and gain errors due to cancelling errors.

¹⁴TUE does not apply to differential conversions.

¹⁵Voltages between VRL and VRH will not cause damage to the pins. However, they may not be converted accurately if the

differential voltage is above the maximum differential voltage. In addition, conversion errors may occur if the common mode

voltage of the differential signal violates the Differential Input common mode voltage specification.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.9.1

ADC Internal Resource Measurements

Table 21. Power Management Control (PMC) Specification

Spec

Characteristic

Symbol

Min

Typical

Max

Unit

PMC Normal Mode

Bandgap 0.62 V

ADC0 channel 145

V_ADC145

V_ADC146

V_ADC147

V_ADC180

V_ADC181

V_ADC182

V_ADC183

—

0.62

1.22

—

Bandgap 1.2 V

ADC0 channel 146

Vreg1p2 Feedback

ADC0 channel 147

V_DD/ 2.045

V_DD/ 1.774

Vreg3p3 / 5.460

Vreg3p3 / 4.758

LVD 1.2 V

ADC0 channel 180

Vreg3p3 Feedback

ADC0 channel 181

LVD 3.3 V

ADC0 channel 182

LVD 5.0 V

ADC0 channel 183

— LDO mode

— SMPS mode

V_DDREG/ 4.758

V_DDREG/7.032

Table 22. Standby RAM Regulator Electrical Specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

Normal Mode

—

Standby Regulator Output

ADC1 channel 194

V_ADC194

1.2

—

Standby Source Bias

150 mV to 360 mV (30mV Increment @

V_ADC195

150

360

vref_sel)

ADC1 channel 195

Default Value 150 mV (@vref_sel = 1 1 1)

Standby Brownout Reference

ADC1 channel 195

V_ADC195

500

—

850

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 23. ADC Band Gap Reference / LVI Electrical Specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

4.75 LVD (from V_DDA

)

V_ADC196

—

4.75

—

ADC1 channel 196

ADC Bandgap

V_ADC45

1.171

1.220

1.269

ADC0 channel 45

ADC1 channel 45

Table 24. Temperature Sensor Electrical Specifications

Spec

Characteristic

Symbol

Min

Typ

Max

Unit

Slope

–40 °C to 100 °C ±1.0 °C

—

5.8

—

mV/ °C

SADC128

100 °C to 150 °C ±1.6 °C

ADC0 channel 128

ADC1 channel 128

Accuracy

—

°C

–40 °C to 150 °C

ADC0 channel 128

ADC1 channel 128

±10.0

Slope is the measured voltage change per °C.

4.10 C90 Flash Memory Electrical Characteristics

Table 25. Flash Program and Erase Specifications

Initial

Spec

Characteristic

Symbol

Min

Typ¹

Max³

Unit

Max²

Double Word (64 bits) Program Time⁴

Page Program Time^4,5

t_dwprogram

t_pprogram

—

500

μs

160

16 KB Block Pre-program and Erase Time

64 KB Block Pre-program and Erase Time

128 KB Block Pre-program and Erase Time

256 KB Block Pre-program and Erase Time

t_16kpperase

t_64kpperase

t_128kpperase

t_256kpperase

270

800

1500

3000

1000

1800

2600

5200

5000

7500

15000

Typical program and erase times assume nominal supply values and operation at 25 ^oC.

Initial factory condition: ≤ 100 program/erase cycles, 25 ^oC, typical supply voltage, 80 MHz minimum system frequency.

The maximum erase time occurs after the specified number of program/erase cycles. This maximum value is characterized

but not guaranteed.

Program times are actual hardware programming times and do not include software overhead.

Page size is 128 bits (4 words).

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 26. Flash EEPROM Module Life

Spec

Characteristic

Symbol

Min

Typical¹

Unit

Number of program/erase cycles per block for 16 KB and 64

KB blocks over the operating temperature range (T_J)

P/E

100,000

—

cycles

Number of program/erase cycles per block for 128 KB and 256

KB blocks over the operating temperature range (T_J)

P/E

1,000

100,000

cycles

years

Minimum Data Retention at 85 °C ambient temperature²

Blocks with 0–1,000 P/E cycles

Retention

—

Blocks with 1,001–10,000 P/E cycles

Blocks with 10,001–100,000 P/E cycles

Typical endurance is evaluated at 25 °C. Product qualification is performed to the minimum specification. For additional

information on the Freescale definition of Typical Endurance, please refer to Engineering Bulletin EB619, Typical Endurance

for Nonvolatile Memory.

Ambient temperature averaged over duration of application, not to exceed product operating temperature range.

Table 27 shows the Platform Flash Configuration Register 1 (PFCPR1) settings versus frequency of operation. Refer to the

device reference manual for definitions of these bit fields.

Table 27. PFCPR1 Settings vs. Frequency of Operation

Maximum Frequency²

(MHz)

Clock

Mode

APC =

RWSC

Spec

WWSC DPFEN³IPFEN³

PFLIM⁴

BFEN⁵

Core

f_sys

Platform

f_platf

Enhanced 264 MHz⁶

132 MHz⁶

100 MHz

132 MHz

0b011

0b010

0b100

0b111

0b01

0b11

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Enhanced/ 200 MHz

Full

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Legacy

132 MHz

0b0

0b1

0b0

0b1

0b00

0b01

0b1x

0b0

0b1

Default setting after reset:

0b00

0b0

Illegal combinations exist. Use entries from the same row in this table.

This is the nominal maximum frequency of operation: platform runs at f_sys/2 in Enhanced Mode .

For maximum flash performance, set to 0b1.

For maximum flash performance, set to 0b10.

For maximum flash performance, set to 0b1.

This is the nominal maximum frequency of operation in Enchanced Mode. Max speed is the maximum speed

allowed including frequency modulation (FM). 270 MHz parts allow for 264 MHz system core clock(f_sys) + 2% FM

and 132 Mhz platform clock (f_platf)+ 2% FM.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.11 AC Specifications

4.11.1 Clocking

The Figure 16 shows the operating frequency domains of various blocks on MPC5674F.

PLLCFG[0:1]

CORE

f_sys

SYSDIV

÷ X

÷ 2

PLATFORM /

BLOCKS /

FLASH

f_platf

EXTAL

PLL

IPG DIV SEL

f_periph

SIU_SYSDIV[SYSCLKDIV[0:1]]

X = 2, 4, 8, or 16

f_etpu

eTPU /

NDEDI

ETPU DIV SEL

SIU_SYSDIV[BYPASS]

X = 1

f_{ebi_cal}

EBI

CAL BUS

SIU_SYSDIV[IPCLKDIV[0:1]]

DIV

SIU_ECCR[EBDF[0:1]]

Note: t_cycsys= 1 / f_sys

t_cyc= 1 / f_platf

D_CLKOUT

÷ 2 = divide-by-2

÷ X = divide-by-X, depending on SIU_SYSDIV[BYPASS]

(D_CLKOUT is not available

on all packages and cannot

be programmed for faster

than fsys/2.)

and SIU_SYSDIV[SYSCLKDIV].

Figure 16. MPC5674F Block Operating Frequency Domain Diagram

Table 28 shows the operating frequencies of various blocks depending on the device’s clocking mode configuration settings (see

Table 29 and Table 30 for descriptions of bit settings).

1, 2

Table 28. MPC5674F Operating Frequencies

etpu

platf

(platform and all blocks (eTPU, eTPU RAM,

SIU_ECCR

4,5

ebi_cal

sys

Mode

Unit

[EBDF[0:1]]³

(core)

except eTPU)

and NDEDI)

Enhanced

Full

264

132

MHz

200

100

200

Legacy

132

The values in the table are specified at:

V_DD= 1.02 V to 1.32 V

V_DDE= 3.0 V to 3.6 V

V_DDEH= 4.5 V to 5.5 V

V_DD33and V_DDSYN= 3.0 V to 3.6 V

T_A= T_Lto T_H.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Up to the maximum frequency rating of the device (refer to Table 1). The f_sysspeed is the nominal maximum frequency.

270 Mhz parts allow for 264 Mhz system clock + 2% FM.

See the MPC5674F Reference Manual for full description as not all bit combinations are valid.

EBI/Calibration bus is not available in all packages.

The EBI/Calibration Bus operating frequency, f_{ebi_cal}, depends on clock divider settings of block’s max allowed

frequency of operation. Normally f_{ebi_cal}= f_platf/2, but can be limited to < f_platf/2 in Full Mode.

Table 29. IPCLKDIV Settings

SIU_SYSDIV

Mode

Description

[IPCLKDIV[0:1]]

Enhanced

CPU frequency is doubled (Max 264Mhz). Platform,

peripheral, and eTPU clocks are 1/2 of CPU frequency

Full

CPU and eTPU frequency is doubled (Max 200Mhz).

Platform and peripheral clocks are 1/2 of CPU frequency.

—

Reserved

Legacy

CPU, eTPU, platform, and peripheral’s clocks all run at

same speed (Max 132Mhz).

Table 30. SYSCLKDIV Settings

SIU_SYSDIV

Description

[SYSCLKDIV[0:1]]

Divide by 2.

Divide by 4.

Divide by 8.

Divide by 16.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.11.2 Pad AC Specifications

Table 31. Pad AC Specifications (V

= 5.0 V, V

= 3.3 V)

DDE

DDEH

Out Delay^2,4

H/H L (ns)

Rise/Fall^3,4

(ns)

Load Drive

(pF)

Spec

Pad

SRC/DSC

→

Medium⁵

152/165

205/220

28/34

70/74

96/96

12/15

28/31

5.3/5.9

22/22

200

52/59

200

12/12

32/32

200

Fast⁶

2.5

1.2

Fast with Slew Rate

40/40

50/50

13/13

19/19

8/8

16/16

21/21

5/5

200

8/8

200

2.4/2.4

5/5

12/12

5/5

200

1.1/1/1

2.6

8/8

2.6

Pull Up/Down (3.6 V max)

Pull Up/Down (5.25 V max)

—

7500

6000

5000/5000

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

_DD= 1.02 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 4.75 V to 5.25 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 32. Derated Pad AC Specifications (V

= 3.3 V)

DDEH

Out Delay^2,3

H/H L (ns)

Rise/Fall^4,3

(ns)

Load Drive

(pF)

Spec

Pad

SRC/DSC

→

Medium⁵

200/210

270/285

37/45

86/86

120/120

15.5/19

38/43

200

69/82

200

18/17

7.6/8.5

30/34

46/49

200

These are worst case values that are estimated from simulation and not tested. The values in the table are simulated at

V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DDEH= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H.

This parameter is supplied for reference and is not guaranteed by design and not tested.

Delay and rise/fall are measured to 20% or 80% of the respective signal.

This parameter is guaranteed by characterization before qualification rather than 100% tested.

Out delay is shown in Figure 17. Add a maximum of one system clock to the output delay for delay with respect to system clock.

V_DDEn/ 2

V_DDEHn/ 2

Pad

Data Input

Rising

Edge

Falling

Edge

Output

Delay

Output

Delay

V_OH

Pad

Output

V_OL

Figure 17. Pad Output Delay

4.12 AC Timing

4.12.1 Generic Timing Diagrams

The generic timing diagrams in Figure 18 and Figure 19 apply to all I/O pins with pad types F and MH. See Appendix A, Signal

Properties and Muxing, for the pad type for each pin.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

D_CLKOUT

V_DDE/ 2

I/O Outputs

V_DDEn/ 2

V_DDEHn/ 2

A – Maximum Output Delay Time

Figure 18. Generic Output Delay/Hold Timing

B – Minimum Output Hold Time

D_CLKOUT

V_DDE/ 2

I/O Inputs

V_DDEn/ 2

V_DDEHn/ 2

A – Minimum Input Setup Time

B – Minimum Input Hold Time

Figure 19. Generic Input Setup/Hold Timing

4.12.2 Reset and Configuration Pin Timing

Table 33. Reset and Configuration Pin Timing

Spec

Characteristic Symbol

Min

Max

Unit

RESET Pulse Width

t_RPW

t_GPW

t_RCSU

t_RCH

—

t_cyc

RESET Glitch Detect Pulse Width

PLLCFG, BOOTCFG, WKPCFG Setup Time to RSTOUT Valid

PLLCFG, BOOTCFG, WKPCFG Hold Time to RSTOUT Valid

Reset timing specified at: V_DDEH= 3.0 V to 5.25 V, V_DD= 1.08 V to 1.32 V, T_A= T_Lto T_H.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

See Notes on t_cycon Figure 16 and Table 28 in Section 4.11.1, “Clocking.”

RESET

RSTOUT

PLLCFG

BOOTCFG

WKPCFG

Figure 20. Reset and Configuration Pin Timing

4.12.3 IEEE 1149.1 Interface Timing

Table 34. JTAG Pin AC Electrical Characteristics

Spec

Characteristic

Symbol

Min

Max

Unit

TCK Cycle Time

t_JCYC

t_JDC

t_TCKRISE

_TMSS,t_TDIS

t_{TMSH, TDIH}

t_TDOV

t_TDOI

100

—

TCK Clock Pulse Width (Measured at V_DDE/ 2)

TCK Rise and Fall Times (40%–70%)

TMS, TDI Data Setup Time

—

TMS, TDI Data Hold Time

—

TCK Low to TDO Data Valid

TCK Low to TDO Data Invalid

TCK Low to TDO High Impedance

JCOMP Assertion Time

t_TDOHZ

t_JCMPPW

t_JCMPS

t_BSDV

—

100

—

JCOMP Setup Time to TCK Low

TCK Falling Edge to Output Valid

TCK Falling Edge to Output Valid out of High Impedance

TCK Falling Edge to Output High Impedance

Boundary Scan Input Valid to TCK Rising Edge

TCK Rising Edge to Boundary Scan Input Invalid

t_BSDVZ

t_BSDHZ

t_BSDST

t_BSDHT

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

JTAG timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 35 for

functional specifications.

TCK

Figure 21. JTAG Test Clock Input Timing

TCK

TMS, TDI

TDO

Figure 22. JTAG Test Access Port Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

TCK

JCOMP

Figure 23. JTAG JCOMP Timing

TCK

Output

Signals

Output

Signals

Input

Signals

Figure 24. JTAG Boundary Scan Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.12.4 Nexus Timing

Table 35. Nexus Debug Port Timing

Spec

Characteristic

Symbol

Min

Max

Unit

MCKO Cycle Time

t_MCYC

t_MDC

2²

–0.1

4.0

t_CYC

MCKO Duty Cycle

0.2

—

MCKO Low to MDO Data Valid⁴

MCKO Low to MSEO Data Valid⁴

MCKO Low to EVTO Data Valid⁴

EVTI Pulse Width

t_MDOV

t_MSEOV

t_EVTOV

t_EVTIPW

t_EVTOPW

t_TCYC

t_MCYC

t_TCYC

t_MCYC

EVTO Pulse Width

—

TCK Cycle Time

4⁵

—

t_CYC

TCK Duty Cycle

t_TDC

—

10 TDI, TMS Data Setup Time

11 TDI, TMS Data Hold Time

12 TCK Low to TDO Data Valid

13 RDY Valid to MCKO⁶

t_NTDIS,t_NTMSS

_NTDIH,t_NTMSH

t_NTDOV

—

All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Nexus timing specified

at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and C_L= 30 pF with

DSC = 0b10.

The Nexus AUX port runs up to 82 MHz (pending characterization). Set NPC_PCR[MKCO_DIV] to correct division depending

on the system frequency, not to exceed maximum Nexus AUX port frequency.

See Notes on t_cycin Table 28 in Section 4.11.1 Clocking.

MDO, MSEO, and EVTO data is held valid until next MCKO low cycle.

Lower frequency is required to be fully compliant to standard.

The RDY pin timing is asynchronous to MCKO. The timing is guaranteed by design to function correctly.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

MCKO

MDO

Output Data Valid

MSEO

EVTO

EVTI

Figure 25. Nexus Timings

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

TCK

TMS, TDI

TDO

Figure 26. Nexus TCK, TDI, TMS, TDO Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.12.5 External Bus Interface (EBI) Timing

Table 36. Bus Operation Timing

66 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Notes

Min

Max

D_CLKOUT Period

t_C

15.2

45%

—

ns Signals are measured at 50% V_DDE

D_CLKOUT Duty Cycle

D_CLKOUT Rise Time

D_CLKOUT Fall Time

t_CDC

t_CRT

t_CFT

t_COH

55%

t_C

—

D_CLKOUT Posedge to Output

Signal Invalid or High Z (Hold Time)

1.0/1.5

—

ns Hold time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 1.0 ns

D_ADD[9:30]

D_BDIP

EBTS = 1: 1.5 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

D_CLKOUT Posedge to Output

Signal Valid (Output Delay)

t_COV

—

7.0/7.5

ns Output valid time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0: 7.0 ns

D_ADD[9:30]

D_BDIP

EBTS = 1: 7.5 ns

D_CS[0:3]

D_DAT[0:15]

D_OE

D_RD_WR

D_TA

D_TS

D_WE[0:3]/D_BE[0:3]

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

Table 36. Bus Operation Timing (continued)

66 MHz (Ext. Bus Freq)^{2 3}

Spec

Characteristic

Symbol

Unit

Notes

Min

Max

Input Signal Valid to D_CLKOUT

Posedge (Setup Time)

t_CIS

5.0/4.5

—

ns Input setup time selectable via

SIU_ECCR[EBTS] bit:

EBTS = 0; 5.0ns

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

EBTS = 1; 4.5ns

D_TS

D_CLKOUT Posedge to Input

Signal Invalid (Hold Time)

t_CIH

1.0

—

D_ADD[9:30]

D_DAT[0:15]

D_RD_WR

D_TA

D_TS

D_ALE Pulse Width

t_APW

t_AAI

6.5

—

ns The timing is for Asynchronous

external memory system.

10 D_ALE Negated to Address Invalid

2.0/1.0 ⁵

ns The timing is for Asynchronous

external memory system.

ALE is measured at 50% of VDDE.

EBI timing specified at V_DD= 1.08 V to 1.32 V, V_DDE= 3.0 V to 3.6 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H, and

C_L= 30 pF with DSC = 0b10.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation (FM).

270 MHz parts allow for 264 MHz system clock + 2% FM.

Depending on the internal bus speed, set the SIU_ECCR[EBDF] bits correctly not to exceed maximum external bus frequency.

The maximum external bus frequency is 66 MHz.

Refer to Fast pad timing in Table 31 and Table 32.

ALE hold time spec is temperature dependant. 1.0 ns spec applies for temperature range -40 to 0 °C. 2.0 ns spec applies to

temperatures > 0 °C. This spec has no dependency on SIU_ECCR[EBTS] bit.

V_{OH_F}

V_DDE/ 2

V_{OL_F}

D_CLKOUT

Figure 27. D_CLKOUT Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

V_DDE/ 2

D_CLKOUT

Output

Bus

V_DDE/ 2

Output

Signal

V_DDE/ 2

Output

Signal

V_DDE/ 2

Figure 28. Synchronous Output Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

D_CLKOUT

V_DDE/ 2

Input

Bus

V_DDE/ 2

Input

Signal

V_DDE/ 2

Figure 29. Synchronous Input Timing

ipg_clk

D_CLKOUT

D_ALE

D_TS

D_ADD/D_DAT

DATA

ADDR

Figure 30. ALE Signal Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

4.12.6 External Interrupt Timing (IRQ Pin)

Table 37. External Interrupt Timing

Spec

Characteristic

IRQ Pulse Width Low

Symbol

Min

Max

Unit

t_IPWL

t_IPWH

t_ICYC

—

t_cyc

IRQ Pulse Width High

t_cyc

IRQ Edge to Edge Time³

t_cyc

IRQ timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_L

to T_H.

See Notes on t_cycon Figure 16 and Table 28 in Section 4.11.1 Clocking.

Applies when IRQ pins are configured for rising edge or falling edge events, but not both.

IRQ

Figure 31. External Interrupt Timing

4.12.7 eTPU Timing

Table 38. eTPU Timing

Spec

Characteristic

Symbol

Min

Max

Unit

eTPU Input Channel Pulse Width

eTPU Output Channel Pulse Width

t_ICPW

—

t_cyc

t_OCPW

1³

t_cyc

eTPU timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 200 pF with SRC = 0b00.

See Notes on t_cycon Figure 16 and Table 28 in Section 4.11.1 Clocking.

This specification does not include the rise and fall times. When calculating the minimum eTPU pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

eTPU Input

and TCRCLK

eTPU

Output

Figure 32. eTPU Timing

4.12.8 eMIOS Timing

Table 39. eMIOS Timing

Spec

Characteristic

Symbol

Min

Max

Unit

eMIOS Input Pulse Width

eMIOS Output Pulse Width

t_MIPW

—

t_cyc

t_MOPW

1³

t_cyc

eMIOS timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, T_A= T_Lto T_H,

and C_L= 50 pF with SRC = 0b00.

See Notes on t_cycon Figure 16 and Table 28 in Section 4.11.1 Clocking.

This specification does not include the rise and fall times. When calculating the minimum eMIOS pulse width, include the rise

and fall times defined in the slew rate control fields (SRC) of the pad configuration registers (PCR).

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

eMIOS Input

eMIOS

Output

Figure 33. eMIOS Timing

4.12.9 DSPI Timing

1 2

Table 40. DSPI Timing

PeripheralBus Freq: 132 MHz

Spec

Characteristic

Symbol

Unit

Min

Max

DSPI Cycle Time^{3, 4}

Master (MTFE = 0)

Slave (MTFE = 0)

Master (MTFE = 1)

Slave (MTFE = 1)

t_SCK

t_SYS* 2

t_SYS*32768*7

PCS to SCK Delay⁵

t_CSC

t_ASC

—

After SCK Delay⁶

Master mode

Slave mode

t_SYS* 2

t_SYS*3 –

constraints ⁷

SCK Duty Cycle

t_SDC

t_A

0.33 * t_SCK

—

0.66 * t_SCK

Slave Access Time

(SS active to SOUT valid)

Slave SOUT Disable Time

t_DIS

—

(SS inactive to SOUT High-Z or invalid)

PCSx to PCSS time

PCSS to PCSx time

t_PCSC

t_PASC

t_SYS* 2

t_SYS* 7

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

1 2

Table 40. DSPI Timing (continued)

PeripheralBus Freq: 132 MHz

Spec

Characteristic

Symbol

Unit

Min

Max

Data Setup Time for Inputs

t_SUI

Master (MTFE = 0)

—

Slave

Master (MTFE = 1, CPHA = 0)⁸

Master (MTFE = 1, CPHA = 1)

Data Hold Time for Inputs

Master (MTFE = 0)

t_HI

t_SUO

t_HO

–3

—

Slave

Master (MTFE = 1, CPHA = 0)⁸

Master (MTFE = 1, CPHA = 1)

Data Valid (after SCK edge)

Master (MTFE = 0)

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

Data Hold Time for Outputs

Master (MTFE = 0)

–5

2.5

—

Slave

Master (MTFE = 1, CPHA = 0)

Master (MTFE = 1, CPHA = 1)

–5

DSPI timing specified at V_DD= 1.08 V to 1.32 V, V_DDEH= 3.0 V to 5.5 V, V_DD33and V_DDSYN= 3.0 V to 3.6 V, and T_A= T_Lto T_H

Speed is the nominal maximum frequency of platform clock (f_platf). Max speed is the maximum speed allowed including

frequency modulation (FM). 270 MHz parts allow for 264 Mhz for system core clock (f_sys) + 2% FM.

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARn[PSSCK] and DSPI_CTARn[CSSCK].

The maximum value is programmable in DSPI_CTARn[PASC] and DSPI_CTARn[ASC].

For example, external master should start SCK clock not earlier than 3 system clock periods after assertion SS

This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

The DSPI in this device can be configured to serialize data to an external device that implements the Microsecond Bus protocol.

DSPI pins support 5 V logic levels or Low Voltage Differential Signalling (LVDS) for data and clock signals to improve high

speed operation.

1, 2

Table 41. DSPI LVDS Timing

Characteristic

Symbol

Min

Max

Unit

LVDS Clock to Data/Chip Select Outputs

t_LVDSDATA

–0.25 ×

t_SCYC

+0.25 ×

t_SCYC

These are typical values that are estimated from simulation.

See DSPI LVDS Pad related data in Table 17.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

Last Data

SIN

First Data

Data

First Data

Last Data

SOUT

Figure 34. DSPI Classic SPI Timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL=0)

SCK Output

(CPOL=1)

Data

First Data

Last Data

SIN

SOUT

Last Data

First Data

Figure 35. DSPI Classic SPI Timing — Master, CPHA = 1

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Data

First Data

Last Data

SOUT

SIN

Data

Last Data

First Data

Figure 36. DSPI Classic SPI Timing — Slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

Data

SOUT

SIN

First Data

Last Data

First Data

Figure 37. DSPI Classic SPI Timing — Slave, CPHA = 1

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

First Data

Last Data

Data

SOUT

First Data

Data

Figure 38. DSPI Modified Transfer Format Timing — Master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

Last Data

First Data

Data

First Data

Last Data

SOUT

Figure 39. DSPI Modified Transfer Format Timing — Master, CPHA = 1

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Electrical Characteristics

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

First Data

Data

Last Data

SOUT

SIN

Last Data

First Data

Figure 40. DSPI Modified Transfer Format Timing — Slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

First Data

Data

SOUT

SIN

First Data

Last Data

Figure 41. DSPI Modified Transfer Format Timing — Slave, CPHA = 1

PCSS

PCSx

Figure 42. DSPI PCS Strobe (PCSS) Timing

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

The latest package outline drawings are available on the product summary pages on our website:

http://www.freescale.com/powerarchitecture. The following table lists the package case number. Use these numbers in the

webpage’s keyword search engine to find the latest package outline drawings.

Table 42. Package Information

Package Type

Case Outline Number

324 TEPBGA

416 TEPBGA

516 TEPBGA

98ASS23840W

98ARE10523D

98ARS10503D

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

5.1

324-Pin Package

The package drawings of the 324-pin TEPBGA package are shown in Figure 43 and Figure 44.

Figure 43. 324 TEPBGA Package (1 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

Figure 44. 324 TEPBGA Package (2 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

5.2

416-Pin Package

The package drawings of the 416-pin TEPBGA package are shown in Figure 45 and Figure 46.

Figure 45. 416 TEPBGA Package (1 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

Figure 46. 416 TEPBGA Package (2 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

5.3

516-Pin Package

The package drawings of the 516-pin TEPBGA package are shown in Figure 47 and Figure 48.

Figure 47. 516 TEPBGA Package (1 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Package Information

Figure 48. 516 TEPBGA Package (2 of 2)

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Product Documentation

This data sheet is labeled as a particular type: Product Preview, Advance Information, or Technical Data. Definitions of these

types are available at: http://www.freescale.com.

The following documents are required for a complete description of the device and are necessary to design properly with the

parts:

•

MPC5674F Microprocessor Reference Manual (document number MPC5674FRM).

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Signal Properties and Muxing

Appendix A Signal Properties and Muxing

The following table shows the signals properties for each pin on the MPC5674F. For each port pin that has an associated

SIU_PCRn register to control its pin properties, the supported functions column lists the functions associated with the

programming of the SIU_PCRn[PA] bit in the order: Primary function (P), Function 2 (F2), Function 3 (F3), and GPIO (G). See

Figure 49.

Table 2. Signal Properties Summary

GPIO/

PCR¹

Pad

I/O Type

Signal Name²

Function³

TCRCLKA

Function Summary

Primary Functions

are listed First

113 TCRCLKA_IRQ7_GPIO113

eTPU A TCR clock

5V M

IRQ7

—

External interrupt request

Secondary Functions

are alternate functions

—

I/O

GPIO Functions are

GPIO113

GPIO

listed Last

Function not implemented on this device

Figure 49. Supported Functions Example

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

Table 43. Signal Properties and Muxing Summary

Package Location

State during

RESET⁷

State

Signal Name²

Function⁴

Function Summary

after RESET⁸

eTPU_A

113 TCRCLKA_IRQ7_

TCRCLKA

eTPU A TCR clock

V_DDEH1

—/Up

GPIO113

IRQ7

External interrupt request

—

I/O

GPIO113

ETPUA0

ETPUA12

—

GPIO

114 ETPUA0_ETPUA12_

GPIO114

eTPU A channel

—/WKPCFG

eTPU A channel (output only)

—

I/O

GPIO114

ETPUA1

ETPUA13

—

GPIO

115 ETPUA1_ETPUA13_

GPIO115

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO115

ETPUA2

ETPUA14

—

GPIO

116 ETPUA2_ETPUA14_

GPIO116

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO116

ETPUA3

ETPUA15

—

GPIO

117 ETPUA3_ETPUA15_

GPIO117

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO117

ETPUA4

ETPUA16

—

GPIO

118 ETPUA4_ETPUA16_

GPIO118

eTPU A channel

eTPU A channel (output only)

—

I/O

GPIO118

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

119 ETPUA5_ETPUA17_

GPIO119

ETPUA5

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

—

ETPUA17

—

eTPU A channel (output only)

—

GPIO119

ETPUA6

ETPUA18

—

GPIO

I/O

120 ETPUA6_ETPUA18_

GPIO120

eTPU A channel

—/WKPCFG

eTPU A channel (output only)

—

GPIO120

ETPUA7

ETPUA19

—

GPIO

I/O

121 ETPUA7_ETPUA19_

GPIO121

eTPU A channel

eTPU A channel (output only)

—

GPIO121

ETPUA8

ETPUA20

—

GPIO

I/O

122 ETPUA8_ETPUA20_

GPIO122

eTPU A channel

—

eTPU A channel (output only)

—

GPIO122

ETPUA9

ETPUA21

—

GPIO

I/O

123 ETPUA9_ETPUA21_

GPIO123

eTPU A channel

eTPU A channel (output only)

—

GPIO123

ETPUA10

ETPUA22

—

GPIO

I/O

124 ETPUA10_ETPUA22_

GPIO124

eTPU A channel

eTPU A channel (output only)

—

GPIO124

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

125 ETPUA11_ETPUA23_

GPIO125

ETPUA11

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

ETPUA23

—

eTPU A channel (output only)

—

GPIO125

ETPUA12

PCSB1

—

GPIO

I/O

126 ETPUA12_PCSB1_

GPIO126

eTPU A channel

—/WKPCFG

DSPI B peripheral chip select

—

GPIO126

ETPUA13

PCSB3

—

GPIO

I/O

127 ETPUA13_PCSB3_

GPIO127

eTPU A channel

DSPI B peripheral chip select

—

GPIO127

ETPUA14

PCSB4

—

GPIO

I/O

128 ETPUA14_PCSB4_

GPIO128

eTPU A channel

DSPI B peripheral chip select

—

GPIO128

ETPUA15

PCSB5

—

GPIO

I/O

129 ETPUA15_PCSB5_

GPIO129

eTPU A channel

DSPI B peripheral chip select

—

GPIO129

ETPUA16

PCSD1

—

GPIO

I/O

130 ETPUA16_PCSD1_

GPIO130

eTPU A channel

DSPI D peripheral chip select

—

GPIO130

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

131 ETPUA17_PCSD2_

GPIO131

ETPUA17

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

—

PCSD2

—

DSPI D peripheral chip select

—

I/O

GPIO131

ETPUA18

PCSD3

—

GPIO

132 ETPUA18_PCSD3_

GPIO132

eTPU A channel

—/WKPCFG

DSPI D peripheral chip select

—

I/O

GPIO132

ETPUA19

PCSD4

—

GPIO

133 ETPUA19_PCSD4_

GPIO133

eTPU A channel

—

DSPI D peripheral chip select

—

I/O

GPIO133

ETPUA20

IRQ8

GPIO

134 ETPUA20_IRQ8_

GPIO134

eTPU A channel

External interrupt request

—

I/O

GPIO134

ETPUA21

IRQ9

GPIO

135 ETPUA21_IRQ9_

GPIO135

eTPU A channel

External interrupt request

—

I/O

GPIO135

ETPUA22

IRQ10

—

GPIO

136 ETPUA22_IRQ10_

GPIO136

eTPU A channel

External interrupt request

—

I/O

GPIO136

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

137 ETPUA23_IRQ11_

ETPUA23

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

—

GPIO137

IRQ11

—

External interrupt request

—

I/O

GPIO137

ETPUA24

IRQ12

—

GPIO

138 ETPUA24_IRQ12_

GPIO138

eTPU A channel

—/WKPCFG

External interrupt request

—

I/O

GPIO138

ETPUA25

IRQ13

—

GPIO

139 ETPUA25_IRQ13_

GPIO139

eTPU A channel

External interrupt request

—

I/O

GPIO139

ETPUA26

IRQ14

—

GPIO

140 ETPUA26_IRQ14_

GPIO140

eTPU A channel

External interrupt request

—

I/O

GPIO140

ETPUA27

IRQ15

—

GPIO

141 ETPUA27_IRQ15_

GPIO141

eTPU A channel

External interrupt request

—

I/O

GPIO141

ETPUA28

PCSC1

—

GPIO

142 ETPUA28_PCSC1_

GPIO142

eTPU A channel

DSPI C peripheral chip select

—

I/O

GPIO142

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

143 ETPUA29_PCSC2_

GPIO143

ETPUA29

eTPU A channel

I/O

V_DDEH1

—/WKPCFG

—

PCSC2

—

DSPI C peripheral chip select

—

GPIO143

ETPUA30

PCSC3

—

GPIO

I/O

144 ETPUA30_PCSC3_

GPIO144

eTPU A channel

—/WKPCFG

DSPI C peripheral chip select

—

GPIO144

ETPUA31

PCSC4

—

GPIO

I/O

145 ETPUA31_PCSC4_

GPIO145

eTPU A channel

DSPI C peripheral chip select

—

GPIO145

GPIO

I/O

eTPU_B

146 TCRCLKB_IRQ6_

GPIO146

TCRCLKB

IRQ6

eTPU B TCR clock

V_DDEH6

—/Up

P19

N19

R19

T23

T24

T25

V25

V26

U22

External interrupt request

—

I/O

GPIO146

ETPUB0

ETPUB16

—

GPIO

147 ETPUB0_ETPUB16_

GPIO147

eTPU B channel

—/WKPCFG

eTPU B channel (output only)

—

I/O

GPIO147

ETPUB1

ETPUB17

—

GPIO

148 ETPUB1_ETPUB17_

GPIO148

eTPU B channel

eTPU B channel (output only)

—

I/O

GPIO148

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

149 ETPUB2_ETPUB18_

GPIO149

ETPUB2

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

R22

R21

P22

P21

N22

M19

T26

R23

R24

R25

R26

P23

U23

T22

U24

U25

U26

T23

ETPUB18

—

eTPU B channel (output only)

—

GPIO149

ETPUB3

ETPUB19

—

GPIO

I/O

150 ETPUB3_ETPUB19_

GPIO150

eTPU B channel

—/WKPCFG

eTPU B channel (output only)

—

GPIO150

ETPUB4

ETPUB20

—

GPIO

I/O

151 ETPUB4_ETPUB20_

GPIO151

eTPU B channel

eTPU B channel (output only)

—

GPIO151

ETPUB5

ETPUB21

—

GPIO

I/O

152 ETPUB5_ETPUB21_

GPIO152

eTPU B channel

eTPU B channel (output only)

—

GPIO152

ETPUB6

ETPUB22

—

GPIO

I/O

153 ETPUB6_ETPUB22_

GPIO153

eTPU B channel

eTPU B channel (output only)

—

GPIO153

ETPUB7

ETPUB23

—

GPIO

I/O

154 ETPUB7_ETPUB23_

GPIO154

eTPU B channel

eTPU B channel (output only)

—

GPIO154

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

155 ETPUB8_ETPUB24_

GPIO155

ETPUB8

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

N21

M22

M20

M21

L19

P24

P25

P26

N24

N25

N26

T24

R22

T25

T26

R23

P22

ETPUB24

—

eTPU B channel (output only)

—

GPIO155

ETPUB9

ETPUB25

—

GPIO

I/O

156 ETPUB9_ETPUB25_

GPIO156

eTPU B channel

—/WKPCFG

eTPU B channel (output only)

—

GPIO156

ETPUB10

ETPUB26

—

GPIO

I/O

157 ETPUB10_ETPUB26_

GPIO157

eTPU B channel

eTPU B channel (output only)

—

GPIO157

ETPUB11

ETPUB27

—

GPIO

I/O

158 ETPUB11_ETPUB27_

GPIO158

eTPU B channel

eTPU B channel (output only)

—

GPIO158

ETPUB12

ETPUB28

—

GPIO

I/O

159 ETPUB12_ETPUB28_

GPIO159

eTPU B channel

eTPU B channel (output only)

—

GPIO159

ETPUB13

ETPUB29

—

GPIO

I/O

160 ETPUB13_ETPUB29_

GPIO160

eTPU B channel

L20

eTPU B channel (output only)

—

GPIO160

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

161 ETPUB14_ETPUB30_

GPIO161

ETPUB14

eTPU B channel

I/O

V_DDEH6

—/WKPCFG

L21

M25

M24

U26

U25

U24

U23

R24

R25

V24

T21

ETPUB30

—

eTPU B channel (output only)

—

GPIO161

ETPUB15

ETPUB31

—

GPIO

I/O

162 ETPUB15_ETPUB31_

GPIO162

eTPU B channel

—/WKPCFG

—

eTPU B channel (output only)

—

GPIO162

ETPUB16

PCSA1

—

GPIO

I/O

163 ETPUB16_PCSA1_

GPIO163

eTPU B channel

P20

R20

T20

T19

DSPI A peripheral chip select

—

GPIO163

ETPUB17

PCSA2

—

GPIO

I/O

164 ETPUB17_PCSA2_

GPIO164

eTPU B channel

DSPI A peripheral chip select

—

GPIO164

ETPUB18

PCSA3

—

GPIO

I/O

165 ETPUB18_PCSA3_

GPIO165

eTPU B channel

W26

W25

DSPI A peripheral chip select

—

GPIO165

ETPUB19

PCSA4

—

GPIO

I/O

166 ETPUB19_PCSA4_

GPIO166

eTPU B channel

DSPI A peripheral chip select

—

GPIO166

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

167 ETPUB20_

ETPUB20

eTPU B channel

I/O

—

V_DDEH6

—/WKPCFG

—

V26

V25

V24

W26

W25

W24

V22

V23

U21

Y25

GPIO167

—

GPIO167

ETPUB21

—

GPIO

I/O

—

168 ETPUB21_

GPIO168

eTPU B channel

—/WKPCFG

—

GPIO168

ETPUB22

—

GPIO

I/O

—

169 ETPUB22_

GPIO169

eTPU B channel

—

GPIO169

ETPUB23

—

GPIO

I/O

—

170 ETPUB23_

GPIO170

eTPU B channel

—

GPIO170

ETPUB24

—

GPIO

I/O

—

171 ETPUB24_

GPIO171

eTPU B channel

—

GPIO171

ETPUB25

—

GPIO

I/O

—

172 ETPUB25_

GPIO172

eTPU B channel

W24 W21

—

GPIO172

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

173 ETPUB26_

ETPUB26

eTPU B channel

I/O

—

V_DDEH6

—/WKPCFG

—

V23

Y25

Y23

Y24

GPIO173

—

GPIO173

ETPUB27

—

GPIO

I/O

—

174 ETPUB27_

GPIO174

eTPU B channel

—/WKPCFG

—

GPIO174

ETPUB28

—

GPIO

I/O

—

175 ETPUB28_

GPIO175

eTPU B channel

Y24 AA24

—

GPIO175

ETPUB29

—

GPIO

I/O

—

176 ETPUB29_

GPIO176

eTPU B channel

Y23

W22

—

GPIO176

ETPUB30

—

GPIO

I/O

—

177 ETPUB30_

GPIO177

eTPU B channel

U20 AA24 AB24

—

GPIO177

ETPUB31

—

GPIO

I/O

—

178 ETPUB31_

GPIO178

eTPU B channel

U19 AB24 Y22

—

GPIO178

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

GPIO, IRQ, FlexRay

440 TCRCLKC_

—

V_DDEH7

—/Up

B22

C21

D20

D22

D21

E22

B26

C25

C26

D25

D26

E24

F22

C25

C26

D25

D26

E24

GPIO440⁹

—

GPIO440

GPIO

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

441 ETPUC0_

GPIO441⁹

—

—/WKPCFG

—

GPIO441

GPIO

—

442 ETPUC1_

GPIO442⁹

—

GPIO442

GPIO

—

443 ETPUC2_

GPIO443⁹

—

GPIO443

GPIO

—

444 ETPUC3_

GPIO444⁹

—

GPIO444

GPIO

—

445 ETPUC4_

GPIO445⁹

—

GPIO445

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

446 ETPUC5_

—

I/O

—

I/O

—

I/O

—

I/O

—

I/O

—

V_DDEH7

—/WKPCFG

E19

E25

E26

F23

F24

F25

F26

E25

E26

F23

F24

F25

F26

GPIO446⁹

—

GPIO446

GPIO

—

447 ETPUC6_

GPIO447⁹

—

—/WKPCFG

—

GPIO447

GPIO

—

448 ETPUC7_

GPIO448⁹

—

GPIO448

—

GPIO

—

449 ETPUC8_

GPIO449⁹

—

GPIO449

—

GPIO

—

450 ETPUC9_IRQ0_

GPIO450⁹

F22

E20

IRQ0

—

External interrupt request

—

I/O

—

GPIO450

—

GPIO

451 ETPUC10__IRQ1_

GPIO451⁹

—

IRQ1

—

External interrupt request

—

I/O

GPIO451

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

452 ETPUC11_IRQ2_

—

V_DDEH7

—/WKPCFG

E21

F19

F21

F20

—

G23

G24

G25

G26

H23

H24

G22

G23

G24

G25

G26

H22

GPIO452⁹

IRQ2

—

External interrupt request

—

I/O

—

GPIO452

—

GPIO

453 ETPUC12_IRQ3_

GPIO453⁹

—

—/WKPCFG

IRQ3

—

External interrupt request

—

I/O

—

GPIO453

—

GPIO

454 ETPUC13_3_IRQ4_

GPIO454⁹

—

IRQ4

—

External interrupt request

—

I/O

—

GPIO454

—

GPIO

455 ETPUC14_4_IRQ5_

GPIO455⁹

—

IRQ5

—

External interrupt request

—

I/O

—

I/O

—

GPIO455

—

GPIO

456 ETPUC15__

GPIO456⁹

—

GPIO456

—

GPIO

457 ETPUC16_FR_A_TX_

GPIO457⁹

—

FR_A_TX

—

FlexRay A transfer

—

I/O

GPIO457

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

458 ETPUC17_FR_A_RX_

GPIO458⁹

—

V_DDEH7

—/WKPCFG

G22

G20

G21

G19

H22

H21

H25

H26

J23

J24

J25

J26

H23

H24

H21

H25

H26

J22

FR_A_RX

—

FlexRay A receive

—

I/O

—

GPIO458

—

GPIO

459 ETPUC18_FR_A_TX_EN_

GPIO459⁹

—

—/WKPCFG

FR_A_TX_EN

—

FlexRay A transfer enable

—

I/O

—

GPIO459

—

GPIO

460 ETPUC19_TXDA_

GPIO460⁹

—

TXDA

—

eSCI A transmit

—

I/O

—

GPIO460

—

GPIO

461 ETPUC20_RXDA _

GPIO461⁹

—

RXDA

—

eSCI A receive

—

I/O

—

GPIO461

—

GPIO

462 ETPUC21_TXDB_

GPIO462⁹

—

TXDB

—

eSCI B transmit

—

I/O

—

GPIO462

—

GPIO

463 ETPUC22_RXDB_

GPIO463⁹

—

RXDB

—

eSCI B receive

—

I/O

GPIO463

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

464 ETPUC23_PCSD5_

GPIO464⁹

—

V_DDEH7

—/WKPCFG

H20

J22

K22

K23

K24

K25

J23

J24

K21

PCSD5

MAA0

MAB0

GPIO464

—

DSPI D peripheral chip select

ADC A Mux Address 0

ADC B Mux Address 0

GPIO

I/O

—

465 ETPUC24_PCSD4_

GPIO465⁹

—

—/WKPCFG

PCSD4

MAA1

MAB1

GPIO465

—

DSPI D peripheral chip select

ADC A Mux Address 1

ADC B Mux Address 1

GPIO

I/O

—

466 ETPUC25_PCSD3_

GPIO466⁹

—

PCSD3

MAA2

MAB2

GPIO466

—

DSPI D peripheral chip select

ADC A Mux Address 2

ADC B Mux Address 2

GPIO

I/O

—

467 ETPUC26_PCSD2_

GPIO467⁹

—

V_DDEH7

—/WKPCFG

J21

J19

J20

K26

L23

L24

J25

J26

K22

PCSD2

—

DSPI D peripheral chip select

—

I/O

—

GPIO467

—

GPIO

468 ETPUC27_PCSD1_

GPIO468⁹

—

PCSD1

—

DSPI D peripheral chip select

—

I/O

—

I/O

—

I/O

GPIO468

—

GPIO

469 ETPUC28_PCSD0_

GPIO469⁹

—

PCSD0

—

DSPI D peripheral chip select

—

GPIO469

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

470 ETPUC29_SCKD_

—

I/O

—

I/O

—

V_DDEH7

—/WKPCFG

K21

K20

K19

L25

L26

M23

K23

K24

K25

GPIO470⁹

SCKD

—

DSPI D clock

—

GPIO470

—

GPIO

471 ETPUC30_SOUTD_

GPIO471⁹

—

—/WKPCFG

SOUTD

—

DSPI D data output

—

I/O

—

GPIO471

—

GPIO

472 ETPUC31_SIND_

GPIO472⁹

—

SIND

—

DSPI D data input

—

I/O

GPIO472

GPIO

eMIOS

179 EMIOS0_ETPUA0_

GPIO179

EMIOS0

ETPUA0

—

eMIOS channel

eTPU A channel

—

I/O

V_DDEH4

—/WKPCFG

AA9 AE10 AC13

AB9 AF10 AB13

Y10 AD11 AD13

—

GPIO179

EMIOS1

ETPUA1

—

GPIO

I/O

180 EMIOS1_ETPUA1_

GPIO180

eMIOS channel

eTPU A channel

—

GPIO180

EMIOS2

ETPUA2

—

GPIO

I/O

181 EMIOS2_ETPUA2_

GPIO181

eMIOS channel

eTPU A channel

—

GPIO181

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

182 EMIOS3_ETPUA3_

GPIO182

EMIOS3

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AA10 AE11 AE13

ETPUA3

—

eTPU A channel

—

GPIO182

EMIOS4

ETPUA4

—

GPIO

I/O

183 EMIOS4_ETPUA4_

GPIO183

eMIOS channel

eTPU A channel

—

—/WKPCFG

—/WKPCFG AB10 AF11 AF13

—

GPIO183

EMIOS5

ETPUA5

—

GPIO

I/O

184 EMIOS5_ETPUA5_

GPIO184

eMIOS channel

eTPU A channel

—

—/WKPCFG

Y11 AD12 AF14

—

GPIO184

EMIOS6

ETPUA6

—

GPIO

I/O

185 EMIOS6_ETPUA6_

GPIO185

eMIOS channel

eTPU A channel

—

AE12 AE14

—

GPIO185

EMIOS7

ETPUA7

—

GPIO

I/O

186 EMIOS7_ETPUA7_

GPIO186

eMIOS channel

eTPU A channel

—

—/WKPCFG AB11 AF12 AD14

—

GPIO186

EMIOS8

ETPUA8

—

GPIO

I/O

187 EMIOS8_ETPUA8_

GPIO187

eMIOS channel

eTPU A channel

—

—/WKPCFG

W10 AC13 AC14

—

GPIO187

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

188 EMIOS9_ETPUA9_

GPIO188

EMIOS9

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

W11 AD13 AF15

ETPUA9

—

eTPU A channel

—

I/O

GPIO188

EMIOS10

SCKD

GPIO

189 EMIOS10_SCKD_

GPIO189

eMIOS channel

DSPI D clock

—

—/WKPCFG

—/WKPCFG AA11 AE13 AE15

—/WKPCFG AB12 AF13 AB14

—/WKPCFG AB13 AF14 AD15

—/WKPCFG AA12 AE14 AC15

—

I/O

GPIO189

EMIOS11

SIND

GPIO

190 EMIOS11_SIND_

GPIO190

eMIOS channel

DSPI D data input

—

I/O

GPIO190

EMIOS12

SOUTC

—

GPIO

191 EMIOS12_SOUTC_

GPIO191

eMIOS channel

DSPI C data output

—

I/O

GPIO191

EMIOS13

SOUTD

—

GPIO

192 EMIOS13_SOUTD_

GPIO192

eMIOS channel

DSPI D data output

—

I/O

GPIO192

EMIOS14

IRQ0

GPIO

193 EMIOS14_IRQ0_

GPIO193

eMIOS channel

External interrupt request

FlexCAN D transmit

GPIO

—/WKPCFG

Y12 AC14 AF17

CNTXD

GPIO193

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

194 EMIOS15_IRQ1_

EMIOS15

eMIOS channel

V_DDEH4

—/WKPCFG

Y13 AD14 AE16

GPIO194

IRQ1

External interrupt request

FlexCAN D receive

GPIO

CNRXD

GPIO194

EMIOS16

ETPUB0

FR_DBG[3]

GPIO195

EMIOS17

ETPUB1

FR_DBG[2]

GPIO196

EMIOS18

ETPUB2

FR_DBG[1]

GPIO197

EMIOS19

ETPUB3

FR_DBG[0]

GPIO198

EMIOS20

ETPUB4

—

I/O

195 EMIOS16_ETPUB0_

GPIO195

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

—/WKPCFG

—/WKPCFG AB14 AF15 AD16

I/O

196 EMIOS17_ETPUB1_

GPIO196

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

—/WKPCFG AA13 AE15 AB15

I/O

197 EMIOS18_ETPUB2_

GPIO197

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

—/WKPCFG

W12 AC15 AD17

I/O

198 EMIOS19_ETPUB3_

GPIO198

eMIOS channel

eTPU B channel

FlexRay debug

GPIO

Y14 AD15 AB16

I/O

199 EMIOS20_ETPUB4_

GPIO199

eMIOS channel

eTPU B channel

—

—/WKPCFG AB15 AF16 AF16

—

I/O

GPIO199

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

200 EMIOS21_ETPUB5_

GPIO200

EMIOS21

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

—/WKPCFG AA14 AE16 AE17

ETPUB5

—

eTPU B channel

—

GPIO200

EMIOS22

ETPUB6

—

GPIO

I/O

201 EMIOS22_ETPUB6_

GPIO201

eMIOS channel

—/WKPCFG

W13 AC16 AC16

eTPU B channel

—

GPIO201

EMIOS23

ETPUB7

—

GPIO

I/O

202 EMIOS23_ETPUB7_

GPIO202

eMIOS channel

Y15 AD16 AA16

eTPU B channel

—

GPIO202

EMIOS24

PCSB0

—

GPIO

I/O

—

203 EMIOS24_PCSB0_

GPIO203

eMIOS channel

—/WKPCFG AB16 AF17 AC17

DSPI B peripheral chip select

—

GPIO203

EMIOS25

PCSB1

—

GPIO

I/O

204 EMIOS25_PCSB1_

GPIO204

eMIOS channel

—/WKPCFG AA15 AE17 AF18

DSPI B peripheral chip select

—

GPIO204

EMIOS26

PCSB2

—

GPIO

I/O

432 EMIOS26_PCSB2_

GPIO432

eMIOS channel

—/WKPCFG

Y16 AD17 AE18

DSPI B peripheral chip select

—

GPIO432

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

433 EMIOS27_PCSB3_

GPIO433

EMIOS27

eMIOS channel

I/O

V_DDEH4

—/WKPCFG

W14 AC17 AD18

PCSB3

—

DSPI B peripheral chip select

—

GPIO433

EMIOS28

PCSC0

—

GPIO

I/O

—

434 EMIOS28_PCSC0_

GPIO434

eMIOS channel

—/WKPCFG

—/WKPCFG AA16 AF18 AC18

DSPI C peripheral chip select

—

GPIO434

EMIOS29

PCSC1

—

GPIO

I/O

435 EMIOS29_PCSC1_

GPIO435

eMIOS channel

—/WKPCFG AA17 AE18 AB17

DSPI C peripheral chip select

—

GPIO435

EMIOS30

PCSC2

—

GPIO

I/O

436 EMIOS30_PCSC2_

GPIO436

eMIOS channel

—/WKPCFG

Y17 AD18 AF19

DSPI C peripheral chip select

—

GPIO436

EMIOS31

PCSC5

—

GPIO

I/O

437 EMIOS31_PCSC5_

GPIO437

eMIOS channel

W15 AC18 AA17

DSPI C peripheral chip select

—

GPIO437

GPIO

I/O

eQADC

ANA0¹⁰

ANA1¹⁰

ANA2¹⁰

eQADC A analog input

AE/up- V_{DDA_A1}

down

ANA0

ANA1

ANA2

ANA0

ANA1

ANA2

—

ANA0

ANA1

ANA2

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

—

ANA3

ANA4

ANA5

ANA6

ANA7

ANA3¹⁰

eQADC A analog input

AE/up- V_{DDA_A1}

down

ANA3

ANA4

ANA5

ANA6

ANA7

ANA3

ANA4

ANA5

ANA6

ANA7

ANA4¹⁰

ANA5¹⁰

ANA6¹⁰

ANA7¹⁰

eQADC A analog input

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

AE/up- V_{DDA_A1}

down

—

ANA8

ANA9

ANA8

eQADC A analog input

eQADC A and B shared analog input

V_{DDA_A1}

V_{DDA_A0}

ANA8

ANA9

ANA8

ANA9

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

ANA10

ANA11

ANA12

ANA13

ANA14

ANA15

ANA16

ANA17

ANA18

ANA19

ANA20

ANA21

ANA22

ANA23

AN24

D10

C10

D11

C11

D12

C12

—

D10

C10

D11

C11

D12

C12

B12

D13

C13

D10

C10

D11

C11

C12

D12

B12

C13

D13

AN25

—

AN26

—

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

—

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

AN27

eQADC A and B shared analog input

eQADC B analog input

V_{DDA_A0}

V_{DDA_B1}

V_{DDA_B0}

V_{DDA_B1}

V_{DDA_B0}

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

—

B15

B13

A13

B14

C14

D14

A14

B15

C15

D15

A15

C16

C17

D16

C18

B13

A13

A14

B14

C14

B15

D14

C15

D15

A15

C17

D16

C16

C18

AN28

AN29

AN30

AN31

AN32

AN33

AN34

AN35

AN36

AN37

AN38

AN39

ANB0

AE/up- V_{DDA_B0}

down

—

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

ANB8

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

ANB8

eQADC B analog input

AE/up- V_{DDA_B0}

down

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

ANB8

ANB1

ANB2

ANB3

ANB4

ANB5

ANB6

ANB7

ANB8

B16

A17

A18

B17

B18

A19

A20

D13

D17

D18

D19

C19

C20

B19

A20

B20

D17

D18

D19

B19

A20

C20

C19

B20

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

AE/up- V_{DDA_B0}

down

V_{DDA_B0}

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

—

ANB9

eQADC B analog input

V_{DDA_B0}

V_{RH_A}

ANB9

ANB10

ANB9

ANB10

C14

C13

C15

C16

D14

C17

D15

C18

D16

D17

B19

C19

D18

A21

B20

A10

A11

A16

A15

B12

B11

D20

B21

A21

C21

D21

A22

B22

C22

A23

B23

C23

D22

A24

B24

A25

A12

A11

A19

A18

B18

B11

A21

B21

C21

A22

B22

D20

C22

D21

D22

A23

B23

C23

A24

B24

E20

A12

A11

A19

A18

B18

B11

ANB10

eQADC B analog input

ANB11

eQADC B analog input

ANB11

ANB12

eQADC B analog input

ANB12

ANB13

eQADC B analog input

ANB13

ANB14

eQADC B analog input

ANB14

ANB15

eQADC B analog input

ANB15

ANB16

eQADC B analog input

ANB16

ANB17

eQADC B analog input

ANB17

ANB18

eQADC B analog input

ANB18

ANB19

eQADC B analog input

ANB19

ANB20

eQADC B analog input

ANB20

ANB21

eQADC B analog input

ANB21

ANB22

eQADC B analog input

ANB22

ANB23

eQADC B analog input

ANB23

VRH_A

VRL_A

ADC A Voltage reference high

ADC A Voltage reference low

ADC B Voltage reference high

ADC B Voltage reference low

ADC B Reference bypass capacitor

ADC A Reference bypass capacitor

Internal logic supply input

ADC A Reference bypass capacitor

Ground

VDDINT

VSSINT

VDDINT

VSSINT

VRH_A

VRL_A

VRH_A

VRL_A

V_{RL_A}

VRL_A

VRH_B

VRL_B

V_{RH_B}

VRH_B

VRL_B

VRH_B

VRL_B

V_{RL_B}

VRL_B

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCA1

VSSA_A1

VDDA_B0

VDDA_B1

REFBYPCB

REFBYPCA

VDDA_A

REFBYPCA1

VSSA_A

VDDA_B

V_{DDA_B0}

V_{DDA_A1}

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCB

REFBYPCA

VDDA_A0

VDDA_A1

REFBYPCA1

VSSA_A1

VDDA_B0

VDDA_B1

VDDE V_{DDA_A0}

VDDE V_{DDA_A1}

V_{DDA_A1}REFBYPCA1

A12

B10

A13

B13

A10

B10

A16

B16

A10

B10

A16

B16

VSSE V_{SSA_A1}

VDDE V_{DDA_B0}

VDDE V_{DDA_B1}

VSSA_A1

VDDA_B0

VDDA_B1

Internal logic supply input

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

—

VSSA_B0

REFBYPCB1

VSSA_B

Ground

VSSE V_{SSA_B0}

VSSA_B0

B14

A14

B17

A17

B17

A17

REFBYPCB1

ADC B Reference bypass capacitor

V_{DDA_B0}REFBYPCB1

REFBYPCB1

FlexRay

248 FR_A_TX_

GPIO248

FR_A_TX

FlexRay A transfer

—

I/O

V_DDE2

—/Up

AA4

AB3

AD4

AE3

AF3

AD5

AE4

AD4

AE3

AF3

AD5

AE4

(–/– for Rev.1of (–/– for Rev.1 of

the device)

—

the device)

—

GPIO248

FR_A_RX

—

GPIO

249 FR_A_RX_

GPIO249

FlexRay A receive

—/Up

(–/– for Rev.1of (–/– for Rev.1 of

the device)

—

I/O

the device)

—

GPIO249

FR_A_TX_EN

—

GPIO

250 FR_A_TX_EN_

GPIO250

FlexRay A transfer enable

—/Up

(–/– for Rev.1of (–/– for Rev.1 of

the device)

—

I/O

the device)

—

GPIO250

FR_B_TX

—

GPIO

251 FR_B_TX_

GPIO251

FlexRay B transfer

—/Up

(–/– for Rev.1of (–/– for Rev.1 of

the device)

—

I/O

the device)

—

GPIO251

FR_B_RX

—

GPIO

252 FR_B_RX_

GPIO252

FlexRay B receive

—/Up

AA5

(–/– for Rev.1of (–/– for Rev.1 of

the device) the device)

—

I/O

—

GPIO252

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

253 FR_B_TX_EN_

FR_B_TX_EN

FlexRay B transfer enable

—

I/O

V_DDE2

—/Up

AB5

AF4

GPIO253

(–/– for Rev.1of (–/– for Rev.1 of

the device) the device)

—

GPIO253

GPIO

FlexCAN

83 CNTXA_TXDA_

GPIO83

CNTXA

TXDA

—

FlexCAN A transmit

V_DDEH4

—/Up

AB17 AF19 AE19

AA18 AE19 AD19

Y18 AD19 AC19

W18 AC19 AA19

W16 AF20 AF20

eSCI A transmit

—

I/O

GPIO83

CNRXA

RXDA

—

GPIO

84 CNRXA_RXDA_

GPIO84

FlexCAN A receive

—/Up

eSCI A receive

—

I/O

GPIO84

CNTXB

PCSC3

—

GPIO

85 CNTXB_PCSC3_

GPIO85

FlexCAN B transmit

—/Up

DSPI C peripheral chip select

—

I/O

GPIO85

CNRXB

PCSC4

—

GPIO

86 CNRXB_PCSC4_

GPIO86

FlexCAN B receive

—/Up

DSPI C peripheral chip select

—

I/O

GPIO86

CNTXC

PCSD3

—

GPIO

87 CNTXC_PCSD3_

GPIO87

FlexCAN C transmit

—/Up

DSPI D peripheral chip select

—

I/O

GPIO87

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

88 CNRXC_PCSD4_

CNRXC

FlexCAN C receive

V_DDEH4

—/Up

W17 AE20 AE20

GPIO88

PCSD4

—

DSPI D peripheral chip select

—

I/O

GPIO88

CNTXD

—

GPIO

246 CNTXD_

GPIO246

FlexCAN D transmit

—/Up

AB21 AD20 AD20

—

I/O

—

GPIO246

CNRXD

—

GPIO

247 CNRXD_

GPIO247

FlexCAN D receive

Y19 AC20 AC20

—

I/O

—

GPIO247

GPIO

eSCI

89 TXDA_

GPIO89

TXDA

—

eSCI A transmit

—

I/O

V_DDEH1

—/Up

—

GPIO89

RXDA

—

GPIO

90 RXDA _

GPIO90

eSCI A receive

—

GPIO90

TXDB

PCSD1

—

GPIO

91 TXDB_PCSD1_

GPIO91

eSCI B transmit

DSPI D peripheral chip select

—

I/O

GPIO91

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

92 RXDB_PCSD5_

RXDB

eSCI B receive

V_DDEH1

V_DDEH4

V_DDEH5

—/Up

—

GPIO92

PCSD5

—

DSPI D peripheral chip select

—

I/O

GPIO92

TXDC

ETRIG0

—

GPIO

244 TXDC_ETRIG0_

GPIO244

eSCI C transmit

—/Up

AF23 AF23

eQADC trigger input

—

I/O

GPIO244

RXDC

—

GPIO

245 RXDC_

GPIO245

eSCI C receive

AD22 AD22

—

I/O

—

GPIO245

GPIO

DSPI

93 SCKA_PCSC1_

GPIO93

SCKA

PCSC1

—

DSPI A clock

I/O

V_DDEH3

—/Up

AD8

AF7

AD7

AB8

AE7

AC7

DSPI C peripheral chip select

—

I/O

GPIO93

SINA

GPIO

94 SINA_PCSC2_

GPIO94

DSPI A data input

AA7

AB7

PCSC2

—

DSPI C peripheral chip select

—

I/O

GPIO94

SOUTA

PCSC5

—

GPIO

95 SOUTA_PCSC5_

GPIO95

DSPI A data output

DSPI C peripheral chip select

—

I/O

GPIO95

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

96 PCSA0_PCSD2_

PCSA0

DSPI A peripheral chip select

I/O

V_DDEH3

—/Up

AB6

AE6

AC6

AC7

AE7

AE5

AD6

AC6

AF6

AD7

AE5

AA8

GPIO96

PCSD2

—

DSPI D peripheral chip select

—

I/O

GPIO96

PCSA1

—

GPIO

97 PCSA1_

GPIO97

DSPI A peripheral chip select

—/Up

—

I/O

—

GPIO97

PCSA2

—

GPIO

98 PCSA2_

GPIO98

DSPI A peripheral chip select

—

I/O

—

GPIO98

PCSA3

—

GPIO

99 PCSA3_

GPIO99

DSPI A peripheral chip select

—

I/O

—

GPIO99

PCSA4

—

GPIO

100 PCSA4_

GPIO100

DSPI A peripheral chip select

—

I/O

—

GPIO100

PCSA5

ETRIG1

—

GPIO

101 PCSA5_ETRIG1_

GPIO101

DSPI A peripheral chip select

AA6

eQADC trigger input

—

I/O

GPIO101

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

102 SCKB_

GPIO102

SCKB

DSPI B clock

I/O

—

I/O

V_DDEH3

—/Up

AA8

AB8

AE8

AE9

AC8

AB9

—

GPIO102

SINB

GPIO

103 SINB_

DSPI B data input

—/Up

GPIO103

—

I/O

—

GPIO103

SOUTB

—

GPIO

104 SOUTB_

GPIO104

DSPI B data output

AF9 AA10

—

I/O

—

GPIO104

PCSB0

PCSD2

—

GPIO

105 PCSB0_PCSD2_

GPIO105

DSPI B peripheral chip select

AD9

AC9

AF8

AE8

AD8

DSPI D peripheral chip select

—

I/O

GPIO105

PCSB1

PCSD0

—

GPIO

106 PCSB1_PCSD0_

GPIO106

DSPI B peripheral chip select

—

DSPI D peripheral chip select

I/O

—

I/O

—

GPIO106

PCSB2

SOUTC

—

GPIO

107 PCSB2_SOUTC_

GPIO107

DSPI B peripheral chip select

DSPI C data output

—

I/O

GPIO107

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

108 PCSB3_SINC_

PCSB3

DSPI B peripheral chip select

V_DDEH3

V_DDEH4

—/Up

—

AD10 AC9

GPIO108

SINC

DSPI C data input

—

I/O

GPIO108

PCSB4

SCKC

GPIO

109 PCSB4_SCKC_

GPIO109

DSPI B peripheral chip select

—/Up

AC8

AF6

AF7

AE6

DSPI C clock

I/O

—

I/O

—

GPIO109

PCSB5

PCSC0

—

GPIO

110 PCSB5_PCSC0_

GPIO110

DSPI B peripheral chip select

DSPI C peripheral chip select

I/O

—

I/O

—

GPIO110

SCKC

GPIO

235 SCKC_SCK_C_LVDSP_

GPIO235

DSPI C clock

MH+

LVDS

AA19 AD21 AD21

AA20 AE22 AE22

AB18 AF21 AF21

SCK_C_LVDSP

LVDS+ downstream signal positive

output clock

—

I/O

GPIO235

SINC

GPIO

236 SINC_SCK_C_LVDSM_

GPIO236

DSPI C data input

MH+

LVDS

V_DDEH4

—/Up

SCK_C_LVDSM

LVDS– downstream signal negative

output clock

—

I/O

GPIO236

SOUTC

GPIO

237 SOUTC_SOUT_C_LVDSP_

GPIO237

DSPI C data output

MH+

LVDS

V_DDEH4

SOUT_C_LVDSP

LVDS+ downstream signal positive

output data

—

GPIO237

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

238 PCSC0_SOUT_C_LVDSM_

GPIO238

PCSC0

DSPI C peripheral chip select

I/O

MH+

LVDS

V_DDEH4

—/Up

AB19 AE21 AE21

SOUT_C_LVDSM

LVDS– downstream signal negative

output data

—

I/O

GPIO238

PCSC1

—

GPIO

239 PCSC1_

GPIO239

DSPI C peripheral chip select

V_DDEH4

V_DDEH5

—/Up

—

AC22 AC22

AE23 AE23

AD23 AD23

AF24 AF24

AE24 AE24

—

I/O

—

GPIO239

PCSC2

—

GPIO

240 PCSC2_GPIO240

241 PCSC3_GPIO241

242 PCSC4_GPIO242

243 PCSC5_GPIO243

DSPI C peripheral chip select

—

I/O

—

GPIO240

PCSC3

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO241

PCSC4

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO242

PCSC5

—

GPIO

DSPI C peripheral chip select

—

I/O

—

GPIO243

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

EBI

256 D_CS0_

D_CS0

EBI chip select 0

—

I/O

V_DDE9

—/Up

—

AD9

GPIO256

—

GPIO256

D_CS2

GPIO

257 D_CS2_D_ADD_DAT31_

GPIO257

EBI chip select 2

V_DDE8

—/Up

D_ADD_DAT31

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

—

I/O

GPIO257

D_CS3

D_TEA

—

GPIO

258 D_CS3_D_TEA_

GPIO258

EBI chip select 3

V_DDE8

—/Up

—

EBI transfer error acknowledge

—

GPIO258

D_ADD12

—

GPIO

I/O

—

259 D_ADD12_

GPIO259

EBI address bus

—

GPIO259

D_ADD13

—

GPIO

I/O

—

260 D_ADD13_

GPIO260

EBI address bus

—

GPIO260

D_ADD14

—

GPIO

I/O

—

261 D_ADD14_

GPIO261

EBI address bus

—

GPIO261

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

262 D_ADD15_

D_ADD15

EBI address bus

I/O

—

V_DDE8

—/Up

—

GPIO262

—

GPIO262

D_ADD16

D_ADD_DAT16

GPIO

I/O

263 D_ADD16_D_ADD_DAT16_

GPIO263

EBI address bus

V_DDE8

—/Up

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO263

D_ADD17

D_ADD_DAT17

GPIO

I/O

264 D_ADD17_D_ADD_DAT17_

GPIO264

EBI address bus

V_DDE8

—/Up

—

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO264

D_ADD18

D_ADD_DAT18

GPIO

I/O

265 D_ADD18_D_ADD_DAT18_

GPIO265

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO265

D_ADD19

D_ADD_DAT19

GPIO

I/O

266 D_ADD19_D_ADD_DAT19_

GPIO266

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO266

D_ADD20

D_ADD_DAT20

GPIO

I/O

267 D_ADD20_D_ADD_DAT20_

GPIO267

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO267

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

268 D_ADD21_D_ADD_DAT21_

GPIO268

D_ADD21

EBI address bus

I/O

V_DDE9

—/Up

—

AB11

AD10

AE10

AF10

AD11

D_ADD_DAT21

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO268

D_ADD22

D_ADD_DAT22

GPIO

I/O

269 D_ADD22_D_ADD_DAT22_

GPIO269

EBI address bus

—/Up

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO269

D_ADD23

D_ADD_DAT23

GPIO

I/O

270 D_ADD23_D_ADD_DAT23_

GPIO270

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO270

D_ADD24

D_ADD_DAT24

GPIO

I/O

271 D_ADD24_D_ADD_DAT24_

GPIO271

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO271

D_ADD25

D_ADD_DAT25

GPIO

I/O

272 D_ADD25_D_ADD_DAT25_

GPIO272

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO272

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

273 D_ADD26_D_ADD_DAT26_

GPIO273

D_ADD26

EBI address bus

I/O

V_DDE9

—/Up

—

AE11

AF11

AD12

AB12

AE12

D_ADD_DAT26

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO273

D_ADD27

D_ADD_DAT27

GPIO

I/O

274 D_ADD27_D_ADD_DAT27_

GPIO274

EBI address bus

—/Up

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO274

D_ADD28

D_ADD_DAT28

GPIO

I/O

275 D_ADD28_D_ADD_DAT28_

GPIO275

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO275

D_ADD29

D_ADD_DAT29

GPIO

I/O

276 D_ADD29_D_ADD_DAT29_

GPIO276

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO276

D_ADD30

D_ADD_DAT30

GPIO

I/O

277 D_ADD30_D_ADD_DAT30_

GPIO277

EBI address bus

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO277

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

278 D_ADD_DAT0_

D_ADD_DAT0

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

P25

P26

N24

N25

N26

GPIO278

—

GPIO278

D_ADD_DAT1

GPIO

I/O

279 D_ADD_DAT1_

GPIO279

EBI data only in non-mux mode.

Address and data in mux mode.

—/Up

—

GPIO279

D_ADD_DAT2

GPIO

I/O

280 D_ADD_DAT2_

GPIO280

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO280

D_ADD_DAT3

GPIO

I/O

281 D_ADD_DAT3_

GPIO281

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO281

D_ADD_DAT4

GPIO

I/O

282 D_ADD_DAT4_

GPIO282

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO282

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

283 D_ADD_DAT5_

D_ADD_DAT5

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

M25

N22

M24

M23

M22

GPIO283

—

GPIO283

D_ADD_DAT6

GPIO

I/O

284 D_ADD_DAT6_

GPIO284

EBI data only in non-mux mode.

Address and data in mux mode.

—/Up

—

GPIO284

D_ADD_DAT7

GPIO

I/O

285 D_ADD_DAT7_

GPIO285

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO285

D_ADD_DAT8

GPIO

I/O

286 D_ADD_DAT8_

GPIO286

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO286

D_ADD_DAT9

GPIO

I/O

287 D_ADD_DAT9_

GPIO287

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO287

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

288 D_ADD_DAT10_

D_ADD_DAT10

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

L26

L25

L24

L23

L22

GPIO288

—

GPIO288

D_ADD_DAT11

GPIO

I/O

289 D_ADD_DAT11_

GPIO289

EBI data only in non-mux mode.

Address and data in mux mode.

—/Up

—

GPIO289

D_ADD_DAT12

GPIO

I/O

290 D_ADD_DAT12_

GPIO290

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO290

D_ADD_DAT13

GPIO

I/O

291 D_ADD_DAT13

_GPIO291

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO291

D_ADD_DAT14

GPIO

I/O

292 D_ADD_DAT14_GPIO292

EBI data only in non-mux mode.

Address and data in mux mode.

—

GPIO292

GPIO

I/O

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

293 D_ADD_DAT15_GPIO293

D_ADD_DAT15

EBI data only in non-mux mode.

Address and data in mux mode.

I/O

V_DDE10

—/Up

—

K26

—

I/O

—

GPIO293

D_RD_WR

—

GPIO

294 D_RD_WR_GPIO294

295 D_WE0_GPIO295

296 D_WE1_GPIO296

297 D_OE_GPIO297

298 D_TS_GPIO298

EBI read/write

V_DDE10

V_DDE8

V_DDE10

V_DDE9

—/Up

—

R26

—

I/O

—

GPIO294

D_WE0

—

GPIO

EBI write enable

—

I/O

—

GPIO295

D_WE1

—

GPIO

EBI write enable

—

I/O

—

GPIO296

D_OE

—

GPIO

EBI output enable

P23

AE9

—

I/O

—

GPIO297

D_TS

—

GPIO

EBI transfer start

—

I/O

—

GPIO298

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

299 D_ALE_GPIO299

D_ALE

EBI Address Latch Enable

—

I/O

—

I/O

V_DDE10

V_DDE9

V_DDE8

—/Up

—

P24

AF9

AB10

—

GPIO299

D_TA

—

GPIO

300 D_TA_GPIO300

301 D_CS1_GPIO301

302 D_BDIP_GPIO302

303 D_WE2_GPIO303

304 D_WE3_GPIO304

EBI transfer acknowledge

—/Up

—

GPIO300

D_CS1

—

GPIO

EBI chip select

—

I/O

—

GPIO301

D_BDIP

—

GPIO

EBI burst data in progress

—

I/O

—

GPIO302

D_WE2

—

GPIO

EBI write enable

—

I/O

—

GPIO303

D_WE3

—

GPIO

EBI write enable

—

I/O

—

GPIO304

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

305 D_ADD9_GPIO305

D_ADD9

EBI address bus

I/O

—

V_DDE8

—/Up

—

GPIO305

D_ADD10

—

GPIO

I/O

—

306 D_ADD10_GPIO306

307 D_ADD11_GPIO307

EBI address bus

—/Up

—

GPIO306

D_ADD11

—

GPIO

I/O

—

EBI address bus

—

GPIO307

GPIO

I/O

Reset and Clocks

—

RESET

External reset input

External reset output

V_DDEH1

RESET/Up

230 RSTOUT

RSTOUT

V_DDEH1RSTOUT/Low

RSTOUT/

High

211 BOOTCFG0_IRQ2_

GPIO211

BOOTCFG0

IRQ2

Boot configuration

V_DDEH1

BOOTCFG/

Down

BOOTCFG/

Down

—

I/O

GPIO211

BOOTCFG1

IRQ3

GPIO

212 BOOTCFG1_IRQ3_

GPIO212

Boot configuration

V_DDEH1

BOOTCFG/

Down

Input/Down

External interrupt request

—

I/O

GPIO212

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

213 WKPCFG_NMI_

WKPCFG

Weak pull configuration input

Critical interrupt to core¹¹

—

V_DDEH1

WKPCFG/Up

Input/Up

—

GPIO213

NMI

—

GPIO213

PLLCFG0

IRQ4

GPIO

208 PLLCFG0_IRQ4_

GPIO208

FMPLL mode configuration input

External interrupt request

—

PLLCFG/Up

Input/Up

—

I/O

GPIO208

PLLCFG1

IRQ5

GPIO

209 PLLCFG1_IRQ5_

GPIO209

FMPLL mode configuration input

External interrupt request

DSPI D data output

GPIO

Input/Up

(for Rev2 of the

device: —/Up)

SOUTD

GPIO209

PLLCFG2

I/O

—

PLLCFG2

FMPLL mode configuration input

PLLCFG/

Down

PLLCFG/

Down

—

XTAL

Crystal oscillator output

Crystal oscillator input

EBI system clock output

V_DD33

V_DDE9

XTAL

W22 AC26 AC26

V22 AB26 AB26

EXTAL

229 D_CLKOUT

D_CLKOUT

CLKOUT/

Enabled

CLKOUT/

Enabled

—

AF12

214 ENGCLK

ENGCLK

EBI engineering clock output

V_DDE2

ENGCLK/

Enabled

ENGCLK/

Enabled

AA1

AD1

Note: EXTCLK (External clock input)

selected through SIU register)

JTAG and Nexus

(see footnote¹²about resets)

–

—

EVTI

227 EVTO

(the BAM uses this pin to

EVTI

Nexus event in

V_DDE2

—/Up

EVTI/Up

EVTO/HI

EVTO

Nexus event out

ABS/Up

select if auto baud rate is on or

off)

Disabled¹⁴

–

219 MCKO

MCKO

Nexus message clock out

V_DDE2

O/Low

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

–

220 MDO0_GPIO220

MDO0¹⁵

Nexus message data out

—

I/O

V_DDE2

O/Low

MDO0/Low

—/Down

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

GPIO220

MDO1¹⁵

—

GPIO

–

221 MDO1_GPIO221

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

O/Low

—

I/O

—

GPIO221

MDO2¹⁵

—

GPIO

–

222 MDO2_GPIO222

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO222

MDO3¹⁵

—

GPIO

–

223 MDO3_GPIO223

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO223

MDO4¹⁵

—

GPIO

–

75 MDO4_GPIO75

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO75

MDO5¹⁵

—

GPIO

–

76 MDO5_GPIO76

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO76

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

–

77 MDO6_GPIO77

MDO6¹⁵

Nexus message data out

—

I/O

V_DDE2

O/Low

—/Down

(GPIO function on this pin is

only available on Rev.2 of the

device)

—

GPIO77

MDO7¹⁵

—

GPIO

–

78 MDO7_GPIO78

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

O/Low

—

I/O

—

GPIO78

MDO8¹⁵

—

GPIO

–

79 MDO8_GPIO79

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO79

MDO9¹⁵

—

GPIO

–

80 MDO9_GPIO80

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO80

MDO10¹⁵

—

GPIO

–

81 MDO10_GPIO81

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO81

MDO11¹⁵

—

GPIO

–

82 MDO11_GPIO82

(GPIO function on this pin is

only available on Rev.2 of the

device)

Nexus message data out

—

I/O

—

GPIO82

GPIO

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

–

231 MDO12_GPIO231

MDO12¹⁵

Nexus message data out

—

I/O

—

I/O

—

I/O

—

I/O

V_DDE2

O/Low

—/Down

AA1

AA2

AA3

—

GPIO231

MDO13¹⁵

—

GPIO

–

232 MDO13_GPIO232

233 MDO14_GPIO233

234 MDO15_GPIO234

Nexus message data out

O/Low

AA1

AA2

AA3

—

GPIO232

MDO14¹⁵

—

GPIO

–

Nexus message data out

—

GPIO233

MDO15¹⁵

—

GPIO

–

Nexus message data out

—

GPIO234

MSEO0¹⁵

MSEO1¹⁵

RDY

GPIO

–

224 MSEO0

225 MSEO1

226 RDY

Nexus message start/end out

Nexus ready output

JTAG test clock input

JTAG test data input

JTAG test data output

JTAG test mode select input

JTAG TAP controller enable

V_DDE2

V_DDEH1

O/Low

MSEO/HI

RDY/HI

O/Low

—

TCK

TDI

TCK

TCK/Down

TDI/Up

TCK/Down

TDI/Up

AB2

AC2

AB1

AB3

AB2

AC2

AB1

AB3

TDI

228 TDO

TDO

TDO/Up

TMS/Up

TDO/Up

TMS/Up

—

TMS

JCOMP

TEST

JCOMP

TEST

JCOMP/Down JCOMP/Down

—

Test mode select (not for customer

use)

TEST/Down

—

VDDSYN

Clock synthesizer power input

VDDE

V_DDSYN

VDDSYN

Y22 AD26 AD26

Table 43. Signal Properties and Muxing Summary (continued)

Package Location

State during

State

Signal Name²

Function⁴

Function Summary

RESET⁷

after RESET⁸

—

VSSSYN

Clock synthesizer ground input

SRAM standby power input

VSSE

VHV

V_DDSYN

V_DDEH1

V_DDREG

VSSSYN

VSTBY

VSSSYN

VSTBY

U22 AA26 AA26

VSTBY

REGSEL

Selects regulator mode (Linear/Switch

mode)

REGSEL

V20

W23 W23

—

REGCTL

Regulator controller output to

base/gate of power transistor

V_DDREG

REGCTL

T22

Y26

—

VSSFL

Tie to V_SS

VSS

V_DDREG

VSSFL

V21 AB25 AB25

U21 AA25 AA25

VDDREG

Source voltage for on-chip regulators

and Low voltage detect circuits

VDDINT V_DDREG

VDDREG

The GPIO number is the same as the corresponding pad configuration register (SIU_PCRn) number in pins that have GPIO functionality. For pins that do not have GPIO

functionality, this number is the PCR number.

The primary signal name is used as the pin label on the BGA map for identification purposes. However, the primary signal function is not available on all devices and

is indicated by a dash in the following table columns: Signal Functions, P/F/G, and I/O Type.

P/A/G stands for Primary/Alternate/GPIO . This column indicates which function on a pin is Primary, Alternate 1, Alternate 2, (Alternate n) and GPIO.

Each line in the Function column corresponds to a separate signal function on the pin. For all device I/O pins, the primary, alternate, or GPIO signal functions are

designated in the PA field of the SIU_PCRn registers except where explicitly noted.

MH = High voltage, medium speed

F = Fast speed

FS = Fast speed with slew

AE = Analog with ESD protection circuitry (up/down = pull up and pull down circuits included in the pad)

VHV = Very high voltage

VDDE (fast I/O) and VDDEH (slow I/O) power supply inputs are grouped into segments. Each segment of VDDEH pins can connect to a separate 3.3–5.0 V (+5%/–10%)

power supply input. Each segment of VDDE pins can connect to a separate 1.8–3.3 V (±10%) power supply.

The Status During Reset pin is sampled after the internal POR is negated. Prior to exiting POR, the signal has a high impedance. The terminology used in this column

is: O – output, I – input, Up – weak pull up enabled, Down – weak pulldown enabled, Low – output driven low, High – output driven high, ABS — Auto Baud Select

(during Reset or until JCOMP assertion). A dash on the left side of the slash denotes that both the input and output buffers for the pin are off. A dash on the right side

of the slash denotes that there is no weak pull up/down enabled on the pin. The signal name to the left or right of the slash indicates the pin is enabled.

The Function After Reset of a GPI function is general purpose input. A dash on the left side of the slash denotes that both the input and output buffers for the pin are

off. A dash on the right side of the slash denotes that there is no weak pull up/down enabled on the pin.

This signal name includes eTPU_C functionality that this device does not have. This is for forward compatibility with devices that have an eTPU_C.

During and just after POR negates, internal pull resistors can be enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system

clock propagates through the device.

¹¹NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through the SIU_IREER and SIU_IFEER registers.

¹²Nexus reset is different than system reset; MDO 1-11 are enabled when trace (RPM or FPM) is enabled, and MDO 12-15 when FPM trace is enabled. MSEO and MCKO

are also dependent on trace (RPM or FPM) being enabled.

¹³The Nexus pins don’t have a “primary” function as they are not configured by the SIU. The pins are selected by asserting JCOMP and configuring the NPC. SIU values

have no effect on the function of these pins once enabled.

¹⁴MCKO is disabled from reset; it can be enabled from the tool (controlled by Nexus NPC_PCR register).

¹⁵Do not connect pin directly to a power supply or ground.

Table 45 lists the pin locations of the power and ground signals on the 324 TEPBGA package.

Table 44. 324-pin Power Supply Locations

VDD

V19

W20

Y21

AA3 AA22 AB2

VDD33

W21

VDDE2

AB4

N10

P10

VDDEH1

VDDEH4

VDDEH6

VDDEH7

AB20 W8

N20

T21

C22

H19

L22

J12

VSS

A22

K11

N13

AA2 AA21 AB1 AB22 B2

B21

L11

C20

L12

L13

Y20

D19

L14

J10

J11

J13

J14

K10

N12

K12

N14

K13

P11

K14

P12

L10

M10 M11 M12 M13 M14 N11

P13

P14 W19

Table 45 lists the pin locations of the power and ground signals on the 416 TEPBGA package.

Table 45. 416-pin Power Supply Locations

VDD

AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26

VDD33

AA4 AA23

VDDE2

N10

P10

P11

R10

R11

T10

T11

T12

U10

U11

U12

AC1 AC5 AF2

VDDEH1

VDDEH3

VDDEH4

VDDEH5

AC10 AF5

AC11 AF22

AC21 AF25

VDDEH6

VDDEH7

N23 AC25

D24

E23 M26

VSS

A26

L13

N16

T17

B25

L15

P12

U14

L16

P13

U15

C24

L17

P14

U16

D23

K10

K11

M13 M14 M15

R12 R13 R14

U17 AC4 AC23 AD3 AD24 AE2 AE25 AF1 AF26

K12

K13

K14

M16 M17 N11

R15 R16 R17

K15

K16

K17

N12

T13

L10

N13 N14

T14 T15

L11

L12

N15

T16

L14

N17

U13

M10 M11 M12

P15 P16 P17

Table 46 lists the pin locations of the power and ground signals on the 516 TEPBGA package.

Table 46. 516-pin Power Supply Locations

VDD

C4 D5

AB4 AB23 AC3 AC12 AC24 AD2 AD25 AE1 AE26

VDD33

VDDE10

L21 AA4 AA11 AA14 AA23

F16

F17

U10

F19

U11

F21

U12

N21

P21 AA22

VDDE2

N10 P10 P11 R10 R11

T10

T11

T12

AC1

AC5

AF2

VDDE8

VDDE9

F10 F11

AA5

AA13 AB6

AB7 AB18 AB19 AB20 AB21

VDDEH1

VDDEH3

VDDEH4

VDDEH5

AC10 AF5

AC11 AF22

AC21 AF25

VDDEH6

VDDEH7

N23 AC25

D24

E23 M26

VSS

A25

B25 B26

C24

E22

L16

P13

U15

D23

F13

E10

K13

E11

K14

M16

R15

E12

K15

M17

R16

E13

K16

N11

R17

E14

K17

E15

L10

E16 E17 E18 E19 E21

L11 L12 L13 L14 L15

N14 N15 N16 N17 P12

T15 T16 T17 U13 U14

F14

K10

M12

P17

K11

M13

R12

K12

L17

P14

U16

M10 M11

M14 M15

R13 R14

N12 N13

T13 T14

P15

U17

P16

AA6 AA21 AB5 AB22 AC4 AC23 AD3 AD24 AE2 AE25

Revision History

Appendix B Revision History

Table 47 describes the changes made to this document between revisions.

Table 47. Revision History

Revision

Description of changes

(Date)

Initial release, NDA Required.

(Sept 2008)

Changes between Rev.2 and Rev. 3:

(Nov 2009)

Added 516-pin package figures.

Signals table: Updates throughout entire table.

Updated Section 4.6, “Power Up/Down Sequencing”

Updated features list.

Updated flash PFCPR1 settings table.

Fixed JTAG Test Clock Input Timing figure so the spec #’s in table matched figure.

Updated Orderable Part numbers table.

Moved signals table to be an appendix.

Added 324-pin package thermals.

Updated part numbers in orderable parts table (missing F: MPC5674F).

FMPLL Electrical Spec table:

Spec #1 changed min values of 4 to 8

Removed last sentence of footnote 2

Added note "Upper tolerance of less than 1% is allowed on 40MHz crystal."

Oscillator Electrical Spec table:

Moved predivider op. frequency spec from this table to the FMPLL Electrical Spec table

Removed footnote #3 (since VDDE9 is an external supply and has no relation to the oscillator, PMC, or PLL).

Added maximum solder temperature to Absolute Max Ratings table.

PMC Operating Conditions table:

Removed JTemp row.

Changed VDDR to VDDREG (naming consistency)

Changed VDD12 to VDD (naming consistency)

PMC Electrical Spec table:

Added VDDREG to this parameter “Trimmed bandgap reference voltage / voltage dependence (V_DDREG)”

Changed VDDSTEP to LVDSTEP12 (naming consistency)

Added two conditons to the opening statements of Section 4.6, “Power Up/Down Sequencing.”

DC Electrical Specifications table:

spec #9 (Fast I/O Input High Voltage)

spec #10 (Fast I/O Input Low Voltage)

spec #24 (Operating Current 1.2 V Supplies; IDD)

spec #25 (Operating Current 3.3 V Supplies; IDDSYN)

spec #32 (Analog Input Current, Channel Off; IINACT_A)

footnote #12 ("IOH_S = {11.6} mA...")

MPC5674F Microcontroller Data Sheet, Rev. 10.1

126

Freescale Semiconductor

Revision History

Table 47. Revision History (continued)

Description of changes

Revision

(Date)

eQADC Conversion Specifications table:

(cont.)

Spec #7, 8: both +/-3, no dependency on frequency

Spec #15, 16: added "(with calibration)" to both

Flash Program and Erase Specifications table:

Added footnote 4 to spec #2.

Updated all initial max value times.

Updated entire AC Specifications: Clocking section.

Pad AC Specifications table: updated Medium pad specs

Derated Pad AC Specifications table: updated all specs

Updated entire Section 4.6, “Power Up/Down Sequencing.”

Updated Absolute Maximum Ratings (AMR) specs 1–11, 15, 16.

Changed name of IDDC to IREGCTL since it is the REGCTL max drive current.

Added two EMC Radiated Emissions Operating Behaviors tables and removed “EMI Testing Specifications”

table.

PMC Electrical Specifications table:

1b: Changed 1% to 2%

1c: Changed 150 to 300 ppm/C

2b: added footnote

2c: Changed from "Trimming step VDD" to "Trimming step VDD12OUT"

DC Electrical Specifications table:

6: Updated min value and added keep-out range

Standby RAM Regulator Electrical Specifications table:

Added brownout spec

PMC electrical spec table, added new specs: SMPS regulator output resistance, SPMS regulator clock

frequency, SMPS regulator overshoot at start-up, SMPS max output current, and voltage variation on current

step.

Added LVD VDDA specs to the PMC electrical spec table.

Removed specs for VDDF and VFLASH since those supplies are shorted with others in the package.

Changes between Rev.3 and Rev.4:

(Aug 2010)

Table “Derated Pad AC Specifications”, Spec #1: Changed 20ns to 200ns.

Added “324-ball TEPBGA Pin Assignments” section and mechanical drawings.

Appendix A (Signals):

Added “(the BAM uses this pin to select if auto baud rate is on or off)” to the EVTO pin description.

Added 324 pinout column.

Changed footnote from “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled through

the SIU DIRER register.“ to “NMI does not have a PCR PA configuration; it is enabled when NMI is enabled

through the SIU_IREER and SIU_IFEER registers.”

Updated eQADC signals to show that eQADC A and B each have dedicated channels (ANx0-23) and shared

channels (AN24-39).

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

127

Revision History

Table 47. Revision History (continued)

Description of changes

Revision

(Date)

“Temperature Sensor Electrical Specifications” table: Changed spec #2 to have one temperature range (-40 - 150

C) and changed spec value from ±1.0 to ±10.0 C.

(cont)

“eQADC Conversion Specifications (Operating)” table: Changed spec #13 (non-disruptive injection current)

values from ±1 to ±3.

"IPCLKDIV Settings" table, removed footnote "eMIOS and DMA are not considered peripherals here."

Note 4 in Maximum Ratings updated from 2.0 V to 1.65 V.

(Feb-2011) Changed I/O Supply Voltage spec in DC Electrical specs, Spec 2, from 1.62 V min to 3.0 V min.

Changed the APC=RWSC value in line 1 of PFCPR1 Settings vs. Frequency of Operation table from 0b011 to

0b100

Changed note 1 for Pad AC Specifications table from Vdde = 1.62 V to 1.98 V to read Vdde = 3.0 V to 3.6 V

Changed note 6 for Signal Properties and Muxing Summary table by removing the voltage range 1.8 V - 3.3 V

to have 3.3 V instead of the range.

Spec 2 in Table 9 “ESD Ratings“ the spec for “ESD for Charged Device Model (CDM)” changed to 250 V (other)

from 500 V (other)

Removed voltage ranges 1.62-1.98 V and 2.25-2.75 V from spec 28 in Table 14

Same content as for Rev. 5

(Feb-2011)

Added entry for Rev. 6 and Rev. 7 to this table to fix a revision-numbering issue.

Added the following footnotes to the “Signal Properties and Muxing Summary” table:

(Mar-2011)

(Jun-2011) • Footnote 10, for the ANA[0:7] signals, “During and just after POR negates, internal pull resistors can be

enabled, resulting in as much as 4 mA of current draw. The pull resistors are disabled when the system clock

propagates through the device.”

• Footnote 15, for MDO[0:15] and MSEO[0:1] signals, “Do not connect pin directly to a power supply or ground.”

Changed min and max values of ID 1 “Nominal bandgap reference voltage“ in Table 11 (PMC Electrical

Specifications) to 0.608 V min and 0.632 V max.

Changed min and max values of Spec 2 “ADC Bandgap” in Table 23 (ADC Band Gap Reference/LVI Electrical

Specifications) to 1.171 V min and 1.269 V max.

Changed Spec 3 of Table 26 (Flash EEPROM Module Life) from 'Minimum Data Retention at 25 °C ambient

temperature' to 'Minimum Data Retention at 85 °C ambient temperature'

Added Spec 41, 42, 43 and 44 to the “DC Electrical Specifications” table

Added Note 25 to the “DC Electrical Specifications” table for Spec 41, 42 and 43

Added Note 26 to the “DC Electrical Specifications” for Spec 44

Added Spec 17 to the “eQADC Conversion Specifications (Operating)” table.

Added Spec 18 to the “eQADC Conversion Specifications (Operating)” table.

Added Note 15 to the “eQADC Conversion Specifications (Operating)” table for Spec 17 and 18.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

128

Freescale Semiconductor

Revision History

Table 47. Revision History (continued)

Revision

(Date)

Description of changes

Removed spec 3 from Table 27 “PFCPR1 Settings vs Frequency of Operation”

(Jun-2011) Updated spec 2a (Untrimmed VRC 1.2V) in Table 11 “PMC Electrical Specifications“ to a max value of

VDD12OUT + 17%.

Updated item 26 (Operating Current VDDA Supply) in table 14 “Electrical Specifications” from 30 mA to 40 mA.

Updated Note 11 for Table 14 (Electrical Specifications) to read IOH_F = {16,32,47,77} mA and

IOL_F = {24,48,71,115} mA for {00,01,10,11} drive mode with VDDE = 3.0 V.

Updated ID 9 in Table 11 (PMC Electrical Specifications) to

V_{REG =}4.5 V, max DC output current with a max of 80 mA

V_REG= 4.25 V, max DC output current, crank condition with a max of 40 mA

Updated Table 17 (DSPI LVDS Pad Specification) with the following:

•

Spec 1 typical value updated from 40 MHz to 50 MHz

Spec 2 added SRC conditions and associated values:

– SRC=0b00 or SRC=0b11 Min 150 mV Max 400 mV

– SRC=0b01 Min 90 mV Max 320 mV

– SRC=0b10 Min 160 mV Max 480 mV

Spec 3

- Min value from 1.075 V to 1.06 V

- Max value from 1.325 V to 1.39 V

Added Spec 5, 6 and 7

•

Updated table 17 "DSPI LVDS pad specification" to include Temperature with a min value of -40 C and max of

150 C

Updated Spec 5 of Table 18, "FMPLL Electrical Specifications" to < 400 us as the Max vaule.

Added the sentence "Violating the VCO min/max range may prevent the system from exiting reset." to the end

of Footnote 16 of Table 18, "FMPLL Electrical Specifications"

Updated Spec 1 of Table 18, "FMPLL Electrical Specifications", Crystal Reference (PLLCFG2 = 0b1) minimum

value from 40 MHz to 16 MHz.

Updated Spec 1 of Table 18, "FMPLL Electrical Specifications", External Reference (PLLCFG2 = 0b1) minimum

value from 40 MHz to 16 MHz.

Removed Note 9, 'Duty cycle can be 20–80% when PLL is used with a pre-divider greater than 1', from Table 18,

"FMPLL Electrical Specifications".

Updated ID 16 in Table 11, “PMC Electrical Specifications”, SMPS regulator clock frequency (after reset) 2.4MHz

Max

Updated Table 16 “Flash EEPROM Module Life”, spec 3, ‘Blocks with 10,001–100,000 P/E cycles’ to 5 Years.

Added Typ column to Table 25, “Flash Program and Erase Specifications”

Updated Table 3, “Absolute Maximum Ratings” with the following:

- Spec 1, ‘1.2 V Core Supply Voltage’, to a Max of 2.0 V

- Spec 3, ‘Clock Synthesizer Voltage’, to a Max of 5.3 V

- Spec 4, ‘I/O Supply Voltage’ to a Max of 5.3 V

- Spec 5, ‘Analog Supply Voltage’ to a Max of 5.3 V

- Note 2 to read, “2.0 V for 10 hours cumulative time, 1.32 V +10% for time remaining.“

- Note 3, “... 5.0 V + 10% ...” to “... 5.25 V + 10 % ...”

- Note 5, “... 3.3 V + 10% ...” to “... 3.60 V + 10 % ...”

Updated Spec 2 (ESD for Charged Device Model (CDM)) of Table 9, “ESD Ratings”, to 500 V

Updated Table 27, “PFCPR1 Settings vs. Frequency of Operation“, Spec 3, APC = RWSC column to 0b100.

Updated Spec 26, “Operating Current 5.0 V Supplies @ f_sys= 264 MHz“ for I_DDAto 50 mA, in Table 14, “DC

electrical specifications”.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

Freescale Semiconductor

129

Revision History

Table 47. Revision History (continued)

Description of changes

Revision

(Date)

Updated Table 1.,"Orderable Part Numbers" with actual available parts. Added new part number

SPC5673FF3MVY2 ,Package description 516 PBGA, w/EBI, Pb-free.Speed is 200 MHz nom and

max.—Removed note attached to “Orderable Part Numbers” and “Freescale Part Number”.

Updated footnotes of Table 3.,"Absolute Maximum Ratings" to:

• 2.0 V for 10 hours cumulative time, 1.2V +10% for time remaining.

• 6.4 V for 10 hours cumulative time, 5.0V +10% for time remaining.

• 5.3 V for 10 hours cumulative time, 3.3V +10% for time remaining.

Updated Table 6.,"Thermal Characteristics, 324-pin Package" to show MPC5674F thermal characteristics.

In Table 10.,"PMC Operating conditions", updated the parameter “Supply voltage VDD 1.2V nominal" to “Core

supply voltage".

In Table 11.,"PMC Electrical Specifications", updated the following rows:

• Parameter “Nominal VRC regulated 1.2V output VDD” updated column “Typ” to 1.27 V.

• The minimum and maximum value of “Untrimmed VRC 1.2V output variation before band gap trim (unloaded)”

updated to “-14%” and “+10%”, respectively.

• The minimum and maximum value of “Trimmed VRC 1.2V output variation after band gap trim (REGCTL load

max. 20mA, VDD load max 1A)” updated to “-10%” and “+5%”, respectively.

In Table 12.,"Power Sequence Pin States for MH and AE pads", updated the row (VDD33 = low, VDDE = high),

parameter “MH+LVDS Pads” to “Outputs disabled”.

In Table 13.,"Power Sequence Pin States for F and FS pads", updated the rows (VDD = low, VDD33 = low,

VDDE = high) and (VDD = high, VDD33 = low, VDDE = high), parameter “F and FS pad” to “Outputs Disabled”.

In Table 14.,"DC Electrical Specifications", updated the spec 'Operating Current 1.2 V Supplies @ f_SYS= 264

MHz' with 'V_DD@ 1.32 V' Max value to 850 mA from 1.0 A, and deleted corresponding footnote stating that the

previous information was preliminary.

Updated current (mA) values in Table 15.,"V_DDE/V_DDEHI/O Pad Average DC Current" from Spec 5 to 13:

• Spec 5 Current (mA) from 6.5 to 7.4

• Spec 6 Current (mA) from 9.4 to 10.5

• Spec 7 Current (mA) from 10.8 to 12.3

• Spec 8 Current (mA) from 33.3 to 35.2

• Spec 9 Current (mA) from 12.0 to 12.7

• Spec 10 Current (mA) from 6.2 to 6.7

• Spec 11 Current (mA) from 4.0 to 4.2

• Spec 12 Current (mA) from 2.4 to 2.6

• Spec 13 Current (mA) from8.9 to 9.

In Table 35.,"Nexus Debug Port Timing", updated the footnote of parameter “tCYC” to “See Notes on tcyc in

Table27”. Removed references to “Section I/O Pad VDD33 Current Specifications” .

Updated Figure 1.,"MPC5674F Orderable Part Number Description" with changes in “Revision of Silicon” and

“Fab Revision ID”.

Updated Table 1.,"Orderable Part Numbers" with changes in Part numbers and Package Description.

10.1

In Figure 1.,"MPC5674F Orderable Part Number Description", replaced “Revision of Silicon for TSMC is 0 for

now. In future, it will be revision 1” with “0 = Rev 0 (TSMC14)”.

MPC5674F Microcontroller Data Sheet, Rev. 10.1

130

Freescale Semiconductor

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