935325864557 [NXP]
RISC Microcontroller;型号: | 935325864557 |
厂家: | NXP |
描述: | RISC Microcontroller 微控制器 外围集成电路 |
文件: | 总74页 (文件大小:894K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
K22P121M100SF9
Rev. 7, 08/2016
Kinetis K22F 128KB Flash
MK22FN128VDC10
100 MHz ARM® Cortex®-M4 Based Microcontroller with FPU
MK22FN128VLL10
MK22FN128VMP10
MK22FN128VLH10
The Kinetis K22 product family members are optimized for cost-
sensitive applications requiring low-power, USB connectivity,
high peripheral integration and processing efficiency with a
floating-point unit. These devices share the comprehensive
enablement and scalability of the Kinetis family.
This product offers:
121 XFBGA (DC)
100 LQFP (LL)
8 x 8 x 0.5 Pitch 0.65 14 x 14 x 1.4 Pitch 0.5
• Run power consumption down to 120 μA/MHz. Static
power consumption down to 2.6 μA with full state retention
and 6 μs wakeup. Lowest static mode down to 120 nA.
• USB LS/FS OTG 2.0 with embedded 3.3 V, USB FS device
crystal-less functionality.
mm
mm
64 MAPBGA (MP)
64 LQFP (LH)
5 x 5 x 1.2 Pitch 0.5 10 x 10 x 1.4 Pitch 0.5
mm mm
Performance
• 100 MHz ARM Cortex-M4 core with DSP instructions
Analog modules
• Two 16-bit SAR ADCs (1.2 MS/s in 12bit mode)
• One 12-bit DAC
delivering 1.25 Dhrystone MIPS per MHz
• Two analog comparators (CMP) with 6-bit DAC
• Accurate internal voltage reference
Memories and memory interfaces
• 128 KB of embedded flash and 24 KB of RAM
• Serial programming interface(EzPort)
• Pre-programmed Kinetis flashloader for one-time, in-
system factory programming
Communication interfaces
• USB LS/FS OTG 2.0 with on-chip transceiver
• USB full-speed device crystal-less operation
• Two SPI modules
System peripherals
• Three UART modules and one low-power UART
• Two I2C: Support for up to 1 Mbps operation
• I2S module
• Flexible low-power modes, multiple wakeup sources
• 4-channel DMA controller
• Independent External and Software Watchdog monitor
Timers
Clocks
• One 8-channel general-purpose/PWM timer
• Two 2-channel general-purpose timers with
quadrature decoder functionality
• Periodic interrupt timers
• Two crystal oscillators: 32 kHz (RTC) and 32-40 kHz or
3-32 MHz
• Three internal oscillators: 32 kHz, 4 MHz, and 48 MHz
• Multi-purpose clock generator with FLL
• 16-bit low-power timer
• Real-time clock with independent power domain
• Programmable delay block
Security and integrity modules
• Hardware CRC module
• 128-bit unique identification (ID) number per chip
• Flash access control to protect proprietary software
Operating Characteristics
• Voltage range (including flash writes): 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Human-machine interface
• Up to 67 general-purpose I/O (GPIO)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Memory
Part Number
Number of GPIOs
Flash (KB)
SRAM (KB)
MK22FN128VDC10
MK22FN128VLL10
MK22FN128VMP10
MK22FN128VLH10
128
128
128
128
24
24
24
24
67
66
40
40
Device Revision Number
Device Mask Set Number
0N74K
SIM_SDID[REVID]
JTAG ID Register[PRN]
0000
0000
Related Resources
Description
Type
Selector
Guide
Resource
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector
KINETISKMCUSELGD
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
K22FPB
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K22P121M100SF9RM
K22P121M100SF9
Data Sheet
The Data Sheet is this document. It includes electrical characteristics
and signal connections.
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_K_xN74K 1
a particular device mask set.
Package
drawing
Package dimensions are provided by part number:
• MK22FN128VDC10
Package drawing:
• 98ASA00595D
• 98ASS23308W
• 98ASA00420D
• 98ASS23234W
• MK22FN128VLL10
• MK22FN128VMP10
• MK22FN128VLH10
1. To find the associated resource, go to nxp.com and perform a search using this term with the x replaced by the revision
of the device you are using.
Figure 1 shows the functional modules in the chip.
2
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
ARM® Cortex™-M4
Core
System
Memories and Memory Interfaces
Clocks
Program
RAM
Frequency-
locked loop
flash
DMA (4 ch)
Debug
(24 KB)
(128 KB)
DSP
FPU
interfaces
Low-leakage
wakeup
Low/high
frequency
oscillators
Serial
programming
Interrupt
interface
(EzPort)
controller
Internal
and external
watchdogs
Internal
reference
clocks
Security
and Integrity
Communication Interfaces
Human-Machine
Interface (HMI)
Analog
Timers
I2C
I2S
x2
Timers
x1 (8ch)
x2 (2ch)
16-bit
SAR ADC x2
CRC
Up to
67 GPIOs
Comparator
Programmable
delay block
Flash access
control
UART
x3
USB OTG
LS/FS
with 6-bit DAC
x2
Periodic
interrupt
timers
12-bit DAC
x1
LPUART
x1
USB LS/FS
transceiver
High
16-bit
low-power
timer
performance
SPI
x2
voltage ref
Independent
real-time
clock
Figure 1. Functional block diagram
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
3.6.1 ADC electrical specifications............................... 34
3.6.2 CMP and 6-bit DAC electrical specifications....... 38
3.6.3 12-bit DAC electrical characteristics....................40
3.6.4 Voltage reference electrical specifications.......... 43
3.7 Timers..............................................................................44
3.8 Communication interfaces............................................... 44
3.8.1 USB electrical specifications............................... 45
3.8.2 DSPI switching specifications (limited voltage
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
2 General................................................................................... 6
2.1 AC electrical characteristics.............................................6
2.2 Nonswitching electrical specifications..............................6
2.2.1 Voltage and current operating requirements....... 6
2.2.2 LVD and POR operating requirements................7
2.2.3 Voltage and current operating behaviors.............8
2.2.4 Power mode transition operating behaviors........ 9
2.2.5 Power consumption operating behaviors............ 10
2.2.6 EMC radiated emissions operating behaviors.....17
2.2.7 Designing with radiated emissions in mind..........18
2.2.8 Capacitance attributes.........................................18
2.3 Switching specifications...................................................18
2.3.1 Device clock specifications..................................18
2.3.2 General switching specifications......................... 19
2.4 Thermal specifications.....................................................20
2.4.1 Thermal operating requirements......................... 20
2.4.2 Thermal attributes................................................20
3 Peripheral operating requirements and behaviors.................. 21
3.1 Core modules.................................................................. 21
3.1.1 SWD electricals .................................................. 21
3.1.2 JTAG electricals.................................................. 22
3.2 System modules.............................................................. 25
3.3 Clock modules................................................................. 25
3.3.1 MCG specifications..............................................25
3.3.2 IRC48M specifications.........................................27
3.3.3 Oscillator electrical specifications........................28
3.3.4 32 kHz oscillator electrical characteristics...........30
3.4 Memories and memory interfaces................................... 31
3.4.1 Flash electrical specifications..............................31
3.4.2 EzPort switching specifications........................... 32
3.5 Security and integrity modules........................................ 33
3.6 Analog............................................................................. 33
range).................................................................. 45
3.8.3 DSPI switching specifications (full voltage
range).................................................................. 47
3.8.4 Inter-Integrated Circuit Interface (I2C) timing...... 48
3.8.5 UART switching specifications............................ 50
3.8.6 I2S/SAI switching specifications..........................50
4 Dimensions............................................................................. 56
4.1 Obtaining package dimensions....................................... 56
5 Pinout......................................................................................57
5.1 K22 Signal Multiplexing and Pin Assignments.................57
5.2 Recommended connection for unused analog and
digital pins........................................................................62
5.3 K22 Pinouts..................................................................... 63
6 Part identification.....................................................................67
6.1 Description.......................................................................67
6.2 Format............................................................................. 67
6.3 Fields............................................................................... 68
6.4 Example...........................................................................68
6.5 121-pin XFBGA part marking.......................................... 69
6.6 64-pin MAPBGA part marking......................................... 69
7 Terminology and guidelines.................................................... 69
7.1 Definitions........................................................................69
7.2 Examples.........................................................................70
7.3 Typical-value conditions.................................................. 70
7.4 Relationship between ratings and operating
requirements....................................................................71
7.5 Guidelines for ratings and operating requirements..........71
8 Revision History...................................................................... 71
4
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
5
NXP Semiconductors
General
Symbol
Description
Min.
–0.3
Max.
3.8
Unit
V
USBVDD
VDD
USB Transceiver supply voltage
Digital supply voltage
–0.3
3.8
V
IDD
Digital supply current
—
145
mA
V
VDIO
Digital input voltage
Analog1
–0.3
VDD + 0.3
VDD + 0.3
25
VAIO
–0.3
V
ID
Maximum current single pin limit (applies to all digital pins)
Analog supply voltage
–25
mA
V
VDDA
VUSB0_DP
VUSB0_DM
VBAT
VDD – 0.3
–0.3
VDD + 0.3
3.63
USB0_DP input voltage
USB0_DM input voltage
RTC battery supply voltage
V
–0.3
3.63
V
–0.3
3.8
V
1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
2.2 Nonswitching electrical specifications
6
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
General
Notes
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
Max.
3.6
3.6
0.1
0.1
3.6
3.6
—
Unit
V
Supply voltage
VDDA
Analog supply voltage
1.71
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
V
–0.1
V
VBAT
RTC battery supply voltage
1.71
V
USBVDD USB Transceiver supply voltage
3.0
V
1
VIH
Input high voltage
0.7 × VDD
0.75 × VDD
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
V
VIL
Input low voltage
—
—
0.35 × VDD
0.3 × VDD
V
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
Analog and I/O pin DC injection current — single pin
• VIN < VSS-0.3V (Negative current injection)
2
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
V
3
VDD voltage required to retain RAM
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
—
1. USB nominal operating voltage is 3.3 V.
2. All analog and I/O pins are internally clamped to VSS through ESD protection diodes. If VIN is less than VIO_MIN or
greater than VIO_MAX, a current limiting resistor is required. The negative DC injection current limiting resistor is
calculated as R=(VIO_MIN-VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD.
2.2.2 LVD and POR operating requirements
Table 2. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
7
NXP Semiconductors
General
Table 2. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VOH Output high voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
1
VOH
Output high voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
VDD – 0.5
—
—
V
1
Table continues on the next page...
8
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
General
Notes
Table 4. Voltage and current operating behaviors (continued)
Symbol Description
1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
Min.
VDD – 0.5
—
Typ.
—
Max.
—
Unit
V
IOHT
VOL
Output high current total for all ports
—
100
mA
Output low voltage — Normal drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
—
—
—
0.5
0.5
V
V
1
1
VOL
Output low voltage — High drive pad except
RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
Output low voltage — RESET_B
2.7 V ≤ VDD ≤ 3.6 V, IOL = 3 mA
1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
Output low current total for all ports
—
—
—
—
0.5
0.5
V
V
VOL
—
—
—
—
—
—
0.5
0.5
100
V
V
IOLT
IIN
mA
Input leakage current (per pin) for full
temperature range
All pins other than high drive port pins
High drive port pins
—
—
—
0.002
0.004
—
0.5
0.5
1.0
μA
μA
μA
1, 2
2
IIN
Input leakage current (total all pins) for full
temperature range
RPU
RPD
Internal pullup resistors
20
20
—
—
50
50
kΩ
kΩ
3
4
Internal pulldown resistors
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7 I/O have both high drive and normal drive capability
selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD=3.6V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
4. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 72 MHz
• Bus clock = 36 MHz
• Flash clock = 24 MHz
• MCG mode: FEI
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
9
NXP Semiconductors
General
Table 5. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
—
—
300
μs
1
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS2 → RUN
• LLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
135
135
75
μs
μs
μs
μs
μs
μs
μs
μs
75
6
6
5.7
5.7
1. Normal boot (FTFA_OPT[LPBOOT]=1)
2.2.5 Power consumption operating behaviors
The current parameters in the table below are derived from code executing a while(1)
loop from flash, unless otherwise noted.
The IDD typical values represent the statistical mean at 25°C, and the IDD maximum
values for RUN, WAIT, VLPR, and VLPW represent data collected at 125°C junction
temperature unless otherwise noted. The maximum values represent characterized
results equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 6. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, CoreMark benchmark code
executing from flash
Table continues on the next page...
10
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
@ 1.8V
Min.
—
Typ.
19.51
19.51
Max.
20.24
20.24
Unit
mA
mA
Notes
2, 3, 4
@ 3.0V
—
IDD_HSRUN High Speed Run mode current - all peripheral
clocks disabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
16.9
17.0
17.63
17.73
mA
mA
5
IDD_HSRUN High Speed Run mode current — all peripheral
clocks enabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
22.8
22.9
23.53
23.63
mA
mA
6
IDD_RUN Run mode current in Compute operation —
CoreMark benchmark code executing from flash
@ 1.8V
@ 3.0V
—
—
11.39
11.58
12.12
12.31
mA
mA
2, 3, 7
IDD_RUN Run mode current in Compute operation —
code executing from flash
@ 1.8V
@ 3.0V
—
—
10.90
10.90
11.90
12.23
mA
mA
7
8
9
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash
@ 1.8V
@ 3.0V
—
—
11.8
11.9
12.53
12.63
mA
mA
IDD_RUN Run mode current — all peripheral clocks
enabled, code executing from flash
@ 1.8V
—
15.5
16.23
mA
@ 3.0V
• @ 25°C
—
—
—
—
15.6
15.6
15.6
16.3
16.33
16.33
16.33
17.03
mA
mA
mA
mA
• @ 70°C
• @ 85°C
• @ 105°C
IDD_RUN Run mode current — Compute operation, code
executing from flash
@ 1.8V
—
10.9
11.63
mA
10
@ 3.0V
• @ 25°C
—
—
—
—
10.9
10.9
10.9
11.5
11.63
11.63
11.63
12.23
mA
mA
mA
mA
• @ 70°C
• @ 85°C
• @ 105°C
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
11
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
—
6.5
7.23
mA
8
IDD_WAIT Wait mode reduced frequency current at 3.0 V
— all peripheral clocks disabled
—
3.9
4.63
mA
11
IDD_VLPR Very-low-power run mode current in Compute
operation — CoreMark benchmark code
executing from flash
@ 1.8V
@ 3.0V
—
—
0.60
0.61
0.88
0.89
mA
mA
2, 3, 12
IDD_VLPR Very-low-power run mode current in Compute
operation, code executing from flash
@ 1.8V
@ 3.0V
—
—
—
0.48
0.48
0.54
0.76
0.76
0.82
mA
mA
mA
12
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
13
14
15
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
—
—
0.79
0.30
1.07
0.59
mA
mA
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
IDD_STOP Stop mode current at 3.0 V
@ -40°C to 25°C
—
—
—
—
0.27
0.31
0.31
0.43
0.33
0.36
0.36
0.66
mA
mA
mA
mA
@ 70°C
@ 85°C
@ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
@ -40°C to 25°C
—
—
—
—
4.2
9.00
31.90
50.95
89.00
µA
µA
µA
µA
@ 70°C
15.8
26.9
43.0
@ 85°C
@ 105°C
IDD_LLS3 Low leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C
—
—
—
—
2.6
6.2
3.30
8.60
µA
µA
µA
µA
@ 70°C
@ 85°C
9.6
12.30
26.00
@ 105°C
15.0
IDD_LLS2 Low leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C
—
—
—
—
2.4
5.2
3.00
6.85
µA
µA
µA
µA
@ 70°C
@ 85°C
7.9
9.95
@ 105°C
12.0
20.00
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
@ -40°C to 25°C
—
1.8
2.10
µA
Table continues on the next page...
12
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
General
Notes
Table 6. Power consumption operating behaviors (continued)
Symbol Description
Min.
—
Typ.
4.3
Max.
5.70
Unit
µA
@ 70°C
@ 85°C
—
6.6
8.10
µA
@ 105°C
—
10.0
17.00
µA
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
@ -40°C to 25°C
—
—
—
—
1.6
3.1
4.7
6.8
1.80
3.90
µA
µA
µA
µA
@ 70°C
@ 85°C
7.00
@ 105°C
10.90
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
@ -40°C to 25°C
@ 70°C
—
—
—
—
0.70
1.78
2.8
0.90
2.09
3.25
6.15
µA
µA
µA
µA
@ 85°C
@ 105°C
4.0
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
@ -40°C to 25°C
@ 70°C
—
—
—
—
0.40
1.38
2.40
3.6
0.49
1.49
2.70
5.65
µA
µA
µA
µA
@ 85°C
@ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
@ -40°C to 25°C
@ 70°C
—
—
—
—
0.12
1.05
2.1
0.19
1.13
2.45
5.35
µA
µA
µA
µA
@ 85°C
@ 105°C
3.3
IDD_VBAT Average current with RTC and 32kHz disabled
at 3.0 V
@ -40°C to 25°C
@ 70°C
—
—
—
—
0.18
0.66
1.52
2.92
0.21
0.86
2.24
4.30
µA
µA
µA
µA
@ 85°C
@ 105°C
IDD_VBAT Average current when CPU is not accessing
RTC registers
@ 1.8V
• @ -40°C to 25°C
—
—
—
—
0.57
0.90
0.90
2.4
0.67
1.2
1.2
3.5
µA
µA
µA
µA
16
• @ 70°C
• @ 85°C
• @ 105°C
@ 3.0V
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
13
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (continued)
Symbol Description
• @ -40°C to 25°C
Min.
Typ.
Max.
Unit
Notes
—
0.67
0.94
µA
• @ 70°C
• @ 85°C
• @ 105°C
—
—
—
1.0
1.0
2.7
1.4
1.4
3.9
µA
µA
µA
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. Cache on and prefetch on, low compiler optimization.
3. Coremark benchmark compiled using IAR 7.2 withs optimization level low.
4. 100 MHz core and system clock, 50 MHz bus clock, and 25 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled.
5. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
6. 100MHz core and system clock, 50MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
7. 72 MHz core and system clock, 36 MHz bus clock, and 24 MHz flash clock. MCG configured for FEE mode. All
peripheral clocks disabled. Compute operation.
8. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks disabled.
9. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. All peripheral
clocks enabled.
10. 72MHz core and system clock, 36MHz bus clock, and 24MHz flash clock. MCG configured for FEI mode. Compute
Operation.
11. 25MHz core and system clock, 25MHz bus clock, and 25MHz flash clock. MCG configured for FEI mode.
12. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. Compute Operation. Code
executing from flash.
13. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled. Code executing from flash.
14. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
enabled but peripherals are not in active operation. Code executing from flash.
15. 4 MHz core, system, and bus clock and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks
disabled.
16. Includes 32kHz oscillator current and RTC operation.
Table 7. Low power mode peripheral adders—typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 32 kHz IRC enabled.
52
52
52
52
52
52
µA
uA
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
228
237
245
251
258
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14
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
General
Unit
Table 7. Low power mode peripheral adders—typical value (continued)
Symbol
Description
Temperature (°C)
-40
25
50
70
85
105
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN
and EREFSTEN] bits. Measured by
entering all modes with the crystal
enabled.
VLLS1
440
440
490
510
510
350
22
490
490
490
560
560
350
22
540
540
540
560
560
350
22
560
560
560
560
560
350
22
570
570
570
610
610
350
22
580
580
680
680
680
350
22
nA
VLLS3
LLS
VLPS
STOP
I48MIRC
ICMP
48 Mhz internal reference clock
µA
µA
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
Includes 6-bit DAC power consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
432
357
388
475
532
810
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Includes selected clock source power
consumption.
MCGIRCLK (4 MHz internal reference
clock)
66
214
45
66
237
45
66
246
45
66
254
45
66
260
45
66
268
45
µA
>OSCERCLK (4 MHz external crystal)
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx, LLS, or
VLLSx mode.
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
42
42
42
42
42
42
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
15
NXP Semiconductors
General
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE mode for 50 MHz and lower frequencies. MCG in FEE mode at
frequencies between 50 MHz and 100MHz.
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 3. Run mode supply current vs. core frequency
16
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 8. EMC radiated emissions operating behaviors for 64 LQFP package
Parame Conditions
ter
Clocks
Frequency range
Level
(Typ.)
Unit
Notes
VEME
Device configuration,
FSYS = 100 MHz
150 kHz–50 MHz
50 MHz–150 MHz
150 MHz–500 MHz
500 MHz–1000 MHz
IEC level
13
24
23
7
dBuV
1, 2, 3
test conditions and EM
testing per standard IEC
61967-2.
FBUS = 50 MHz
External crystal = 10 MHz
Supply voltages:
Temp = 25°C
L
4
1. Measurements were made per IEC 61967-2 while the device was running typical application code.
2. Measurements were performed on the 64LQFP device, MK22FN128VLH10 .
3. The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
4. IEC Level Maximums: M ≤ 18dBmV, L ≤ 24dBmV, K ≤ 30dBmV, I ≤ 36dBmV, H ≤ 42dBmV .
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
17
NXP Semiconductors
General
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to nxp.com
• Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 10. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed run mode
fSYS
fBUS
System and core clock
Bus clock
—
—
100
50
MHz
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
72
—
MHz
MHz
fSYS_USB
System and core clock when Full Speed USB in
operation
20
fBUS
Bus clock
—
—
—
50
25
25
MHz
MHz
MHz
fFLASH
fLPTMR
Flash clock
LPTMR clock
VLPR mode1
fSYS
fBUS
fFLASH
fERCLK
System and core clock
Bus clock
—
—
—
—
4
4
MHz
MHz
MHz
MHz
Flash clock
1
External reference clock
16
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18
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
General
Notes
Table 10. Device clock specifications (continued)
Symbol
Description
Min.
—
Max.
25
Unit
MHz
MHz
MHz
MHz
fLPTMR_pin
LPTMR clock
fLPTMR_ERCLK LPTMR external reference clock
—
16
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
—
12.5
4
—
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
50
—
—
ns
3
4
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
ns
Mode select (EZP_CS) hold time after reset
deassertion
2
—
Bus clock
cycles
Port rise and fall time
• Slew disabled
5
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
• Slew enabled
10
5
ns
ns
—
—
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
30
16
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter
pulses can be recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
5. 25 pF load
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
19
NXP Semiconductors
General
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
2.4.2 Thermal attributes
Board
type
Symbol
Descripti
on
121
XFBGA
100 LQFP 64 LQFP
64
MAPBGA
Unit
Notes
Single-layer RθJA
(1s)
Thermal
46.6
63
50
53
44
36
69
51
57
44
33
53.8
46.0
45.8
41.0
43.4
°C/W
1
2
3
3
4
resistance,
junction to
ambient
(natural
convection)
Four-layer
(2s2p)
RθJA
Thermal
39.3
39.0
35.3
36.7
°C/W
°C/W
°C/W
°C/W
resistance,
junction to
ambient
(natural
convection)
Single-layer RθJMA
(1s)
Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
Four-layer
(2s2p)
RθJMA
Thermal
resistance,
junction to
ambient
(200 ft./min.
air speed)
—
RθJB
Thermal
resistance,
junction to
board
Table continues on the next page...
20
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Board
type
Symbol
Descripti
on
121
XFBGA
100 LQFP 64 LQFP
64
MAPBGA
Unit
Notes
—
—
RθJC
Thermal
resistance,
junction to
case
11.5
18
18
25.7
°C/W
5
6
ΨJT
Thermal
characteriz
ation
0.9
3
3
0.4
°C/W
parameter,
junction to
package
top outside
center
(natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air)with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental
Conditions—Forced Convection (Moving Air) with the board horizontal.
4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 13. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
S1
SWD_CLK frequency of operation
• Serial wire debug
0
33
—
MHz
ns
S2
S3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/S1
15
—
ns
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Kinetis K22F 128KB Flash, Rev. 7, 08/2016
21
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 13. SWD full voltage range electricals (continued)
Symbol
S4
Description
Min.
—
8
Max.
3
Unit
ns
SWD_CLK rise and fall times
S9
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
ns
S10
S11
S12
1.4
—
5
—
ns
25
—
ns
ns
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 5. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
S9
S10
Input data valid
S11
Output data valid
S12
S11
Output data valid
Figure 6. Serial wire data timing
22
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
10
20
• JTAG and CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
ns
ns
• JTAG and CJTAG
J4
J5
TCLK rise and fall times
—
20
1
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
—
—
25
25
—
—
19
19
—
—
J6
J7
—
—
8
J8
J9
J10
J11
J12
J13
J14
1
—
—
100
8
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
Table 15. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
10
15
• JTAG and CJTAG
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
33
—
—
ns
ns
• JTAG and CJTAG
J4
J5
J6
J7
TCLK rise and fall times
—
20
1.4
—
3
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
—
—
27
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Kinetis K22F 128KB Flash, Rev. 7, 08/2016
23
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 15. JTAG full voltage range electricals (continued)
Symbol
J8
Description
Min.
—
Max.
27
Unit
ns
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J9
8
—
ns
J10
J11
J12
J13
J14
1.4
—
—
ns
26.2
26.2
—
ns
TCLK low to TDO high-Z
—
ns
TRST assert time
100
8
ns
TRST setup time (negation) to TCLK high
—
ns
J2
J4
J3
J3
TCLK (input)
J4
Figure 7. Test clock input timing
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 8. Boundary scan (JTAG) timing
24
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 9. Test Access Port timing
TCLK
TRST
J14
J13
Figure 10. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.1 MCG specifications
Table 16. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft
Δfints_t
fints_t
Internal reference frequency (slow clock) —
factory trimmed at nominal VDD and 25 °C
—
32.768
—
kHz
Total deviation of internal reference frequency
(slow clock) over voltage and temperature
—
31.25
—
+0.5/-0.7
—
2
39.0625
0.6
%
Internal reference frequency (slow clock) —
user trimmed
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.3
2
%fdco
%fdco
1, 2
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
—
4
—
5
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
20.97
MHz
3, 4
frequency range
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
—
Table continues on the next page...
26
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
2197 × ffll_ref
High range (DRS=11)
2929 × ffll_ref
—
95.98
—
MHz
Jcyc_fll
FLL period jitter
—
180
150
—
ps
—
—
—
—
• fVCO = 48 MHz
• fVCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
1
ms
7
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. 2.0 V <= VDD <= 3.6 V.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
400
48
500
—
μA
Internal reference frequency
—
MHz
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
—
high voltage (VDD=1.89V-3.6V) over 0°C to 70°C
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
—
—
0.2
0.4
0.5
1.0
%firc48m
%firc48m
%firc48m
1
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over full
temperature
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
1
1
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over full
temperature
Regulator disable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
—
—
0.4
0.5
1.0
1.5
Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 17. IRC48M specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
—
—
0.1
%fhost
2
over voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
3
1. The maximum value represents characterized results equivalent to the mean plus or minus three times the standard
deviation (mean 3 sigma).
2. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation. It
is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1, USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
3. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable the
clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1 or
• MCG operating in an external clocking mode and MCG_C7[OSCSEL]=10 or MCG_C5[PLLCLKEN0]=1, or
• SIM_SOPT2[PLLFLLSEL]=11
3.3.3 Oscillator electrical specifications
3.3.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high-gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
EXTAL load capacitance
—
—
—
2, 3
Table continues on the next page...
28
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
—
Typ.
—
Max.
—
Unit
Notes
2, 3
Cy
RF
XTAL load capacitance
Feedback resistor — low-frequency, low-power
mode (HGO=0)
—
—
—
MΩ
MΩ
MΩ
MΩ
kΩ
2, 4
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx and Cy can be provided by using either integrated capacitors or external components.
4. When low-power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other device.
3.3.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
32
—
40
kHz
Table continues on the next page...
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29
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 19. Oscillator frequency specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
—
8
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
8
—
32
MHz
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
50
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.3.4 32 kHz oscillator electrical characteristics
3.3.4.1 32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
30
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.4.2 32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.
The oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the
applied clock must be within the range of VSS to VBAT
.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 22. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
—
1
—
13
113
904
ms
ms
thversall
Erase All high-voltage time
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 23. Flash command timing specifications
Symbol Description
Min.
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec2k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
1
1
—
—
45
μs
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
31
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 23. Flash command timing specifications (continued)
Symbol Description
Min.
—
Typ.
—
Max.
30
Unit
μs
Notes
trdrsrc
tpgm4
tersscr
trd1all
trdonce
Read Resource execution time
1
—
2
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
65
145
114
0.9
30
μs
—
14
ms
ms
μs
—
—
1
—
—
1
tpgmonce Program Once execution time
—
100
140
—
—
μs
—
2
tersall
Erase All Blocks execution time
—
1150
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
—
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 24. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 25. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
32
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.2 EzPort switching specifications
Table 26. EzPort switching specifications
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
—
EP1
EZP_CK frequency of operation (all commands except
READ)
fSYS/2
MHz
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
—
fSYS/8
—
MHz
ns
2 x tEZP_CK
5
5
—
ns
—
ns
2
—
ns
5
—
ns
—
0
25
—
ns
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
ns
—
12
ns
EZP_CK
EP2
EP3
EP4
EZP_CS
EP9
EP8
EP7
EZP_Q (output)
EZP_D (input)
EP5
EP6
Figure 11. EzPort Timing Diagram
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
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33
NXP Semiconductors
Peripheral operating requirements and behaviors
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 27 and Table 28 are achievable on the
differential pins ADCx_DPx, ADCx_DMx.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
Ground voltage Delta to VSS (VSS – VSSA
)
0
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
24.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20
—
1200
Ksps
Continuous conversions
enabled, subsequent
conversion time
Table continues on the next page...
34
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 27. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
Min.
Typ.1
Max.
Unit
Notes
Crate
ADC conversion 16-bit mode
rate
5
No ADC hardware averaging
37
—
461
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 12. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
35
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
• <12-bit modes
—
—
1.0
0.5
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
95
Table continues on the next page...
36
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
16-bit single-ended mode
78
90
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor voltage 25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
37
NXP Semiconductors
Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 29. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
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Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 30. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Peripheral operating requirements and behaviors
3.6.3.2 12-bit DAC operating behaviors
Table 31. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
330
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
1200
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
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Peripheral operating requirements and behaviors
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 17. Typical INL error vs. digital code
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Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 18. Offset at half scale vs. temperature
3.6.4 Voltage reference electrical specifications
Table 32. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
Notes
1.71
3.6
V
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
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Peripheral operating requirements and behaviors
Table 33. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1920
1.1950
1.1980
V
1
nominal VDDA and temperature=25°C
Vout
Voltage reference output with user trim at
nominal VDDA and temperature=25°C
1.1945
1.1950
1.1955
V
1
Vstep
Vtdrift
Voltage reference trim step
—
—
0.5
—
—
mV
mV
1
1
Temperature drift (Vmax -Vmin across the full
temperature range)
15
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
Low-power buffer current
High-power buffer current
1
1
Ihp
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 34. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
70
°C
Table 35. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vtdrift
Temperature drift (Vmax -Vmin across the limited
temperature range)
—
10
mV
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
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Peripheral operating requirements and behaviors
3.8.1 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org.
NOTE
The MCGFLLCLK does not meet the USB jitter or
signaling rate specifications for certification.
The IRC48M meets the USB jitter and signaling rate
specifications for certification in Device mode when the
USB clock recovery mode is enabled. It does not meet the
USB signaling rate specifications for certification in Host
mode operation.
3.8.2 DSPI switching specifications (limited voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provide DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-2
8.5
—
—
—
ns
ns
ns
ns
16.2
0
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
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NXP Semiconductors
Peripheral operating requirements and behaviors
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 19. DSPI classic SPI timing — master mode
Table 37. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
—
12.5
—
MHz
ns
1
DS9
DSPI_SCK input cycle time
4 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2 (tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
21.4
—
ns
ns
2.6
7
—
ns
—
ns
—
—
17
17
ns
ns
1. The maximum operating frequency is measured with noncontinuous CS and SCK. When DSPI is configured with
continuous CS and SCK, the SPI clock must not be greater than 1/6 of the bus clock. For example, when the bus clock
is 60 MHz, the SPI clock must not be greater than 10 MHz.
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Peripheral operating requirements and behaviors
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
Last data
DSPI_SOUT
Data
Data
DS13
First data
DSPI_SIN
Figure 20. DSPI classic SPI timing — slave mode
3.8.3 DSPI switching specifications (full voltage range)
The Deserial Serial Peripheral Interface (DSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The tables below provides DSPI timing characteristics for classic SPI timing modes.
Refer to the SPI chapter of the Reference Manual for information on the modified
transfer formats used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
12.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-4.5
24.6
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
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Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 21. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
6.25
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
29.5
—
ns
ns
3.2
7
—
ns
—
ns
—
—
25
25
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 22. DSPI classic SPI timing — slave mode
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Peripheral operating requirements and behaviors
3.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 40. I 2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency
fSCL
0
4
100
—
0
4001
—
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
02
2505
—
3.453
—
04
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
0.92
—
µs
ns
ns
ns
µs
µs
Data set-up time
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and
SCL lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
7. Cb = total capacitance of the one bus line in pF.
Table 41. I 2C 1 Mbps timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
0.5
0.26
0.26
0
—
—
—
—
µs
µs
µs
µs
Set-up time for a repeated START condition
Data hold time for I2C bus devices
tSU; STA
tHD; DAT
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 41. I 2C 1 Mbps timing (continued)
Characteristic
Symbol
tSU; DAT
tr
Minimum
Maximum
Unit
ns
Data set-up time
50
—
120
120
—
, 2
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
20 +0.1Cb
20 +0.1Cb
0.26
ns
2
tf
ns
tSU; STO
tBUF
µs
Bus free time between STOP and START
condition
0.5
—
µs
Pulse width of spikes that must be suppressed by
the input filter
tSP
0
50
ns
1. The maximum SCL clock frequency of 1 Mbps can support maximum bus loading when using the High drive pins across
the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 23. Timing definition for devices on the I2C bus
3.8.5 UART switching specifications
See General switching specifications.
3.8.6 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
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Peripheral operating requirements and behaviors
3.8.6.1 Normal Run, Wait and Stop mode performance over a limited
operating voltage range
This section provides the operating performance over a limited operating voltage for
the device in Normal Run, Wait and Stop modes.
Table 42. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
18
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 24. I2S/SAI timing — master modes
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
51
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 43. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (limited voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
2.7
80
3.6
—
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
2
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
20
—
—
—
25
ns
ns
ns
ns
ns
4.5
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 25. I2S/SAI timing — slave modes
3.8.6.2 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
52
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 44. I2S/SAI master mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1.0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
27
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 26. I2S/SAI timing — master modes
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
80
3.6
—
V
S11
ns
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
53
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 45. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes (full voltage
range) (continued)
Num.
S12
Characteristic
Min.
Max.
55%
Unit
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
5.8
—
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
28.5
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
5.8
2
—
ns
ns
ns
—
—
26.3
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 27. I2S/SAI timing — slave modes
3.8.6.3 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 46. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
1.71
Table continues on the next page...
Max.
Unit
Operating voltage
3.6
V
54
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Peripheral operating requirements and behaviors
Table 46. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
Characteristic
I2S_MCLK cycle time
Min.
Max.
Unit
S1
S2
S3
S4
S5
62.5
45%
250
45%
—
—
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
-1
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 28. I2S/SAI timing — master modes
Table 47. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
250
3.6
—
V
S11
S12
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
55
NXP Semiconductors
Dimensions
Table 47. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
S13
Characteristic
Min.
Max.
Unit
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
7
—
—
ns
ns
S14
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
63
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
30
4
—
—
72
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 29. I2S/SAI timing — slave modes
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
56
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Pinout
If you want the drawing for this package
64-pin LQFP
Then use this document number
98ASS23234W
64-pin MAPBGA
100-pin LQFP
98ASA00420D
98ASS23308W
98ASA00595D
121-pin XFBGA
5 Pinout
5.1 K22 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
121
100
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
BGA LQFP LQFP MAP
BGA
E4
1
1
A1
PTE0/
CLKOUT32 SE4a
K
ADC1_
ADC1_
SE4a
PTE0/
CLKOUT32 PCS1
K
SPI1_
UART1_TX
UART1_RX
I2C1_SDA
I2C1_SCL
RTC_
CLKOUT
E3
E2
F4
H7
G4
F3
2
3
4
5
6
7
2
B1
—
—
—
—
—
PTE1/
LLWU_P0
ADC1_
SE5a
ADC1_
SE5a
PTE1/
LLWU_P0
SPI1_
SOUT
SPI1_SIN
—
—
—
—
—
PTE2/
LLWU_P1
ADC1_
SE6a
ADC1_
SE6a
PTE2/
LLWU_P1
SPI1_SCK
UART1_
CTS_b
PTE3
ADC1_
SE7a
ADC1_
SE7a
PTE3
SPI1_SIN
UART1_
RTS_b
SPI1_
SOUT
PTE4/
LLWU_P2
DISABLED
DISABLED
DISABLED
PTE4/
LLWU_P2
SPI1_
PCS0
LPUART0_
TX
PTE5
PTE6
PTE5
PTE6
SPI1_
PCS2
LPUART0_
RX
SPI1_
PCS3
LPUART0_ I2S0_
CTS_b MCLK
USB_SOF_
OUT
E6
G7
L6
8
3
4
C5
C4
—
VDD
VDD
VDD
9
VSS
VSS
VSS
—
10
11
12
13
14
—
5
VSS
VSS
VSS
F1
F2
G1
G2
H1
E1
D1
E2
D2
—
USB0_DP
USB0_DM
USBVDD
NC
USB0_DP
USB0_DM
USBVDD
NC
USB0_DP
USB0_DM
USBVDD
NC
6
7
8
—
ADC0_DP1 ADC0_DP1 ADC0_DP1
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
57
NXP Semiconductors
Pinout
121
100
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
BGA LQFP LQFP MAP
BGA
H2
15
—
—
ADC0_
DM1
ADC0_
DM1
ADC0_
DM1
J1
16
—
—
ADC1_
DP1/
ADC1_
DP1/
ADC1_
DP1/
ADC0_DP2 ADC0_DP2 ADC0_DP2
J2
17
—
—
ADC1_
DM1/
ADC1_
DM1/
ADC1_
DM1/
ADC0_
DM2
ADC0_
DM2
ADC0_
DM2
K1
K2
18
19
9
G1
F1
ADC0_
DP0/
ADC0_
DP0/
ADC0_
DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
10
ADC0_
DM0/
ADC0_
DM0/
ADC0_
DM0/
ADC1_
DM3
ADC1_
DM3
ADC1_
DM3
L1
L2
20
21
11
12
G2
F2
ADC1_
DP0/
ADC1_
DP0/
ADC1_
DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
ADC1_
DM0/
ADC1_
DM0/
ADC1_
DM0/
ADC0_
DM3
ADC0_
DM3
ADC0_
DM3
F5
G5
G6
F6
L3
22
23
24
25
26
13
14
15
16
17
F4
G4
G3
F3
H1
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VREF_
OUT/
VREF_
OUT/
VREF_
OUT/
CMP1_IN5/ CMP1_IN5/ CMP1_IN5/
CMP0_IN5/ CMP0_IN5/ CMP0_IN5/
ADC1_
SE18
ADC1_
SE18
ADC1_
SE18
K5
K4
27
—
18
—
H2
—
DAC0_
OUT/
DAC0_
OUT/
DAC0_
OUT/
CMP1_IN3/ CMP1_IN3/ CMP1_IN3/
ADC0_
SE23
ADC0_
SE23
ADC0_
SE23
CMP0_IN4/ CMP0_IN4/ CMP0_IN4/
ADC1_
SE23
ADC1_
SE23
ADC1_
SE23
L4
L5
K6
H5
28
29
30
31
19
20
21
—
H3
H4
H5
—
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
PTE24
ADC0_
SE17
ADC0_
SE17
PTE24
I2C0_SCL
EWM_
OUT_b
58
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Pinout
121
100
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
BGA LQFP LQFP MAP
BGA
J5
32
—
—
PTE25
ADC0_
ADC0_
PTE25
I2C0_SDA
EWM_IN
SE18
SE18
H6
33
—
—
PTE26/
CLKOUT32
K
DISABLED
PTE26/
CLKOUT32
K
RTC_
CLKOUT
USB_
CLKIN
J6
34
22
D3
PTA0
JTAG_
TCLK/
PTA0
UART0_
CTS_b
FTM0_CH5
JTAG_
TCLK/
EZP_CLK
SWD_CLK/
EZP_CLK
SWD_CLK
H8
J7
35
36
23
24
D4
E5
PTA1
PTA2
JTAG_TDI/
EZP_DI
PTA1
PTA2
UART0_RX FTM0_CH6
UART0_TX FTM0_CH7
JTAG_TDI
EZP_DI
JTAG_
TDO/
JTAG_
TDO/
EZP_DO
TRACE_
SWO/
TRACE_
SWO
EZP_DO
H9
37
25
D5
PTA3
JTAG_
TMS/
PTA3
UART0_
RTS_b
FTM0_CH0
JTAG_
TMS/
SWD_DIO
SWD_DIO
J8
38
39
26
27
G5
F5
PTA4/
LLWU_P3
NMI_b/
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
FTM0_CH2
NMI_b
EZP_CS_b
K7
PTA5
DISABLED
PTA5
USB_
CLKIN
I2S0_TX_
BCLK
JTAG_
TRST_b
E5
G3
K8
40
41
42
—
—
28
—
—
VDD
VDD
VDD
VSS
VSS
VSS
H6
PTA12
DISABLED
PTA12
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
I2S0_TXD0 FTM1_QD_
PHA
L8
K9
43
44
29
—
G6
—
PTA13/
LLWU_P4
DISABLED
DISABLED
PTA13/
LLWU_P4
I2S0_TX_
FS
FTM1_QD_
PHB
PTA14
PTA14
SPI0_
PCS0
I2S0_RX_
BCLK
L9
45
46
—
—
—
—
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
I2S0_RXD0
J10
SPI0_
SOUT
UART0_
CTS_b
I2S0_RX_
FS
H10
47
—
—
PTA17
ADC1_
SE17
ADC1_
SE17
PTA17
SPI0_SIN
UART0_
RTS_b
I2S0_
MCLK
L10
K10
L11
48
49
50
30
31
32
G7
H7
H8
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
FTM0_
FLT2
FTM_
CLKIN0
K11
51
33
G8
PTA19
XTAL0
XTAL0
FTM1_
FLT0
FTM_
CLKIN1
LPTMR0_
ALT1
J11
52
53
34
35
F8
F7
RESET_b
RESET_b
RESET_b
G11
PTB0/
LLWU_P5
ADC0_
SE8/
ADC0_
SE8/
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_
PHA
ADC1_SE8 ADC1_SE8
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
59
NXP Semiconductors
Pinout
121
100
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
BGA LQFP LQFP MAP
BGA
G10
54
36
F6
PTB1
ADC0_
SE9/
ADC1_SE9 ADC1_SE9
ADC0_
SE9/
PTB1
I2C0_SDA
FTM1_CH1
FTM1_QD_
PHB
G9
G8
55
56
—
57
58
59
37
38
—
—
—
—
E7
E8
—
—
—
—
PTB2
PTB3
PTB8
PTB9
PTB10
PTB11
ADC0_
SE12
ADC0_
SE12
PTB2
PTB3
PTB8
PTB9
PTB10
PTB11
I2C0_SCL
I2C0_SDA
UART0_
RTS_b
FTM0_
FLT3
ADC0_
SE13
ADC0_
SE13
UART0_
CTS_b
FTM0_
FLT0
D11
E10
D10
C10
DISABLED
LPUART0_
RTS_b
DISABLED
SPI1_
PCS1
LPUART0_
CTS_b
ADC1_
SE14
ADC1_
SE14
SPI1_
PCS0
LPUART0_
RX
FTM0_
FLT1
ADC1_
SE15
ADC1_
SE15
SPI1_SCK
LPUART0_
TX
FTM0_
FLT2
—
—
60
61
62
—
—
39
—
—
VSS
VSS
VSS
VDD
VDD
VDD
B10
E6
PTB16
DISABLED
PTB16
PTB17
PTB18
PTB19
PTB20
PTB21
SPI1_
SOUT
UART0_RX FTM_
CLKIN0
EWM_IN
E9
D9
C9
F10
F9
63
64
65
66
67
40
41
42
—
—
D7
D6
C7
—
PTB17
PTB18
PTB19
PTB20
PTB21
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
SPI1_SIN
UART0_TX FTM_
CLKIN1
EWM_
OUT_b
FTM2_CH0 I2S0_TX_
BCLK
FTM2_QD_
PHA
FTM2_CH1 I2S0_TX_
FS
FTM2_QD_
PHB
CMP0_
OUT
—
CMP1_
OUT
F8
E8
68
69
—
—
—
—
PTB22
PTB23
DISABLED
DISABLED
PTB22
PTB23
SPI0_
PCS5
B9
D8
C8
70
71
72
43
44
45
D8
C6
B7
PTC0
ADC0_
SE14
ADC0_
SE14
PTC0
SPI0_
PCS4
PDB0_
EXTRG
USB_SOF_
OUT
PTC1/
LLWU_P6
ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6
SPI0_
PCS3
UART1_
RTS_b
FTM0_CH0
I2S0_TXD0 LPUART0_
RTS_b
PTC2
ADC0_
SE4b/
ADC0_
SE4b/
PTC2
SPI0_
PCS2
UART1_
CTS_b
FTM0_CH1
I2S0_TX_
FS
LPUART0_
CTS_b
CMP1_IN0
CMP1_IN0
B8
73
46
C8
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_
PCS1
UART1_RX FTM0_CH2 CLKOUT
I2S0_TX_
BCLK
LPUART0_
RX
—
—
74
75
76
47
48
49
E3
E4
B8
VSS
VDD
VSS
VSS
VDD
VDD
A8
PTC4/
DISABLED
PTC4/
LLWU_P8
SPI0_
PCS0
UART1_TX FTM0_CH3
CMP1_
OUT
LPUART0_
TX
LLWU_P8
60
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Pinout
121
100
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
BGA LQFP LQFP MAP
BGA
D7
C7
B7
A7
77
78
79
80
50
51
52
53
A8
A7
B6
A6
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
CMP0_IN1
PTC5/
LLWU_P9
SPI0_SCK
SPI0_
LPTMR0_
ALT2
I2S0_RXD0
CMP0_
OUT
FTM0_CH2
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10 SOUT
PDB0_
EXTRG
I2S0_RX_
BCLK
I2S0_
MCLK
PTC7
PTC7
SPI0_SIN
USB_SOF_ I2S0_RX_
OUT
FS
PTC8
ADC1_
SE4b/
ADC1_
SE4b/
PTC8
I2S0_
MCLK
CMP0_IN2
CMP0_IN2
D6
81
54
B5
PTC9
ADC1_
SE5b/
ADC1_
SE5b/
PTC9
I2S0_RX_
BCLK
FTM2_
FLT0
CMP0_IN3
CMP0_IN3
C6
C5
82
83
55
56
B4
A5
PTC10
PTC11/
ADC1_
SE6b
ADC1_
SE6b
PTC10
I2C1_SCL
I2C1_SDA
I2S0_RX_
FS
ADC1_
ADC1_
SE7b
PTC11/
LLWU_P11
LLWU_P11 SE7b
B6
A6
A5
B5
F7
E7
D5
84
85
86
87
88
89
90
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTC12
PTC13
PTC14
PTC15
VSS
DISABLED
PTC12
PTC13
PTC14
PTC15
DISABLED
DISABLED
DISABLED
VSS
VSS
VDD
VDD
VDD
PTC16
DISABLED
PTC16
PTC17
PTC18
PTD0/
LPUART0_
RX
C4
B4
D4
D3
C3
B3
A3
A2
B2
A1
A11
91
92
93
94
95
96
97
98
99
100
—
—
—
57
58
59
60
61
62
63
64
—
—
—
PTC17
PTC18
DISABLED
DISABLED
DISABLED
LPUART0_
TX
LPUART0_
RTS_b
C3
A4
C2
B3
A3
C1
B2
A2
—
PTD0/
LLWU_P12
SPI0_
UART2_
RTS_b
LPUART0_
RTS_b
LLWU_P12 PCS0
PTD1
ADC0_
SE5b
ADC0_
SE5b
PTD1
SPI0_SCK
UART2_
CTS_b
LPUART0_
CTS_b
PTD2/
LLWU_P13
DISABLED
DISABLED
DISABLED
PTD2/
LLWU_P13 SOUT
SPI0_
UART2_RX
LPUART0_ I2C0_SCL
RX
PTD3
PTD3
SPI0_SIN
UART2_TX
LPUART0_ I2C0_SDA
TX
PTD4/
LLWU_P14
PTD4/
LLWU_P14 PCS1
SPI0_
UART0_
RTS_b
FTM0_CH4
FTM0_CH5
EWM_IN
SPI1_
PCS0
PTD5
ADC0_
SE6b
ADC0_
SE6b
PTD5
SPI0_
PCS2
UART0_
CTS_b
EWM_
OUT_b
SPI1_SCK
PTD6/
LLWU_P15 SE7b
ADC0_
ADC0_
SE7b
PTD6/
LLWU_P15 PCS3
SPI0_
UART0_RX FTM0_CH6
UART0_TX FTM0_CH7
FTM0_
FLT0
SPI1_
SOUT
PTD7
NC
DISABLED
PTD7
FTM0_
FLT1
SPI1_SIN
NC
NC
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
61
NXP Semiconductors
Pinout
121
100
64
64
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
BGA LQFP LQFP MAP
BGA
K3
H4
B11
C11
H11
C1
D2
D1
E1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
J3
H3
J9
J4
A10
A9
B1
C2
L7
F11
E11
A4
5.2 Recommended connection for unused analog and digital
pins
The following table shows the recommended connections for analog interface pins if
those analog interfaces are not used in the customer's application.
Table 48. Recommended connection for unused analog interfaces
Pin Type
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Short recommendation
Float
Detailed recommendation
Analog input - Float
Analog input - Float
Analog output - Float
Analog output - Float
Analog output - Float
Analog output - Float
Analog input - Float
PGAx/ADCx
ADCx/CMPx
VREF_OUT
DACx_OUT
RTC_WAKEUP_B
XTAL32
Float
Float
Float
Float
Float
Float
EXTAL32
Table continues on the next page...
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Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Pinout
Table 48. Recommended connection for unused analog interfaces (continued)
Pin Type
GPIO/Analog
Short recommendation
Float
Detailed recommendation
Analog input - Float
PTA18/EXTAL0
PTA19/XTAL0
PTx/ADCx
GPIO/Analog
GPIO/Analog
GPIO/Analog
GPIO/Digital
Float
Float
Float
Float
Analog output - Float
Float (default is analog input)
Float (default is analog input)
PTx/CMPx
PTA0/JTAG_TCLK
Float (default is JTAG with
pulldown)
GPIO/Digital
GPIO/Digital
GPIO/Digital
GPIO/Digital
PTA1/JTAG_TDI
PTA2/JTAG_TDO
PTA3/JTAG_TMS
PTA4/NMI_b
Float
Float
Float
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
USB
PTx
Float
Float (default is disabled)
USB0_DP
USB0_DM
USBVDD
VBAT
Float
Float
USB
Float
Float
USB
Tie to ground through 10kΩ
Float
Tie to ground through 10kΩ
Float
VBAT
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFL
VSSA
VREFH
VREFL
VSSA
Always connect to VDD
potential
Always connect to VDD
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
Always connect to VSS
potential
5.3 K22 Pinouts
This figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
63
NXP Semiconductors
Pinout
PTE0/CLKOUT32K
PTE1/LLWU_P0
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
VSS
4
USB0_DP
5
PTC1/LLWU_P6
PTC0
USB0_DM
6
USBVDD
7
PTB19
NC
8
PTB18
ADC0_DP0/ADC1_DP3
9
PTB17
ADC0_DM0/ADC1_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM0/ADC0_DM3
VDDA
10
11
12
13
14
15
16
PTB16
PTB3
PTB2
PTB1
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
VREFL
VSSA
Figure 30. K22 64 LQFP Pinout Diagram (top view)
64
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Pinout
1
2
3
4
5
6
7
8
PTE0/
CLKOUT32K
PTD4/
LLWU_P14
PTC11/
LLWU_P11
PTC6/
LLWU_P10 LLWU_P9
PTC5/
A
B
C
D
E
F
PTD7
PTD1
PTC8
A
B
C
D
E
F
PTE1/
LLWU_P0 LLWU_P15
PTD6/
PTC4/
PTC2
PTD3
PTC10
VSS
PTC9
VDD
PTC7
LLWU_P8
PTD2/
PTD5
PTD0/
LLWU_P13 LLWU_P12
PTC1/
LLWU_P6
PTC3/
PTB19
LLWU_P7
USB0_DM
NC
PTA0
VSS
PTA1
PTA3
PTA2
PTB18
PTB16
PTB17
PTB2
PTC0
PTB3
USB0_DP USBVDD
VDD
ADC0_DM0/ADC1_DM0/
ADC1_DM3 ADC0_DM3
PTB0/
LLWU_P5
VSSA
VREFL
VDDA
VREFH
PTA5
PTB1
RESET_b
PTA19
ADC0_DP0/ ADC1_DP0/
ADC1_DP3 ADC0_DP3
PTA4/
LLWU_P3 LLWU_P4
PTA13/
G
H
VDD
G
H
VREF_OUT/
DAC0_OUT/
CMP1_IN5/
CMP1_IN3/
CMP0_IN5/
ADC0_SE23
ADC1_SE18
XTAL32
3
EXTAL32
4
VBAT
5
PTA12
6
VSS
7
PTA18
8
1
2
Figure 31. K22 64 MAPBGA Pinout Diagram (transparent top view)
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
65
NXP Semiconductors
Pinout
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE0/CLKOUT32K
VDD
2
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VSS
3
PTC3/LLWU_P7
PTC2
4
5
PTC1/LLWU_P6
PTC0
PTE4/LLWU_P2
PTE5
6
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
PTE6
8
VDD
9
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
USB0_DP
USB0_DM
USBVDD
NC
ADC0_DP1
ADC0_DM1
ADC1_DP1/ADC0_DP2
ADC1_DM1/ADC0_DM2
ADC0_DP0/ADC1_DP3
ADC0_DM0/ADC1_DM3
ADC1_DP0/ADC0_DP3
ADC1_DM0/ADC0_DM3
VDDA
VSS
PTB11
PTB10
PTB9
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
VREFH
VREFL
VSSA
Figure 32. K22 100 LQFP Pinout Diagram (top view)
66
NXP Semiconductors
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
Part identification
1
2
3
4
5
6
7
8
9
10
11
PTD4/
LLWU_P14
PTC4/
LLWU_P8
A
B
C
D
E
F
G
H
J
PTD7
PTD5
NC
PTC14
PTC13
PTC8
NC
NC
NC
A
B
C
D
E
F
PTD6/
LLWU_P15
PTC3/
LLWU_P7
NC
NC
NC
NC
PTD3
PTC18
PTC17
PTC15
PTC12
PTC10
PTC9
VDD
PTC7
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTA3
PTB16
PTB11
PTB10
PTB9
NC
NC
PTD2/
LLWU_P13
PTC11/
LLWU_P11
PTC6/
LLWU_P10
NC
PTC2
PTD0/
LLWU_P12
PTC5/
PTC1/
LLWU_P9 LLWU_P6
NC
PTD1
PTE1/
PTC16
VDD
PTB8
NC
PTE2/
PTE0/
VDD
VSS
PTB23
PTB22
PTB3
PTA1
LLWU_P1 LLWU_P0 CLKOUT32K
USB0_DP USB0_DM
PTE6
VSS
NC
PTE3
PTE5
NC
VDDA
VREFH
PTE24
PTE25
VSSA
PTB20
PTB1
NC
PTB0/
LLWU_P5
USBVDD
NC
VREFL
PTE26/
VSS
G
H
J
PTE4/
ADC0_DP1 ADC0_DM1
PTA17
PTA16
VSS
NC
CLKOUT32K LLWU_P2
ADC1_DP1/ ADC1_DM1/
ADC0_DP2 ADC0_DM2
PTA4/
LLWU_P3
NC
NC
PTA0
VBAT
PTA2
PTA5
NC
RESET_b
PTA19
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
ADC0_DP0/ ADC0_DM0/
ADC1_DP3 ADC1_DM3
CMP0_IN4/
ADC1_SE23
K
L
NC
PTA12
PTA14
K
L
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
ADC1_DP0/ ADC1_DM0/
ADC0_DP3 ADC0_DM3
PTA13/
LLWU_P4
XTAL32
4
EXTAL32
5
VSS
6
NC
7
PTA15
9
VDD
10
PTA18
11
1
2
3
8
Figure 33. K22 121 XFBGA Pinout Diagram (top view)
6 Part identification
6.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
67
NXP Semiconductors
Part identification
6.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
6.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow, full
reel
• P = Prequalification
• K = Fully qualified, general market flow, 100
piece reel
K##
A
Kinetis family
Key attribute
• K22
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
Silicon revision
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
R
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 XFBGA (8 mm x 8 mm)
• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• R = Tape and reel
68
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Terminology and guidelines
6.4 Example
This is an example part number:
MK22FN128VDC10
6.5 121-pin XFBGA part marking
The 121-pin XFBGA package parts follow the part-marking scheme in the following
table.
Table 49. 121-pin XFBGA part marking
MK Partnumber
MK Part Marking
MK22FN128VDC10
M22J7VDC
6.6 64-pin MAPBGA part marking
The 64-pin MAPBGA package parts follow the part-marking scheme in the following
table.
Table 50. 64-pin MAPBGA part marking
MK Partnumber
MK Part Marking
MK22FN128VMP10
M22J7V
7 Terminology and guidelines
7.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Table continues on the next page...
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
69
NXP Semiconductors
Terminology and guidelines
Term
Definition
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
7.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
7.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
70
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Revision History
Unit
Symbol
Description
Ambient temperature
Supply voltage
Value
TA
25
°C
V
VDD
3.3
7.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
7.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8 Revision History
The following table provides a revision history for this document.
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
71
NXP Semiconductors
Revision History
Table 51. Revision History
Rev. No.
Date
Substantial Changes
7
08/2016
• Added Terminology and Guidelines section
• Updated the front matter section
• Added Device Revision Number Table
• Updated Chip Errata naming convention in Related Resource table
6
10/2015
• In "Power consumption operating behaviors" section, added "Low power mode
peripheral adders—typical value" table
• In "Thermal operating requirements" table, in footnote, corrected "TJ = TA + ΘJA" to
"TJ = TA + RΘJA
"
• Updated "IRC48M specifications" table
• Updated "NVM program/erase timing specifications" table; updated values for thversall
(Erase All high-voltage time)
• In "Slave mode DSPI timing (limited voltage range)" table, added footnote regarding
maximum frequency of operation
• Added new section, "Recommended connections for unused analog and digital pins"
5
4/2015
• On page 1:
• In first bullet of introduction, updated power consumption data to align with the
data in the "Power consumption operating behaviors" table
• In second bullet of introduction, added "USB FS device crystal-less
functionality"
• Under "Communication interfaces," updated I2C bullet to indicate support for up
to 1 Mbps operation
• Under "Operating characteristics," specified that voltage range includes flash
writes
• In "Voltage and current operating requirements" table:
• Removed content related to positive injection
• Updated footnote 1 to say that all analog and I/O pins are internally clamped to
VSS only (not VSS and VDD)through ESD protection diodes.
• In"Power consumption operating behaviors" table:
• Added additional temperature data in power consumption table
• Added Max IDD values based on characterization results equivalent to mean +
3 sigma
• Updated "EMC radiated emissions operating behaviors" table
• In "Thermal operating requirements" table, added the following footnote for ambient
temperature: "Maximum TA can be exceeded only if the user ensures that TJ does not
exceed maximum TJ. The simplest method to determine TJ is: TJ = TA + ΘJA x chip
power dissipation"
• Updated "IRC48M Specifications":
• Updated maximum values for Δfirc48m_ol_lv and Δfirc48m_ol_hv (full temperature)
• Added specifications for Δfirc48m_ol_hv (-40°C to 85°C)
• Updated notes in "USB electrical specifications" section
• In "I2C timing" table,
• Added the following footnote on maximum Fast mode value for SCL Clock
Frequency: "The maximum SCL Clock Frequency in Fast mode with maximum
bus loading can only be achieved when using the High drive pins across the full
voltage range and when using the Normal drive pins and VDD ≥ 2.7 V."
• Updated minimum Fast mode value for LOW period of the SCL clock to 1.25 µ
• Added "I2C 1 Mbps timing" table
• Specified that the figure, "K22F 64 LQFP Pinout Diagram" is a top view
• Specified that the figure, "K22F 64 MAPBGA Pinout Diagram" is a transparent top
view
• Specified that the figure, "K22F 100 LQFP Pinout Diagram" is a top view
Table continues on the next page...
72
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
NXP Semiconductors
Revision History
Table 51. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Removed Section 6, "Ordering parts."
• Corrected part marking shown in "64-pin MAPBGA part marking" table
4
7/2014
In "Power consumption operating behaviors table":
• Updated existing typical power measurements
• Added new typical power measurements for the following:
• IDD_HSRUN (High Speed Run mode current executing CoreMark code)
• IDD_RUNCO (Run mode current in Compute operation, executing CoreMark
code)
• IDD_RUN (Run mode current in Compute operation, executing while(1) loop)
• IDD_VLPR (Very Low Power mode current executing CoreMark code)
• IDD_VLPR (Very Low Power Run mode current in Compute operation,
executing while(1) loop)
3
5/2014
• In "Voltage and current operating ratings" table, updated maximum digital supply
current
• Updated "Voltage and current operating behaviors" table
• Updated "Power mode transition operating behaviors" table
• Updated "Power consumption operating behaviors" table
• Updated "EMC radiated emissions operating behaviors for 64 LQFP package" table
• Updated "Thermal attributes" table
• Updated "MCG specifications" table
• Updated "IRC48M specifications" table
• Updated "16-bit ADC operating conditions" table
• Updated "Voltage reference electrical specifications" section
• Added "121-pin XFBGA part marking" table
• Added "64-pin MAPBGA part marking" table
2
1
4/2014
3/2014
• In "Voltage and current operating requirements" table, added row for USBVDD
• Updated "Voltage and current operating behaviors" table
• Updated "Thermal attributes" table
• Updated "IRC48M specifications" table
Initial public release
Kinetis K22F 128KB Flash, Rev. 7, 08/2016
73
NXP Semiconductors
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