935325909574 [NXP]
Microprocessor;
NXP 
Document Number S9S08RN16DS
Rev 1, 02/2014
Freescale Semiconductor
Data Sheet: Technical Data
S9S08RN16DS
S9S08RN16 Series Data
Sheet
Supports: S9S08RN16 and S9S08RN8
Key features
• Development support
– Single-wire background debug interface
– Breakpoint capability to allow three breakpoints
setting during in-circuit debugging
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger
modes
• 8-Bit S08 central processor unit (CPU)
– Up to 20 MHz bus at 2.7 V to 5.5 V across
temperature range of -40 °C to 125 °C
– Supporting up to 40 interrupt/reset sources
– Supporting up to four-level nested interrupt
– On-chip memory
– Up to 16 KB flash read/program/erase over full
operating voltage and temperature
– Up to 256 byte EEPROM with ECC; 2-byte
erase sector; EEPROM program and erase
while executing code from flash
– Up to 2048 byte random-access memory (RAM)
– Flash and RAM access protection
• Power-saving modes
– One low-power stop mode; reduced power wait
mode
– Peripheral clock enable register can disable
clocks to unused modules, reducing currents;
allows clocks to remain enabled to specific
peripherals in stop3 mode
• Clocks
– Oscillator (XOSC) - loop-controlled Pierce
oscillator; crystal or ceramic resonator
– Internal clock source (ICS) - containing a
frequency-locked-loop (FLL) controlled by
internal or external reference; precision
trimming of internal reference allowing 1%
deviation across temperature range of 0 °C to
70 °C and -40 °C to 85 °C, 1.5% deviation
across temperature range of -40 °C to 105 °C,
and 2% deviation across temperature range of
-40 °C to 125 °C; up to 20 MHz
• System protection
– Watchdog with independent clock source
– Low-voltage detection with reset or interrupt;
selectable trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
Freescale reserves the right to change the detail specifications as may be
required to permit improvements in the design of its products.
© 2014 Freescale Semiconductor, Inc.
• Peripherals
– ACMP - one analog comparator with both positive and negative inputs; separately selectable interrupt on
rising and falling comparator output; filtering
– ADC - 12-channel, 12-bit resolution for 48-, 32-pin packages; 10-channel, 10-bit resolution for 20-pin
package; 8-channel, 10-bit for 16-pin package; 2.5 µs conversion time; data buffers with optional watermark;
automatic compare function; internal bandgap reference channel; operation in stop mode; optional hardware
trigger
– CRC - programmable cyclic redundancy check module
– FTM - two flex timer modulators modules including one 6-channel and one 2-channel ones; 16-bit counter;
each channel can be configured for input capture, output compare, edge- or center-aligned PWM mode
– IIC - One inter-integrated circuit module; up to 400 kbps; multi-master operation; programmable slave
address; supporting broadcast mode and 10-bit addressing
– MTIM - One modulo timer with 8-bit prescaler and overflow interrupt
– RTC - 16-bit real time counter (RTC)
– SCI - two serial communication interface (SCI/UART) modules optional 13-bit break; full duplex non-return to
zero (NRZ); LIN extension support
– SPI - one 8-bit serial peripheral interface (SPI) modules; full-duplex or single-wire bidirectional; master or
slave mode
– TSI - supporting up to 16 external electrodes; configurable software or hardware scan trigger; fully support
freescale touch sensing software library; capability to wake MCU from stop3 mode
• Input/Output
– Up to 35 GPIOs including one output-only pin
– One 8-bit keyboard interrupt module (KBI)
– Two true open-drain output pins
– Four, ultra-high current sink pins supporting 20 mA source/sink current
• Package options
– 48-pin LQFP
– 32-pin LQFP
– 20-pin TSSOP
– 16-pin TSSOP
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
2
Freescale Semiconductor, Inc.
Table of Contents
1 Ordering parts...........................................................................4
5.2.2 Debug trace timing specifications.........................16
5.2.3 FTM module timing...............................................17
5.3 Thermal specifications.......................................................18
5.3.1 Thermal characteristics.........................................18
6 Peripheral operating requirements and behaviors....................19
6.1 External oscillator (XOSC) and ICS characteristics...........19
6.2 NVM specifications............................................................21
6.3 Analog...............................................................................23
6.3.1 ADC characteristics...............................................23
6.3.2 Analog comparator (ACMP) electricals.................25
6.4 Communication interfaces.................................................26
6.4.1 SPI switching specifications..................................26
6.5 Human-machine interfaces (HMI)......................................29
6.5.1 TSI electrical specifications...................................29
7 Dimensions...............................................................................29
7.1 Obtaining package dimensions.........................................29
8 Pinout........................................................................................30
8.1 Signal multiplexing and pin assignments...........................30
8.2 Device pin assignment......................................................32
9 Revision history.........................................................................34
1.1 Determining valid orderable parts......................................4
2 Part identification......................................................................4
2.1 Description.........................................................................4
2.2 Format...............................................................................4
2.3 Fields.................................................................................4
2.4 Example............................................................................5
3 Parameter Classification...........................................................5
4 Ratings......................................................................................5
4.1 Thermal handling ratings...................................................5
4.2 Moisture handling ratings..................................................6
4.3 ESD handling ratings.........................................................6
4.4 Voltage and current operating ratings...............................6
5 General.....................................................................................7
5.1 Nonswitching electrical specifications...............................7
5.1.1 DC characteristics.................................................7
5.1.2 Supply current characteristics...............................14
5.1.3 EMC performance.................................................15
5.2 Switching specifications.....................................................15
5.2.1 Control timing........................................................15
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
3
Ordering parts
1 Ordering parts
1.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to freescale.com and perform a part number search for the
following device numbers: RN16 and RN8.
2 Part identification
2.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
2.2 Format
Part numbers for this device have the following format:
S 9 S08 RN AA F1 B CC
2.3 Fields
This table lists the possible values for each field in the part number (not all combinations
are valid):
Field
Description
Values
• S = fully qualified, general market flow
• 9 = flash based
S
Qualification status
Memory
9
S08
RN
AA
Core
• S08 = 8-bit CPU
Device family
• RN
Approximate flash size in KB
• 16 = 16 KB
• 8 = 8 KB
F1
B
Fab and mask set identifier
Temperature range (°C)
Package designator
• W2
• M = –40 to 125
• LF = 48-LQFP
CC
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
4
Freescale Semiconductor, Inc.
Parameter Classification
Values
Field
Description
• LC = 32-LQFP
• TJ = 20-TSSOP
• TG = 16-TSSOP
2.4 Example
This is an example part number:
S9S08RN16W2MLF
3 Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods.
To give the customer a better understanding, the following classification is used and the
parameters are tagged accordingly in the tables where appropriate:
Table 1. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant sample size
across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices under
typical conditions unless otherwise noted. All values shown in the typical column are within this category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the
parameter tables where appropriate.
4 Ratings
4.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
5
Ratings
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
4.3 ESD handling ratings
Symbol
VHBM
VCDM
ILAT
Description
Min.
-6000
-500
Max.
+6000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
Electrostatic discharge voltage, charged-device model
Latch-up current at ambient temperature of 125°C
1
2
3
V
-100
+100
mA
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78D, IC Latch-up Test.
• Test was performed at 125 °C case temperature (Class II).
• I/O pins pass +100/-100 mA I-test with Idd current limit at 400mA.
• I/O pins pass +20/-100 mA I-test with Idd current limit at 1000mA.
• Supply groups pass 1.5 Vccmax.
• RESET_B pin was only tested with negative I-test due to product conditioning requirement.
4.4 Voltage and current operating ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in below table may affect
device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this document.
This device contains circuitry protecting against damage due to high static voltage or
electrical fields; however, it is advised that normal precautions be taken to avoid
application of any voltages higher than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate
logic voltage level (for instance, either VSS or VDD) or the programmable pullup resistor
associated with the pin is enabled.
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
6
Freescale Semiconductor, Inc.
General
Unit
Symbol
VDD
Description
Min.
–0.3
—
Max.
5.8
Supply voltage
V
mA
V
IDD
Maximum current into VDD
120
VDIO
Digital input voltage (except RESET, EXTAL, XTAL, or true
open drain pin PTA2 and PTA3)
–0.3
VDD + 0.3
Digital input voltage (true open drain pin PTA2 and PTA3)
Analog1, RESET, EXTAL, and XTAL input voltage
-0.3
–0.3
–25
6
VDD + 0.3
25
V
V
VAIO
ID
Instantaneous maximum current single pin limit (applies to all
port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. All digital I/O pins, except open-drain pin PTA2 and PTA3, are internally clamped to VSS and VDD. PTA2 and PTA3 is only
clamped to VSS
.
5 General
5.1 Nonswitching electrical specifications
5.1.1 DC characteristics
This section includes information about power supply requirements and I/O pin
characteristics.
Table 2. DC characteristics
Symbol
—
C
—
C
Descriptions
Operating voltage
Output high All I/O pins, standard- 5 V, Iload
Min
2.7
Typical1
Max
5.5
—
Unit
V
—
—
—
VOH
=
=
=
=
VDD - 0.8
V
voltage
drive strength
-5 mA
C
C
C
D
3 V, Iload
-2.5 mA
VDD - 0.8
VDD - 0.8
VDD - 0.8
—
—
—
—
—
—
V
V
High current drive
pins, high-drive
strength2
5 V, Iload
-20 mA
3 V, Iload
-10 mA
V
IOHT
Output high
current
Max total IOH for all
ports
5 V
3 V
—
—
—
—
—
—
-100
-50
mA
VOL
C
C
Output low All I/O pins, standard- 5 V, Iload = 5
0.8
V
V
voltage
drive strength
mA
3 V, Iload
2.5 mA
=
—
—
0.8
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
7
Nonswitching electrical specifications
Table 2. DC characteristics (continued)
Symbol
C
Descriptions
Min
Typical1
Max
Unit
C
High current drive
pins, high-drive
strength2
5 V, Iload
=20 mA
—
—
0.8
V
C
D
3 V, Iload
10 mA
=
—
—
0.8
V
IOLT
VIH
VIL
Output low
current
Max total IOL for all
ports
5 V
—
—
—
—
—
—
—
—
—
100
mA
3 V
50
P
C
P
C
C
Input high
voltage
All digital inputs
All digital inputs
All digital inputs
VDD>4.5V
VDD>2.7V
VDD>4.5V
VDD>2.7V
—
0.70 × VDD
0.75 × VDD
—
—
—
V
V
Input low
voltage
0.30 × VDD
0.35 × VDD
—
—
Vhys
|IIn|
Input
hysteresis
0.06 × VDD
mV
µA
µA
P
P
Input leakage
current
All input only pins
(per pin)
VIN = VDD or
VSS
—
—
0.1
0.1
1
1
|IOZ
|
Hi-Z (off-
state) leakage
current
All input/output (per VIN = VDD or
pin) VSS
|IOZTOT
|
C
P
Total leakage All input only and I/O VIN = VDD or
—
—
—
—
2
µA
combined for
all inputs and
Hi-Z pins
VSS
RPU
Pullup
resistors
All digital inputs,
when enabled (all I/O
pins other than PTA2
and PTA3)
—
30.0
50.0
60.0
kΩ
3
RPU
P
D
Pullup
PTA2 and PTA3 pin
—
30.0
kΩ
resistors
IIC
DC injection
current4, 5, 6
Single pin limit
VIN < VSS
VIN > VDD
,
-0.2
-5
—
—
2
mA
Total MCU limit,
includes sum of all
stressed pins
25
CIn
C
C
Input capacitance, all pins
RAM retention voltage
—
—
—
—
—
7
pF
V
VRAM
2.0
—
1. Typical values are measured at 25 °C. Characterized, not tested.
2. Only PTB4, PTB5 support ultra high current output.
3. The specified resistor value is the actual value internal to the device. The pullup value may appear higher when measured
externally on the pin.
4. All functional non-supply pins, except for PTA2 and PTA3, are internally clamped to VSS and VDD
.
5. Input must be current-limited to the value specified. To determine the value of the required current-limiting resistor,
calculate resistance values for positive and negative clamp voltages, then use the large one.
6. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current
conditions. If the positive injection current (VIn > VDD) is higher than IDD, the injection current may flow out of VDD and could
result in external power supply going out of regulation. Ensure that external VDD load will shunt current higher than
maximum injection current when the MCU is not consuming power, such as no system clock is present, or clock rate is
very low (which would reduce overall power consumption).
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
8
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Table 3. LVD and POR Specification
Symbol
VPOR
C
D
C
Description
Min
1.5
4.2
Typ
1.75
4.3
Max
2.0
Unit
V
POR re-arm voltage1, 2
VLVDH
Falling low-voltage detect
threshold - high range (LVDV
= 1)3
4.4
V
VLVW1H
VLVW2H
VLVW3H
VLVW4H
VHYSH
C
C
C
C
C
C
Falling low- Level 1 falling
4.3
4.5
4.6
4.7
—
4.4
4.5
4.5
4.6
4.7
4.8
—
V
V
voltage
warning
threshold -
high range
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
4.6
V
Level 4 falling
(LVWV = 11)
4.7
V
High range low-voltage
detect/warning hysteresis
100
2.61
mV
V
VLVDL
Falling low-voltage detect
threshold - low range (LVDV =
0)
2.56
2.66
VLVDW1L
VLVDW2L
VLVDW3L
VLVDW4L
VHYSDL
VHYSWL
VBG
C
C
C
C
C
C
P
Falling low- Level 1 falling
2.62
2.72
2.82
2.92
—
2.7
2.8
2.9
3.0
40
2.78
2.88
2.98
3.08
—
V
V
voltage
warning
threshold -
low range
(LVWV = 00)
Level 2 falling
(LVWV = 01)
Level 3 falling
(LVWV = 10)
V
Level 4 falling
(LVWV = 11)
V
Low range low-voltage detect
hysteresis
mV
mV
V
Low range low-voltage
warning hysteresis
Buffered bandgap output 4
—
80
—
1.14
1.16
1.18
1. Maximum is highest voltage that POR is guaranteed.
2. POR ramp time must be longer than 20us/V to get a stable startup.
3. Rising thresholds are falling threshold + hysteresis.
4. Voltage factory trimmed at VDD = 5.0 V, Temp = 125 °C
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
9
Nonswitching electrical specifications
strength) (VDD =5 V)
Typical I OHVs. VDD-VOH (low drive
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°
0
1
2
3
4
5
6
7
I OH (mA)
Figure 1. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 5 V)
Typical I OHVs. VDD-VOH (low drive
strength) (VDD =3 V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°C
0
1
2
3
4
5
6
7
I OH(mA)
Figure 2. Typical IOH Vs. VDD-VOH (standard drive strength) (VDD = 3 V)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
10
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
strength) (VDD =5 V)
Typical I OHVs. VDD-VOH (highdrive
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°C
0
5
10
15
20
25
30
I OH(mA)
Figure 3. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 5 V)
Typical I OHVs. VDD-VOH (highdrive
strength) (VDD =3 V)
1.2
1
0.8
0.6
0.4
0.2
0
125°C
25°C
-40°C
0
5
10
15
20
25
30
I OH(mA)
Figure 4. Typical IOH Vs. VDD-VOH (high drive strength) (VDD = 3 V)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
11
Nonswitching electrical specifications
Typical I OLVs. VOL(low drivestrength) (V
DD =5 V)
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°
0
1
2
3
4
5
6
7
I OL(mA)
Figure 5. Typical IOL Vs. VOL (standard drive strength) (VDD = 5 V)
Typical I OLVs. VOL(low drivestrength) (V
DD =3 V)
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°C
0
1
2
3
4
5
6
7
I OL(mA)
Figure 6. Typical IOL Vs. VOL (standard drive strength) (VDD = 3 V)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
12
Freescale Semiconductor, Inc.
Nonswitching electrical specifications
Typical I OLVs. VOL(highdrivestrength) (V
DD =5 V)
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°C
0
5
10
15
20
25
30
I OL(mA)
Figure 7. Typical IOL Vs. VOL (high drive strength) (VDD = 5 V)
Typical I OLVs. VOL(highdrivestrength) (V
DD =3 V)
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
125°C
25°C
-40°
0
5
10
15
20
25
30
I OL(mA)
Figure 8. Typical IOL Vs. VOL (high drive strength) (VDD = 3 V)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
13
Nonswitching electrical specifications
5.1.2 Supply current characteristics
This section includes information about power supply current in various operating modes.
Table 4. Supply current characteristics
Num
C
C
C
Parameter
Symbol Bus Freq
VDD (V)
Typical1
7.60
4.65
1.90
7.05
4.40
1.85
5.88
3.70
1.85
5.35
3.42
1.80
10.9
6.10
1.69
8.18
5.14
1.44
8.50
5.07
1.59
6.11
4.10
1.34
5.95
3.50
1.24
5.45
3.25
1.20
4.6
Max
—
—
—
—
—
—
—
—
—
—
—
—
14.0
—
—
—
—
—
13.0
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
Temp
1
Run supply current FEI
mode, all modules on; run
from flash
RIDD
RIDD
RIDD
RIDD
WIDD
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
20 MHz
10 MHz
1 MHz
—
5
mA -40 to 125 °C
mA -40 to 125 °C
mA -40 to 125 °C
mA -40 to 125 °C
mA -40 to 125 °C
C
C
3
5
3
5
3
5
3
5
3
2
3
4
5
C
C
Run supply current FEI
mode, all modules off &
gated; run from flash
C
C
P
C
Run supply current FBE
mode, all modules on; run
from RAM
C
P
C
Run supply current FBE
mode, all modules off &
gated; run from RAM
C
C
C
Wait mode current FEI
mode, all modules on
6
7
C
C
Stop3 mode supply
current no clocks active
(except 1kHz LPO
clock)2, 3
S3IDD
5
3
µA
µA
-40 to 125 °C
-40 to 125 °C
—
4.5
C
ADC adder to stop3
—
—
5
40
—
-40 to 125 °C
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
14
Freescale Semiconductor, Inc.
Switching specifications
Table 4. Supply current characteristics (continued)
Num
C
Parameter
Symbol Bus Freq
VDD (V)
Typical1
Max
Unit
Temp
ADLPC = 1
C
3
39
—
ADLSMP = 1
ADCO = 1
MODE = 10B
ADICLK = 11B
TSI adder to stop34
PS = 010B
8
C
C
—
—
5
3
121
120
—
—
µA
-40 to 125 °C
NSCN = 0x0F
EXTCHRG = 0
REFCHRG = 0
DVOLT = 01B
LVD adder to stop35
9
C
C
—
—
5
3
128
124
—
—
µA
-40 to 125 °C
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. RTC adder cause <1 µA IDD increase typically, RTC clock source is 1kHz LPO clock.
3. ACMP adder cause <10 µA IDD increase typically.
4. The current varies with TSI configuration and capacity of touch electrode. Please refer toTSI electrical specifications.
5. LVD is periodically woken up from stop3 by 5% duty cycle. The period is equal to or less than 2 ms.
5.1.3 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should
consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and
AN1259 for advice and guidance specifically targeted at optimizing EMC performance.
5.2 Switching specifications
5.2.1 Control timing
Table 5. Control timing
Num
C
P
P
Rating
Bus frequency (tcyc = 1/fBus
Internal low power oscillator frequency
Symbol
fBus
Min
DC
Typical1
—
Max
20
Unit
MHz
KHz
1
2
)
fLPO
0.67
1.0
1.25
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
15
Switching specifications
Table 5. Control timing (continued)
Num
C
Rating
Symbol
Min
1.5 ×
Typical1
Max
Unit
3
D
External reset pulse width2
textrst
—
—
ns
tSelf_reset
34 × tcyc
500
4
5
D
D
Reset low drive
trstdrv
—
—
—
—
ns
ns
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
6
7
D
D
BKGD/MS hold time after issuing background
debug force reset to enter user or BDM modes3
tMSH
tILIH
100
100
—
—
—
—
ns
ns
Keyboard interrupt pulse
width
Asynchronous
path2
D
C
C
Synchronous path
—
tIHIL
tRise
tFall
1.5 × tcyc
—
10.2
9.5
—
—
—
ns
ns
ns
8
Port rise and fall time -
standard drive strength
(load = 50 pF)4
—
—
C
C
Port rise and fall time -
high drive strength (load =
50 pF)4
—
tRise
tFall
—
—
5.4
4.6
—
—
ns
ns
1. Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of tMSH after
VDD rises above VLVD
.
4. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range -40 °C to 125 °C.
textrst
RESET PIN
Figure 9. Reset timing
tIHIL
KBIPx
KBIPx
tILIH
Figure 10. KBIPx timing
5.2.2 Debug trace timing specifications
Table 6. Debug trace operating behaviors
Symbol
tcyc
Description
Clock period
Min.
Max.
Unit
MHz
ns
Frequency dependent
twl
Low pulse width
2
—
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
16
Freescale Semiconductor, Inc.
Switching specifications
Table 6. Debug trace operating behaviors (continued)
Symbol
Description
Min.
2
Max.
—
3
Unit
ns
twh
tr
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
—
—
3
ns
tf
3
ns
ts
—
—
ns
th
Data hold
2
ns
Figure 11. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 12. Trace data specifications
5.2.3 FTM module timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the
fastest clock that can be used as the optional external source to the timer counter. These
synchronizers operate from the current bus rate clock.
Table 7. FTM input timing
No.
C
Function
Symbol
Min
Max
Unit
1
D
External clock
frequency
fTCLK
0
fBus/4
Hz
2
3
4
5
D
D
D
D
External clock
period
tTCLK
tclkh
4
—
—
—
—
tcyc
tcyc
tcyc
tcyc
External clock
high time
1.5
1.5
1.5
External clock
low time
tclkl
Input capture
pulse width
tICPW
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
17
Thermal specifications
tTCLK
tclkh
TCLK
tclkl
Figure 13. Timer external clock
tICPW
FTMCHn
FTMCHn
tICPW
Figure 14. Timer input capture pulse
5.3 Thermal specifications
5.3.1 Thermal characteristics
This section provides information about operating temperature range, power dissipation,
and package thermal resistance. Power dissipation on I/O pins is usually small compared
to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-
determined rather than being controlled by the MCU design. To take PI/O into account in
power calculations, determine the difference between actual pin voltage and VSS or VDD
and multiply by the pin current for each I/O pin. Except in cases of unusually high pin
current (heavy loads), the difference between pin voltage and VSS or VDD will be very
small.
Table 8. Thermal characteristics
Rating
Symbol
Value
Unit
Operating temperature range TA
(packaged)
TL to TH -40 to 125
°C
°C
Junction temperature range
TJ
-40 to 135
Thermal resistance single-layer board
48-pin LQFP
32-pin LQFP
20-pin TSSOP
16-pin TSSOP
θJA
θJA
θJA
θJA
82
°C/W
°C/W
°C/W
°C/W
88
116
130
Thermal resistance four-layer board
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
18
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 8. Thermal characteristics (continued)
Rating
48-pin LQFP
Symbol
Value
Unit
θJA
θJA
θJA
θJA
58
59
76
87
°C/W
°C/W
°C/W
°C/W
32-pin LQFP
20-pin TSSOP
16-pin TSSOP
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts - chip internal power
PI/O = Power dissipation on input and output pins - user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship
between PD and TJ (if PI/O is neglected) is:
PD = K ÷ (TJ + 273 °C)
Solving the equations above for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
where K is a constant pertaining to the particular part. K can be determined by measuring
PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be
obtained by solving the above equations iteratively for any value of TA.
6 Peripheral operating requirements and behaviors
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
19
Peripheral operating requirements and behaviors
6.1 External oscillator (XOSC) and ICS characteristics
Table 9. XOSC and ICS specifications (temperature range = -40 to 125 °C ambient)
Num
C
C
C
Characteristic
Low range (RANGE = 0)
Symbol
Min
32
4
Typical1
Max
40
Unit
kHz
1
Oscillator
crystal or
resonator
flo
fhi
—
—
High range (RANGE = 1)
FEE or FBE mode2
20
MHz
C
C
High range (RANGE = 1),
high gain (HGO = 1),
FBELP mode
fhi
4
4
—
—
20
20
MHz
MHz
High range (RANGE = 1),
low power (HGO = 0),
FBELP mode
fhi
2
3
D
D
Load capacitors
C1, C2
RF
See Note3
—
Feedback
resistor
Low Frequency, Low-Power
Mode4
—
—
—
—
—
—
—
—
MΩ
MΩ
MΩ
MΩ
Low Frequency, High-Gain
Mode
10
1
High Frequency, Low-
Power Mode
High Frequency, High-Gain
Mode
1
4
5
D
D
Series resistor -
Low Frequency
Low-Power Mode 4
High-Gain Mode
Low-Power Mode4
RS
RS
—
—
—
—
200
—
—
—
—
kΩ
kΩ
kΩ
Series resistor -
High Frequency
D
D
D
Series resistor -
High
Frequency,
High-Gain Mode
4 MHz
8 MHz
16 MHz
—
—
—
0
0
0
—
—
—
kΩ
kΩ
kΩ
6
C
C
C
C
Crystal start-up
time Low range
= 39.0625 kHz
crystal; High
Low range, low power
Low range, high power
High range, low power
High range, high power
tCSTL
—
—
—
—
1000
800
3
—
—
—
—
ms
ms
ms
ms
tCSTH
range = 20 MHz
1.5
crystal5, 6
7
8
T
D
D
Internal reference start-up time
tIRST
fextal
—
0.03125
0
20
—
—
50
5
µs
Square wave
FEE or FBE mode2
MHz
MHz
input clock
frequency
FBELP mode
20
9
P
Average internal reference frequency -
trimmed
fint_t
—
39.0625
—
kHz
10
11
P
P
DCO output frequency range - trimmed
fdco_t
16
—
—
—
20
MHz
Total deviation Over full voltage range and
of DCO output temperature range of -40 to
Δfdco_t
2.0
from trimmed
125 °C
frequency5
C
Over full voltage range and
temperature range of -40 to
105 °C
1.5
%fdco
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
20
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 9. XOSC and ICS specifications (temperature range = -40 to 125 °C ambient)
(continued)
Num
C
Characteristic
Symbol
Min
Typical1
Max
Unit
C
Over fixed voltage and
1.0
temperature range of 0 to
70 °C
12
13
C
C
FLL acquisition time5, 7
tAcquire
CJitter
—
—
—
2
ms
Long term jitter of DCO output clock
(averaged over 2 ms interval)8
0.02
0.2
%fdco
1. Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value.
2. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25
kHz to 39.0625 kHz.
3. See crystal or resonator manufacturer's recommendation.
4. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE = HGO =
0.
5. This parameter is characterized and not tested on each device.
6. Proper PC board layout procedures must be followed to achieve specifications.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed, or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as
the reference, this specification assumes it is already running.
8. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage
for a given interval.
XOSC
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Figure 15. Typical crystal or resonator circuit
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
21
Peripheral operating requirements and behaviors
6.2 NVM specifications
This section provides details about program/erase times and program/erase endurance for
the flash and EEPROM memories.
Table 10. Flash characteristics
C
Characteristic
Symbol
Min1
Typical2
Max3
Unit4
D
Supply voltage for program/erase -40 °C
to 125 °C
Vprog/erase
2.7
—
5.5
V
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
Supply voltage for read operation
NVM Bus frequency
VRead
fNVMBUS
fNVMOP
tVFYALL
tRD1BLK
tRD1BLK
tRD1SEC
tDRD1SEC
tRDONCE
tPGM2
2.7
1
—
—
5.5
25
V
MHz
MHz
tcyc
tcyc
tcyc
tcyc
tcyc
tcyc
ms
NVM Operating frequency
Erase Verify All Blocks
Erase Verify Flash Block
Erase Verify EEPROM Block
Erase Verify Flash Section
Erase Verify EEPROM Section
Read Once
0.8
1
1.05
17338
16913
810
—
—
—
—
—
—
—
—
484
—
—
555
—
—
450
Program Flash (2 word)
Program Flash (4 word)
Program Once
0.12
0.20
0.20
0.10
0.17
0.25
0.32
96.01
95.98
19.10
4.81
96.01
—
0.12
0.21
0.21
0.10
0.18
0.26
0.33
100.78
100.75
20.05
5.05
100.78
—
0.29
0.46
0.21
0.27
0.43
0.60
0.77
101.49
101.44
20.08
20.57
101.48
464
tPGM4
ms
tPGMONCE
tDPGM1
tDPGM2
tDPGM3
tDPGM4
tERSALL
tERSBLK
tERSPG
tDERSPG
tUNSECU
tVFYKEY
tMLOADU
nFLPE
ms
Program EEPROM (1 Byte)
Program EEPROM (2 Byte)
Program EEPROM (3 Byte)
Program EEPROM (4 Byte)
Erase All Blocks
ms
ms
ms
ms
ms
Erase Flash Block
ms
Erase Flash Sector
ms
Erase EEPROM Sector
Unsecure Flash
ms
ms
Verify Backdoor Access Key
Set User Margin Level
tcyc
tcyc
Cycles
—
—
407
FLASH Program/erase endurance TL to
TH = -40 °C to 125 °C
10 k
100 k
—
C
C
EEPROM Program/erase endurance TL
to TH = -40 °C to 125 °C
nFLPE
tD_ret
50 k
15
500 k
100
—
—
Cycles
years
Data retention at an average junction
temperature of TJavg = 85°C after up to
10,000 program/erase cycles
1. Minimum times are based on maximum fNVMOP and maximum fNVMBUS
2. Typical times are based on typical fNVMOP and maximum fNVMBUS
3. Maximum times are based on typical fNVMOP and typical fNVMBUS plus aging
4. tcyc = 1 / fNVMBUS
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
22
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Program and erase operations do not require any special power sources other than the
normal VDD supply. For more detailed information about program/erase operations, see
the Memory section.
6.3 Analog
6.3.1 ADC characteristics
Table 11. 5 V 12-bit ADC operating conditions
Characteri
stic
Conditions
Symb
Min
Typ1
Max
Unit
Comment
Supply
voltage
Absolute
VDDA
ΔVDDA
ΔVSSA
2.7
—
0
5.5
V
—
Delta to VDD (VDD-VDDAD
)
-100
-100
+100
+100
mV
mV
2
Ground
voltage
Delta to VSS (VSS-VSSA
)
0
Input
voltage
VADIN
CADIN
RADIN
RAS
VREFL
—
—
4.5
3
VREFH
5.5
V
Input
capacitance
pF
kΩ
kΩ
Input
resistance
—
5
—
Analog
source
resistance
12-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
External to
MCU
—
—
—
—
2
5
•
•
10-bit mode
fADCK > 4 MHz
fADCK < 4 MHz
—
—
—
—
—
—
5
•
•
10
10
8-bit mode
(all valid fADCK
)
ADC
conversion
clock
High speed (ADLPC=0)
Low power (ADLPC=1)
fADCK
0.4
0.4
—
—
8.0
4.0
MHz
—
frequency
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
23
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
z ADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
ZAS
leakage
due to
input
ADC SAR
ENGINE
R AS
R ADIN
protection
v ADIN
C AS
v AS
R ADIN
R ADIN
R ADIN
INPUT PIN
INPUT PIN
INPUT PIN
C ADIN
Figure 16. ADC input impedance equivalency diagram
Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA
)
Characteristic
Supply current
ADLPC = 1
Conditions
C
Symb
Min
Typ1
Max
Unit
T
IDDA
—
133
—
µA
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 1
T
T
T
IDDA
—
—
—
218
327
582
—
—
µA
µA
µA
ADLSMP = 0
ADCO = 1
Supply current
ADLPC = 0
IDDA
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
IDDAD
990
ADLSMP = 0
ADCO = 1
Supply current
Stop, reset, module
off
T
P
IDDA
—
2
0.011
3.3
1
5
µA
ADC asynchronous High speed (ADLPC
clock source = 0)
fADACK
MHz
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
24
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 12. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
Low power (ADLPC
= 1)
1.25
2
3.3
Conversion time
(including sample
time)
Short sample
(ADLSMP = 0)
T
tADC
—
—
—
—
20
40
—
—
—
—
ADCK
cycles
Long sample
(ADLSMP = 1)
Sample time
Short sample
(ADLSMP = 0)
T
tADS
3.5
23.5
ADCK
cycles
Long sample
(ADLSMP = 1)
Total unadjusted
Error2
12-bit mode
10-bit mode
8-bit mode
T
P
P4
ETUE
DNL
INL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5.0
1.5
—
LSB3
LSB3
LSB3
LSB3
LSB3
2.0
1.0
—
0.7
Differential Non-
Linearity
12-bit mode
10-bit mode5
8-bit mode5
T
1.0
P
P4
0.25
0.15
1.0
0.5
0.25
—
Integral Non-Linearity 12-bit mode
10-bit mode
T
T
0.3
0.5
0.25
—
8-bit mode
T
0.15
2.0
Zero-scale error6
Full-scale error7
Quantization error
12-bit mode
10-bit mode
8-bit mode
C
EZS
P
0.25
0.65
2.5
1.0
1.0
—
P4
T
12-bit mode
10-bit mode
8-bit mode
EFS
T
0.5
1.0
1.0
0.5
T
0.5
≤12 bit modes
D
D
D
EQ
EIL
m
—
LSB3
mV
Input leakage error8 all modes
IIn * RAS
3.266
3.638
1.396
Temp sensor slope
-40°C– 25°C
25°C– 125°C
—
—
—
—
—
—
mV/°C
Temp sensor voltage 25°C
D
VTEMP25
V
1. Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. Includes quantization.
3. 1 LSB = (VREFH - VREFL)/2N
4. 10-bit mode only for package LQFP48/32, TSSOP20/16. Those parameters are only achieved by the design
characterization.
5. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes
6. VADIN = VSSA
7. VADIN = VDDA
8. IIn = leakage current (refer to DC characteristics)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
25
Peripheral operating requirements and behaviors
6.3.2 Analog comparator (ACMP) electricals
Table 13. Comparator electrical specifications
C
D
T
Characteristic
Supply voltage
Symbol
VDDA
IDDA
VAIN
VAIO
VH
Min
2.7
Typical
—
Max
5.5
20
Unit
V
Supply current (Operation mode)
Analog input voltage
—
10
µA
V
D
P
C
C
T
VSS - 0.3
—
—
VDDA
40
Analog input offset voltage
Analog comparator hysteresis (HYST=0)
Analog comparator hysteresis (HYST=1)
Supply current (Off mode)
Propagation Delay
—
mV
mV
mV
nA
µs
—
15
20
VH
—
20
30
IDDAOFF
tD
—
60
—
C
—
0.4
1
6.4 Communication interfaces
6.4.1 SPI switching specifications
The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
VDD and 70% VDD, unless noted, and 100 pF load on all SPI pins. All timing assumes
slew rate control is disabled and high drive strength is enabled for SPI output pins.
Table 14. SPI master mode timing
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
fBus/2048
fBus/2
Hz
fBus is the bus
clock
2
3
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
2 x tBus
2048 x tBus
ns
tSPSCK
tSPSCK
ns
tBus = 1/fBus
1/2
—
—
—
—
—
—
—
—
—
4
1/2
—
5
tWSPSCK Clock (SPSCK) high or low time
tBus - 30
1024 x tBus
6
tSU
tHI
tv
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
15
0
—
—
ns
7
ns
8
—
0
25
ns
9
tHO
tRI
—
ns
10
—
tBus - 25
ns
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
26
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 14. SPI master mode timing (continued)
Nu
m.
Symbol Description
Min.
Max.
Unit
Comment
tFI
Fall time input
Rise time output
Fall time output
11
tRO
tFO
—
25
ns
—
1
SS
(OUTPUT)
3
2
10
10
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
11
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 17. SPI master mode timing (CPHA=0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. SPI master mode timing (CPHA=1)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
27
Peripheral operating requirements and behaviors
Table 15. SPI slave mode timing
Nu
m.
Symbol
Description
Min.
Max.
Unit
Comment
1
fop
Frequency of operation
0
fBus/4
Hz
fBus is the bus clock as
defined in .
2
3
4
5
6
7
8
tSPSCK
tLead
tLag
SPSCK period
Enable lead time
Enable lag time
4 x tBus
—
—
ns
tBus
tBus
ns
tBus = 1/fBus
1
1
—
—
—
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tBus - 30
15
—
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
—
ns
25
—
ns
—
tBus
ns
Time to data active from
high-impedance state
9
tdis
Slave MISO disable time
—
tBus
ns
Hold time to high-
impedance state
10
11
12
tv
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
—
0
25
—
ns
ns
ns
—
—
—
tHO
tRI
—
tBus - 25
tFI
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
SS
(INPUT)
2
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
12
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 19. SPI slave mode timing (CPHA = 0)
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
28
Freescale Semiconductor, Inc.
Dimensions
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
MISO
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
note
(OUTPUT)
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 20. SPI slave mode timing (CPHA=1)
6.5 Human-machine interfaces (HMI)
6.5.1 TSI electrical specifications
Table 16. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Type
100
—
Max
—
Unit
µA
Fixed power consumption in run mode
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
—
—
10
µA
µA
µs
pF
%
TSI_TEN
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
Voltage variation of VP & VM around nominal
values
-10
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
29
Pinout
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
16-pin TSSOP
Then use this document number
98ASH70247A
20-pin TSSOP
98ASH70169A
32-pin LQFP
98ASH70029A
48-pin LQFP
98ASH00962A
8 Pinout
8.1 Signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
Table 17. Pin availability by package pin-count
Pin Number
Lowest Priority <-- --> Highest
48-LQFP 32-LQFP 20-TSSOP 16-TSSOP
Port Pin
PTD11
PTD01
PTE4
PTE3
—
Alt 1
Alt 2
Alt 3
Alt 4
—
1
2
1
2
—
—
—
—
3
—
—
—
—
3
—
—
—
—
—
—
—
—
—
—
—
FTM2CH3
—
—
FTM2CH2
—
3
—
—
3
TCLK2
—
—
4
BUSOUT
—
—
5
—
—
—
—
—
—
—
—
VDD
VREFH
VREFL
VSS
6
4
—
—
4
—
—
4
—
VDDA
VSSA
—
7
5
—
8
6
—
9
7
5
5
PTB7
PTB6
—
SCL
SDA
—
EXTAL
XTAL
Vss
10
11
12
13
14
15
16
17
18
8
6
6
—
—
—
9
—
—
—
7
—
—
—
7
NC
NC
PTB51
PTB41
PTC3
PTC2
PTD7
—
—
—
—
—
FTM2CH5
FTM2CH4
FTM2CH3
FTM2CH2
—
SS0
MISO0
ADP11
ADP10
—
—
—
10
11
12
—
8
8
9
—
—
—
TSI9
TSI8
—
10
—
Table continues on the next page...
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
30
Freescale Semiconductor, Inc.
Pinout
Table 17. Pin availability by package pin-count (continued)
Pin Number
Lowest Priority <-- --> Highest
48-LQFP 32-LQFP 20-TSSOP 16-TSSOP
Port Pin
PTD6
PTD5
PTC1
PTC0
PTB3
PTB2
PTB1
PTB0
PTA7
PTA6
NC
Alt 1
Alt 2
—
Alt 3
Alt 4
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
—
—
13
14
15
16
17
18
19
20
—
—
—
—
21
22
23
24
25
26
27
28
—
—
—
—
29
30
31
32
—
—
11
12
13
14
15
16
—
—
—
—
—
—
—
—
17
18
19
20
—
—
—
—
—
—
—
—
1
—
—
—
—
9
—
—
—
—
—
—
—
—
FTM2CH1
FTM2CH0
MOSI0
ADP9
ADP8
ADP7
ADP6
ADP5
ADP4
ADP3
ADP2
TSI7
TSI6
TSI5
TSI4
TSI3
TSI2
TSI1
TSI0
—
KBI0P7
KBI0P6
KBI0P5
KBI0P4
—
10
11
12
—
—
—
—
—
—
—
—
13
14
15
16
—
—
—
—
—
—
—
—
1
SPSCK0
TXD0
RXD0
FTM2FAULT2
FTM2FAULT1
—
—
—
—
—
—
—
—
Vss
VDD
—
PTD4
PTD3
PTD2
PTA32
PTA22
PTA1
PTA0
PTC7
PTC6
NC
—
—
—
—
—
—
—
TSI15
TSI14
—
—
—
—
KBI0P3
KBI0P2
KBI0P1
KBI0P0
—
TXD0
RXD0
FTM0CH1
FTM0CH0
TxD1
RxD1
SCL
SDA
ACMP1
ACMP0
—
—
ADP1
ADP0
TSI13
TSI12
—
—
PTE2
PTE1
PTE0
PTC5
PTC4
—
—
—
—
—
—
—
—
MISO0
MOSI0
SPSCK0
FTM0CH1
FTM0CH0
—
—
—
—
—
—
—
—
TSI11
TSI10
RESET
MS
—
—
2
2
—
—
BKGD
1. This is a high current drive pin when operated as output.
2. This is a true open-drain pin when operated as output.
Note
When an alternative function is first enabled, it is possible to
get a spurious edge to the module. User software must clear any
associated flags before interrupts are enabled. The table above
illustrates the priority if multiple modules are enabled. The
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
31
Pinout
highest priority module will have control over the pin. Selecting
a higher priority pin function with a lower priority function
already enabled can cause spurious edges to the lower priority
module. Disable all modules that share a pin before enabling
another module.
8.2 Device pin assignment
1
2
1
2
36
35
PTD1/FTM2CH3
PTD0/FTM2CH2
PTA2/KBI0P2/RxD0/SDA
1
2
PTA3/KBI0P3/TxD0/SCL
3
PTE4/TCLK2
34 PTD2/TSI14
33
PTD3/TSI15
32 PTD4
4
PTE3/BUSOUT
5
V
DD
REFH
SSA /V
6
31
30
V
DD
V
SS
V
DDA /V
7
V
REFL
8
29 NC
28 PTA6/FTM2FAULT1/ADP2/TSI0
PTA7/FTM2FAULT2/ADP3/TSI1
26 PTB0/KBI0P4/RxD0/ADP4/TSI2
25
V
SS
9
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
10
11
27
V
SS
NC 12
PTB1/KBI0P5/TxD0/ADP5/TSI3
1. High source/sink current pins
2. True open drain pins
Figure 21. S9S08RN16 48-pin LQFP package
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
32
Freescale Semiconductor, Inc.
Pinout
1
1
2
1
2
3
4
5
6
7
8
PTD1/FTM2CH3
PTD0/FTM2CH2
24
23
22
21
20
19
18
17
PTA2/KBI0P2/RxD0/SDA
2
PTA3/KBI0P3/TxD0/SCL
V
PTD2/TSI14
PTD3/TSI15
DD
DDA REFH
V
/V
/V
V
PTA6/FTM2FAULT1/ADP2/TSI0
PTA7/FTM2FAULT2/ADP3/TSI1
PTB0/KBI0P4/RxD0/ADP4/TSI2
PTB1/KBI0P5/TxD0/ADP5/TSI3
SSA REFL
V
SS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
Pins in
are not available on less pin-count packages.
bold
1. High source/sink current pins
2. True open drain pins
Figure 22. S9S08RN16 32-pin LQFP package
RESET
20
19
18
17
16
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0
PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
1
2
BKGD/MS
2
V
PTA2/KBI0P2/RxD0/SDA
3
DD
2
V
PTA3/KBI0P3/TxD0/SCL
SS
4
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
PTB0/KBI0P4/RxD0/ADP4/TSI2
PTB1/KBI0P5/TxD0/ADP5/TSI3
PTB2/KBI0P6/SPSCK0/ADP6/TSI4
PTB3/KBI0P7/MOSI0/ADP7/TSI5
PTC0/FTM2CH0/ADP8/TSI6
PTC1/FTM2CH1/ADP9/TSI7
5
15
14
13
6
1
PTB5/FTM2CH5/SS0
7
1
PTB4/FTM2CH4/MISO0
8
PTC3/FTM2CH3/ADP11/TSI9
PTC2/FTM2CH2/ADP10/TSI8
12
11
9
10
Pins in bold are not available on less pin-count packages.
1. High source/sink current pins
2. True open drain pins
Figure 23. S9S08RN16 20-pin TSSOP package
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
Freescale Semiconductor, Inc.
33
Revision history
16
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0
PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
RESET
BKGD/MS
1
2
3
4
5
6
7
8
15
14
13
2
V
PTA2/KBI0P2/RxD0/SDA
DD
2
V
PTA3/KBI0P3/TxD0/SCL
SS
PTB7/SCL/EXTAL
PTB6/SDA/XTAL
12
11
10
9
PTB0/KBI0P4/RxD0/ADP4/TSI2
PTB1/KBI0P5/TxD0/ADP5/TSI3
PTB2/KBI0P6/SPSCK0/ADP6/TSI4
PTB3/KBI0P7/MOSI0/ADP7/TSI5
1
PTB5/FTM2CH5/SS0
1
PTB4/FTM2CH4/MISO0
1. High source/sink current pins
2. True open drain pins
Figure 24. S9S08RN16 16-pin TSSOP package
9 Revision history
The following table provides a revision history for this document.
Table 18. Revision history
Rev. No.
Date
Substantial Changes
1
02/2014
Initial Release
S9S08RN16 Series Data Sheet, Rev1, 02/2014.
34
Freescale Semiconductor, Inc.
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Document Number S9S08RN16DS
Revision 1, 02/2014
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