935325938557_技术文档

Document Number T4240

Rev. 1, 05/2016

NXP Semiconductors

Data Sheet: Technical Data

T4240

QorIQ T4240 Data Sheet

Features

• 32 SerDes lanes at up to 10 Gb/s

• 12 e6500 cores built on Power Architecture®

technology and arranged as clusters of four e6500

cores sharing a 2 MB L2 cache

• Ethernet interfaces

– Up to four 10 Gbps Ethernet MACs

– Up to sixteen 1 Gbps Ethernet MACs

– Combinations of 1 Gbps and 10 Gbps Ethernet

MACs

• 1.5 MB CoreNet platform cache (CPC)

• Hierarchical interconnect fabric

– IEEE Std 1588™ support

– CoreNet fabric supporting coherent and non-

coherent transactions with prioritization and

bandwidth allocation amongst CoreNet end-points

– 1.6 Tbps coherent read bandwidth

• High-speed peripheral interfaces

– Four PCI Express 2.0/3.0 controllers running at up

to 8 GT/s with one controllers supporting end-point,

single-root I/O virtualization (SR-IOV)

– Two Serial RapidIO 2.0 controllers running at up to

5 Gbaud

• Three 64-bit DDR3 SDRAM memory controllers

– DDR3 and DDR3L with ECC and interleaving

support

– Interlaken look-aside interface for TCAM

connection

• Data Path Acceleration Architecture (DPAA)

incorporating acceleration for the following functions:

– Packet parsing, classification, and distribution

(Frame Manager 1.1)

• Additional peripheral interfaces

– Two Serial ATA (SATA 2.0) controllers

– Two high-speed USB 2.0 controllers with integrated

PHY

– Queue management for scheduling, packet

sequencing, and congestion management (Queue

Manager 1.1)

– Enhanced secure digital host controller (SD/MMC/

eMMC)

– Hardware buffer management for buffer allocation

and de-allocation (Buffer Manager 1.1)

– Cryptography Acceleration (SEC 5.0)

– RegEx Pattern Matching Acceleration (PME 2.0)

– Decompression/Compression Acceleration (DCE

1.0)

– Enhanced Serial peripheral interface (eSPI)

– Four I2C controllers

– Four 2-pin UARTs or two 4-pin DUARTs

– Integrated flash controller supporting NAND and

NOR flash

• Three 8-channel DMA engines

– DPAA chip-to-chip interconnect via RapidIO

Message Manager (RMan 1.0)

• 1932 FC-PBGA package, 45 mm x 45 mm, 1mm pitch

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Table of Contents

1 Overview.............................................................................................. 3

3.16 JTAG controller.........................................................................124

3.17 I2C interface.............................................................................. 127

3.18 GPIO interface...........................................................................130

3.19 High-speed serial interfaces (HSSI).......................................... 132

4 Hardware design considerations...........................................................188

4.1 System clocking........................................................................ 188

4.2 Power supply design..................................................................204

4.3 Decoupling recommendations...................................................213

4.4 SerDes block power supply decoupling recommendations.......213

4.5 Connection recommendations................................................... 214

4.6 Thermal......................................................................................225

4.7 Recommended thermal model...................................................226

4.8 Thermal management information............................................ 226

5 Package information.............................................................................229

5.1 Package parameters for the FC-PBGA......................................229

5.2 Mechanical dimensions of the FC-PBGA................................. 229

6 Security fuse processor.........................................................................231

7 Ordering information............................................................................231

7.1 Part numbering nomenclature....................................................231

7.2 Orderable part numbers addressed by this document................232

8 Revision history....................................................................................234

2 Pin assignments....................................................................................3

2.1 1932 ball layout diagrams......................................................... 4

2.2 Pinout list...................................................................................10

3 Electrical characteristics.......................................................................73

3.1 Overall DC electrical characteristics.........................................73

3.2 Power sequencing......................................................................80

3.3 Power-down requirements.........................................................82

3.4 Power characteristics.................................................................83

3.5 Power-on ramp rate................................................................... 90

3.6 Input clocks............................................................................... 91

3.7 RESET initialization..................................................................96

3.8 DDR3 and DDR3L SDRAM controller.................................... 97

3.9 eSPI interface.............................................................................103

3.10 DUART interface...................................................................... 106

3.11 Ethernet interface, Ethernet management interface 1 and 2,

IEEE Std 1588........................................................................... 107

3.12 USB interface............................................................................ 116

3.13 Integrated flash controller..........................................................118

3.14 Enhanced secure digital host controller (eSDHC).....................121

3.15 Multicore programmable interrupt controller (MPIC).............. 123

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

2

NXP Semiconductors

Overview

1 Overview

The T4240 QorIQ integrated multicore communications processor combines 12 dual-

threaded cores built on Power Architecture® technology with high-performance data path

acceleration and network and peripheral bus interfaces required for networking, telecom/

datacom, wireless infrastructure, and military/aerospace applications.

This chip can be used for combined control, data path, and application layer processing in

routers, switches, gateways, and general-purpose embedded computing systems. Its high

level of integration offers significant performance benefits compared to multiple discrete

devices, while also simplifying board design.

This figure shows the block diagram of the chip.

Power Architecture Power Architecture Power Architecture Power Architecture

e6500

512 KB

Plat Cache

64-bit DDR3/3L

with ECC

32 KB

D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache

64-bit DDR3/3L

with ECC

512 KB

Plat Cache

2 MB Banked L2

64-bit DDR3/3L

with ECC

512 KB

Plat Cache

MPIC

TM

CoreNet

PreBoot Loader

Security Monitor

Coherency Fabric

(peripheral access management unit)

PAMU

Internal BootROM

Power mgmt

FMan

Real-time

debug

Watch point

cross-

trigger

QMan

SEC

SD/MMC

eSPI

Parse, classify,

distribute

Parse, classify,

distribute

3x DMA

BMan

RMan

PME

DCE

Buffer

Perf

Monitor

4 x UART

Trace

1G 1G 1G

2

1/10G

1/10G 1/10G

4x I C

Aurora

1G 1G 1G

IFC

2 x USB2.0 w/PHY

Clocks/Reset

16 lanes up to 10 GHz SerDes

GPIO

CCSR

Figure 1. Block diagram

2 Pin assignments

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

3

Pin assignments

2.1 1932 ball layout diagrams

This table shows the complete view of the T4240 ball map. Figure 3, Figure 4, Figure 5,

and Figure 6 show quadrant views of the ballmap.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

4

NXP Semiconductors

Pin assignments

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

A

B

C

D

E

F

G

H

J

SEE DETAIL A

SEE DETAIL B

K

L

M

N

P

R

T

U

V

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

AR

AT

AU

AV

AW

AY

BA

BB

BC

BD

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AK

AL

AM

AN

AP

AR

AT

AU

AV

AW

AY

BA

BB

BC

BD

SEE DETAIL C

SEE DETAIL D

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

DDR Interface 1

I2C

DDR Interface 2

eSPI

DDR Interface 3

eSDHC

IFC

DUART

MPIC

LP Trust

DDR Clocking

SerDes 2

IEEE1588

DMA

Trust

System Control

DFT

ASLEEP

Clocking

SerDes 1

USB CLK

Ethernet Cont. 2

No Connects

Debug

JTAG

SerDes 3

Ethernet MI 1

Analog signals

SerDes 4

Ethernet MI 2

Power

USB PHY 1 and 2

Ethernet Cont. 1

Ground

Figure 2. Complete BGA Map for the T4240

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

5

Pin assignments

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

D1_

MA

[12]

D1_

MAPAR_

ERR_B

D1_

MBA

[2]

D1_

MCKE

[0]

D1_

MCKE

[3]

EC2_

RXD

[0]

EC2_

RXD

[1]

EC1_

RXD

[2]

EC1_

RX_

DV

TSEC_C

SD1_

RX

[1]

SD1_

RX

[3]

SD1_

RX

[5]

SD1_

RX

[7]

G1VDD

[01]

G1VDD

[02]

G1VDD

[03]

S1GND

[01]

S1GND

[02]

S1GND

[03]

S1GND

[04]

A

LK_IN

D1_

MA

[11]

D1_

MA

[09]

D1_

MA

[14]

D1_

MA

[15]

D1_

MCKE

[2]

D1_

MCKE

[1]

EC2_

RX_

CLK

EC1_

RX_

CLK

SD1_

RX

_B[1]

SD1_

RX

_B[3]

SD1_

RX

_B[5]

SD1_

RX

_B[7]

G1VDD

[04]

G1VDD

[05]

G1VDD

[06]

GND

[002]

GND

[003]

S1GND

[05]

S1GND

[06]

S1GND

[07]

S1GND

[08]

S1GND

[09]

B

D1_

MA

[08]

D1_

MA

[07]

GND_

DET

[1]

EC2_

RX_

DV

EC2_

RXD

[2]

EC1_

RXD

[0]

EC1_

TX_

EN

SD1_

RX

[0]

SD1_

RX

[2]

SD1_

RX

[4]

SD1_

RX

[6]

GND

[009]

GND

[010]

GND

[011]

GND

[012]

GND

[013]

GND

[014]

S1GND

[10]

S1GND

[11]

S1GND

[12]

S1GND

[13]

S1GND

[14]

C

D

E

C

D

E

D1_

MA

[06]

D1_

MDQ

[02]

D1_

MDQ

[06]

D1_

MDQS

_B[09]

D1_

MDM

[0]

D1_

MDQ

[05]

EC2_

RXD

[3]

EC2_

TXD

[0]

EC1_

GTX_

CLK125

SD1_

RX

_B[0]

SD1_

RX

_B[2]

SD1_

RX

_B[4]

SD1_

RX

_B[6]

G1VDD

[07]

GND

[015]

GND

[016]

EMI2_

MDC

S1GND

[15]

S1GND

[16]

S1GND

[17]

S1GND

[18]

S1GND

[19]

D1_

MA

[04]

D1_

MA

[05]

D1_

MDQ

[03]

D1_

MDQ

[07]

D1_

MDQ

[01]

D1_

MDQ

[04]

EC2_

GTX_

CLK125

EC1_

RXD

[1]

GND

[021]

GND

[022]

GND

[023]

GND

[024]

EMI2_

MDIO

S1GND

[20]

S1GND

[21]

S1GND

[22]

S1GND

[23]

S1GND

[24]

S1GND

[25]

S1GND

[26]

S1GND

[27]

S1GND

[28]

D1_

MA

[03]

D1_

MDQS

[00]

D1_

MDQS

_B[00]

D1_

MDQ

[00]

EC2_

TXD

[1]

EC2_

TXD

[2]

EC1_

GTX_

CLK

TSEC_C

LK_OUT

SD1_

TX

[1]

SD1_

TX

[3]

SD1_

TX

[5]

SD1_

TX

[7]

G1VDD

[08]

GND

[025]

GND

[026]

GND

[027]

GND

[028]

GND

[029]

X1GND

[01]

X1GND

[02]

X1GND

[03]

X1GND

[04]

F

D1_

MA

[01]

D1_

MA

[02]

D1_

MDQ

[10]

D1_

MDQS

[01]

D1_

MDQ

[09]

D1_

MDQ

[13]

EC2_

TX_

EN

EC2_

TXD

[3]

EC1_

RXD

[3]

SD1_

TX

_B[1]

SD1_

TX

_B[3]

SD1_

TX

_B[5]

SD1_

TX

_B[7]

GND

[034]

GND

[035]

GND

[036]

EMI1_

MDC

X1GND

[05]

X1GND

[06]

X1GND

[07]

X1GND

[08]

X1GND

[09]

G

H

J

G

H

J

D1_

MDIC

[1]

D1_

MDQ

[11]

D1_

MDQS

_B[01]

D1_

MDQS

_B[10]

D1_

MDM

[1]

D1_

MDQ

[12]

EC2_

GTX_

CLK

EC1_

TXD

[0]

SD1_

TX

[0]

SD1_

TX

[2]

SD1_

TX

[4]

SD1_

TX

[6]

G1VDD

[09]

GND

[038]

GND

[039]

GND

[040]

EMI1_

MDIO

X1GND

[10]

X1GND

[11]

X1GND

[12]

X1GND

[13]

X1GND

[14]

D1_

MCK

_B[3]

D1_

MCK

[3]

D1_

MDQ

[15]

D1_

MDQ

[14]

D1_

MDQ

[08]

TSEC_A

LARM_O

UT2

SD1_

TX

_B[0]

SD1_

TX

_B[2]

SD1_

TX

_B[4]

SD1_

TX

_B[6]

GND

[044]

GND

[045]

GND

[046]

GND

[047]

UART2_ UART2_

SOUT SIN

GND

[048]

X1GND

[15]

X1GND

[16]

X1GND

[17]

X1GND

[18]

X1GND

[19]

D1_

MCK

[0]

D1_

MDQ

[29]

D1_

MDQ

[28]

D1_

MDQ

[21]

D1_

MDQ

[20]

EC1_

TXD

[1]

TSEC_A

LARM_O

UT1

G1VDD

[10]

GND

[051]

GND

[052]

GND

[053]

UART2_ UART2_

X1GND

[20]

X1VDD

[1]

X1VDD

[2]

X1VDD

[3]

X1VDD

[4]

X1VDD

[5]

X1VDD

[6]

X1VDD

[7]

X1VDD

[8]

RTS_B

CTS_B

K

D1_

MCK

[1]

D1_

MCK

_B[0]

D1_

MDQ

[25]

D1_

MDQ

[24]

D1_

MDQ

[17]

D1_

MDQ

[16]

EC1_

TXD

[2]

TSEC_P

ULSE_O

UT2

SD1_

PLL1_

TPD

AVDD_

SD1_

PLL1

AGND_

SD1_PLL

1

AGND_

SD1_PLL

2

AVDD_

SD1_

PLL2

SD1_

PLL2_

TPD

GND

[057]

GND

[058]

GND

[059]

UART1_

SOUT

GND

[060]

LVDD

[1]

X1GND

[21]

X1GND

[22]

L

D1_

MCK

_B[1]

D1_

MDQS

_B[12]

D1_

MDM

[3]

D1_

MDQS

_B[11]

D1_

MDM

[2]

EC1_

TXD

[3]

TSEC_P

ULSE_O

UT1

SD1_

IMP_

CAL_RX

SD1_

PLL1_

TPA

SD1_

PLL2_

TPA

SD1_

IMP_

CAL_TX

G1VDD

[11]

GND

[062]

GND

[063]

GND

[064]

UART1_ UART1_

RTS_B

GND

[065]

S1GND

[29]

X1GND

[23]

S1GND

[30]

X1GND

[24]

SIN

M

N

P

M

N

P

D1_

MCK

_B[2]

D1_

MCK

[2]

D1_

MDQS

[03]

D1_

MDQS

_B[03]

D1_

MDQS

[02]

D1_

MDQS

_B[02]

TSEC_T TSEC_T

RIG_IN

2

SD1_

REF_

CLK2_B

GND

[069]

GND

[070]

GND

[071]

IIC2_

SCL

UART1_

CTS_B

IIC4_

SCL

IIC3_

SCL

S1GND

[31]

S1VDD

[1]

S1GND

[32]

S1GND

[33]

S1GND

[34]

S1GND

[35]

RIG_IN

1

D1_

MDIC

[0]

D1_

MDQ

[31]

D1_

MDQ

[30]

D1_

MDQ

[23]

D1_

MDQ

[22]

SD1_

REF_

CLK1

SD1_

REF_

CLK1_B

SD1_

REF_

CLK2

G1VDD

[12]

GND

[074]

GND

[075]

GND

[076]

IIC2_

SDA

GND

[077]

IIC4_

SDA

IIC3_

SDA

GND

[078]

GND

[079]

GND

[080]

S1GND

[36]

S1VDD

[2]

S1VDD

[3]

D1_

MAPAR_

OUT

D1_

MA

[00]

D1_

MDQ

[27]

D1_

MDQ

[26]

D1_

MDQ

[19]

D1_

MDQ

[18]

SENSE

VDD_

CA

SENSE

GND_

CA

GND

[083]

GND

[084]

GND

[085]

IIC1_

SCL

IIC1_

SDA

DVDD

[1]

DVDD

[2]

LVDD

[2]

LVDD

[3]

S1GND

[37]

S1GND

[38]

S1GND

[39]

S1GND

[40]

S1GND

[41]

R

T

R

T

D1_

MA

[10]

D1_

MECC

[5]

D1_

MECC

[4]

D1_

MDQ

[36]

D1_

MDQ

[37]

G1VDD

[13]

GND

[088]

GND

[089]

GND

[090]

GND

[091]

GND

[092]

GND

[093]

AVDD_

D1

GND

[094]

G1VDD

[14]

VDD

[01]

GND

[095]

NC

[45]

S1VDD

[4]

S1VDD

[5]

S1VDD

[6]

S1VDD

[7]

D1_

MBA

[0]

D1_

MBA

[1]

D1_

MECC

[1]

D1_

MECC

[0]

D1_

MDQ

[32]

D1_

MDQ

[33]

D1_

MDQ

[44]

D1_

MDQ

[45]

D1_

MDQ

[40]

D1_

MDQ

[41]

GND

[099]

GND

[100]

GND

[101]

GND

[102]

G1VDD

[15]

GND

[103]

VDD

[02]

GND

[104]

VDD

[03]

GND

[105]

VDD

[04]

GND

[106]

U

V

U

V

D1_

MDQS

_B[17]

D1_

MDM

[8]

D1_

MDM

[4]

D1_

MDQS

_B[13]

D1_

MDM

[5]

D1_

MDQS

_B[14]

G1VDD

[16]

D1_

MRAS_B

GND

[113]

GND

[114]

GND

[115]

GND

[116]

D1_

MVREF

GND

[117]

G1VDD

[17]

VDD

[09]

GND

[118]

VDD

[10]

GND

[119]

VDD

[11]

GND

[120]

VDD

[12]

D1_

MCS

_B[2]

D1_

MDQS

[08]

D1_

MDQS

_B[08]

D1_

MDQS

_B[04]

D1_

MDQS

[04]

D1_

MDQS

_B[05]

D1_

MDQS

[05]

D1_

MWE_B

GND

[128]

GND

[129]

GND

[130]

GND

[131]

GND

[132]

GND

[133]

G1VDD

[18]

GND

[134]

VDD

[16]

GND

[135]

VDD

[17]

GND

[136]

VDD

[18]

GND

[137]

W

Y

W

Y

D1_

MCS

_B[0]

D1_

MECC

[7]

D1_

MECC

[6]

D1_

MDQ

[38]

D1_

MDQ

[39]

D1_

MDQ

[46]

D1_

MDQ

[47]

D1_

MDQ

[42]

D1_

MDQ

[43]

G1VDD

[19]

GND

[145]

GND

[146]

GND

[147]

GND

[148]

G1VDD

[20]

VDD

[23]

GND

[149]

VDD

[24]

GND

[150]

VDD

[25]

GND

[151]

VDD

[26]

D1_

MODT

[0]

D1_

MECC

[3]

D1_

MECC

[2]

D1_

MDQ

[34]

D1_

MDQ

[35]

D1_

MDQ

[61]

D1_

MCAS_B

GND

[165]

GND

[166]

GND

[167]

GND

[168]

GND

[169]

GND

[170]

GND

[171]

G1VDD

[21]

GND

[172]

VDD

[30]

GND

[173]

VDD

[31]

GND

[174]

VDD

[32]

GND

[175]

AA

AB

AA

AB

D1_

MODT

[2]

D1_

MDQ

[52]

D1_

MDQ

[53]

D1_

MDQ

[48]

D1_

MDQ

[60]

D1_

MDM

[7]

D1_

MDQS

_B[07]

D1_

MDQ

[62]

D1_

MDQ

[58]

G1VDD

[22]

GND

[182]

GND

[183]

GND

[184]

GND

[185]

G1VDD

[23]

VDD

[37]

GND

[186]

VDD

[38]

GND

[187]

VDD

[39]

GND

[188]

VDD

[40]

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

DDR Interface 1

DDR Interface 2

DDR Interface 3

IFC

DUART

I2C

eSPI

eSDHC

MPIC

LP Trust

DDR Clocking

SerDes 2

IEEE1588

DMA

Trust

System Control

DFT

ASLEEP

Clocking

SerDes 1

USB CLK

Ethernet Cont. 2

No Connects

Debug

JTAG

SerDes 3

Ethernet MI 1

Analog signals

SerDes 4

Ethernet MI 2

Power

USB PHY 1 and 2

Ethernet Cont. 1

Ground

Figure 3. Detail A

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

6

NXP Semiconductors

Pin assignments

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

SD2_

RX

[1]

SD2_

RX

[3]

SD2_

RX

[5]

SD2_

RX

[7]

USB2_

DRV

VBUS

SDHC_

DAT

[2]

SPI_

CS

_B[1]

IFC_

A

[30]

IFC_

A

[27]

IFC_

CS

_B[6]

IFC_

CS

_B[3]

S2GND

[01]

S2GND

[02]

S2GND

[03]

S2GND

[04]

S2GND

[05]

SDHC_

CLK

SDHC_

CD_B

SPI_

MOSI

IFC_

CLK2

GND

[001]

A

SD2_

RX

_B[1]

SD2_

RX

_B[3]

SD2_

RX

_B[5]

SD2_

RX

_B[7]

USB2_

PWR

FAULT

SDHC_

DAT

[0]

SDHC_

DAT

[3]

IFC_

A

[26]

IFC_

CS

_B[5]

IFC_

CS

_B[2]

S2GND

[06]

S2GND

[07]

S2GND

[08]

S2GND

[09]

S2GND

[10]

GND

[004]

GND

[005]

SPI_

CLK

IFC_

CLK0

GND

[006]

GND

[007]

GND

[008]

B

SD2_

RX

[0]

SD2_

RX

[2]

SD2_

RX

[4]

SD2_

RX

[6]

USB2_

VBUS

CLMP

SDHC_

DAT

[1]

SPI_

CS

_B[0]

SPI_

CS

_B[2]

IFC_

A

[31]

IFC_

A

[29]

IFC_

CS

_B[7]

IFC_

CS

_B[4]

IFC_

CS

_B[0]

IFC_

CS

_B[1]

S2GND

[11]

S2GND

[12]

S2GND

[13]

S2GND

[14]

S2GND

[15]

SDHC_

WP

SPI_

MISO

NC_

DET

C

D

E

C

SD2_

RX

_B[0]

SD2_

RX

_B[2]

SD2_

RX

_B[4]

SD2_

RX

_B[6]

USB_

IBIAS_

REXT

USB_

AGND

[1]

SPI_

CS

_B[3]

IFC_

PAR

[1]

IFC_

A

[28]

IFC_

AD

[31]

IFC_

WE

_B[2]

IFC_

WE

_B[3]

S2GND

[16]

S2GND

[17]

S2GND

[18]

S2GND

[19]

SDHC_

CMD

GND

[017]

HRESET_

B

GND

[018]

GND

[019]

GND

[020]

D

USB1_

DRV

VBUS

IFC_

PAR

[0]

IFC_

AD

[30]

IFC_

AD

[29]

IFC_

AD

[28]

IFC_

WE

_B[0]

S2GND

[20]

S2GND

[21]

S2GND

[22]

S2GND

[23]

S2GND

[24]

S2GND

[25]

S2GND

[26]

S2GND

[27]

X2GND

[01]

SCAN_

MODE_B

TMP_

IFC_

OE_B

IFC_

CLE

USBCLK

DETECT_B NDDQS PERR_B

E

SD2_

TX

[1]

SD2_

TX

[3]

SD2_

TX

[5]

SD2_

TX

[7]

USB1_

PWR

FAULT

IFC_

PAR

[3]

IFC_

PAR

[2]

IFC_

AD

[27]

IFC_

RB

_B[1]

IFC_

RB

_B[0]

IFC_

WP

_B[0]

X2GND

[02]

X2GND

[03]

X2GND

[04]

X2GND

[05]

X2GND

[06]

GND

[030]

TEST_ PORESET_ GND

SEL_B

GND

[032]

GND

[033]

B

[031]

F

SD2_

TX

_B[1]

SD2_

TX

_B[3]

SD2_

TX

_B[5]

SD2_

TX

_B[7]

USB1_

VBUS

CLMP

IFC_

AD

[26]

IFC_

AD

[24]

IFC_

AD

[25]

X2GND

[07]

X2GND

[08]

X2GND

[09]

X2GND

[10]

X2GND

[11]

RESET_

REQ_B

NC

[01]

NC

[02]

NC

[03]

NC

[04]

IFC_

TE

GND

[037]

ASLEEP

IFC_BCTL

G

H

J

G

SD2_

TX

[0]

SD2_

TX

[2]

SD2_

TX

[4]

SD2_

TX

[6]

IFC_

AD

[22]

IFC_

AD

[23]

IFC_

NDDDR_

CLK

X2GND

[12]

X2GND

[13]

X2GND

[14]

X2GND

[15]

X2GND

[16]

USB2_

UID

NC

[05]

GND

[041]

NC

[06]

NC

[07]

GND

[042]

NC

[08]

GND

[043]

IFC_

CLK1

IFC_

AVD

H

SD2_

TX

_B[0]

SD2_

TX

_B[2]

SD2_

TX

_B[4]

SD2_

TX

_B[6]

USB_

AGND

[2]

IFC_

AD

[20]

IFC_

AD

[21]

X2GND

[17]

X2GND

[18]

X2GND

[19]

X2GND

[20]

USB1_

UDM

NC

[09]

NC

[10]

NC

[11]

NC

[12]

NC

[13]

NC

[14]

GND

[049]

GND

[050]

TRST_B

TDO

TDI

J

USB_

HVDD

[1]

IFC_

AD

[18]

IFC_

AD

[19]

X2VDD

[1]

X2VDD

[2]

X2VDD

[3]

X2VDD

[4]

X2VDD

[5]

X2VDD

[6]

X2VDD

[7]

X2VDD

[8]

USB1_

UDP

GND

[054]

NC

[15]

NC

[16]

GND

[055]

NC

[17]

NC

[18]

GND

[056]

TMS

TCK

K

SD2_

PLL1_

TPD

AVDD_

SD2_

PLL1

AGND_

SD2_PLL

1

AGND_

SD2_PLL

2

AVDD_

SD2_

PLL2

SD2_

PLL2_

TPD

USB_

AGND

[3]

IFC_

AD

[16]

IFC_

AD

[17]

X2GND

[21]

X2GND

[22]

USB1_

UID

NC

[19]

NC

[20]

NC

[21]

NC

[22]

NC

[23]

NC

[24]

GND

[061]

EVT_B

[4]

EVT_B CKSTP_

[3]

OUT_B

L

SD2_

IMP_

CAL_RX

SD2_

PLL1_

TPA

SD2_

PLL2_

TPA

SD2_

IMP_

CAL_TX

USB_

AGND

[4]

IFC_

AD

[14]

IFC_

AD

[15]

X2GND

[23]

S2GND

[28]

X2GND

[24]

X2VDD

[9]

USB2_

UDM

NC

[25]

GND

[066]

NC

[26]

NC

[27]

NC

[28]

NC

[29]

GND

[067]

EVT_B

[2]

EVT_B

[1]

GND

[068]

M

N

P

M

N

SD2_

REF_

CLK1_B

USB_

AGND

[5]

USB_

HVDD

[2]

IFC_

AD

[12]

IFC_

AD

[13]

DMA2_

DREQ

_B[0]

S2GND

[29]

S2GND

[30]

S2GND

[31]

S2GND

[32]

S2GND

[33]

X2GND

[25]

USB2_

UDP

NC

[30]

NC

[31]

NC

[32]

NC

[33]

GND

[072]

NC

[34]

EVT_B

[0]

GND

[073]

CLK_

OUT

SD2_

REF_

CLK1

SD2_

REF_

CLK2_B

SD2_

REF_

CLK2

USB_

SVDD

[1]

USB_

SVDD

[2]

USB_

OVDD

[1]

USB_

OVDD

[2]

IFC_

AD

[10]

IFC_

AD

[11]

DMA2_

DDONE

_B[0]

DMA1_

DREQ

_B[0]

DMA2_

DACK

_B[0]

S2VDD

[1]

S2VDD

[2]

S2GND

[34]

GND

[081]

NC

[35]

NC

[36]

NC

[37]

NC

[38]

NC

[39]

GND

[082]

P

FA_

ANALOG_

G_V

IFC_

AD

[08]

IFC_

AD

[09]

DMA1_

DACK

_B[0]

DMA1_

DDONE

_B[0]

S2GND

[35]

S2GND

[36]

S2GND

[37]

S2GND

[38]

S2GND

[39]

VDD_

LP

PROG_

SFP

OVDD

[1]

GND

[086]

FA_

VL

NC

[40]

NC

[41]

NC

[42]

NC

[43]

NC

[44]

GND

[087]

IRQ

[05]

R

T

R

LP_

TMP_

DETECT_B

FA_

ANALOG_

IFC_

AD

[06]

IFC_

AD

[07]

S2VDD

[3]

S2VDD

[4]

S2VDD

[5]

S2VDD

[6]

AVDD_

PLAT

PROG_

MTR

OVDD

[2]

GND

[096]

NC

[46]

NC

[47]

NC

[48]

NC

[49]

GND

[097]

NC

[50]

IRQ_

OUT_B

IRQ

[07]

GND

[098]

IRQ

[08]

T

IFC_

AD

[04]

IFC_

AD

[05]

VDD

[05]

GND

[107]

VDD

[06]

GND

[108]

VDD

[07]

GND

[109]

VDD

[08]

OVDD

[3]

GND

[110]

NC

[51]

GND

[111]

NC

[52]

NC

[53]

NC

[54]

NC

[55]

GND

[112]

IRQ

[11]

IRQ

[02]

IRQ

[04]

SYSCLK

U

V

U

IFC_

AD

[02]

IFC_

AD

[03]

GND

[121]

VDD

[13]

GND

[122]

VDD

[14]

GND

[123]

VDD

[15]

GND

[124]

OVDD

[4]

GND

[125]

TH_

VDD

GND

[126]

NC

[56]

NC

[57]

NC

[58]

NC

[59]

GND

[127]

IRQ

[09]

IRQ

[00]

IRQ

[01]

RTC

V

IFC_

AD

[00]

IFC_

AD

[01]

VDD

[19]

GND

[138]

VDD

[20]

GND

[139]

VDD

[21]

GND

[140]

VDD

[22]

OVDD

[5]

GND

[141]

TH_

TPA

GND

[142]

NC

[60]

NC

[61]

NC

[62]

GND

[143]

NC

[63]

IRQ

[06]

IRQ

[03]

GND

[144]

IRQ

[10]

W

Y

W

Y

SENSE

VDD_

PL

SENSE

VDD_

CC

GND

[152]

VDD

[27]

GND

[153]

VDD

[28]

GND

[154]

VDD

[29]

GND

[155]

OVDD

[6]

GND

[156]

TD1_

CATHODE

GND

[157]

GND

[158]

GND

[159]

GND

[160]

GND

[161]

GND

[162]

GND

[163]

GND

[164]

G3VDD

[01]

G3VDD

[02]

SENSE

GND_

PL

SENSE

GND_

CC

D3_

MDQ

[59]

D3_

MDQ

[63]

D3_

MDQS

[07]

D3_

MDQS

_B[16]

D3_

MDQ

[57]

D3_

MDQ

[61]

D3_

MODT

[1]

D3_

MODT

[3]

VDD

[33]

GND

[176]

VDD

[34]

GND

[177]

VDD

[35]

GND

[178]

VDD

[36]

OVDD

[7]

GND

[179]

TD1_

ANODE

GND

[180]

GND

[181]

AA

AB

AA

AB

D3_

MDQ

[58]

D3_

MDQ

[62]

D3_

MDQS

_B[07]

D3_

MDM

[7]

D3_

MDQ

[56]

D3_

MDQ

[60]

D3_

MA

[13]

GND

[189]

VDD

[41]

GND

[190]

VDD

[42]

GND

[191]

VDD

[43]

GND

[192]

G3VDD

[03]

GND

[193]

GND

[194]

GND

[195]

GND

[196]

GND

[197]

GND

[198]

G3VDD

[04]

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

DDR Interface 1

DDR Interface 2

DDR Interface 3

IFC

DUART

I2C

eSPI

eSDHC

MPIC

LP Trust

DDR Clocking

SerDes 2

IEEE1588

DMA

Trust

System Control

DFT

ASLEEP

Clocking

SerDes 1

USB CLK

Ethernet Cont. 2

No Connects

Debug

JTAG

SerDes 3

Ethernet MI 1

Analog signals

SerDes 4

Ethernet MI 2

Power

USB PHY 1 and 2

Ethernet Cont. 1

Ground

Figure 4. Detail B

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

7

Pin assignments

1

2

3

GND

[199]

4

5

MDQS

_B[15]

6

GND

[200]

7

8

GND

[201]

9

10 11 12 13 14 15 16 17 18 19 20 21 22

MDQS

_B[16]

D1_

MCS

_B[3]

D1_

MCS

_B[1]

D1_

MDM

[6]

D1_

MDQ

[49]

D1_

MDQ

[56]

D1_

MDQS

[07]

D1_

MDQ

[63]

D1_

MDQ

[59]

GND

[202]

G2VDD

[01]

GND

[203]

VDD

[44]

GND

[204]

VDD

[45]

GND

[205]

VDD

[46]

GND

[206]

AC

AD

AE

AF

AG

AH

AJ

AC

AD

AE

AF

AG

AH

AJ

D1_

MA

[13]

D1_

MDQS

_B[06]

D1_

MDQ

[55]

D1_

MDQ

[51]

D1_

MDQ

[57]

G1VDD

[24]

GND

[219]

GND

[220]

GND

[221]

GND

[222]

GND

[223]

GND

[224]

GND

[225]

GND

[226]

G2VDD

[02]

VDD

[51]

GND

[227]

VDD

[52]

GND

[228]

VDD

[53]

GND

[229]

VDD

[54]

D1_

MODT

[1]

D1_

MODT

[3]

D1_

MDQS

[06]

D1_

MDQ

[54]

D1_

MDQ

[50]

D2_

MDQ

[51]

D2_

MDQS

_B[07]

D2_

MDQS

[07]

D2_

MDQ

[63]

D2_

MDQ

[59]

GND

[239]

GND

[240]

GND

[241]

GND

[242]

G2VDD

[03]

GND

[243]

VDD

[58]

GND

[244]

VDD

[59]

GND

[245]

VDD

[60]

GND

[246]

D2_

MDQ

[54]

D2_

MDQ

[50]

D2_

MDM

[7]

D2_

MDQS

_B[16]

D2_

MDQ

[62]

D2_

MDQ

[58]

G1VDD

[25]

G1VDD

[26]

GND

[255]

GND

[256]

GND

[257]

GND

[258]

GND

[259]

GND

[260]

G2VDD

[04]

VDD

[65]

GND

[261]

VDD

[66]

GND

[262]

VDD

[67]

GND

[263]

VDD

[68]

D2_

MODT

[1]

D2_

MDQS

_B[15]

D2_

MDQS

_B[06]

D2_

MDQS

[06]

D2_

MDQ

[55]

D2_

MDQ

[56]

D2_

MDQ

[57]

G2VDD

[05]

GND

[273]

GND

[274]

GND

[275]

GND

[276]

GND

[277]

GND

[278]

G2VDD

[06]

GND

[279]

VDD

[72]

GND

[280]

VDD

[73]

GND

[281]

VDD

[74]

GND

[282]

D2_

MODT

[3]

D2_

MCS

_B[1]

D2_

MDM

[6]

D2_

MDQ

[49]

D2_

MDQ

[48]

D2_

MDQ

[53]

D2_

MDQ

[52]

D2_

MDQ

[60]

D2_

MDQ

[61]

GND

[291]

GND

[292]

GND

[293]

D2_

MVREF

GND

[294]

G2VDD

[07]

VDD

[79]

GND

[295]

VDD

[80]

GND

[296]

VDD

[81]

GND

[297]

VDD

[82]

D2_

MCS

_B[3]

G2VDD

[08]

GND

[307]

GND

[308]

GND

[309]

GND

[310]

GND

[311]

GND

[312]

GND

[313]

GND

[314]

GND

[315]

GND

[316]

AVDD_

D2

GND

[317]

G2VDD

[09]

GND

[318]

VDD

[86]

GND

[319]

VDD

[87]

GND

[320]

VDD

[88]

S3VDD

[1]

D2_

MODT

[2]

D2_

MA

[13]

D2_

MDQ

[42]

D2_

MDQ

[43]

D2_

MDQ

[35]

D2_

MDQ

[34]

D2_

MECC

[3]

D2_

MECC

[2]

GND

[328]

GND

[329]

GND

[330]

GND

[331]

GND

[332]

OVDD

[8]

GND

[333]

VDD

[89]

GND

[334]

VDD

[90]

GND

[335]

VDD

[91]

S3GND

[01]

S3GND

[02]

AK

AL

AM

AN

AP

AR

AT

AK

AL

AM

AN

AP

AR

AT

D2_

MODT

[0]

D2_

MDQ

[46]

D2_

MDQ

[47]

D2_

MDQ

[39]

D2_

MDQ

[38]

D2_

MECC

[7]

D2_

MECC

[6]

SD3_

REF_

CLK1

SD3_

REF_

CLK1_B

G2VDD

[10]

GND

[344]

GND

[345]

GND

[346]

GND

[347]

D1_

TPA

NC

[71]

TD2_

ANODE CATHODE

TD2_

NC

[72]

NC

[73]

S3GND

[06]

DDRCLK

D2_

MDQS

_B[05]

D2_

MDQS

[05]

D2_

MDQS

[04]

D2_

MDQS

_B[04]

D2_

MDQS

[08]

D2_

MDQS

_B[08]

SENSE

VDD_

CB

SENSE

GND_

CB

D2_

GND

[352]

GND

[353]

GND

[354]

GND

[355]

D2_

TPA

NC

[75]

NC

[76]

NC

[77]

S3GND

[07]

S3VDD

[7]

S3GND

[08]

S3GND

[09]

MWE_B MCAS_B

D2_

MDM

[5]

D2_

MDQS

_B[14]

D2_

MDQS

_B[13]

D2_

MDM

[4]

D2_

MDQS

_B[17]

D2_

MDM

[8]

SD3_

IMP_

CAL_RX

SD3_

PLL1_

TPA

G2VDD

MCS

[11]

GND

[360]

GND

[361]

GND

[362]

GND

[363]

NC

[78]

NC

[79]

NC

[80]

NC

[81]

NC

[82]

S3GND

[12]

X3GND

[01]

S3GND

[13]

_B[2]

D2_

MRAS_B

D2_

MDQ

[40]

D2_

MDQ

[41]

D2_

MDQ

[33]

D2_

MDQ

[32]

D2_

MECC

[1]

D2_

MECC

[0]

SD3_

PLL1_

TPD

AVDD_

SD3_

PLL1

AGND_

SD3_PLL

1

GND

[369]

GND

[370]

GND

[371]

GND

[372]

AVDD_

CGA1

GND

[373]

GND

[374]

GND

[375]

NC

[83]

X3GND

[03]

X3GND

[04]

MCS

_B[0]

D2_

MDQ

[44]

D2_

MDQ

[45]

D2_

MDQ

[37]

D2_

MDQ

[36]

D2_

MECC

[5]

D2_

MECC

[4]

G2VDD

MBA

[12]

GND

[379]

GND

[380]

GND

[381]

GND

[382]

AVDD_

CGA2

AVDD_

CGA3

AVDD_

CGB2

AVDD_

CGB1

X3GND

[05]

X3VDD

[1]

X3VDD

[2]

X3VDD

[3]

X3VDD

[4]

X3VDD

[5]

[0]

D2_

MBA

[1]

D2_

MA

[10]

SD3_

TX

_B[0]

SD3_

TX

_B[2]

SD3_

TX

_B[4]

GND

[385]

GND

[386]

GND

[387]

GND

[388]

GND

[389]

GND

[390]

GND

[391]

GND

[392]

GND

[393]

GND

[394]

GND

[395]

GND

[396]

GND

[397]

GND

[398]

X3GND

[06]

X3GND

[07]

X3GND

[08]

D2_

MA

[00]

D2_

MDQ

[18]

D2_

MDQ

[22]

D2_

MDQS

_B[02]

D2_

MDM

[2]

D2_

MDQ

[16]

D2_

MDQ

[20]

D2_

MDQ

[10]

D2_

MDQ

[14]

D2_

MDQS

_B[01]

D2_

MDM

[1]

D2_

MDQ

[08]

D2_

MDQ

[12]

SD3_

TX

[0]

SD3_

TX

[2]

SD3_

TX

[4]

G2VDD

[13]

GND

[404]

GND

[405]

X3GND

[11]

X3GND

[12]

X3GND

[13]

AU

AV

AW

AY

BA

BB

BC

BD

AU

AV

AW

AY

BA

BB

BC

BD

D2_

MAPAR_

OUT

D2_

MDIC

[0]

D2_

MDQ

[19]

D2_

MDQ

[23]

D2_

MDQS

[02]

D2_

MDQS

_B[11]

D2_

MDQ

[17]

D2_

MDQ

[21]

D2_

MDQ

[11]

D2_

MDQ

[15]

D2_

MDQS

[01]

D2_

MDQS

_B[10]

D2_

MDQ

[09]

D2_

MDQ

[13]

SD3_

TX

_B[1]

SD3_

TX

_B[3]

GND

[410]

GND

[411]

X3GND

[16]

X3GND

[17]

X3GND

[18]

X3GND

[19]

D2_

MCK

_B[2]

SD3_

TX

[1]

SD3_

TX

[3]

G2VDD

[14]

GND

[414]

GND

[415]

GND

[416]

GND

[417]

GND

[418]

GND

[419]

GND

[420]

GND

[421]

GND

[422]

GND

[423]

GND

[424]

GND

[425]

GND

[426]

GND

[427]

NC

[84]

X3GND

[21]

X3GND

[22]

X3GND

[23]

D2_

MCK

_B[0]

D2_

MCK

[2]

D2_

MDQ

[26]

D2_

MDQ

[30]

D2_

MDQS

_B[03]

D2_

MDM

[3]

D2_

MDQ

[24]

D2_

MDQ

[28]

D2_

MDQ

[02]

D2_

MDQ

[06]

D2_

MDQS

_B[00]

D2_

MDM

[0]

D2_

MDQ

[00]

D2_

MDQ

[04]

GND

[433]

GND

[434]

S3GND

[14]

S3GND

[15]

S3GND

[16]

S3GND

[17]

S3GND

[18]

S3GND

[19]

D2_

MCK

[0]

D2_

MDQ

[27]

D2_

MDQ

[31]

D2_

MDQS

[03]

D2_

MDQS

_B[12]

D2_

MDQ

[25]

D2_

MDQ

[29]

D2_

MDQ

[03]

D2_

MDQ

[07]

D2_

MDQS

[00]

D2_

MDQS

_B[09]

D2_

MDQ

[01]

D2_

MDQ

[05]

SD3_

RX

_B[0]

SD3_

RX

_B[2]

SD3_

RX

_B[4]

G2VDD

[15]

GND

[437]

GND

[438]

S3GND

[23]

S3GND

[24]

S3GND

[25]

D2_

MCK

[1]

D2_

MCK

_B[1]

GND_

DET

[2]

SD3_

RX

[0]

SD3_

RX

[2]

SD3_

RX

[4]

GND

[442]

GND

[443]

GND

[444]

GND

[445]

GND

[446]

GND

[447]

GND

[448]

GND

[449]

GND

[450]

GND

[451]

GND

[452]

GND

[453]

GND

[454]

S3GND

[28]

S3GND

[29]

S3GND

[30]

D2_

MCK

[3]

D2_

MCK

_B[3]

D2_

MA

[01]

D2_

MA

[04]

D2_

MA

[05]

D2_

MA

[07]

D2_

MA

[09]

D2_

MA

[12]

D2_

MA

[14]

D2_

MA

[15]

D2_

MCKE

[3]

SD3_

RX

_B[1]

SD3_

RX

_B[3]

G2VDD

[16]

G2VDD

[17]

G2VDD

[18]

G2VDD

[19]

G2VDD

[20]

S3GND

[33]

S3GND

[34]

S3GND

[35]

S3GND

[36]

D2_

MDIC

[1]

D2_

MA

[02]

D2_

MA

[03]

D2_

MA

[06]

D2_

MA

[08]

D2_

MA

[11]

D2_

MAPAR_

ERR_B

D2_

MBA

[2]

D2_

MCKE

[2]

D2_

MCKE

[0]

D2_

MCKE

[1]

SD3_

RX

[1]

SD3_

RX

[3]

G2VDD

[21]

G2VDD

[22]

G2VDD

[23]

G2VDD

[24]

G2VDD

[25]

S3GND

[38]

S3GND

[39]

S3GND

[40]

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

DDR Interface 1

DDR Interface 2

DDR Interface 3

IFC

DUART

I2C

eSPI

eSDHC

MPIC

LP Trust

DDR Clocking

SerDes 2

IEEE1588

DMA

Trust

System Control

DFT

ASLEEP

Clocking

SerDes 1

USB CLK

Ethernet Cont. 2

No Connects

Debug

JTAG

SerDes 3

Ethernet MI 1

Analog signals

SerDes 4

Ethernet MI 2

Power

USB PHY 1 and 2

Ethernet Cont. 1

Ground

Figure 5. Detail C

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

8

NXP Semiconductors

Pin assignments

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

D3_

MDQ

[51]

D3_

MDQ

[50]

D3_

MCS

_B[3]

D3_

MCS

_B[1]

VDD

[47]

GND

[207]

VDD

[48]

GND

[208]

VDD

[49]

GND

[209]

VDD

[50]

G3VDD

[05]

GND

[210]

AVDD_

D3

GND

[211]

GND

[212]

GND

[213]

GND

[214]

GND

[215]

GND

[216]

GND

[217]

GND

[218]

AC

AD

AE

AF

AG

AH

AJ

AC

AD

AE

AF

AG

AH

AJ

D3_

MDQ

[55]

D3_

MDQ

[54]

D3_

MDQ

[43]

D3_

MDQ

[42]

D3_

MDQ

[34]

D3_

MDQ

[35]

D3_

MODT

[2]

GND

[230]

VDD

[55]

GND

[231]

VDD

[56]

GND

[232]

VDD

[57]

GND

[233]

G3VDD

[06]

GND

[234]

D3_

MVREF

GND

[235]

GND

[236]

GND

[237]

GND

[238]

G3VDD

[07]

D3_

MDQS

[06]

D3_

MDQS

_B[06]

D3_

MDQ

[47]

D3_

MDQ

[46]

D3_

MDQ

[38]

D3_

MDQ

[39]

D3_

MODT

[0]

VDD

[61]

GND

[247]

VDD

[62]

GND

[248]

VDD

[63]

GND

[249]

VDD

[64]

G3VDD

[08]

GND

[250]

NC

[64]

GND

[251]

GND

[252]

GND

[253]

GND

[254]

D3_

MCAS_B

D3_

MDQS

_B[15]

D3_

MDM

[6]

D3_

MDQS

[05]

D3_

MDQS

_B[05]

D3_

MDQS

_B[04]

D3_

MDQS

[04]

D3_

MCS

_B[0]

GND

[264]

VDD

[69]

GND

[265]

VDD

[70]

GND

[266]

VDD

[71]

GND

[267]

G3VDD

[09]

GND

[268]

D3_

TPA

GND

[269]

GND

[270]

GND

[271]

GND

[272]

G3VDD

[10]

D3_

MDQ

[49]

D3_

MDQ

[48]

D3_

MDQS

_B[14]

D3_

MDM

[5]

D3_

MDM

[4]

D3_

MDQS

_B[13]

D3_

MCS

_B[2]

VDD

[75]

GND

[283]

VDD

[76]

GND

[284]

VDD

[77]

GND

[285]

VDD

[78]

G3VDD

[11]

GND

[286]

NC

[65]

GND

[287]

GND

[288]

GND

[289]

GND

[290]

D3_

MWE_B

D3_

MDQ

[53]

D3_

MDQ

[52]

D3_

MDQ

[41]

D3_

MDQ

[40]

D3_

MDQ

[32]

D3_

MDQ

[33]

GND

[298]

VDD

[83]

GND

[299]

VDD

[84]

GND

[300]

VDD

[85]

GND

[301]

G3VDD

[12]

GND

[302]

NC

[66]

GND

[303]

GND

[304]

GND

[305]

GND

[306]

D3_

MRAS_B

G3VDD

[13]

D3_

MDQ

[45]

D3_

MDQ

[44]

D3_

MDQ

[36]

D3_

MDQ

[37]

D3_

MBA

[0]

D3_

MBA

[1]

S3VDD

[2]

S3VDD

[3]

S3VDD

[4]

S4VDD

[1]

S4VDD

[2]

S4VDD

[3]

S4VDD

[4]

GND

[321]

GND

[322]

NC

[67]

NC

[68]

GND

[323]

GND

[324]

GND

[325]

GND

[326]

GND

[327]

D3_

MECC

[3]

D3_

MECC

[2]

D3_

MA

[10]

S3GND

[03]

S3GND

[04]

S3GND

[05]

S4GND

[01]

S4GND

[02]

S4GND

[03]

S4GND

[04]

S4GND

[05]

NC

[69]

NC

[70]

GND

[336]

GND

[337]

GND

[338]

GND

[339]

GND

[340]

GND

[341]

GND

[342]

GND

[343]

G3VDD

[14]

AK

AL

AM

AN

AP

AR

AT

AK

AL

AM

AN

AP

AR

AT

SD3_

REF_

CLK2

SD4_

REF_

CLK1

SD4_

REF_

CLK2_B

SD4_

REF_

CLK2

D3_

MECC

[7]

D3_

MECC

[6]

D3_

MDQS

_B[08]

D3_

MDQS

[08]

D3_

MDQ

[26]

D3_

MDQ

[27]

D3_

MAPAR_

OUT

D3_

MA

[00]

S3VDD

[5]

S3VDD

[6]

S4VDD

[5]

S4VDD

[6]

S4GND

[06]

NC

[74]

GND

[348]

GND

[349]

GND

[350]

GND

[351]

SD3_

REF_

CLK2_B

SD4_

REF_

CLK1_B

D3_

MECC

[4]

D3_

MECC

[5]

D3_

MDM

[8]

D3_

MDQS

_B[17]

D3_

MDQ

[30]

D3_

MDQ

[31]

D3_

MDIC

[0]

S3GND

[10]

S3GND

[11]

S4GND

[07]

S4GND

[08]

S4GND

[09]

S4GND

[10]

S4GND

[11]

X4GND

[01]

GND

[356]

GND

[357]

GND

[358]

GND

[359]

G3VDD

[15]

SD3_

PLL2_

TPA

SD3_

IMP_

CAL_TX CAL_RX

SD4_

IMP_

SD4_

PLL1_

TPA

SD4_

PLL2_

TPA

SD4_

IMP_

CAL_TX

D3_

MECC

[0]

D3_

MECC

[1]

D3_

MDQS

_B[03]

D3_

MDQS

[03]

D3_

MCK

_B[2]

D3_

MCK

[2]

X3GND

[02]

X4GND

[02]

S4GND

[12]

X4GND

[03]

X4VDD

[1]

GND

[364]

GND

[365]

GND

[366]

GND

[367]

GND

[368]

AGND_

SD3_PLL

2

AVDD_

SD3_

PLL2

SD3_

PLL2_

TPD

SD4_

PLL1_

TPD

AVDD_

SD4_

PLL1

AGND_

SD4_PLL

1

AGND_

SD4_PLL

2

AVDD_

SD4_

PLL2

SD4_

PLL2_

TPD

D3_

MDQ

[12]

D3_

MDQ

[08]

D3_

MDM

[1]

D3_

MDQ

[11]

D3_

MDM

[3]

D3_

MDQS

_B[12]

D3_

MCK

_B[1]

X4GND

[04]

X4GND

[05]

GND

[376]

GND

[377]

GND

[378]

G3VDD

[16]

D3_

MDQ

[13]

D3_

MDQ

[09]

D3_

MDQS

_B[10]

D3_

MDQS

_B[01]

D3_

MDQ

[10]

D3_

MDQ

[24]

D3_

MDQ

[25]

D3_

MCK

_B[0]

D3_

MCK

[1]

X3VDD

[6]

X3VDD

[7]

X3VDD

[8]

X4VDD

[2]

X4VDD

[3]

X4VDD

[4]

X4VDD

[5]

X4VDD

[6]

X4VDD

[7]

X4VDD

[8]

X4VDD

[9]

GND

[383]

GND

[384]

SD3_

TX

_B[6]

SD4_

TX

_B[0]

SD4_

TX

_B[2]

SD4_

TX

_B[4]

SD4_

TX

_B[6]

D3_

MDQS

[01]

D3_

MDQ

[14]

D3_

MDQ

[28]

D3_

MDQ

[29]

D3_

MCK

[0]

X3GND

[09]

X3GND

[10]

X4GND

[06]

X4GND

[07]

X4GND

[08]

X4GND

[09]

GND

[399]

GND

[400]

GND

[401]

GND

[402]

GND

[403]

G3VDD

[17]

SD3_

TX

[6]

SD4_

TX

[0]

SD4_

TX

[2]

SD4_

TX

[4]

SD4_

TX

[6]

D3_

MDQ

[04]

D3_

MDM

[0]

D3_

MDQ

[15]

D3_

MDQ

[19]

D3_

MCK

_B[3]

D3_

MCK

[3]

X3GND

[14]

X3GND

[15]

X4GND

[10]

X4GND

[11]

X4GND

[12]

X4GND

[13]

X4GND

[14]

GND

[406]

GND

[407]

GND

[408]

GND

[409]

AU

AV

AW

AY

BA

BB

BC

BD

AU

AV

AW

AY

BA

BB

BC

BD

SD3_

TX

_B[5]

SD3_

TX

_B[7]

SD4_

TX

_B[1]

SD4_

TX

_B[3]

SD4_

TX

_B[5]

SD4_

TX

_B[7]

D3_

MDQ

[05]

D3_

MDQS

_B[09]

D3_

MDQ

[03]

D3_

MDQS

[02]

D3_

MDQ

[18]

D3_

MDQ

[23]

D3_

MDIC

[1]

X3GND

[20]

X4GND

[15]

X4GND

[16]

X4GND

[17]

X4GND

[18]

X4GND

[19]

GND

[412]

GND

[413]

G3VDD

[18]

SD3_

TX

[5]

SD3_

TX

[7]

SD4_

TX

[1]

SD4_

TX

[3]

SD4_

TX

[5]

SD4_

TX

[7]

D3_

MDQ

[02]

D3_

MDQS

_B[02]

D3_

MDQ

[22]

D3_

MA

[01]

D3_

MA

[02]

X3GND

[24]

X4GND

[20]

X4GND

[21]

X4GND

[22]

X4GND

[23]

X4GND

[24]

GND

[428]

GND

[429]

GND

[430]

GND

[431]

GND

[432]

D3_

MDQ

[00]

D3_

MDQS

[00]

D3_

MDQ

[07]

D3_

MDQ

[21]

D3_

MDQ

[17]

D3_

MDQS

_B[11]

D3_

MA

[03]

S3GND

[20]

S3GND

[21]

S3GND

[22]

S4GND

[13]

S4GND

[14]

S4GND

[15]

S4GND

[16]

S4GND

[17]

S4GND

[18]

S4GND

[19]

S4GND

[20]

X4GND

[25]

GND

[435]

GND

[436]

G3VDD

[19]

SD3_

RX

_B[6]

SD4_

RX

_B[0]

SD4_

RX

_B[2]

SD4_

RX

_B[4]

SD4_

RX

_B[6]

D3_

MDQ

[01]

D3_

MDQS

_B[00]

D3_

MDQ

[06]

D3_

MDQ

[20]

D3_

MDQ

[16]

D3_

MDM

[2]

D3_

MA

[04]

D3_

MA

[05]

S3GND

[26]

S3GND

[27]

S4GND

[21]

S4GND

[22]

S4GND

[23]

S4GND

[24]

GND

[439]

GND

[440]

GND

[441]

SD3_

RX

[6]

SD4_

RX

[0]

SD4_

RX

[2]

SD4_

RX

[4]

SD4_

RX

[6]

GND_

DET

[3]

D3_

MA

[06]

S3GND

[31]

S3GND

[32]

S4GND

[25]

S4GND

[26]

S4GND

[27]

S4GND

[28]

S4GND

[29]

GND

[455]

GND

[456]

GND

[457]

GND

[458]

GND

[459]

GND

[460]

GND

[461]

G3VDD

[20]

SD3_

RX

_B[5]

SD3_

RX

_B[7]

SD4_

RX

_B[1]

SD4_

RX

_B[3]

SD4_

RX

_B[5]

SD4_

RX

_B[7]

D3_

MCKE

[1]

D3_

MCKE

[2]

D3_

MBA

[2]

D3_

MA

[14]

D3_

MA

[12]

D3_

MA

[08]

D3_

MA

[07]

S3GND

[37]

S4GND

[30]

S4GND

[31]

S4GND

[32]

S4GND

[33]

S4GND

[34]

G3VDD

[21]

G3VDD

[22]

G3VDD

[23]

SD3_

RX

[5]

SD3_

RX

[7]

SD4_

RX

[1]

SD4_

RX

[3]

SD4_

RX

[5]

SD4_

RX

[7]

D3_

MCKE

[3]

D3_

MCKE

[0]

D3_

MA

[15]

D3_

MAPAR_

ERR_B

D3_

MA

[09]

D3_

MA

[11]

S3GND

[41]

S4GND

[35]

S4GND

[36]

S4GND

[37]

S4GND

[38]

S4GND

[39]

G3VDD

[24]

G3VDD

[25]

G3VDD

[26]

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

DDR Interface 1

DDR Interface 2

DDR Interface 3

IFC

DUART

I2C

eSPI

eSDHC

MPIC

LP Trust

DDR Clocking

SerDes 2

IEEE1588

DMA

Trust

System Control

DFT

ASLEEP

Clocking

SerDes 1

USB CLK

Ethernet Cont. 2

No Connects

Debug

JTAG

SerDes 3

Ethernet MI 1

Analog signals

SerDes 4

Ethernet MI 2

Power

USB PHY 1 and 2

Ethernet Cont. 1

Ground

Figure 6. Detail D

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

9

Pin assignments

2.2 Pinout list

This table provides the pinout listing for the T4240 by bus. Primary functions are bolded

in the table.

Table 1. Pinout list by bus

Signal

Signal description

Package

type

Power supply

Notes

number

DDR SDRAM Memory Interface 1

D1_MA00

D1_MA01

D1_MA02

D1_MA03

D1_MA04

D1_MA05

D1_MA06

D1_MA07

D1_MA08

D1_MA09

D1_MA10

D1_MA11

D1_MA12

D1_MA13

D1_MA14

D1_MA15

Address

R2

G1

G2

F2

O

I

G1V _DD

---

G1V _DD

---

1, 18

---

2

E1

E2

D1

C2

C1

B3

T1

B2

A3

AD1

B5

B6

D1_MAPAR_ERR_B

D1_MAPAR_OUT

D1_MBA0

Address Parity Error

Address Parity Out

Bank Select

A4

R1

U1

U2

A5

AA2

K2

L2

O

D1_MBA1

Bank Select

D1_MBA2

Bank Select

D1_MCAS_B

D1_MCK0

Column Address Strobe

Clock

D1_MCK0_B

D1_MCK1

Clock Complements

Clock

L1

D1_MCK1_B

D1_MCK2

Clock Complements

Clock

M1

N2

N1

J2

D1_MCK2_B

D1_MCK3

Clock Complements

Clock

D1_MCK3_B

D1_MCKE0

Clock Complements

Clock Enable

J1

A7

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

10

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D1_MCKE1

D1_MCKE2

D1_MCKE3

Clock Enable

B8

B7

O

G1V _DD

2

Clock Enable

G1V _DD

2

Clock Enable

A8

O

2

D1_MCS0_B

Chip Select

Y1

O

---

3

D1_MCS1_B

Chip Select

AC2

W1

AC1

P2

O

D1_MCS2_B

Chip Select

O

D1_MCS3_B

Chip Select

O

D1_MDIC0

Driver Impedence Calibration

IO

O

D1_MDIC1

Driver Impedence Calibration

H1

D7

H7

M8

M5

V7

3

D1_MDM0/D1_MDQS09

D1_MDM1/D1_MDQS10

D1_MDM2/D1_MDQS11

D1_MDM3/D1_MDQS12

D1_MDM4/D1_MDQS13

D1_MDM5/D1_MDQS14

D1_MDM6/D1_MDQS15

D1_MDM7/D1_MDQS16

D1_MDM8/D1_MDQS17

D1_MDQ00

Data Mask

Data

1

O

1

O

1

O

1

O

1

V10

AC4

AB10

V5

O

1

O

1

O

1

O

1

F7

IO

---

D1_MDQ01

Data

E7

D1_MDQ02

Data

D4

E4

D1_MDQ03

Data

D1_MDQ04

Data

E8

D1_MDQ05

Data

D8

D5

E5

D1_MDQ06

Data

D1_MDQ07

Data

D1_MDQ08

Data

J8

D1_MDQ09

Data

G7

G4

H4

H8

G8

J6

D1_MDQ10

Data

D1_MDQ11

Data

D1_MDQ12

Data

D1_MDQ13

Data

D1_MDQ14

Data

D1_MDQ15

Data

J4

D1_MDQ16

Data

L8

D1_MDQ17

Data

L7

D1_MDQ18

Data

R8

R7

D1_MDQ19

Data

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

11

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D1_MDQ20

D1_MDQ21

D1_MDQ22

D1_MDQ23

D1_MDQ24

D1_MDQ25

D1_MDQ26

D1_MDQ27

D1_MDQ28

D1_MDQ29

D1_MDQ30

D1_MDQ31

D1_MDQ32

D1_MDQ33

D1_MDQ34

D1_MDQ35

D1_MDQ36

D1_MDQ37

D1_MDQ38

D1_MDQ39

D1_MDQ40

D1_MDQ41

D1_MDQ42

D1_MDQ43

D1_MDQ44

D1_MDQ45

D1_MDQ46

D1_MDQ47

D1_MDQ48

D1_MDQ49

D1_MDQ50

D1_MDQ51

D1_MDQ52

D1_MDQ53

D1_MDQ54

D1_MDQ55

D1_MDQ56

D1_MDQ57

Data

K8

K7

IO

G1V _DD

---

G1V _DD

---

P8

P7

L5

L4

R5

R4

K5

K4

P5

P4

U7

U8

AA7

AA8

T7

T8

Y7

Y8

U11

U12

Y12

Y13

U9

U10

Y10

Y11

AB7

AC7

AE6

AD7

AB5

AB6

AE5

AD6

AC9

AD9

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

12

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D1_MDQ58

D1_MDQ59

D1_MDQ60

D1_MDQ61

D1_MDQ62

D1_MDQ63

Data

AB13

AC13

AB9

AA9

AB12

AC12

F5

IO

G1V _DD

---

28

---

28

---

28

---

28

---

28

---

28

---

28

G1V _DD

D1_MDQS00

Data Strobe

D1_MDQS00_B

D1_MDQS01

Data Strobe

F6

Data Strobe

G5

D1_MDQS01_B

D1_MDQS02

Data Strobe

H5

Data Strobe

N7

D1_MDQS02_B

D1_MDQS03

Data Strobe

N8

Data Strobe

N4

D1_MDQS03_B

D1_MDQS04

Data Strobe

N5

Data Strobe

W8

D1_MDQS04_B

D1_MDQS05

Data Strobe

W7

Data Strobe

W11

W10

AE4

AD4

AC11

AB11

W4

D1_MDQS05_B

D1_MDQS06

Data Strobe

D1_MDQS06_B

D1_MDQS07

Data Strobe

D1_MDQS07_B

D1_MDQS08

Data Strobe

D1_MDQS08_B

D1_MDQS09/D1_MDM0

D1_MDQS09_B

D1_MDQS10/D1_MDM1

D1_MDQS10_B

D1_MDQS11/D1_MDM2

D1_MDQS11_B

D1_MDQS12/D1_MDM3

D1_MDQS12_B

D1_MDQS13/D1_MDM4

D1_MDQS13_B

D1_MDQS14/D1_MDM5

D1_MDQS14_B

D1_MDQS15/D1_MDM6

D1_MDQS15_B

Data Strobe

W5

Data Strobe (x4 support)

D7

D6

H7

H6

M8

M7

M5

M4

V7

V8

V10

V11

AC4

AC5

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

13

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D1_MDQS16/D1_MDM7

D1_MDQS16_B

D1_MDQS17/D1_MDM8

D1_MDQS17_B

D1_MECC0

Data Strobe (x4 support)

Error Correcting Code

On Die Termination

Row Address Strobe

Write Enable

AB10

AC10

V5

IO

O

G1V _DD

---

G1V _DD

28

---

28

---

2

V4

U5

D1_MECC1

U4

D1_MECC2

AA5

AA4

T5

D1_MECC3

D1_MECC4

D1_MECC5

T4

D1_MECC6

Y5

D1_MECC7

Y4

D1_MODT0

AA1

AE1

AB2

AE2

V2

D1_MODT1

O

2

D1_MODT2

O

2

D1_MODT3

O

2

D1_MRAS_B

D1_MWE_B

O

---

W2

O

DDR SDRAM Memory Interface 2

D2_MA00

Address

AU1

BC5

BD4

BD5

BC6

BC7

BD7

BC9

BD8

BC10

AT2

O

I

G2V _DD

---

1, 18

---

D2_MA01

D2_MA02

D2_MA03

D2_MA04

D2_MA05

D2_MA06

D2_MA07

D2_MA08

D2_MA09

D2_MA10

D2_MA11

BD9

BC11

AK2

D2_MA12

D2_MA13

D2_MA14

BC13

BC14

D2_MA15

D2_MAPAR_ERR_B

D2_MAPAR_OUT

D2_MBA0

Address Parity Error

Address Parity Out

Bank Select

BD11

AV1

O

AR2

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

14

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D2_MBA1

D2_MBA2

Bank Select

AT1

BD12

AM2

BA1

O

IO

O

IO

G2V _DD

---

2

Bank Select

Column Address Strobe

Clock

G2V _DD

D2_MCAS_B

D2_MCK0

D2_MCK0_B

Clock Complements

Clock

AY1

D2_MCK1

BB1

D2_MCK1_B

Clock Complements

Clock

BB2

D2_MCK2

AY2

D2_MCK2_B

Clock Complements

Clock

AW2

BC2

D2_MCK3

D2_MCK3_B

Clock Complements

Clock Enable

Chip Select

Driver Impedence Calibration

Data Mask

Data

BC3

D2_MCKE0

BD15

BD16

BD13

BC15

AP2

D2_MCKE1

2

D2_MCKE2

2

D2_MCKE3

2

D2_MCS0_B

---

3

D2_MCS1_B

AH2

D2_MCS2_B

AN1

D2_MCS3_B

AJ1

D2_MDIC0

AV2

D2_MDIC1

BD3

3

D2_MDM0/D2_MDQS09

D2_MDM1/D2_MDQS10

D2_MDM2/D2_MDQS11

D2_MDM3/D2_MDQS12

D2_MDM4/D2_MDQS13

D2_MDM5/D2_MDQS14

D2_MDM6/D2_MDQS15

D2_MDM7/D2_MDQS16

D2_MDM8/D2_MDQS17

D2_MDQ00

AY14

AU14

AU7

1

AY7

1

AN8

1

AN4

1

AH4

1

AF10

AN11

AY15

BA15

AY11

BA11

AY16

BA16

AY12

BA12

1

---

D2_MDQ01

Data

D2_MDQ02

Data

D2_MDQ03

Data

D2_MDQ04

Data

D2_MDQ05

Data

D2_MDQ06

Data

D2_MDQ07

Data

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

15

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D2_MDQ08

D2_MDQ09

D2_MDQ10

D2_MDQ11

D2_MDQ12

D2_MDQ13

D2_MDQ14

D2_MDQ15

D2_MDQ16

D2_MDQ17

D2_MDQ18

D2_MDQ19

D2_MDQ20

D2_MDQ21

D2_MDQ22

D2_MDQ23

D2_MDQ24

D2_MDQ25

D2_MDQ26

D2_MDQ27

D2_MDQ28

D2_MDQ29

D2_MDQ30

D2_MDQ31

D2_MDQ32

D2_MDQ33

D2_MDQ34

D2_MDQ35

D2_MDQ36

D2_MDQ37

D2_MDQ38

D2_MDQ39

D2_MDQ40

D2_MDQ41

D2_MDQ42

D2_MDQ43

D2_MDQ44

D2_MDQ45

Data

AU15

AV15

AU11

AV11

AU16

AV16

AU12

AV12

AU8

AV8

AU4

AV4

AU9

AV9

AU5

AV5

AY8

BA8

AY4

BA4

AY9

BA9

AY5

BA5

AP8

AP7

AK8

AK7

AR8

AR7

AL8

IO

G2V _DD

---

G2V _DD

---

AL7

AP4

AP5

AK4

AK5

AR4

AR5

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

16

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D2_MDQ46

D2_MDQ47

D2_MDQ48

D2_MDQ49

D2_MDQ50

D2_MDQ51

D2_MDQ52

D2_MDQ53

D2_MDQ54

D2_MDQ55

D2_MDQ56

D2_MDQ57

D2_MDQ58

D2_MDQ59

D2_MDQ60

D2_MDQ61

D2_MDQ62

D2_MDQ63

Data

AL4

AL5

IO

G2V _DD

---

28

G2V _DD

AH6

AH5

AF8

AE8

AH8

AH7

AF7

AG7

AG9

AG10

AF13

AE13

AH10

AH11

AF12

AE12

BA13

AY13

AV13

AU13

AV6

D2_MDQS00

Data Strobe

D2_MDQS00_B

D2_MDQS01

Data Strobe

D2_MDQS01_B

D2_MDQS02

Data Strobe

D2_MDQS02_B

D2_MDQS03

Data Strobe

AU6

Data Strobe

BA6

D2_MDQS03_B

D2_MDQS04

Data Strobe

AY6

Data Strobe

AM7

AM8

AM5

AM4

AG6

AG5

AE11

AE10

AM10

AM11

AY14

BA14

D2_MDQS04_B

D2_MDQS05

Data Strobe

D2_MDQS05_B

D2_MDQS06

Data Strobe

D2_MDQS06_B

D2_MDQS07

Data Strobe

D2_MDQS07_B

D2_MDQS08

Data Strobe

D2_MDQS08_B

D2_MDQS09/D2_MDM0

D2_MDQS09_B

Data Strobe

Data Strobe (x4 support)

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

17

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D2_MDQS10/D2_MDM1

D2_MDQS10_B

D2_MDQS11/D2_MDM2

D2_MDQS11_B

D2_MDQS12/D2_MDM3

D2_MDQS12_B

D2_MDQS13/D2_MDM4

D2_MDQS13_B

D2_MDQS14/D2_MDM5

D2_MDQS14_B

D2_MDQS15/D2_MDM6

D2_MDQS15_B

D2_MDQS16/D2_MDM7

D2_MDQS16_B

D2_MDQS17/D2_MDM8

D2_MDQS17_B

D2_MECC0

Data Strobe (x4 support)

Error Correcting Code

On Die Termination

AU14

AV14

AU7

IO

O

G2V _DD

---

G2V _DD

28

---

28

---

28

---

28

---

28

---

28

---

28

---

28

---

2

AV7

AY7

BA7

AN8

AN7

AN4

AN5

AH4

AG4

AF10

AF11

AN11

AN10

AP11

AP10

AK11

AK10

AR11

AR10

AL11

AL10

AL2

D2_MECC1

D2_MECC2

D2_MECC3

D2_MECC4

D2_MECC5

D2_MECC6

D2_MECC7

D2_MODT0

D2_MODT1

On Die Termination

AG2

AK1

O

2

D2_MODT2

On Die Termination

O

2

D2_MODT3

On Die Termination

AH1

O

2

D2_MRAS_B

Row Address Strobe

AP1

O

---

D2_MWE_B

Write Enable

AM1

O

DDR SDRAM Memory Interface 3

D3_MA00

D3_MA01

D3_MA02

D3_MA03

D3_MA04

D3_MA05

D3_MA06

Address

AL44

AW43

AW44

AY43

BA43

BA44

BB44

O

G3V _DD

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

18

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D3_MA07

D3_MA08

D3_MA09

D3_MA10

D3_MA11

D3_MA12

D3_MA13

D3_MA14

D3_MA15

Address

BC43

BC42

BD41

AK44

BD42

BC40

AB44

BC39

BD38

BD40

AL43

AJ43

AJ44

BC38

AE44

AT43

AR43

AR44

AP44

AN44

AN43

AU44

AU43

BD37

BC35

BC36

BD36

AF44

AC44

AG43

AC43

AM43

AV44

AU36

AP36

BA41

AP40

AG40

O

I

G3V _DD

---

Address

G3V _DD

---

Address

---

Address

---

Address

---

Address

---

Address

---

Address

---

Address

---

D3_MAPAR_ERR_B

D3_MAPAR_OUT

D3_MBA0

Address Parity Error

Address Parity Out

Bank Select

Column Address Strobe

Clock

1, 18

---

O

IO

O

---

D3_MBA1

---

D3_MBA2

---

D3_MCAS_B

D3_MCK0

---

D3_MCK0_B

Clock Complements

Clock

---

D3_MCK1

---

D3_MCK1_B

Clock Complements

Clock

---

D3_MCK2

---

D3_MCK2_B

Clock Complements

Clock

---

D3_MCK3

---

D3_MCK3_B

Clock Complements

Clock Enable

Chip Select

---

D3_MCKE0

2

D3_MCKE1

2

D3_MCKE2

2

D3_MCKE3

2

D3_MCS0_B

---

D3_MCS1_B

Chip Select

---

D3_MCS2_B

Chip Select

---

D3_MCS3_B

Chip Select

---

D3_MDIC0

Driver Impedence Calibration

Data Mask

3

D3_MDIC1

3

D3_MDM0/D3_MDQS09

D3_MDM1/D3_MDQS10

D3_MDM2/D3_MDQS11

D3_MDM3/D3_MDQS12

D3_MDM4/D3_MDQS13

1, 28

Data Mask

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

19

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D3_MDM5/D3_MDQS14

D3_MDM6/D3_MDQS15

D3_MDM7/D3_MDQS16

D3_MDM8/D3_MDQS17

D3_MDQ00

Data Mask

AG38

AF35

AB39

AM37

AY35

BA35

AW37

AV37

AU35

AV35

BA37

AY37

AP35

AR35

AR38

AP38

AP34

AR34

AT38

AU38

BA40

AY40

AV40

AU40

BA39

AY39

AW41

AV41

AR40

AR41

AL40

AL41

AT40

AT41

AM40

AM41

AH40

AH41

O

G3V _DD

1, 28

Data Mask

Data

O

G3V _DD

1, 28

---

O

IO

D3_MDQ01

Data

D3_MDQ02

Data

D3_MDQ03

Data

D3_MDQ04

Data

D3_MDQ05

Data

D3_MDQ06

Data

D3_MDQ07

Data

D3_MDQ08

Data

D3_MDQ09

Data

D3_MDQ10

Data

D3_MDQ11

Data

D3_MDQ12

Data

D3_MDQ13

Data

D3_MDQ14

Data

D3_MDQ15

Data

D3_MDQ16

Data

D3_MDQ17

Data

D3_MDQ18

Data

D3_MDQ19

Data

D3_MDQ20

Data

D3_MDQ21

Data

D3_MDQ22

Data

D3_MDQ23

Data

D3_MDQ24

Data

D3_MDQ25

Data

D3_MDQ26

Data

D3_MDQ27

Data

D3_MDQ28

Data

D3_MDQ29

Data

D3_MDQ30

Data

D3_MDQ31

Data

D3_MDQ32

Data

D3_MDQ33

Data

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

20

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D3_MDQ34

D3_MDQ35

D3_MDQ36

D3_MDQ37

D3_MDQ38

D3_MDQ39

D3_MDQ40

D3_MDQ41

D3_MDQ42

D3_MDQ43

D3_MDQ44

D3_MDQ45

D3_MDQ46

D3_MDQ47

D3_MDQ48

D3_MDQ49

D3_MDQ50

D3_MDQ51

D3_MDQ52

D3_MDQ53

D3_MDQ54

D3_MDQ55

D3_MDQ56

D3_MDQ57

D3_MDQ58

D3_MDQ59

D3_MDQ60

D3_MDQ61

D3_MDQ62

D3_MDQ63

Data

AD40

AD41

AJ40

AJ41

AE40

AE41

AH38

AH37

AD38

AD37

AJ38

AJ37

AE38

AE37

AG35

AG34

AC35

AC34

AH35

AH34

AD35

AD34

AB40

AA40

AB36

AA36

AB41

AA41

AB37

AA37

AY36

BA36

AT37

AR37

AV39

AW39

AN41

AN40

IO

G3V _DD

---

G3V _DD

D3_MDQS00

Data Strobe

D3_MDQS00_B

D3_MDQS01

D3_MDQS01_B

D3_MDQS02

D3_MDQS02_B

D3_MDQS03

D3_MDQS03_B

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

21

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

D3_MDQS04

Data Strobe

AF41

AF40

AF37

AF38

AE34

AE35

AA38

AB38

AL38

AL37

AU36

AV36

AP36

AR36

BA41

AY41

AP40

AP41

AG40

AG41

AG38

AG37

AF35

AF34

AB39

AA39

AM37

AM38

AN37

AN38

AK35

AK34

AM34

AM35

AL36

AL35

AE43

AA43

IO

O

G3V _DD

---

D3_MDQS04_B

D3_MDQS05

Data Strobe

G3V _DD

---

28

---

28

---

28

---

28

---

28

---

28

---

28

---

28

---

28

---

2

Data Strobe

D3_MDQS05_B

D3_MDQS06

Data Strobe

D3_MDQS06_B

D3_MDQS07

Data Strobe

D3_MDQS07_B

D3_MDQS08

Data Strobe

D3_MDQS08_B

D3_MDQS09/D3_MDM0

D3_MDQS09_B

D3_MDQS10/D3_MDM1

D3_MDQS10_B

D3_MDQS11/D3_MDM2

D3_MDQS11_B

D3_MDQS12/D3_MDM3

D3_MDQS12_B

D3_MDQS13/D3_MDM4

D3_MDQS13_B

D3_MDQS14/D3_MDM5

D3_MDQS14_B

D3_MDQS15/D3_MDM6

D3_MDQS15_B

D3_MDQS16/D3_MDM7

D3_MDQS16_B

D3_MDQS17/D3_MDM8

D3_MDQS17_B

D3_MECC0

Data Strobe

Data Strobe (x4 support)

Error Correcting Code

On Die Termination

D3_MECC1

D3_MECC2

D3_MECC3

D3_MECC4

D3_MECC5

D3_MECC6

D3_MECC7

D3_MODT0

D3_MODT1

O

2

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

22

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

D3_MODT2

D3_MODT3

On Die Termination

AD43

AA44

AH43

AG44

O

G3V _DD

2

On Die Termination

Row Address Strobe

Write Enable

G3V _DD

2

D3_MRAS_B

D3_MWE_B

---

Integrated Flash Controller

IFC_A26/GPIO2_18

IFC_A27/GPIO2_19

IFC_A28/GPIO2_20

IFC_A29/GPIO2_21

IFC_A30/GPIO2_22

IFC_A31/GPIO2_23

IFC_AD00/cfg_gpinput0

IFC_AD01/cfg_gpinput1

IFC_AD02/cfg_gpinput2

IFC_AD03/cfg_gpinput3

IFC_AD04/cfg_gpinput4

IFC_AD05/cfg_gpinput5

IFC_AD06/cfg_gpinput6

IFC_AD07/cfg_gpinput7

IFC_AD08/cfg_rcw_src0

IFC_AD09/cfg_rcw_src1

IFC_AD10/cfg_rcw_src2

IFC_AD11/cfg_rcw_src3

IFC_AD12/cfg_rcw_src4

IFC_AD13/cfg_rcw_src5

IFC_AD14/cfg_rcw_src6

IFC_AD15/cfg_rcw_src7

IFC_AD16

IFC Address

B40

A40

D39

C39

A39

C38

O

OV _DD

1

O

1

O

1

O

1

O

1

IFC Address/Data

W39

W40

V39

V40

U40

U41

T39

T40

R39

R40

P40

P41

N39

N40

M39

M40

L40

L41

K39

K40

J39

IO

4, 21

29

IFC_AD17

5, 20

4, 21

20

IFC_AD18

IFC_AD19

IFC_AD20

IFC_AD21/cfg_dram_type

IFC_AD22

J40

H40

H41

G40

G41

IFC_AD23

20

IFC_AD24

20

IFC_AD25/GPIO2_25/

20

IFC_WP1_B

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

23

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

IFC_AD26/GPIO2_26/

IFC_WP2_B

IFC Address/Data

G39

IO

OV _DD

20

IFC_AD27/GPIO2_27/

IFC Address/Data

F40

OV _DD

20

IFC_WP3_B

IFC_AD28/GPIO2_28

IFC Address/Data

E41

E40

IO

OV _DD

20

IFC_AD29/GPIO2_29/

IFC_RB2_B

IFC_AD30/GPIO2_30/

IFC_RB3_B

IFC Address/Data

E39

D41

IO

OV _DD

20

IFC_AD31/GPIO2_31/

IFC_RB4_B

IFC_AVD

IFC Address Valid

IFC Buffer Control

IFC Command Latch Enable

IFC Clock

H44

G44

E43

B38

H42

A38

C43

C44

B43

A42

C41

B41

A41

C40

H43

E36

E42

E38

D38

F38

F37

E37

F43

F42

E40

O

IO

O

IO

I

OV _DD

1, 5

1

IFC_BCTL

IFC_CLE/cfg_rcw_src8

IFC_CLK0

1, 4, 25

1

IFC_CLK1

IFC Clock

1

IFC_CLK2

IFC Clock

1

IFC_CS0_B

IFC Chip Select

1, 6

1

IFC_CS1_B/GPIO2_10

IFC_CS2_B/GPIO2_11

IFC_CS3_B/GPIO2_12

IFC_CS4_B/GPIO1_09

IFC_CS5_B/GPIO1_10

IFC_CS6_B/GPIO1_11

IFC_CS7_B/GPIO1_12

IFC_NDDDR_CLK

IFC_NDDQS

IFC Chip Select

IFC NAND DDR Clock

IFC DQS Strobe

20

IFC_OE_B

IFC Output Enable

IFC Address and Data Parity

IFC Parity Error

1, 5

20

IFC_PAR0/GPIO2_13

IFC_PAR1/GPIO2_14

IFC_PAR2/GPIO2_16

IFC_PAR3/GPIO2_17

IFC_PERR_B/GPIO2_15

IFC_RB0_B

20

1, 18

8

IFC Ready / Busy CS0

IFC Ready / Busy CS1

IFC Ready / Busy CS 2

I

IFC_RB1_B

I

8

IFC_RB2_B/IFC_AD29/

I

1

GPIO2_29

IFC_RB3_B/IFC_AD30/

IFC Ready / Busy CS 3

E39

I

OV _DD

1

GPIO2_30

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

24

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

IFC_RB4_B/IFC_AD31/

IFC Ready / Busy CS 4

D41

I

OV _DD

1

GPIO2_31

IFC_TE/cfg_ifc_te

IFC External Transceiver

Enable

G42

O

OV _DD

1, 4

IFC_WE0_B

IFC_WE2_B

IFC_WE3_B

IFC_WP0_B

IFC Write Enable

IFC Write Protect

E44

D42

D44

F44

G41

O

OV _DD

1, 5

1

1, 5

1

IFC_WP1_B/IFC_AD25/

GPIO2_25

IFC_WP2_B/IFC_AD26/

GPIO2_26

IFC Write Protect

G39

F40

O

OV _DD

1

IFC_WP3_B/IFC_AD27/

GPIO2_27

DUART

UART1_CTS_B/GPIO1_21/

UART3_SIN

Clear To Send

Ready to Send

N11

M10

I

DV _DD

1

UART1_RTS_B/GPIO1_19/

O

UART3_SOUT

UART1_SIN/GPIO1_17

Receive Data

Transmit Data

Clear To Send

M11

L10

K11

I

O

I

DV _DD

1

UART1_SOUT/GPIO1_15

UART2_CTS_B/GPIO1_22/

UART4_SIN

UART2_RTS_B/GPIO1_20/

Ready to Send

K10

O

DV _DD

1

UART4_SOUT

UART2_SIN/GPIO1_18

Receive Data

Transmit Data

J11

J10

N11

I

O

I

DV _DD

1

UART2_SOUT/GPIO1_16

UART3_SIN/UART1_CTS_B/ Receive Data

GPIO1_21

UART3_SOUT/

UART1_RTS_B/GPIO1_19

Transmit Data

M10

K11

K10

O

I

DV _DD

1

UART4_SIN/UART2_CTS_B/ Receive Data

GPIO1_22

UART4_SOUT/

Transmit Data

O

UART2_RTS_B/GPIO1_20

I2C

IIC1_SCL

Serial Clock (supports PBL)

Serial Data (supports PBL)

Serial Clock

R10

R11

N10

P10

N13

P13

IO

DV _DD

7, 8

IIC1_SDA

IIC2_SCL

IIC2_SDA

Serial Data

IIC3_SCL/GPIO4_00

IIC3_SDA/GPIO4_01

Serial Clock

Serial Data

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

25

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

IIC4_SCL/GPIO4_02/EVT5_B Serial Clock

IIC4_SDA/GPIO4_03/EVT6_B Serial Data

N12

P12

IO

DV _DD

7, 8

DV _DD

7, 8

eSPI Interface

SPI_CLK

SPI Clock

B37

C35

O

OV _DD

1

SPI_CS0_B/GPIO2_00/

SPI Chip Select

1, 22

SDHC_DAT4

SPI_CS1_B/GPIO2_01/

SDHC_DAT5

SPI Chip Select

A36

C36

D36

O

OV _DD

1, 22

SPI_CS2_B/GPIO2_02/

SDHC_DAT6

SPI_CS3_B/GPIO2_03/

SDHC_DAT7

SPI_MISO

SPI_MOSI

Master In Slave Out

Master Out Slave In

C37

A37

I

OV _DD

---

IO

20

eSDHC

SDHC_CD_B

Card Detection

A34

A33

D33

B34

C34

A35

B35

C35

I

OV _DD

26

1

SDHC_CLK/GPIO2_09

SDHC_CMD/GPIO2_04

SDHC_DAT0/GPIO2_05

SDHC_DAT1/GPIO2_06

SDHC_DAT2/GPIO2_07

SDHC_DAT3/GPIO2_08

Host to Card Clock

O

Command/Response

IO

22

---

Data

SDHC_DAT4/SPI_CS0_B/

GPIO2_00

SDHC_DAT5/SPI_CS1_B/

GPIO2_01

Data

A36

C36

D36

C33

IO

I

OV _DD

---

26

SDHC_DAT6/SPI_CS2_B/

GPIO2_02

Data

SDHC_DAT7/SPI_CS3_B/

GPIO2_03

Data

SDHC_WP

Card Write Protection

Programmable Interrupt Controller

IRQ00

External Interrupts

V43

V44

U43

W42

U44

R42

W41

T42

I

OV _DD

1

IRQ01

External Interrupts

IRQ02

IRQ03/GPIO1_23

IRQ04/GPIO1_24

IRQ05/GPIO1_25

IRQ06/GPIO1_26

IRQ07/GPIO1_27

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

26

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

IRQ08/GPIO1_28

IRQ09/GPIO1_29

IRQ10/GPIO1_30

IRQ11/GPIO1_31

IRQ_OUT_B/EVT9_B

External Interrupts

T44

V42

W44

U42

T41

I

OV _DD

1

External Interrupts

Interrupt Output

OV _DD

1

I

1

I

1

O

1, 6, 7

LP Trust

Low Power Tamper Detect

Trust

LP_TMP_DETECT_B

TMP_DETECT_B

T27

E35

I

V _DD_LP

OV _DD

---

1

Tamper Detect

System Control

HRESET_B

Hard Reset

D35

F35

G33

IO

I

OV _DD

6, 7

---

PORESET_B

RESET_REQ_B

Power On Reset

Reset Request (POR or Hard)

O

1, 5

Power Management

ASLEEP/GPIO1_13/

Asleep

G34

O

OV _DD

1, 4

cfg_xvdd_sel

Clocking

RTC/GPIO1_14

Real Time Clock

System Clock

V33

U34

I

OV _DD

1

SYSCLK

---

DDR Clocking

DDRCLK

DDR Controllers Clock

AL14

I

OV _DD

---

Debug

CKSTP_OUT_B

CLK_OUT

EVT0_B

Checkstop Out

Clock Out

Event 0

L44

N44

N42

M43

M42

L43

L42

N12

P12

P44

O

OV _DD

DV _DD

OV _DD

1, 6, 7

2

O

IO

9

EVT1_B

Event 1

---

EVT2_B

Event 2

EVT3_B

Event 3

EVT4_B

Event 4

EVT5_B/IIC4_SCL/GPIO4_02 Event 5

EVT6_B/IIC4_SDA/GPIO4_03 Event 6

EVT7_B/DMA2_DACK0_B/

Event 7

GPIO4_08

EVT8_B/DMA2_DDONE0_B/ Event 8

GPIO4_09

P42

T41

IO

OV _DD

---

EVT9_B/IRQ_OUT_B

Event 9

DFT

SCAN_MODE_B

TEST_SEL_B

Reserved for internal use only

E33

F34

I

OV _DD

10

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

27

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

JTAG

TCK

Test Clock

K44

J43

K42

K41

J42

I

OV _DD

---

TDI

Test Data In

OV _DD

9

2

9

TDO

Test Data Out

Test Mode Select

Test Reset

O

I

TMS

TRST_B

I

SerDes 1

SD1_IMP_CAL_RX

SD1_IMP_CAL_TX

SerDes Receive Impedence

Calibration

M16

M22

I

S1V _DD

X1V _DD

11

16

SerDes Transmit Impedance

Calibration

SD1_PLL1_TPA

SD1_PLL1_TPD

SD1_PLL2_TPA

SD1_PLL2_TPD

SD1_REF_CLK1

SD1_REF_CLK1_B

Reserved for internal use only

SerDes PLL 1 Reference Clock

M18

L16

M20

L22

P18

P19

O

I

AVDD_SD1_PLL1

X1V _DD

12

---

AVDD_SD1_PLL2

X1V _DD

S1V _DD

SerDes PLL 1 Reference Clock

Complement

I

S1V _DD

SD1_REF_CLK2

SerDes PLL 2 Reference Clock

P21

N21

I

S1V _DD

---

SD1_REF_CLK2_B

SerDes PLL 2 Reference Clock

Complement

SD1_RX0

SerDes Receive Data

(positive)

C15

D15

A16

B16

C17

D17

A18

B18

C19

D19

I

S1V _DD

---

SD1_RX0_B

SD1_RX1

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD1_RX1_B

SD1_RX2

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD1_RX2_B

SD1_RX3

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD1_RX3_B

SD1_RX4

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD1_RX4_B

SerDes Receive Data

(negative)

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

28

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

SD1_RX5

SerDes Receive Data

(positive)

A20

B20

C21

D21

A22

B22

H15

J15

I

S1V _DD

---

SD1_RX5_B

SD1_RX6

SerDes Receive Data

(negative)

I

S1V _DD

X1V _DD

SerDes Receive Data

(positive)

I

SD1_RX6_B

SD1_RX7

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD1_RX7_B

SD1_TX0

SerDes Receive Data

(negative)

I

SerDes Transmit Data

(positive)

O

SD1_TX0_B

SD1_TX1

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

F16

G16

H17

J17

SD1_TX1_B

SD1_TX2

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD1_TX2_B

SD1_TX3

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

F18

G18

H19

J19

SD1_TX3_B

SD1_TX4

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD1_TX4_B

SD1_TX5

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

F20

G20

H21

J21

SD1_TX5_B

SD1_TX6

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD1_TX6_B

SD1_TX7

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

F22

G22

SD1_TX7_B

SerDes Transmit Data

(negative)

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

29

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

SerDes 2

SD2_IMP_CAL_RX

SD2_IMP_CAL_TX

SerDes Receive Impedence

Calibration

M23

M29

I

S2V _DD

11

SerDes Transmit Impedance

Calibration

X2V _DD

16

SD2_PLL1_TPA

SD2_PLL1_TPD

SD2_PLL2_TPA

SD2_PLL2_TPD

SD2_REF_CLK1

SD2_REF_CLK1_B

Reserved for internal use only

SerDes PLL 1 Reference Clock

M25

L23

M27

L29

P24

N24

O

I

AVDD_SD2_PLL1

X2V _DD

12

---

AVDD_SD2_PLL2

X2V _DD

S2V _DD

SerDes PLL 1 Reference Clock

Complement

I

S2V _DD

SD2_REF_CLK2

SerDes PLL 2 Reference Clock

P27

P26

I

S2V _DD

---

SD2_REF_CLK2_B

SerDes PLL 2 Reference Clock

Complement

SD2_RX0

SerDes Receive Data

(positive)

C23

D23

A24

B24

C25

D25

A26

B26

C27

D27

A28

B28

C29

D29

I

S2V _DD

---

SD2_RX0_B

SD2_RX1

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD2_RX1_B

SD2_RX2

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD2_RX2_B

SD2_RX3

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD2_RX3_B

SD2_RX4

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD2_RX4_B

SD2_RX5

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD2_RX5_B

SD2_RX6

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

SD2_RX6_B

SerDes Receive Data

(negative)

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

30

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

SD2_RX7

SerDes Receive Data

(positive)

A30

B30

H23

J23

F24

G24

H25

J25

F26

G26

H27

J27

F28

G28

H29

J29

F30

G30

I

S2V _DD

---

SD2_RX7_B

SD2_TX0

SerDes Receive Data

(negative)

I

S2V _DD

X2V _DD

SerDes Transmit Data

(positive)

O

SD2_TX0_B

SD2_TX1

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX1_B

SD2_TX2

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX2_B

SD2_TX3

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX3_B

SD2_TX4

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX4_B

SD2_TX5

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX5_B

SD2_TX6

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX6_B

SD2_TX7

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD2_TX7_B

SerDes Transmit Data

(negative)

SerDes 3

SD3_IMP_CAL_RX

SD3_IMP_CAL_TX

SerDes Receive Impedence

Calibration

AN19

AN25

I

S3V _DD

X3V _DD

11

16

SerDes Transmit Impedance

Calibration

SD3_PLL1_TPA

SD3_PLL1_TPD

SD3_PLL2_TPA

Reserved for internal use only

AN21

AP19

AN23

O

AVDD_SD3_PLL1

X3V _DD

12

AVDD_SD3_PLL2

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

31

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

SD3_PLL2_TPD

SD3_REF_CLK1

SD3_REF_CLK1_B

Reserved for internal use only

SerDes PLL 1 Reference Clock

AP25

AL21

AL22

O

I

X3V _DD

12

S3V _DD

---

SerDes PLL 1 Reference Clock

Complement

I

SD3_REF_CLK2

SerDes PLL 2 Reference Clock

AL24

I

S3V _DD

---

SD3_REF_CLK2_B

SerDes PLL 2 Reference Clock

Complement

AM24

SD3_RX0

SerDes Receive Data

(positive)

BB18

BA18

BD19

BC19

BB20

BA20

BD21

BC21

BB22

BA22

BD23

BC23

BB24

BA24

BD25

BC25

AU18

AT18

I

S3V _DD

X3V _DD

---

SD3_RX0_B

SD3_RX1

SerDes Receive Data

(negative)

SerDes Receive Data

(positive)

I

SD3_RX1_B

SD3_RX2

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD3_RX2_B

SD3_RX3

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD3_RX3_B

SD3_RX4

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD3_RX4_B

SD3_RX5

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD3_RX5_B

SD3_RX6

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD3_RX6_B

SD3_RX7

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD3_RX7_B

SD3_TX0

SerDes Receive Data

(negative)

I

SerDes Transmit Data

(positive)

O

SD3_TX0_B

SerDes Transmit Data

(negative)

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

32

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

SD3_TX1

SerDes Transmit Data

(positive)

AW19

AV19

AU20

AT20

AW21

AV21

AU22

AT22

AW23

AV23

AU24

AT24

AW25

AV25

O

X3V _DD

---

SD3_TX1_B

SD3_TX2

SerDes Transmit Data

(negative)

X3V _DD

SerDes Transmit Data

(positive)

SD3_TX2_B

SD3_TX3

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD3_TX3_B

SD3_TX4

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD3_TX4_B

SD3_TX5

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD3_TX5_B

SD3_TX6

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD3_TX6_B

SD3_TX7

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD3_TX7_B

SerDes Transmit Data

(negative)

SerDes 4

SD4_IMP_CAL_RX

SD4_IMP_CAL_TX

SerDes Receive Impedence

Calibration

AN26

AN32

I

S4V _DD

X4V _DD

11

16

SerDes Transmit Impedance

Calibration

SD4_PLL1_TPA

SD4_PLL1_TPD

SD4_PLL2_TPA

SD4_PLL2_TPD

SD4_REF_CLK1

SD4_REF_CLK1_B

Reserved for internal use only

SerDes PLL 1 Reference Clock

AN28

AP26

AN30

AP32

AL27

AM27

O

I

AVDD_SD4_PLL1

X4V _DD

12

---

AVDD_SD4_PLL2

X4V _DD

S4V _DD

SerDes PLL 1 Reference Clock

Complement

I

S4V _DD

SD4_REF_CLK2

SerDes PLL 2 Reference Clock

AL30

AL29

I

S4V _DD

---

SD4_REF_CLK2_B

SerDes PLL 2 Reference Clock

Complement

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

33

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

SD4_RX0

SerDes Receive Data

(positive)

BB26

BA26

BD27

BC27

BB28

BA28

BD29

BC29

BB30

BA30

BD31

BC31

BB32

BA32

BD33

BC33

AU26

AT26

AW27

AV27

AU28

AT28

I

S4V _DD

---

SD4_RX0_B

SD4_RX1

SerDes Receive Data

(negative)

S4V _DD

X4V _DD

---

SerDes Receive Data

(positive)

I

SD4_RX1_B

SD4_RX2

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD4_RX2_B

SD4_RX3

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD4_RX3_B

SD4_RX4

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD4_RX4_B

SD4_RX5

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD4_RX5_B

SD4_RX6

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD4_RX6_B

SD4_RX7

SerDes Receive Data

(negative)

I

SerDes Receive Data

(positive)

I

SD4_RX7_B

SD4_TX0

SerDes Receive Data

(negative)

I

SerDes Transmit Data

(positive)

O

SD4_TX0_B

SD4_TX1

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD4_TX1_B

SD4_TX2

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD4_TX2_B

SerDes Transmit Data

(negative)

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

34

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

SD4_TX3

SerDes Transmit Data

(positive)

AW29

AV29

AU30

AT30

AW31

AV31

AU32

AT32

AW33

AV33

O

X4V _DD

---

SD4_TX3_B

SD4_TX4

SerDes Transmit Data

(negative)

X4V _DD

SerDes Transmit Data

(positive)

SD4_TX4_B

SD4_TX5

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD4_TX5_B

SD4_TX6

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD4_TX6_B

SD4_TX7

SerDes Transmit Data

(negative)

SerDes Transmit Data

(positive)

SD4_TX7_B

SerDes Transmit Data

(negative)

USB PHY 1 & 2

USB1_DRVVBUS

USB1_PWRFAULT

USB PHY Digital signal - Drive

VBUS

E32

F32

O

I

USB_HV _DD

---

USB PHY Digital signal -

Power Fault

USB1_UDM

USB PHY Data Minus

USB PHY Data Plus

USB PHY ID Detect

USB PHY VBUS

J31

K31

L32

G32

A32

IO

I

USB_HV _DD

USB_OV _DD

USB_HV _DD

---

USB1_UDP

USB1_UID

USB1_VBUSCLMP

USB2_DRVVBUS

I

USB PHY Digital signal - Drive

VBUS

O

USB2_PWRFAULT

USB PHY Digital signal -

Power Fault

B32

I

USB_HV _DD

---

USB2_UDM

USB PHY Data Minus

USB PHY Data Plus

USB PHY ID Detect

USB PHY VBUS

M31

N31

H32

C32

D31

IO

I

USB_HV _DD

USB_OV _DD

USB_HV _DD

-

---

23

USB2_UDP

USB2_UID

USB2_VBUSCLMP

USB_IBIAS_REXT

I

USB PHY Impedance

Calibration

IO

USB CLK

USB PHY Clock In

IEEE1588

USBCLK

E34

I

OV _DD

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

35

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

TSEC_1588_ALARM_OUT1/ Alarm Out 1

GPIO3_03

K13

O

I

LV _DD

1

TSEC_1588_ALARM_OUT2/ Alarm Out 2

GPIO3_04

J12

LV _DD

TSEC_1588_CLK_IN/

Clock In

A14

F14

M14

L13

N15

N14

GPIO3_00

TSEC_1588_CLK_OUT/

GPIO3_05

Clock Out

Pulse Out 1

Pulse Out 2

Trigger In 1

Trigger In 2

O

I

TSEC_1588_PULSE_OUT1/

GPIO3_06

TSEC_1588_PULSE_OUT2/

GPIO3_07

TSEC_1588_TRIG_IN1/

GPIO3_01

TSEC_1588_TRIG_IN2/

I

GPIO3_02

Ethernet Management Interface 1

EMI1_MDC

EMI1_MDIO

Management Data Clock

Management Data In/Out

G13

H13

O

LV _DD

---

6

IO

Ethernet Management Interface 2

EMI2_MDC

EMI2_MDIO

Management Data Clock (1.2V

open drain)

D13

O

OV _DD

7, 13

Management Data In/Out (1.2V

open drain)

E13

IO

Ethernet Controller 1

EC1_GTX_CLK/GPIO3_13

EC1_GTX_CLK125

Transmit Clock Out

Reference Clock

Receive Data

F12

D12

C12

E12

A12

G12

B12

A13

H12

K12

L12

M12

C13

O

I

LV _DD

1

---

1

EC1_RXD0/GPIO3_19

EC1_RXD1/GPIO3_18

EC1_RXD2/GPIO3_17

EC1_RXD3/GPIO3_16

EC1_RX_CLK/GPIO3_15

EC1_RX_DV/GPIO3_14

EC1_TXD0/GPIO3_11

EC1_TXD1/GPIO3_10

EC1_TXD2/GPIO3_09

EC1_TXD3/GPIO3_08

EC1_TX_EN/GPIO3_12

I

Receive Data

I

1

Receive Data

I

1

Receive Data

I

1

Receive Clock

Receive Data Valid

Transmit Data

Transmit Enable

I

1

I

1

O

1

1, 14

Ethernet Controller 2

EC2_GTX_CLK/GPIO3_25

Transmit Clock Out

Reference Clock

H10

E10

O

I

LV _DD

1

EC2_GTX_CLK125

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

36

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

EC2_RXD0/GPIO3_31

EC2_RXD1/GPIO3_30

EC2_RXD2/GPIO3_29

EC2_RXD3/GPIO3_28

EC2_RX_CLK/GPIO3_27

EC2_RX_DV/GPIO3_26

EC2_TXD0/GPIO3_23

EC2_TXD1/GPIO3_22

EC2_TXD2/GPIO3_21

EC2_TXD3/GPIO3_20

EC2_TX_EN/GPIO3_24

Receive Data

A10

A11

C11

D10

B10

C10

D11

F10

F11

G11

G10

I

LV _DD

1

Receive Data

Receive Clock

Receive Data Valid

Transmit Data

Transmit Enable

LV _DD

1

I

1

I

1

I

1

I

1

O

1

1, 14

DMA

DMA1_DACK0_B/GPIO4_05 DMA1 channel 0 acknowledge

DMA1_DDONE0_B/GPIO4_06 DMA1 channel 0 done

DMA1_DREQ0_B/GPIO4_04 DMA1 channel 0 request

R43

R44

P43

P44

O

I

OV _DD

1

DMA2_DACK0_B/GPIO4_08/ DMA2 channel 0 acknowledge

O

EVT7_B

DMA2_DDONE0_B/

GPIO4_09/EVT8_B

DMA2 channel 0 done

P42

N41

O

I

OV _DD

1

DMA2_DREQ0_B/GPIO4_07 DMA2 channel 0 request

Analog signals

D1_MVREF

SSTL1.35/1.5 Reference

Voltage

V13

I

G1V _DD/2

---

D1_TPA

Reserved for internal use only

AL13

AH13

-

I

-

12

---

D2_MVREF

SSTL1.35/1.5 Reference

Voltage

G2V _DD/2

D2_TPA

Reserved for internal use only

AM13

AD32

-

I

-

12

---

D3_MVREF

SSTL1.35/1.5 Reference

Voltage

G3V _DD/2

D3_TPA

Reserved for internal use only

Thermal diode anode pin

AF32

R32

-

12

FA_ANALOG_G_V

FA_ANALOG_PIN

TD1_ANODE

TD1_CATHODE

TD2_ANODE

TD2_CATHODE

TH_TPA

-

15

T32

-

15

AA34

Y34

Internal Diode

-

19, 24

12

Thermal diode cathode pin

Thermal diode anode pin

AL16

AL17

W32

Thermal diode cathode pin

Thermal Test Point Analog

Power-On-Reset Configuration

cfg_dram_type/IFC_AD21

Power-On-Reset Configuration

Signal

J40

I

OV _DD

1, 4

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

37

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

cfg_gpinput0/IFC_AD00

cfg_gpinput1/IFC_AD01

cfg_gpinput2/IFC_AD02

cfg_gpinput3/IFC_AD03

cfg_gpinput4/IFC_AD04

cfg_gpinput5/IFC_AD05

cfg_gpinput6/IFC_AD06

cfg_gpinput7/IFC_AD07

cfg_ifc_te/IFC_TE

Power-On-Reset Configuration

Signal

W39

W40

V39

V40

U40

U41

T39

T40

G42

R39

R40

P40

P41

N39

N40

M39

M40

E43

G34

I

OV _DD

1, 4

Power-On-Reset Configuration

Signal

OV _DD

1, 4

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

cfg_rcw_src0/IFC_AD08

cfg_rcw_src1/IFC_AD09

cfg_rcw_src2/IFC_AD10

cfg_rcw_src3/IFC_AD11

cfg_rcw_src4/IFC_AD12

cfg_rcw_src5/IFC_AD13

cfg_rcw_src6/IFC_AD14

cfg_rcw_src7/IFC_AD15

cfg_rcw_src8/IFC_CLE

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

Power-On-Reset Configuration

Signal

cfg_xvdd_sel/ASLEEP/

GPIO1_13

Power-On-Reset Configuration

Signal

General Purpose Input/Output

GPIO1_09/IFC_CS4_B

GPIO1_10/IFC_CS5_B

GPIO1_11/IFC_CS6_B

GPIO1_12/IFC_CS7_B

General Purpose Input/Output

C41

B41

A41

C40

IO

OV _DD

---

General Purpose Input/Output

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

38

NXP Semiconductors

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GPIO1_13/ASLEEP/

General Purpose Input/Output

G34

O

OV _DD

1, 4

cfg_xvdd_sel

GPIO1_14/RTC

General Purpose Input/Output

V33

L10

J10

IO

OV _DD

DV _DD

---

GPIO1_15/UART1_SOUT

GPIO1_16/UART2_SOUT

GPIO1_17/UART1_SIN

GPIO1_18/UART2_SIN

M11

J11

GPIO1_19/UART1_RTS_B/

M10

UART3_SOUT

GPIO1_20/UART2_RTS_B/

UART4_SOUT

General Purpose Input/Output

K10

N11

K11

IO

DV _DD

---

GPIO1_21/UART1_CTS_B/

UART3_SIN

GPIO1_22/UART2_CTS_B/

UART4_SIN

GPIO1_23/IRQ03

GPIO1_24/IRQ04

GPIO1_25/IRQ05

GPIO1_26/IRQ06

GPIO1_27/IRQ07

GPIO1_28/IRQ08

GPIO1_29/IRQ09

GPIO1_30/IRQ10

GPIO1_31/IRQ11

General Purpose Input/Output

W42

U44

R42

W41

T42

T44

V42

W44

U42

C35

IO

OV _DD

---

GPIO2_00/SPI_CS0_B/

SDHC_DAT4

GPIO2_01/SPI_CS1_B/

SDHC_DAT5

General Purpose Input/Output

A36

C36

D36

IO

OV _DD

---

GPIO2_02/SPI_CS2_B/

SDHC_DAT6

GPIO2_03/SPI_CS3_B/

SDHC_DAT7

GPIO2_04/SDHC_CMD

GPIO2_05/SDHC_DAT0

GPIO2_06/SDHC_DAT1

GPIO2_07/SDHC_DAT2

GPIO2_08/SDHC_DAT3

GPIO2_09/SDHC_CLK

GPIO2_10/IFC_CS1_B

GPIO2_11/IFC_CS2_B

General Purpose Input/Output

D33

B34

C34

A35

B35

A33

C44

B43

IO

OV _DD

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

39

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GPIO2_12/IFC_CS3_B

GPIO2_13/IFC_PAR0

GPIO2_14/IFC_PAR1

GPIO2_15/IFC_PERR_B

GPIO2_16/IFC_PAR2

GPIO2_17/IFC_PAR3

GPIO2_18/IFC_A26

GPIO2_19/IFC_A27

GPIO2_20/IFC_A28

GPIO2_21/IFC_A29

GPIO2_22/IFC_A30

GPIO2_23/IFC_A31

General Purpose Input/Output

A42

E38

D38

E37

F38

F37

B40

A40

D39

C39

A39

C38

G41

IO

OV _DD

---

OV _DD

---

GPIO2_25/IFC_AD25/

IFC_WP1_B

GPIO2_26/IFC_AD26/

IFC_WP2_B

General Purpose Input/Output

G39

F40

IO

OV _DD

---

GPIO2_27/IFC_AD27/

IFC_WP3_B

GPIO2_28/IFC_AD28

General Purpose Input/Output

E41

E40

IO

OV _DD

---

GPIO2_29/IFC_AD29/

IFC_RB2_B

GPIO2_30/IFC_AD30/

IFC_RB3_B

General Purpose Input/Output

E39

D41

A14

N15

N14

K13

J12

IO

OV _DD

LV _DD

---

GPIO2_31/IFC_AD31/

IFC_RB4_B

GPIO3_00/

TSEC_1588_CLK_IN

GPIO3_01/

TSEC_1588_TRIG_IN1

GPIO3_02/

TSEC_1588_TRIG_IN2

GPIO3_03/

TSEC_1588_ALARM_OUT1

GPIO3_04/

TSEC_1588_ALARM_OUT2

GPIO3_05/

TSEC_1588_CLK_OUT

F14

M14

L13

M12

GPIO3_06/

TSEC_1588_PULSE_OUT1

GPIO3_07/

TSEC_1588_PULSE_OUT2

GPIO3_08/EC1_TXD3

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

40

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GPIO3_09/EC1_TXD2

GPIO3_10/EC1_TXD1

GPIO3_11/EC1_TXD0

GPIO3_12/EC1_TX_EN

GPIO3_13/EC1_GTX_CLK

GPIO3_14/EC1_RX_DV

GPIO3_15/EC1_RX_CLK

GPIO3_16/EC1_RXD3

GPIO3_17/EC1_RXD2

GPIO3_18/EC1_RXD1

GPIO3_19/EC1_RXD0

GPIO3_20/EC2_TXD3

GPIO3_21/EC2_TXD2

GPIO3_22/EC2_TXD1

GPIO3_23/EC2_TXD0

GPIO3_24/EC2_TX_EN

GPIO3_25/EC2_GTX_CLK

GPIO3_26/EC2_RX_DV

GPIO3_27/EC2_RX_CLK

GPIO3_28/EC2_RXD3

GPIO3_29/EC2_RXD2

GPIO3_30/EC2_RXD1

GPIO3_31/EC2_RXD0

GPIO4_00/IIC3_SCL

General Purpose Input/Output

L12

K12

H12

C13

F12

A13

B12

G12

A12

E12

C12

G11

F11

F10

D11

G10

H10

C10

B10

D10

C11

A11

A10

N13

P13

N12

P12

P43

R43

R44

N41

P44

IO

LV _DD

---

LV _DD

DV _DD

OV _DD

GPIO4_01/IIC3_SDA

GPIO4_02/IIC4_SCL/EVT5_B General Purpose Input/Output

GPIO4_03/IIC4_SDA/EVT6_B General Purpose Input/Output

GPIO4_04/DMA1_DREQ0_B General Purpose Input/Output

GPIO4_05/DMA1_DACK0_B General Purpose Input/Output

GPIO4_06/DMA1_DDONE0_B General Purpose Input/Output

GPIO4_07/DMA2_DREQ0_B General Purpose Input/Output

GPIO4_08/DMA2_DACK0_B/ General Purpose Input/Output

EVT7_B

GPIO4_09/

General Purpose Input/Output

P42

IO

OV _DD

---

DMA2_DDONE0_B/EVT8_B

Power and Ground Signals

GND001

GND002

GND

A43

B11

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

41

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND003

GND004

GND005

GND006

GND007

GND008

GND009

GND010

GND011

GND012

GND013

GND014

GND015

GND016

GND017

GND018

GND019

GND020

GND021

GND022

GND023

GND024

GND025

GND026

GND027

GND028

GND029

GND030

GND031

GND032

GND033

GND034

GND035

GND036

GND037

GND038

GND039

GND040

GND

B13

B33

B36

B39

B42

B44

C4

---

C5

C6

C7

C8

C9

D3

D9

D34

D37

D40

D43

E3

E6

E9

E11

F3

F4

F8

F9

F13

F33

F36

F39

F41

G3

G6

G9

G43

H3

H9

H11

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

42

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND041

GND042

GND043

GND044

GND045

GND046

GND047

GND048

GND049

GND050

GND051

GND052

GND053

GND054

GND055

GND056

GND057

GND058

GND059

GND060

GND061

GND062

GND063

GND064

GND065

GND066

GND067

GND068

GND069

GND070

GND071

GND072

GND073

GND074

GND075

GND076

GND077

GND078

GND

H34

H37

H39

J3

---

J5

J7

J9

J13

J41

J44

K3

K6

K9

K33

K36

K43

L3

L6

L9

L11

L39

M3

M6

M9

M13

M34

M41

M44

N3

N6

N9

N37

N43

P3

P6

P9

P11

P14

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

43

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND079

GND080

GND081

GND082

GND083

GND084

GND085

GND086

GND087

GND088

GND089

GND090

GND091

GND092

GND093

GND094

GND095

GND096

GND097

GND098

GND099

GND100

GND101

GND102

GND103

GND104

GND105

GND106

GND107

GND108

GND109

GND110

GND111

GND112

GND113

GND114

GND115

GND116

GND

P15

P16

P33

P39

R3

---

R6

R9

R31

R41

T3

T6

T9

T10

T11

T12

T14

T17

T31

T37

T43

U3

U6

U13

U14

U16

U18

U20

U22

U24

U26

U28

U31

U33

U39

V3

V6

V9

V12

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

44

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND117

GND118

GND119

GND120

GND121

GND122

GND123

GND124

GND125

GND126

GND127

GND128

GND129

GND130

GND131

GND132

GND133

GND134

GND135

GND136

GND137

GND138

GND139

GND140

GND141

GND142

GND143

GND144

GND145

GND146

GND147

GND148

GND149

GND150

GND151

GND152

GND153

GND154

GND

V14

V17

V19

V21

V23

V25

V27

V29

V31

V34

V41

W3

---

W6

W9

W12

W13

W14

W16

W18

W20

W22

W24

W26

W28

W31

W33

W37

W43

Y3

Y6

Y9

Y14

Y17

Y19

Y21

Y23

Y25

Y27

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

45

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND155

GND156

GND157

GND158

GND159

GND160

GND161

GND162

GND163

GND164

GND165

GND166

GND167

GND168

GND169

GND170

GND171

GND172

GND173

GND174

GND175

GND176

GND177

GND178

GND179

GND180

GND181

GND182

GND183

GND184

GND185

GND186

GND187

GND188

GND189

GND190

GND191

GND192

GND

Y29

Y31

---

Y35

Y36

Y37

Y38

Y39

Y40

Y41

Y42

AA3

AA6

AA10

AA11

AA12

AA13

AA14

AA16

AA18

AA20

AA22

AA24

AA26

AA28

AA31

AA35

AA42

AB3

AB4

AB8

AB14

AB17

AB19

AB21

AB23

AB25

AB27

AB29

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

46

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND193

GND194

GND195

GND196

GND197

GND198

GND199

GND200

GND201

GND202

GND203

GND204

GND205

GND206

GND207

GND208

GND209

GND210

GND211

GND212

GND213

GND214

GND215

GND216

GND217

GND218

GND219

GND220

GND221

GND222

GND223

GND224

GND225

GND226

GND227

GND228

GND229

GND230

GND

AB31

AB32

AB33

AB34

AB35

AB42

AC3

---

AC6

AC8

AC14

AC16

AC18

AC20

AC22

AC24

AC26

AC28

AC31

AC33

AC36

AC37

AC38

AC39

AC40

AC41

AC42

AD3

AD5

AD8

AD10

AD11

AD12

AD13

AD14

AD17

AD19

AD21

AD23

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

47

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND231

GND232

GND233

GND234

GND235

GND236

GND237

GND238

GND239

GND240

GND241

GND242

GND243

GND244

GND245

GND246

GND247

GND248

GND249

GND250

GND251

GND252

GND253

GND254

GND255

GND256

GND257

GND258

GND259

GND260

GND261

GND262

GND263

GND264

GND265

GND266

GND267

GND268

GND

AD25

AD27

AD29

AD31

AD33

AD36

AD39

AD42

AE3

---

AE7

AE9

AE14

AE16

AE18

AE20

AE22

AE24

AE26

AE28

AE31

AE33

AE36

AE39

AE42

AF3

AF4

AF5

AF6

AF9

AF14

AF17

AF19

AF21

AF23

AF25

AF27

AF29

AF31

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

48

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND269

GND270

GND271

GND272

GND273

GND274

GND275

GND276

GND277

GND278

GND279

GND280

GND281

GND282

GND283

GND284

GND285

GND286

GND287

GND288

GND289

GND290

GND291

GND292

GND293

GND294

GND295

GND296

GND297

GND298

GND299

GND300

GND301

GND302

GND303

GND304

GND305

GND306

GND

AF33

AF36

AF39

AF42

AG3

---

AG8

AG11

AG12

AG13

AG14

AG16

AG18

AG20

AG22

AG24

AG26

AG28

AG31

AG33

AG36

AG39

AG42

AH3

AH9

AH12

AH14

AH17

AH19

AH21

AH23

AH25

AH27

AH29

AH31

AH33

AH36

AH39

AH42

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

49

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND307

GND308

GND309

GND310

GND311

GND312

GND313

GND314

GND315

GND316

GND317

GND318

GND319

GND320

GND321

GND322

GND323

GND324

GND325

GND326

GND327

GND328

GND329

GND330

GND331

GND332

GND333

GND334

GND335

GND336

GND337

GND338

GND339

GND340

GND341

GND342

GND343

GND344

GND

AJ3

AJ4

---

AJ5

AJ6

AJ7

AJ8

AJ9

AJ10

AJ11

AJ12

AJ14

AJ16

AJ18

AJ20

AJ30

AJ31

AJ34

AJ35

AJ36

AJ39

AJ42

AK3

AK6

AK9

AK12

AK13

AK15

AK17

AK19

AK33

AK36

AK37

AK38

AK39

AK40

AK41

AK42

AL3

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

50

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND345

GND346

GND347

GND348

GND349

GND350

GND351

GND352

GND353

GND354

GND355

GND356

GND357

GND358

GND359

GND360

GND361

GND362

GND363

GND364

GND365

GND366

GND367

GND368

GND369

GND370

GND371

GND372

GND373

GND374

GND375

GND376

GND377

GND378

GND379

GND380

GND381

GND382

GND

AL6

AL9

---

AL12

AL33

AL34

AL39

AL42

AM3

AM6

AM9

AM12

AM33

AM36

AM39

AM42

AN3

AN6

AN9

AN12

AN34

AN35

AN36

AN39

AN42

AP3

AP6

AP9

AP12

AP14

AP15

AP16

AP37

AP39

AP42

AR3

AR6

AR9

AR12

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

51

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND383

GND384

GND385

GND386

GND387

GND388

GND389

GND390

GND391

GND392

GND393

GND394

GND395

GND396

GND397

GND398

GND399

GND400

GND401

GND402

GND403

GND404

GND405

GND406

GND407

GND408

GND409

GND410

GND411

GND412

GND413

GND414

GND415

GND416

GND417

GND418

GND419

GND420

GND

AR39

AR42

AT3

---

AT4

AT5

AT6

AT7

AT8

AT9

AT10

AT11

AT12

AT13

AT14

AT15

AT16

AT34

AT35

AT36

AT39

AT42

AU3

AU10

AU37

AU39

AU41

AU42

AV3

AV10

AV38

AV42

AW3

AW4

AW5

AW6

AW7

AW8

AW9

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

52

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

GND421

GND422

GND423

GND424

GND425

GND426

GND427

GND428

GND429

GND430

GND431

GND432

GND433

GND434

GND435

GND436

GND437

GND438

GND439

GND440

GND441

GND442

GND443

GND444

GND445

GND446

GND447

GND448

GND449

GND450

GND451

GND452

GND453

GND454

GND455

GND456

GND457

GND458

GND

AW10

AW11

AW12

AW13

AW14

AW15

AW16

AW35

AW36

AW38

AW40

AW42

AY3

---

AY10

AY38

AY42

BA3

BA10

BA34

BA38

BA42

BB4

BB5

BB6

BB7

BB8

BB9

BB10

BB11

BB12

BB13

BB14

BB15

BB16

BB35

BB36

BB37

BB38

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

53

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

GND459

GND

BB39

BB40

BB41

C3

---

GND460

---

GND461

GND_DET1

GND_DET2

GND_DET3

USB_AGND1

USB_AGND2

USB_AGND3

USB_AGND4

USB_AGND5

X1GND01

X1GND02

X1GND03

X1GND04

X1GND05

X1GND06

X1GND07

X1GND08

X1GND09

X1GND10

X1GND11

X1GND12

X1GND13

X1GND14

X1GND15

X1GND16

X1GND17

X1GND18

X1GND19

X1GND20

X1GND21

X1GND22

X1GND23

X1GND24

X2GND01

X2GND02

X2GND03

BB3

BB42

D32

J32

USB PHY 1 Transceiver GND

Serdes 1 Transceiver GND

Serdes 2 Transceiver GND

L31

M32

N30

F15

F17

F19

F21

G14

G15

G17

G19

G21

H14

H16

H18

H20

H22

J14

J16

J18

J20

J22

K14

L15

L19

M17

M21

E31

F23

F25

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

54

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

X2GND04

X2GND05

X2GND06

X2GND07

X2GND08

X2GND09

X2GND10

X2GND11

X2GND12

X2GND13

X2GND14

X2GND15

X2GND16

X2GND17

X2GND18

X2GND19

X2GND20

X2GND21

X2GND22

X2GND23

X2GND24

X2GND25

X3GND01

X3GND02

X3GND03

X3GND04

X3GND05

X3GND06

X3GND07

X3GND08

X3GND09

X3GND10

X3GND11

X3GND12

X3GND13

X3GND14

X3GND15

X3GND16

Serdes 2 Transceiver GND

Serdes 3 Transceiver GND

F27

F29

---

F31

G23

G25

G27

G29

G31

H24

H26

H28

H30

H31

J24

J26

J28

J30

L26

L30

M24

M28

N29

AN20

AN24

AP18

AP22

AR17

AT17

AT19

AT21

AT23

AT25

AU17

AU19

AU21

AU23

AU25

AV17

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

55

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

X3GND17

X3GND18

X3GND19

X3GND20

X3GND21

X3GND22

X3GND23

X3GND24

X4GND01

X4GND02

X4GND03

X4GND04

X4GND05

X4GND06

X4GND07

X4GND08

X4GND09

X4GND10

X4GND11

X4GND12

X4GND13

X4GND14

X4GND15

X4GND16

X4GND17

X4GND18

X4GND19

X4GND20

X4GND21

X4GND22

X4GND23

X4GND24

X4GND25

S1GND01

S1GND02

S1GND03

S1GND04

S1GND05

Serdes 3 Transceiver GND

Serdes 4 Transceiver GND

Serdes 1 core logic GND

AV18

AV20

AV22

AV24

AW18

AW20

AW22

AW24

AM32

AN27

AN31

AP29

AP33

AT27

AT29

AT31

AT33

AU27

AU29

AU31

AU33

AU34

AV26

AV28

AV30

AV32

AV34

AW26

AW28

AW30

AW32

AW34

AY34

A15

---

A17

A19

A21

B14

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

56

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

S1GND06

S1GND07

S1GND08

S1GND09

S1GND10

S1GND11

S1GND12

S1GND13

S1GND14

S1GND15

S1GND16

S1GND17

S1GND18

S1GND19

S1GND20

S1GND21

S1GND22

S1GND23

S1GND24

S1GND25

S1GND26

S1GND27

S1GND28

S1GND29

S1GND30

S1GND31

S1GND32

S1GND33

S1GND34

S1GND35

S1GND36

S1GND37

S1GND38

S1GND39

S1GND40

S1GND41

S2GND01

S2GND02

Serdes 1 core logic GND

Serdes 2 core logic GND

B15

B17

B19

B21

C14

C16

C18

C20

C22

D14

D16

D18

D20

D22

E14

E15

E16

E17

E18

E19

E20

E21

E22

M15

M19

N16

N18

N19

N20

N22

P17

R18

R19

R20

R21

R22

A23

A25

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

57

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

S2GND03

S2GND04

S2GND05

S2GND06

S2GND07

S2GND08

S2GND09

S2GND10

S2GND11

S2GND12

S2GND13

S2GND14

S2GND15

S2GND16

S2GND17

S2GND18

S2GND19

S2GND20

S2GND21

S2GND22

S2GND23

S2GND24

S2GND25

S2GND26

S2GND27

S2GND28

S2GND29

S2GND30

S2GND31

S2GND32

S2GND33

S2GND34

S2GND35

S2GND36

S2GND37

S2GND38

S2GND39

S3GND01

Serdes 2 core logic GND

Serdes 3 core logic GND

A27

A29

A31

B23

B25

B27

B29

B31

C24

C26

C28

C30

C31

D24

D26

D28

D30

E23

E24

E25

E26

E27

E28

E29

E30

M26

N23

N25

N26

N27

N28

P28

R23

R24

R25

R26

R27

AK21

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

58

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

S3GND02

S3GND03

S3GND04

S3GND05

S3GND06

S3GND07

S3GND08

S3GND09

S3GND10

S3GND11

S3GND12

S3GND13

S3GND14

S3GND15

S3GND16

S3GND17

S3GND18

S3GND19

S3GND20

S3GND21

S3GND22

S3GND23

S3GND24

S3GND25

S3GND26

S3GND27

S3GND28

S3GND29

S3GND30

S3GND31

S3GND32

S3GND33

S3GND34

S3GND35

S3GND36

S3GND37

S3GND38

S3GND39

Serdes 3 core logic GND

AK22

AK23

AK24

AK25

AL20

AM19

AM21

AM22

AM23

AM25

AN18

AN22

AY17

AY18

AY19

AY20

AY21

AY22

AY23

AY24

AY25

BA17

BA19

BA21

BA23

BA25

BB17

BB19

BB21

BB23

BB25

BC17

BC18

BC20

BC22

BC24

BD18

BD20

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

59

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

S3GND40

S3GND41

S4GND01

S4GND02

S4GND03

S4GND04

S4GND05

S4GND06

S4GND07

S4GND08

S4GND09

S4GND10

S4GND11

S4GND12

S4GND13

S4GND14

S4GND15

S4GND16

S4GND17

S4GND18

S4GND19

S4GND20

S4GND21

S4GND22

S4GND23

S4GND24

S4GND25

S4GND26

S4GND27

S4GND28

S4GND29

S4GND30

S4GND31

S4GND32

S4GND33

S4GND34

S4GND35

S4GND36

Serdes 3 core logic GND

Serdes 4 core logic GND

BD22

BD24

AK26

AK27

AK28

AK29

AK30

AL31

AM26

AM28

AM29

AM30

AM31

AN29

AY26

AY27

AY28

AY29

AY30

AY31

AY32

AY33

BA27

BA29

BA31

BA33

BB27

BB29

BB31

BB33

BB34

BC26

BC28

BC30

BC32

BC34

BD26

BD28

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

60

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

S4GND37

S4GND38

S4GND39

Serdes 4 core logic GND

Serdes1 PLL 1 GND

Serdes1 PLL 2 GND

Serdes2 PLL 1 GND

Serdes2 PLL 2 GND

Serdes3 PLL 1 GND

Serdes3 PLL 2 GND

Serdes4 PLL 1 GND

Serdes4 PLL 2 GND

GND Sense pin

BD30

BD32

BD34

L18

L20

L25

L27

AP21

AP23

AP28

AP30

R13

AM17

AA33

AA32

R30

T30

U30

V30

W30

Y30

AA30

AK14

R14

R15

A2

---

AGND_SD1_PLL1

AGND_SD1_PLL2

AGND_SD2_PLL1

AGND_SD2_PLL2

AGND_SD3_PLL1

AGND_SD3_PLL2

AGND_SD4_PLL1

AGND_SD4_PLL2

SENSEGND_CA

SENSEGND_CB

SENSEGND_CC

SENSEGND_PL

OVDD1

GND Sense pin

General I/O supply

UART/I2C supply

OV _DD

OVDD2

OV _DD

OVDD3

OV _DD

OVDD4

OV _DD

OVDD5

OV _DD

OVDD6

OV _DD

OVDD7

OV _DD

OVDD8

OV _DD

DVDD1

DV _DD

DVDD2

UART/I2C supply

DV _DD

G1VDD01

DDR supply for port 1

G1V _DD

G1VDD02

A6

G1VDD03

A9

G1VDD04

B1

G1VDD05

B4

G1VDD06

B9

G1VDD07

D2

G1VDD08

F1

G1VDD09

H2

G1VDD10

K1

G1VDD11

M2

G1VDD12

P1

G1VDD13

T2

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

61

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

G1VDD14

G1VDD15

G1VDD16

G1VDD17

G1VDD18

G1VDD19

G1VDD20

G1VDD21

G1VDD22

G1VDD23

G1VDD24

G1VDD25

G1VDD26

G2VDD01

G2VDD02

G2VDD03

G2VDD04

G2VDD05

G2VDD06

G2VDD07

G2VDD08

G2VDD09

G2VDD10

G2VDD11

G2VDD12

G2VDD13

G2VDD14

G2VDD15

G2VDD16

G2VDD17

G2VDD18

G2VDD19

G2VDD20

G2VDD21

G2VDD22

G2VDD23

G2VDD24

G2VDD25

DDR supply for port 1

DDR supply for port 2

T15

U15

---

G1V _DD

---

G1V _DD

G2V _DD

---

V1

V15

W15

Y2

Y15

AA15

AB1

AB15

AD2

AF1

AF2

AC15

AD15

AE15

AF15

AG1

AG15

AH15

AJ2

AJ15

AL1

AN2

AR1

AU2

AW1

BA2

BC1

BC4

BC8

BC12

BC16

BD2

BD6

BD10

BD14

BD17

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

62

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

G3VDD01

G3VDD02

G3VDD03

G3VDD04

G3VDD05

G3VDD06

G3VDD07

G3VDD08

G3VDD09

G3VDD10

G3VDD11

G3VDD12

G3VDD13

G3VDD14

G3VDD15

G3VDD16

G3VDD17

G3VDD18

G3VDD19

G3VDD20

G3VDD21

G3VDD22

G3VDD23

G3VDD24

G3VDD25

G3VDD26

S1VDD1

DDR supply for port 3

SerDes1 core logic supply

SerDes2 core logic supply

Y43

Y44

---

G3V _DD

---

G3V _DD

S1V _DD

S2V _DD

AB30

AB43

AC30

AD30

AD44

AE30

AF30

AF43

AG30

AH30

AH44

AK43

AM44

AP43

AT44

AV43

AY44

BB43

BC37

BC41

BC44

BD35

BD39

BD43

N17

S1VDD2

P20

S1VDD3

P22

S1VDD4

T19

S1VDD5

T20

S1VDD6

T21

S1VDD7

T22

S2VDD1

P23

S2VDD2

P25

S2VDD3

T23

S2VDD4

T24

S2VDD5

T25

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

63

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

S2VDD6

S3VDD1

S3VDD2

S3VDD3

S3VDD4

S3VDD5

S3VDD6

S3VDD7

S4VDD1

S4VDD2

S4VDD3

S4VDD4

S4VDD5

S4VDD6

X1VDD1

X1VDD2

X1VDD3

X1VDD4

X1VDD5

X1VDD6

X1VDD7

X1VDD8

X2VDD1

X2VDD2

X2VDD3

X2VDD4

X2VDD5

X2VDD6

X2VDD7

X2VDD8

X2VDD9

X3VDD1

X3VDD2

X3VDD3

X3VDD4

X3VDD5

X3VDD6

X3VDD7

SerDes2 core logic supply

SerDes3 core logic supply

SerDes4 core logic supply

SerDes1 transceiver supply

SerDes2 transceiver supply

SerDes3 transceiver supply

T26

AJ22

AJ23

AJ24

AJ25

AL23

AL25

AM20

AJ26

AJ27

AJ28

AJ29

AL26

AL28

K15

---

S2V _DD

---

S3V _DD

S4V _DD

X1V _DD

X2V _DD

X3V _DD

---

K16

K17

K18

K19

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29

K30

M30

AR18

AR19

AR20

AR21

AR22

AR23

AR24

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

64

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

X3VDD8

X4VDD1

X4VDD2

X4VDD3

X4VDD4

X4VDD5

X4VDD6

X4VDD7

X4VDD8

X4VDD9

LVDD1

SerDes3 transceiver supply

SerDes4 transceiver supply

AR25

AN33

AR26

AR27

AR28

AR29

AR30

AR31

AR32

AR33

L14

---

X3V _DD

---

X4V _DD

LV _DD

Ethernet controller and GPIO

supply

LVDD2

LVDD3

Ethernet controller and GPIO

supply

R16

R17

---

LV _DD

---

Ethernet controller and GPIO

supply

FA_VL

Reserved for internal use only

R33

T29

R29

---

FA_VL

15

---

PROG_MTR

PROG_SFP

PROG_MTR

PROG_SFP

SFP Fuse Programming

Override supply

TH_VDD

VDD01

VDD02

VDD03

VDD04

VDD05

VDD06

VDD07

VDD08

VDD09

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17

VDD18

Thermal Monitor Unit supply

Supply for cores and platform

V32

T16

U17

U19

U21

U23

U25

U27

U29

V16

V18

V20

V22

V24

V26

V28

W17

W19

W21

---

TH_V _DD

V _DD

27

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

65

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

VDD19

VDD20

VDD21

VDD22

VDD23

VDD24

VDD25

VDD26

VDD27

VDD28

VDD29

VDD30

VDD31

VDD32

VDD33

VDD34

VDD35

VDD36

VDD37

VDD38

VDD39

VDD40

VDD41

VDD42

VDD43

VDD44

VDD45

VDD46

VDD47

VDD48

VDD49

VDD50

VDD51

VDD52

VDD53

VDD54

VDD55

VDD56

Supply for cores and platform

W23

W25

---

V _DD

---

V _DD

---

W27

W29

Y16

Y18

Y20

Y22

Y24

Y26

Y28

AA17

AA19

AA21

AA23

AA25

AA27

AA29

AB16

AB18

AB20

AB22

AB24

AB26

AB28

AC17

AC19

AC21

AC23

AC25

AC27

AC29

AD16

AD18

AD20

AD22

AD24

AD26

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

66

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

VDD57

VDD58

VDD59

VDD60

VDD61

VDD62

VDD63

VDD64

VDD65

VDD66

VDD67

VDD68

VDD69

VDD70

VDD71

VDD72

VDD73

VDD74

VDD75

VDD76

VDD77

VDD78

VDD79

VDD80

VDD81

VDD82

VDD83

VDD84

VDD85

VDD86

VDD87

VDD88

VDD89

VDD90

VDD91

VDD_LP

Supply for cores and platform

AD28

AE17

AE19

AE21

AE23

AE25

AE27

AE29

AF16

AF18

AF20

AF22

AF24

AF26

AF28

AG17

AG19

AG21

AG23

AG25

AG27

AG29

AH16

AH18

AH20

AH22

AH24

AH26

AH28

AJ17

AJ19

AJ21

AK16

AK18

AK20

R28

---

V _DD

---

V _DD

V _DD_LP

Low Power Security Monitor

supply

AVDD_CGA1

e6500 Cluster Group A PLL1

supply

AP13

---

AVDD_CGA1

---

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

67

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

AVDD_CGA2

AVDD_CGA3

AVDD_CGB1

AVDD_CGB2

e6500 Cluster Group A PLL2

supply

AR13

AR14

AR16

AR15

---

AVDD_CGA2

---

e6500 Cluster Group A PLL3

supply

---

AVDD_CGA3

AVDD_CGB1

AVDD_CGB2

---

e6500 Cluster Group B PLL1

supply

e6500 Cluster Group B PLL2

supply

AVDD_PLAT

Platform PLL supply

DDR1 PLL supply

T28

T13

---

AVDD_PLAT

---

AVDD_D1

AVDD_D2

DDR2 PLL supply

AJ13

AC32

L17

AVDD_D2

AVDD_D3

DDR3 PLL supply

AVDD_D3

AVDD_SD1_PLL1

AVDD_SD1_PLL2

AVDD_SD2_PLL1

AVDD_SD2_PLL2

AVDD_SD3_PLL1

AVDD_SD3_PLL2

AVDD_SD4_PLL1

AVDD_SD4_PLL2

SENSEVDD_CA

SerDes1 PLL 1 supply

SerDes1 PLL 2 supply

SerDes2 PLL 1 supply

SerDes2 PLL 2 supply

SerDes3 PLL 1 supply

SerDes3 PLL 2 supply

SerDes4 PLL 1 supply

SerDes4 PLL 2 supply

AVDD_SD1_PLL1

AVDD_SD1_PLL2

AVDD_SD2_PLL1

AVDD_SD2_PLL2

AVDD_SD3_PLL1

AVDD_SD3_PLL2

AVDD_SD4_PLL1

AVDD_SD4_PLL2

SENSEVDD_CA

L21

L24

L28

AP20

AP24

AP27

AP31

R12

Vdd Sense pin for core cluster

A

SENSEVDD_CB

SENSEVDD_CC

Vdd Sense pin for core cluster

B

AM16

Y33

---

SENSEVDD_CB

SENSEVDD_CC

---

Vdd Sense pin for core cluster

C

SENSEVDD_PL

USB_HVDD1

Vdd Sense pin for platform

Y32

K32

---

SENSEVDD_PL

USB_HV _DD

---

USB PHY Transceiver 3.3V

Supply

USB_HVDD2

USB_OVDD1

USB_OVDD2

USB PHY Transceiver 3.3V

Supply

N32

P31

P32

---

USB_HV _DD

USB_OV _DD

---

USB PHY Transceiver 1.8V

Supply

USB PHY Transceiver 1.8V

Supply

USB_SVDD1

USB_SVDD2

USB PHY Analog 1.0V Supply

P29

P30

---

USB_SV _DD

---

No Connection Pins

NC01

NC02

NC03

No Connection

G35

G36

G37

---

12

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

68

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

NC04

NC05

NC06

NC07

NC08

NC09

NC10

NC11

NC12

NC13

NC14

NC15

NC16

NC17

NC18

NC19

NC20

NC21

NC22

NC23

NC24

NC25

NC26

NC27

NC28

NC29

NC30

NC31

NC32

NC33

NC34

NC35

NC36

NC37

NC38

NC39

NC40

NC41

No Connection

G38

H33

H35

H36

H38

J33

---

12

No Connection

---

J34

J35

J36

J37

J38

K34

K35

K37

K38

L33

L34

L35

L36

L37

L38

M33

M35

M36

M37

M38

N33

N34

N35

N36

N38

P34

P35

P36

P37

P38

R34

R35

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

69

Pin assignments

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

type

Power supply

Notes

number

NC42

NC43

NC44

NC45

NC46

NC47

NC48

NC49

NC50

NC51

NC52

NC53

NC54

NC55

NC56

NC57

NC58

NC59

NC60

NC61

NC62

NC63

NC64

NC65

NC66

NC67

NC68

NC69

NC70

NC71

NC72

NC73

NC74

NC75

NC76

NC77

NC78

NC79

No Connection

R36

R37

---

12

No Connection

---

12

R38

T18

T33

T34

T35

T36

T38

U32

U35

U36

U37

U38

V35

V36

V37

V38

W34

W35

W36

W38

AE32

AG32

AH32

AJ32

AJ33

AK31

AK32

AL15

AL18

AL19

AL32

AM14

AM15

AM18

AN13

AN14

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

70

NXP Semiconductors

Pin assignments

Notes

Table 1. Pinout list by bus (continued)

Signal

Signal description

Package

Power supply

type

number

NC80

NC81

NC82

NC83

NC84

NC_DET

No Connection

AN15

AN16

AN17

AP17

AW17

C42

---

12

No Connection

---

1. Functionally, this pin is an output or an input, but structurally it is an I/O because it

either samples configuration input during reset, is a muxed pin, or has other

manufacturing test functions. This pin will therefore be described as an I/O for boundary

scan.

2. This output is actively driven during reset rather than being tri-stated during reset.

3. MDIC[0] is grounded through an 237 Ω (for Rev. 1) or 187 Ω (for Rev. 2) precision

1% resistor and MDIC[1] is connected to GV _DDthrough an 237 Ω (for Rev. 1) or 187 Ω

(for Rev. 2) precision 1% resistor. For either full or half driver strength calibration of

DDR I/Os, use the same MDIC resistor value of 237 Ω (for Rev. 1) or 187 Ω (for Rev. 2).

Memory controller register setting can be used to determine automatic calibration is done

to full or half drive strength. These pins are used for automatic calibration of the DDR3/

DDR3L IOs. The MDIC[0:1] pins must be connected to 237 Ω (for Rev. 1) or 187 Ω (for

Rev. 2) precision 1% resistors.

4. This pin is a reset configuration pin. It has a weak (~20 kΩ) internal pull-up P-FET that

is enabled only when the processor is in its reset state. This pull-up is designed such that

it can be overpowered by an external 4.7 kΩ resistor. However, if the signal is intended to

be high after reset, and if there is any device on the net that might pull down the value of

the net at reset, a pull-up or active driver is needed.

5. Pin must NOT be pulled down during power-on reset. This pin may be pulled up,

driven high, or if there are any externally connected devices, left in tristate. If this pin is

connected to a device that pulls down during reset, an external pull-up is required to drive

this pin to a safe state during reset.

6. Recommend that a weak pull-up resistor (2 to 10 kΩ) be placed on this pin to the

respective power supply, or appropriate pull up resistor value for signals like HRESET_B

which might require 1 kΩ.

7. This pin is an open-drain signal.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

71

Pin assignments

8. Recommend a pull-up resistor be placed on this pin to the respective power supply. In

the I2C interface, the value of the resistor should be calculated such that maximum rise

time stays under 300 ns as well as VOL be under 0.4 V at IOL = 3 mA IOL and I2C load

capacitance which should not exceed 400 pF.

9. This pin has a weak (~20 kΩ) internal pull-up P-FET that is always enabled.

10. These are test signals for factory use only and must be pulled up (100 Ω to 1 kΩ) to

the respective power supply for normal operation.

11. This pin requires a 200 Ω pull-up to respective power supply.

12. Do not connect. These pins should be left floating.

13. These pins must be pulled up to 1.2 V through a 180 Ω 1% resistor for MDC and a

330 Ω 1% resistor for MDIO.

14. This pin requires an external 1 kΩ pull-down resistor to prevent PHY from seeing a

valid Transmit Enable before it is actively driven.

15. These pins must be pulled to ground (GND).

16. This pin requires a 698 Ω pull-up to respective power supply.

18. Recommend that a weak pull-up resistor (4.7 kΩ) be placed on this pin to the

respective power supply.

19. These pins should be tied to ground if the diode is not utilized for temperature

monitoring.

20. This pin requires a pull-up of 10 to 50 kΩ to its corresponding I/O supply if it is not a

GPIO or not used as one.

21. This pin always needs to be either pulled up by 10 to 50 kΩ or down by 4.7 kΩ to

GND, depending on the intended RCW setting to be high or low, respectively.

22. If used as SDHC signal, pull-up 10 to 100 kΩ to the respective I/O supply.

23. New board designs should leave a place holder for a series resistor and capacitor

filter, which is in parallel and very close proximity to a 1%, 10 kΩ resistor pulling

USB_IBIAS_REXT low. This allows the flexibility of populating them if needed to

avoid board coupled noise to this pin. An SMD ceramic 100 nF low ESL in series with

100 Ω SMD resistor will do the filtration needed with slight variations that suit each

board case.

24. The non-ideality factor over temperature range 85C⁰ to 105C⁰, n = 1.006 0.003,

with approximate error +/- 1 C⁰ and approximate error under +/- 3 C⁰ for temperature

range 0 C⁰ to 85C⁰.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

72

NXP Semiconductors

Electrical characteristics

25. In GPCM mode, this pin also serves as IFC_WE1_B.

26. T4240/T4160/T4080 Rev. 2 silicon requires SDHC_CD_B and SDHC_WP signals

even when eMMC/eSDHC is used.

27. TH_VDD is a quiet power domain used for the Thermal Unit. Despite being de-

featured, it should be connected to a quiet recommended supply level.

28. When Dn_MDQS_B[9:17] pins are not used; terminate with 50 Ω to VTT or 100 Ω to

GND. Place termination close to T4 pin when discrete x8 or x16 DRAM is used or close

to the DIMM connector when signals are connected to DIMM connector to be used only

by DIMMs with x8 or x16 DRAM.

29. For T4160, this pin may be left floating or pulled up. For T4080, this pin must be

pulled to ground. Pull with a 4.7 k resistor.

Warning

See "Connection Recommendations" for additional details on

properly connecting these pins for specific applications.

3 Electrical characteristics

This section provides the AC and DC electrical specifications for the chip. The chip is

currently targeted to these specifications, some of which are independent of the I/O cell

but are included for a more complete reference. These are not purely I/O buffer design

specifications.

3.1 Overall DC electrical characteristics

This section describes the ratings, conditions, and other characteristics.

3.1.1 Absolute maximum ratings

This table provides the absolute maximum ratings.

Table 2. Absolute maximum ratings¹

Absolute Maximum Ratings for Supply Voltage Levels

Characteristic

Symbol

Min

Max

Unit

Notes

9, 11

Core and platform

supply voltage

V_DD

-0.3

1.08

V

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

73

Electrical characteristics

Table 2. Absolute maximum ratings¹(continued)

PLL supply voltage

(core, platform, DDR)

AV_DD_CGAn

-0.3

1.98

V

11

AV_DD_CGBn

AV_DD_PLAT

AV_DD_Dn

PLL supply voltage

(SerDes, filtered from

AV_DD_SDn_PLLn

-0.3

1.65

1.48

XnV_DD

)

Fuse programming

override supply

PROG_SFP

TH_V_DD

OV_DD

-0.3

1.98

V

11

Thermal monitor unit

supply

10, 11

11

eSHDC, eSPI, DMA,

MPIC, GPIO, system

control and power

management, clocking,

debug, IFC, DDRCLK

supply, and JTAG I/O

voltage

DUART, I²C I/O voltage DV_DD

-0.3

2.75

1.98

1.58

V

11

DDR3 DRAM I/O

voltage

GnV_DD

V

11

DDR3L DRAM I/O

voltage

-0.3

1.42

1.08

Main power supply for SnV_DD

internal circuitry of

SerDes and pad power

supply for SerDes

receivers

Pad power supply for

SerDes transmitter

XnV_DD

LV_DD

-0.3

1.65

1.45

2.75

1.98

V

8, 11

11

Ethernet, Ethernet

management interface

1 (EMI1) 1588, GPIO

I/O voltage

Ethernet management

interface 2 (EMI2) I/O

voltage

—

-0.3

1.32

V

7, 11

USB PHY Transceiver USB_HV_DD

-0.3

3.63

1.98

1.08

V

11

supply voltage

USB_OV_DD

USB PHY Analog

supply voltage

USB_SV_DD

V_{DD_LP}

Low Power Security

Monitor supply

-0.3

1.08

V

11

Absolute Maximum Ratings for Storage Temperature Conditions

Characteristic

Symbol

Min

Max

Unit

Notes

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

74

NXP Semiconductors

Electrical characteristics

Table 2. Absolute maximum ratings¹(continued)

Storage temperature

range

T_STG

-55

155

°C

—

Absolute Maximum Ratings for Input Signal Voltage Levels

Symbol Min_DCV Max_DCV Min Max

Interface Input Signal

Unit

Notes

Undersho Overshoot

ot Voltage Voltage

V_input

GND

V_input

DDR3 and DDR3L

DRAM signals

MV_IN

Nominal

-0.3

Nominal

GV_DDx 1.1

V

2, 13

5

GV_DD

1.05

x

DDR3 and DDR3L

DRAM reference

D_n_MV_REF

GND

Nominal

GV_DD/2 x

1.05

Nominal

GV_DD/2 x

1.1

Ethernet (except EMI2), LV_IN

1588, GPIO signals

Nominal

LV_DDx 1.1

Nominal

4, 5

3, 5

LV_DD

1.15

x

eSHDC, eSPI, DMA,

MPIC, GPIO, system

control and power

management, clocking,

debug, IFC, DDRCLK

supply, and JTAG

signals

OV_IN

Nominal

OV_DDx 1.1

OV_DD

1.15

x

DUART, I²C signals

DV_IN

GND

Nominal

DV_DDx 1.1

-0.3

0.3

Nominal

V

5, 6

5

DV_DD

1.15

x

SerDes

signals

No internal SV_IN

termination

0.8 V

maximum

signal

S_nGND

Nominal

SnV_DD

1.05

x

SnV_DD

1.1

x

selected

swing

starting

from 0.3 V

0.8 V

maximum

signal

swing

starting

from -0.4 V

S_nGND

Nominal

-0.4

+0.4

SnV_DD

1.05

x

50 Ω

SV_IN

+0.3

internal

termination

selected

USB PHY Transceiver USB_HV_IN

signals

USB_AGN USB_HV_DD-0.3

+ 0.3

USB_HV_DD

+ 0.3

V

5, 12

—

D

USB_OV_IN

USB_AGN USB_OV_D-0.3

USB_OV_D

_Dx 1.15

D

_Dx 1.1

Ethernet management

interface 2 signals

—

GND

1.2 x 1.1

-0.3

1.2 x 1.15

LP Trust signal

V_{IN_LP}

GND

1.05 x

1.1 x

—

LP_TMP_DETECT_B

V_{DD_LP}

Notes:

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

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75

Electrical characteristics

Table 2. Absolute maximum ratings¹

1. Functional operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional

operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent

damage to the device.

2. Caution: MV_INmust not exceed GV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

3. Caution: OV_INmust not exceed OV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

4. Caution:LV_INmust not exceed LV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

5. (G,O,L,D,S, USB_H, USB_O)V_INmay overshoot/undershoot to a voltage and for a maximum duration as shown in Figure

7. Note that the Dn_MV_REFmaximum slew rate is restricted to 25 kv/s.

6. Caution: DV_INmust not exceed DV_DDby more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during

power-on reset and power-down sequences.

7. Ethernet MII management interface 2 pins function as open drain I/Os. The interface shall conform to 1.2 V nominal

voltage levels.

8. The cfg_xvdd_sel (ASLEEP) reset configuration pin must select the correct XV_DDvoltage.

9. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the

sense pin. For additional information, see the "Ganged sense-line implementation example" section in the T4240 QorIQ

Integrated Processor Design Checklist (AN4559). See also note 6 in Table 3.

10. Thermal monitoring unit is de featured on current silicon, but TH_V_DDshould be biased always.

11. Exposing device to Absolute Maximum Ratings conditions for long periods of time may affect reliability or cause

permanent damage.

12. USB Overshoot or Undershoot signal time should be under 10% of signal rise time or under 2 nSec.

13. Typical DDR interface uses ODT enabled mode. For test purposes with ODT off mode, simulation should be done first so

as to make sure that the overshoot signal level at the input pin does not exceed GV_DDby more than 10%. The Overshoot/

Undershoot period should comply with JEDEC standards.

3.1.2 Recommended operating conditions

This table provides the recommended operating conditions for this chip.

NOTE

The values shown are the recommended operating conditions

and proper device operation outside these conditions is not

guaranteed.

Table 3. Recommended operating conditions

Characteristic

Core and platform supply voltage At initial start-up

During normal operation

Symbol

Recommended

Value

Unit Notes

V_DD

( VID or 1.025 V)

30 mV

V

4, 5, 6,

7, 9

VID 30 mV

Table continues on the next page...

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Electrical characteristics

Table 3. Recommended operating conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit Notes

V 11

PLL supply voltage (core, platform, DDR)

AV_DD_CGAn

AV_DD_CGBn

AV_DD_PLAT

AV_DD_Dn

1.8 V 90 mV

PLL supply voltage (SerDes, filtered from XnV_DD

)

AV_DD_SDn_PLLn 1.5 V 75 mV or

1.35 V 67 mV

V

-

Fuse programming override supply

Thermal monitor unit supply

PROG_SFP

TH_V_DD

OV_DD

1.8 V 90 mV

V

2

8

-

eSHDC, eSPI, DMA, MPIC, GPIO, system control and power

management, clocking, debug, IFC, DDRCLK supply, and JTAG

I/O voltage

DUART, I²C I/O voltage

DV_DD

2.5 V 125 mV

1.8 V 90 mV

1.5 V 75 mV

1.35 V 67 mV

1.0 V 50 mV

V

-

DDR DRAM I/O voltage

DDR3

GnV_DD

DDR3L

Main power supply for internal circuitry of SerDes and pad power

supply for SerDes receivers

SnV_DD

XnV_DD

V

-

Pad power supply for SerDes transmitters

1.5 V 75 mV

1.35 V 67 mV

2.5 V 125 mV

1.8 V 90 mV

1.2 V 60 mV

3.3 V 165 mV

1.8 V 90 mV

Ethernet, Ethernet management interface 1 (EMI1), 1588, GPIO

I/O voltage

LV_DD

V

1

Ethernet management interface 2 (EMI2) I/O voltage

USB PHY Transceiver supply voltage

-

V

10

USB_HV_DD

USB_OV_DD

USB_SV_DD

-

USB PHY Analog supply voltage

At initial start-up

( VID or 1.025 V )

30 mV

6,7,9

During normal operation

VID 30 mV

1.0 V 50 mV

GND to GV_DD

Low Power Security Monitor supply

Input voltage

V_{DD_LP}

MV_IN

V

-

DDR3 and DDR3L DRAM

signals

DDR3 and DDR3L DRAM

reference

Dn_MV_REF

LV_IN

GV_DD/2 1%

GND to LV_DD

GND to OV_DD

V

-

Ethernet (except EMI2),

1588, GPIO signals

eSHDC, eSPI, DMA, MPIC, OV_IN

GPIO, system control and

power management,

clocking, debug, IFC,

DDRCLK supply, and JTAG

signals

DUART, I²C signals

DV_IN

SV_IN

GND to DV_DD

GND to SV_DD

V

-

SerDes signals

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

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77

Electrical characteristics

Table 3. Recommended operating conditions (continued)

Characteristic

Symbol

Recommended

Value

Unit Notes

USB PHY Transceiver

signals

USB_HV_IN

GND to USB_HV_DD

GND to USB_OV_DD

GND to 1.2V

V

-

USB_OV_IN

-

V

-

Ethernet management

3

interface 2 (EMI2) signals

LP Trust signal

LP_TMP_DETECT_B

V_{IN_LP}

GND to V_{DD_LP}

V

-

Operating temperature range

Normal operation

T_A,

T_J

T_A= 0 (min) to

T_J= 105(max)

T_A= -40 (min) to

T_J= 105(max)

T_A= 0 (min) to

T_J= 70 (max)

°C

Extended Temperature

T_A,

T_J

°C

-

Secure boot fuse

programming

T_A,

T_J

2

1. Selecting RGMII limits to LV_DD= 2.5 V.

2. PROG_SFP must be supplied 1.8 V and the chip must operate in the specified fuse programming temperature range only

during secure boot fuse programming. For all other operating conditions, PROG_SFP must be tied to GND, subject to the

power sequencing constraints shown in Power sequencing.

3. Ethernet MII management interface 2 pins function as open drain I/Os. The interface conforms to 1.2 V nominal voltage

levels.

4. Refer to Voltage ID (VID) controllable supply and Core and platform supply voltage filtering for additional information.

5. Supply voltage specified at the voltage sense pin. Voltage input pins should be regulated to provide specified voltage at the

sense pin. For additional information, see the "Ganged sense-line implementation example" section in the T4240 QorIQ

Integrated Processor Design Checklist (AN4559).

6. Operation at 1.1V is allowable for up to 25ms at initial power on. Alternatively the initial start-up voltage can power up

straight to the VID voltage if the system has previously programmed that specific part’s VID value.

7. Voltage ID (VID) operating range is between 0.975V to 1.025V. Regulator selection should be based on Vout range wider

than VIDmin to VIDmax with resolution of 12.5mV or better.

8. Keep this pin biased to the specified voltage, despite the thermal monitoring unit being de-featured.

9. If VID is known at initial start-up, set VDD=VID else if VID is not known at initial start-up, set VDD to 1.025V and change it

immediately, to VDD=VID after reading VID at the beginning of booting.

10.This supply does not have a designated pin in this device because it is used only for EMI2 signals external pull-up resistor

source.

11.Keep filter close to pin. Voltage and tolerance for AV_DDis defined at the input of the PLL supply filter and not the pin of

AV_DD

.

This figure shows the undershoot and overshoot voltages at the interfaces of the chip.

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NXP Semiconductors

Electrical characteristics

Maximum overshoot

D/X/S/G/L/OV

DD

V

IH

GND

V

IL

Minimum undershoot

Overshoot/undershoot period

Notes:

The overshoot/undershoot period should be less than 10% of shortest possible toggling period " bit time", of the

input signal or per input signal specific protocol requirement. For GPIO input signal overshoot/undershoot period,

it should be less than 10% of the SYSCLK period.

Figure 7. Overshoot/Undershoot voltage for USB_OV_IN/USB_HV_IN/LV_IN/OV_IN/MV_IN/

SV_IN/DV_IN

See Table 3 for actual recommended core voltage. Voltage to the processor interface I/Os

are provided through separate sets of supply pins and must be provided at the voltages

shown in Table 3. The input voltage threshold scales with respect to the associated I/O

supply voltage. DV_DD, OV_DDand LV_DDbased receivers are simple CMOS I/O circuits

and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses

differential receivers referenced by the externally supplied Dn_MV_REFsignal (nominally

set to GV_DD/2) as is appropriate for the SSTL_1.35/SSTL_1.5 electrical signaling

standard. The DDR DQS receivers cannot be operated in single-ended fashion. The

complement signal must be properly driven and cannot be grounded.

3.1.3 Output driver characteristics

This chip provides information on the characteristics of the output driver strengths.

NOTE

These values are preliminary estimates.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

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79

Electrical characteristics

Table 4. Output drive capability

Driver type

Output impedance (Ω)

Supply voltage

Notes

DDR3 signal

18(full-strength mode)

GV_DD= 1.5 V

1

27(half-strength mode)

DDR3L signal

18(full-strength mode)

GV_DD= 1.35 V

1

27(half-strength mode)

Ethernet signals

45

LV_DD= 2.5 V

OV_DD= 1.8 V

DV_DD= 2.5 V

DV_DD= 1.8 V

2

eSPI, JTAG, system control, Integrated flash controller (IFC)

DUART, I²C

1. The drive strength of the DDR3 or DDR3L interface in half-strength mode is at T_j= 105 °C and at GV_DD(min).

2. Impedance value varies by +/- 20%

3.2 Power sequencing

For power up, the requirements are as follows:

1. Bring up V_DD, SnV_DD, USB_SV_DD, V_DD_LP, USB_HV_DD, LV_DD, DV_DD,

USB_OV_DD, OV_DD, TH_V_DD, AV_DD(cores, platform, DDR), GnV_DD, XnV_DD, and

AV_DD_SDn_PLLn. Drive PROG_SFP = GND.

• PORESET_B input must be driven asserted and held during this step.

Power supplies in this step have no ordering requirement with respect to one another

except for the USB power supplies per the following note.

NOTE

a. USB_SV_DDsupply must ramp before or after the

USB_HV_DDand USB_OV_DDsupplies have ramped.

The supply set that ramp first must reach 90% of its

final value before a supply from the other set can be

ramped up.

b. USB_HV_DDand USB_OV_DDsupplies among

themselves are sequence independent.

c. USB_HV_DDrise time (10% to 90%) has a minimum of

100 us.

2. Negate PORESET_B input as long as the required assertion/hold time has been met

per Table 21.

3. For secure boot fuse programming, use the following steps:

a. After negation of PORESET_B, drive PROG_SFP = 1.8 V after a required

minimum delay per Table 5.

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NXP Semiconductors

Electrical characteristics

b. After fuse programming is completed, it is required to return PROG_SFP =

GND before the system is power cycled (PORESET_B assertion) or powered

down (V_DDramp down) per the required timing specified in Table 5. See

Security fuse processor, for additional details.

Warning

No activity other than that required for secure boot fuse

programming is permitted while PROG_SFP is driven

to any voltage above GND, including the reading of the

fuse block. The reading of the fuse block may only

occur while PROG_SFP = GND.

From a system standpoint, if any of the I/O power

supplies ramp prior to the V_DDsupply, there will be a

brief period as the V_DDpowers up that the I/Os

associated with that I/O supply may go from being tri-

stated to an indeterminate state (either driven to a logic

one or zero), and extra current may be drawn by the

device.

Only 300,000 POR cycles are permitted per lifetime of

a device. Note that this value is based on design

estimates and is preliminary.

All supplies must be at their stable values within 400 ms.

If using Trust Architecture Security Monitor battery backed features, then ensure that

both, OVDD is ramped to recommended operational voltage, and SYSCLK is running,

prior to VDD ramping up to the 0.5 Volt level. The running system clock should have a

minimum frequency of 800HZ and a maximum frequency no greater than the supported

maximum system clock frequency as in Table 14 table.

This figure provides the PROG_SFP timing diagram.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

81

Electrical characteristics

Fuse programming

10% PROG_SFP

PROG_SFP

90% V_DD

t

PROG_SFP_VDD

V

DD

t_{PROG_SFP_PROG}

t_{PROG_SFP_DELAY}

90% OV_DD

t_{PROG_SFP_RST}

90% OV_DD

PORESET_B

NOTE: PROG_SFP must be stable at 1.8 V prior to initiating fuse programming.

Figure 8. PROG_SFP timing diagram

This table provides information on the power-down and power-up sequence parameters

for PROG_SFP.

Table 5. PROG_SFP timing ⁵

Driver type

Min

Max

Unit

SYSCLKs

Notes

t_{PROG_SFP_DELAY}

t_{PROG_SFP_PROG}

t_{PROG_SFP_VDD}

t_{PROG_SFP_RST}

100

0

-

1

2

3

4

μs

0

1. Delay required from the deassertion of PORESET_B to driving PROG_SFP ramp up. Delay measured from PORESET_B

deassertion at 90% OV_DDto 10% PROG_SFP ramp up.

2. Delay required from fuse programming finished to PROG_SFP ramp down start. Fuse programming must complete while

PROG_SFP is stable at 1.8 V. No activity other than that required for secure boot fuse programming is permitted while

PROG_SFP driven to any voltage above GND, including the reading of the fuse block. The reading of the fuse block may

only occur while PROG_SFP = GND. After fuse programming is completed, it is required to return PROG_SFP = GND.

3. Delay required from PROG_SFP ramp down complete to V_DDramp down start. PROG_SFP must be grounded to

minimum 10% PROG_SFP before V_DDis at 90% V_DD

4. Delay required from PROG_SFP ramp down complete to PORESET_B assertion. PROG_SFP must be grounded to

minimum 10% PROG_SFP before PORESET_B assertion reaches 90% OV_DD

.

5. Only two secure boot fuse programming events are permitted per lifetime of a device.

Warning

PROG_SFP ramp up slew rate must not exceed 25kV/s. Ramp

down does not have a slew rate constraint.

3.3 Power-down requirements

The power-down cycle must complete such that power supply values are below 0.4 V

before a new power-up cycle can be started.

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NXP Semiconductors

Electrical characteristics

If performing secure boot fuse programming per Power sequencing, it is required that

PROG_SFP = GND before the system is power cycled (PORESET_B assertion) or

powered down (V_DDramp down) per the required timing specified in Table 5.

NOTE

All input signals, including I/Os that are configured as inputs,

driven into the chip need to monotonically increase/decrease

through entire rise/fall durations.

3.4 Power characteristics

This table shows the power dissipations of the V_DDand S_nV_DDsupply for various

operating platform clock frequencies versus the core and DDR clock frequencies when

Altivec power is gated off. See the e6500 core reference manual, section 8.6.1, "Altivec

Power Down - Software Controlled Entry" for details on how to place Altivec in low

power state.

Table 6. T4240 Power dissipation for rev 2 silicon with Altivec power-gated off¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME/FM

freq (MHz)

V_DD

(V)

SnV_DD

(V)

Junction

temp. (ºC)

VDD

(Core +

Platform) Platfor

+ SVDD

Power

(W)¹

VDD

(Core +

SnV_DDNotes

power

(W)⁹

(MT/s)

m)

Power

Typical

1500

1667

1800

667

733

1600

1866

500/667

550/733

VID

1.0

65

32

29.7

2.3

2, 3

Thermal

Maximum

Typical

105

42

50

35

52

61

38

54

64

39.7

47.7

32.7

49.7

58.7

35.7

51.7

61.7

2.3

4, 5

5, 6, 7

2, 3

VID

1.0

65

Thermal

Maximum

Typical

105

4, 5

5, 6, 7

2, 3

65

Thermal

Maximum

Notes:

105

4, 5

5, 6, 7

1. Combined power of V_DDand S_nV_DDwith platform at power-on reset default state, all DDR controllers and all SerDes banks

active. Does not include I/O power and Altivec is power-gated off.

2. Typical power assumes Dhrystone running with activity factor of 60% (on all cores) and is executing DMA on the platform

with 100% activity factor.

3. Typical power based on nominal process distribution for this device.

4. Thermal power assumes Dhrystone running with activity factor of 60% (on all cores) and executing DMA on the platform at

100% activity factor.

5. Thermal and maximum power are based on worst-case process distribution for this device.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

83

Electrical characteristics

Table 6. T4240 Power dissipation for rev 2 silicon with Altivec power-gated off¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME/FM

freq (MHz)

V_DD

(V)

SnV_DD

(V)

Junction

temp. (ºC)

VDD

(Core +

Platform) Platfor

+ SVDD

Power

(W)¹

VDD

(Core +

SnV_DDNotes

power

(W)⁹

(MT/s)

m)

Power

6. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the

platform at 115% activity factor.

7. Maximum power provided for power supply design sizing.

8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.

9. Total SnVDD Power Conditions (S1,S2,S3,S4). This represents the highest possible power at 105ºC based upon worst-

case voltage tolerances and data patterns. Use the equations in Table 9 for average power at 105ºC.

a- SerDes1: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.

b- SerDes2: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.

c- SerDes3: 8 lanes @ 10.3125 G.

d- SerDes4: 4 lanes @ 10 G, 4 lanes @ 5 G.

Table 7. T4241 Power dissipation for rev 2 silicon with Altivec power-gated off¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME/FM

freq (MHz)

V_DD

(V)

SnV_DD

(V)

Junction

temp. (ºC)

VDD

(Core +

Platform) Platfor

+ SVDD

Power

(W)¹

VDD

(Core +

SnV_DDNotes

power

(W)⁹

(MT/s)

m)

Power

Typical

1500

1667

1800

667

733

1600

1866

500/667

550/733

VID

1.0

65

29.1

26.8

2.3

2, 3

Thermal

Maximum

Typical

105

37.5

45.2

32.2

43.7

52.5

34.1

45.1

54.6

35.2

42.9

29.9

41.4

50.2

31.8

42.8

52.3

2.3

4, 5

5, 6, 7

2, 3

VID

1.0

65

Thermal

Maximum

Typical

105

4, 5

5, 6, 7

2, 3

65

Thermal

Maximum

Notes:

105

4, 5

5, 6, 7

1. Combined power of V_DDand S_nV_DDwith platform at power-on reset default state, all DDR controllers and all SerDes banks

active. Does not include I/O power and Altivec is power-gated off.

2. Typical power assumes Dhrystone running with activity factor of 60% (on all cores) and is executing DMA on the platform

with 100% activity factor.

3. Typical power based on nominal process distribution for this device.

4. Thermal power assumes Dhrystone running with activity factor of 60% (on all cores) and executing DMA on the platform at

100% activity factor.

5. Thermal and maximum power are based on worst-case process distribution for this device.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

84

NXP Semiconductors

Electrical characteristics

Table 7. T4241 Power dissipation for rev 2 silicon with Altivec power-gated off¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME/FM

freq (MHz)

V_DD

(V)

SnV_DD

(V)

Junction

temp. (ºC)

VDD

(Core +

Platform) Platfor

+ SVDD

Power

(W)¹

VDD

(Core +

SnV_DDNotes

power

(W)⁹

(MT/s)

m)

Power

6. Maximum power assumes Dhrystone running with activity factor at 100% (on all cores) and is executing DMA on the

platform at 115% activity factor.

7. Maximum power provided for power supply design sizing.

8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.

9. Total SnVDD Power Conditions (S1,S2,S3,S4). This represents the highest possible power at 105ºC based upon worst-

case voltage tolerances and data patterns. Use the equations in Table 9 for average power at 105ºC.

a- SerDes1: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.

b- SerDes2: 2 lanes @ 10.3125 G, 6 lanes @ 3.125 G.

c- SerDes3: 8 lanes @ 10.3125 G.

d- SerDes4: 4 lanes @ 10 G, 4 lanes @ 5 G.

This table shows the power dissipations of the V_DDand SnV_DDsupplies for various

operating platform clock frequencies versus the core and DDR clock frequencies when

Altivec power is on.

Table 8. T4240 Power dissipation for rev 2 silicon with Altivec enabled¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME

V_DD

(V)

SnV_DD

(V)

Junction VDD(Cor

temp. (ºC) e +

VDD

(Core+

SnV_DDNotes

/FM freq

(MHz)

power

(W)⁹

Platform) Platform

+ SVDD ) power

(W)¹

(MT/s)

Typical

1500

1667

1800

667

733

1600

1866

500/667

VID

1.0

65

35

32.7

42.7

50.7

35.7

52.7

61.7

38.7

54.7

63.7

2.3

2, 3

Thermal

Maximum

Typical

105

45

53

38

55

64

41

57

66

4, 5

5, 6, 7

2, 3

550/733

VID

1.0

65

Thermal

Maximum

Typical

105

4, 5

5, 6, 7

2, 3

65

Thermal

Maximum

Notes:

105

4, 5

5, 6, 7

1. Combined power of V_DDand S_nV_DDwith platform at power-on reset default state, all DDR controllers and all SerDes banks

active. Does not include I/O power.

2. Typical power assumes Altivec benchmark running (on all cores) and is executing DMA on the platform with 100% activity

factor.

3. Typical power based on nominal process distribution for this device.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

85

Electrical characteristics

Table 8. T4240 Power dissipation for rev 2 silicon with Altivec enabled¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME

V_DD

(V)

SnV_DD

(V)

Junction VDD(Cor

temp. (ºC) e +

VDD

(Core+

SnV_DDNotes

/FM freq

(MHz)

power

(W)⁹

Platform) Platform

+ SVDD ) power

(W)¹

(MT/s)

4. Thermal power assumes Altivec benchmark running with work power activity factor of 100% (on all cores) and executing

DMA on the platform at 100% activity factor.

5. Thermal and maximum power are based on worst-case process distribution for this device.

6. Maximum power assumes Altivec benchmark running with work power activity factor at 100% (on all cores) and is

executing DMA on the platform at 115% activity factor.

7. Maximum power provided for power supply design sizing.

8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.

9. Total SnVDD Power Conditions (S1,S2,S3,S4). This represents the highest possible power at 105ºC based upon worst-

case voltage tolerances and data patterns. Use the equations in Table 9 for average power at 105ºC.

a- SerDes1: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.

b- SerDes2: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.

c- SerDes3: 8-lanes @ 10.3125 G.

d- SerDes4: 4-lanes @ 10 G, 4-lanes @ 5 G.

Table 9. T4241 Power dissipation for rev 2 silicon with Altivec enabled¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME

V_DD

(V)

SnV_DD

(V)

Junction VDD(Cor

temp. (ºC) e +

VDD

(Core+

SnV_DDNotes

/FM freq

(MHz)

power

(W)⁹

Platform) Platform

+ SVDD ) power

(W)¹

(MT/s)

Typical

1500

1667

1800

667

733

1600

1866

500/667

VID

1.0

65

31.5

40.4

48.1

34.9

47.1

55.9

37.0

48.7

58.2

29.2

38.1

45.8

32.6

44.8

53.6

34.7

46.4

55.9

2.3

2, 3

Thermal

Maximum

Typical

105

4, 5

5, 6, 7

2, 3

550/733

VID

1.0

65

Thermal

Maximum

Typical

105

4, 5

5, 6, 7

2, 3

65

Thermal

Maximum

Notes:

105

4, 5

5, 6, 7

1. Combined power of V_DDand S_nV_DDwith platform at power-on reset default state, all DDR controllers and all SerDes banks

active. Does not include I/O power.

2. Typical power assumes Altivec benchmark running (on all cores) and is executing DMA on the platform with 100% activity

factor.

3. Typical power based on nominal process distribution for this device.

4. Thermal power assumes Altivec benchmark running with work power activity factor of 100% (on all cores) and executing

DMA on the platform at 100% activity factor.

5. Thermal and maximum power are based on worst-case process distribution for this device.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

86

NXP Semiconductors

Electrical characteristics

Table 9. T4241 Power dissipation for rev 2 silicon with Altivec enabled¹

8

Power

mode

Core

freq

(MHz) (MHz)

Plat

freq

DDR

data

rate

PME

V_DD

(V)

SnV_DD

(V)

Junction VDD(Cor

temp. (ºC) e +

VDD

(Core+

SnV_DDNotes

/FM freq

(MHz)

power

(W)⁹

Platform) Platform

+ SVDD ) power

(W)¹

(MT/s)

6. Maximum power assumes Altivec benchmark running with work power activity factor at 100% (on all cores) and is

executing DMA on the platform at 115% activity factor.

7. Maximum power provided for power supply design sizing.

8. Voltage ID (VID) operating range is between 0.975 V to 1.025 V.

9. Total SnVDD Power Conditions (S1,S2,S3,S4). This represents the highest possible power at 105ºC based upon worst-

case voltage tolerances and data patterns. Use the equations in Table 9 for average power at 105ºC.

a- SerDes1: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.

b- SerDes2: 2-lanes @ 10.3125 G, 6-lanes SGMII @ 3.125 G.

c- SerDes3: 8-lanes @ 10.3125 G.

d- SerDes4: 4-lanes @ 10 G, 4-lanes @ 5 G.

This table provides low power mode saving estimation.

Table 10. T4240/T4160/T4080 rev 2 single core, single cluster low power mode power

savings, 1.0 V ^1,2,3,7

Mode

Temp

65°C

Core

Freque

ncy =

Core

Frequency = Frequency =

1.667 GHz 1.5 GHz

Core

Units

Comment

Notes

1.8 GHz

PH10

PH15

PH20

PCL10

0.95

0.27

0.33

0.9

0.88

0.79

Watts Saving realized

moving from PH00

to PH10 state,

4

single core.

0.25

0.33

0.9

0.22

0.33

0.9

Watts Saving realized

moving from PH10

state to PH15

4,5

4

state, single core.

Watts Saving realized

moving from PH15

to PH20 state,

single core.

Watts Saving realized

moving from PH20

to PCL10 for single

cluster.

6

LPM20 (T4080)

LPM20 (T4160)

65°C

1.2

1.0

Watts Saving realized

moving from

6

PCL10 to LPM20.

Watts Saving realized

moving from

PCL10 to LPM20.

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

87

Electrical characteristics

Table 10. T4240/T4160/T4080 rev 2 single core, single cluster low power mode power

savings, 1.0 V ^1,2,3,7(continued)

Mode

Temp

Core

Freque

ncy =

Core

Frequency = Frequency =

1.667 GHz 1.5 GHz

Core

Units

Comment

Notes

1.8 GHz

LPM20 (T4240)

LPM40

65°C

1.8

1.5

Watts Saving realized

moving from

6

PCL10 to LPM20.

1.33

0.83

Watts Saving realized

moving from

LPM20 to LPM40.

Notes:

1. Power for V_DDonly.

2. Typical power assumes Dhrystone running (PH00 state) with activity factor of 60%.

3. Typical power based on nominal process distribution for this device.

4. PH10, PH15, PH20 power savings with one core. Maximum savings would be N times, where N is the number of used

cores.

5. Require both threads of the core to enter the same low-power mode.

6. See the e6500 reference manual and the T4240 reference manual for additional low power mode details.

7. Also applicable for lower power T4241 devices.

This table provides all the estimated I/O power supply values based on preliminary

measurements.

Table 11. T4240/T4241 I/O power dissipation

I/O Power Supply

Used in

Parameter

Typical (mW)

Maximum

(mw)

Notes

LVCMOS

OV_DD1.8 V

eSHDC, eSPI, DMA,

MPIC, GPIO

—

140

—

1, 3, 4, 5

management,

clocking, debug, IFC,

DDRCLK supply, and

JTAG

LVCMOS

LV_DD1.8 V

LV_DD2.5 V

Ethernet, Ethernet

management

interface 1 (EMI1),

1588, GPIO

—

122

198

—

Ethernet, Ethernet

management

interface 1 (EMI1),

1588, GPIO

LVCMOS

DV_DD1.8 V

DV_DD2.5 V

DUART, I 2 C

—

12

—

17

PROG_SFP 1.8V Fuse programming

200

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

88

NXP Semiconductors

Electrical characteristics

Table 11. T4240/T4241 I/O power dissipation (continued)

I/O Power Supply

Used in

Parameter

Typical (mW)

Maximum

(mw)

Notes

LVCMOS

DDR I/O

USB_PHY

V_DD_LP 1 V

Low Power Security

Monitor

—

8

—

GV_DD1.5 V

Dn_MV_REF

All three DDR

controllers

1866 MT/s

3500

3100

—

5000

4900

—

1, 2, 5

All three DDR

controllers

1600 MT/s

DDR3 and DDR3L

DRAM reference

—

USB_OV_DD1.8 V USB PHY

Transceiver supply

54

—

1, 5

voltage

USB_PHY

USB_HV_DD3.3 V USB PHY

—

59

—

Transceiver supply

voltage

USB_PHY

PLL

USB_SV_DD1 V

USB PHY Analog

supply voltage

—

6

—

AV_DD_CGAn 1.8 PLL of core and

15 for each

1, 5

V

system

AV_DD_CGBn 1.8

V

AV_DD_PLAT 1.8

V

PLL_DDR

AV_DD_Dn 1.8 V

PLL of DDR

—

15

60

—

PLL_SerDes

AV_DD

PLL of SerDes

_SDn_PLLn 1.5

V or 1.35 V

SerDes, 1.35

XV_DD, 1.0 V

SV_DD

Pad power

SV_DD

F_i= Lane data P_ SV_DD

=

—

6

supply for single

SerDes module's

receivers

rate in Gbps

155.047 +

16.766 * N +

3.287 * (Sum(n_i

* F_i)) 15 mW

N = Total

number of lanes

used

n_i= number of

lanes running at

F_irate

SerDes, 1.35

XV_DD, 1.0 V

SV_DD

Pad power

XV_DD

F_i= Lane data P_ XV_DD

=

—

6

supply for single

SerDes module's

transmitters

rate in Gbps

53.256 + 50.685

* N + 0.683 *

(Sum(n_i* F_i))

15 mW

N = Total

number of lanes

used

n_i= number of

lanes running at

F_irate

Notes:

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

89

Electrical characteristics

I/O Power Supply

Table 11. T4240/T4241 I/O power dissipation

Used in

Parameter

Typical (mW)

Maximum

(mw)

Notes

1. The maximum values are dependent on actual use case such as what application, external components used,

environmental conditions such as temperature, voltage and frequency. This is not intended to be the maximum guaranteed

power. Expect different results depending on the use case. The maximum values are estimated and they are based on

simulations at 105 °C junction temperature.

2. Typical DDR power numbers are based on one 2-rank DIMM with 20% utilization, while maximum assumes 40% utilization

of bus. These values are good for thermal design but for supply design it should be assumed 100% utilization of bus where

DDR I/O power can be up to 9.6 Watts for the three controllers in T4240. Writes at 60 Ω ODT & full.

3. Assuming 15 pF total capacitance load.

4. GPIOs are supported on 1.8 V and 2.5 V rails as specified in the hardware specification.

5. The typical values are estimates and based on measurements at nominal recommended voltage for the I/O power supply

and assuming at 65° C junction temperature.

6. The total power numbers of XV_DDand SV_DDdepend on the customer's application usecase. Power formulas assume 105°

C junction temperature. If one PLL is used, then subtract 60 mW from the resulting P_ SV_DD. The following examples show

how to use the formulas in estimating P_ SV_DDand P_ XV_DDfor different SerDes usecases.

Example 1:

On a SerDes block running SGMII at 3.125 Gbps on one lane, the SerDes typical powers are expected to be:

P_ SV_DD= 155.047 + 16.766 * 1 + 3.287 *(1 * 3.125) 15 mW - (60 mW "because one PLL is used" ) = 122 mW 15 mW

P_ XV_DD= 53.256 + 50.685 * 1 + 0.683 * (1 * 3.125) 15 mW = 106 mW 15 mW

Example 2:

On a SerDes block running PCIe at 5 Gbps on eight lanes, the SerDes typical powers are expected to be:

P_ SV_DD= 155.047 + 16.766 * 8 + 3.287 * (8 * 5) 15 mW - (60 mW "because one PLL is used" ) = 361 15 mW

P_ XV_DD= 53.256 + 50.685 * 8 + 0.683 *(8 * 5) 15 mW = 486 mW 15 mW

Example 3:

On a single SerDes block running XFI at 10.3125 Gbps on two lanes and SGMII at 3.75 G on four lanes, the single SerDes

module typical powers are expected to be:

P_ SV_DD= 155.047 + 16.766 * 6 + 3.287 * (2 * 10.3125 + 4 * 3.75 ) 15 mW = 373 mW 15 mW

P_ XV_DD= 53.256 + 50.685 * 6 + 0.683 * (2 * 10.3125 + 4 * 3.75) 15 mW = 382 mW 15 mW

3.5 Power-on ramp rate

This section describes the AC electrical specifications for the power-on ramp rate

requirements. Controlling the maximum power-on ramp rate is required to avoid excess

in-rush current.

This table provides the power supply ramp rate specifications.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

90

NXP Semiconductors

Electrical characteristics

Table 12. Power supply ramp rate

Parameter

Min

Max

Unit

V/ms

Notes

1, 2

Required ramp rate for all voltage supplies (including OV_DD/DV_DD/ GnV_DD

SnV_DD/XnV_DD/LV_DD, all core and platform V_DDsupplies, Dn_MV_REFand all AV_DD

/

-

25

supplies.)

Required ramp rate for PROG_SFP

V/ms

1, 2

Note:

1. Ramp rate is specified as a linear ramp from 10 to 90%. If non-linear (for example, exponential), the maximum rate of

change from 200 to 500 mV is the most critical as this range might falsely trigger the ESD circuitry.

2. Over full recommended operating temperature range (see Table 3).

3.6 Input clocks

3.6.1 System clock (SYSCLK) and real-time clock (RTC) timing

specifications

This section provides the system clock and real-time clock DC and AC timing

specifications.

3.6.1.1 SYSCLK and RTC DC timing specifications

This table provides the SYSCLK and RTC DC specifications.

Table 13. SYSCLK and RTC DC electrical characteristics³

Parameter

Input high voltage

Symbol

Min

Typical

Max

Unit

Notes

V_IH

V_IL

C_IN

1.25

—

V

1

Input low voltage

—

0.6

—

V

Input capacitance (SYSCLK)

—

3.3

pF

—

Input capacitance (RTC)

C_IN

I_IN

—

2.6

—

pF

μA

—

2

Input current (OV_IN= 0 V or OV_IN

OV_DD)

=

-50

50

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol OV_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3. At recommended operating conditions with OV_DD= 1.8 V, see Table 3.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

91

Electrical characteristics

3.6.1.2 SYSCLK and RTC AC timing specifications

This table provides the SYSCLK AC timing specifications.

Table 14. SYSCLK AC timing specifications⁵

Parameter/Condition

SYSCLK frequency

Symbol

f_SYSCLK

Min

Typ

Max

Unit

MHz

Notes

1, 2

66.7

7.5

40

1

—

133.3

15

SYSCLK cycle time

SYSCLK duty cycle

SYSCLK slew rate

t_SYSCLK

ns

1, 2

2

t_KHK/ t_SYSCLK

60

%

—

4

V/ns

ps

3

SYSCLK peak period jitter

—

150

500

—

4

SYSCLK jitter phase noise at -56 dBc —

—

KHz

V

AC Input Swing voltage

ΔV_AC

0.6 x OV_DD

1 x OV_DD

6

Notes:

1. Caution: The relevant clock ratio settings must be chosen such that the resulting SYSCLK frequency do not exceed their

respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at OV_DD/2.

3. Slew rate as measured from 0.35 x OV_DDto 0.65 x OV_DD

.

4. Phase noise is calculated as FFT of TIE jitter.

5. At recommended operating conditions with OV_DD= 1.8V, see Table 3.

6. AC swing measured relative to half OV_DDor VIH and VIL have equal absolute offset from OV_DD/2, So, Swing = (VIH-VIL)/

OVDD and ΔV_AC= Swing x OV_DD

This table provides the RTC AC timing specifications.

Table 15. RTC AC timing specifications⁵

Parameter/Condition

RTC frequency

Symbol

Min

Typ

Max

Unit

MHz

Notes

1, 2

f_RTC

t_RTC

—

platform

clock/16

—

RTC cycle time

16/platform

clock

ns

1, 2

RTC duty cycle

t_KHK/ t_RTC

40

—

60

%

2

RTC slew rate

—

1

4

V/ns

ps

3

RTC peak period jitter

RTC jitter phase noise at -56 dBc

AC Input Swing voltage

—

150

500

—

4

—

KHz

V

ΔV_AC

0.6 x OV_DD

1 x OV_DD

6

Notes:

1. Caution: The relevant clock ratio settings must be chosen such that it fits IEEE1588, or MPIC, or RCPM requirements.

2. Measured at the rising edge and/or the falling edge at OV_DD/2.

3. Slew rate as measured from 0.35 x OV_DDto 0.65 x OV_DD

.

4. Phase noise is calculated as FFT of TIE jitter.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

92

NXP Semiconductors

Electrical characteristics

Table 15. RTC AC timing specifications⁵

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

5. At recommended operating conditions with OV_DD= 1.8V, see Table 3.

6. AC swing measured relative to half OV_DDor VIH and VIL have equal absolute offset from OV_DD/2, So, Swing = (VIH-VIL)/

OVDD and ΔV_AC= Swing x OV_DD

3.6.2 Spread-spectrum sources

Spread-spectrum clock sources are an increasingly popular way to control

electromagnetic interference emissions (EMI) by spreading the emitted noise to a wider

spectrum and reducing the peak noise magnitude in order to meet industry and

government requirements. These clock sources intentionally add long-term jitter to

diffuse the EMI spectral content. The jitter specification given in this table considers

short-term (cycle-to-cycle) jitter only. The clock generator's cycle-to-cycle output jitter

should meet the chip's input cycle-to-cycle jitter requirement. Frequency modulation and

spread are separate concerns; the chip is compatible with spread-spectrum sources if the

recommendations listed in this table are observed.

Table 16. Spread-spectrum clock source recommendations³

Parameter

Frequency modulation

Min

Max

Unit

Notes

-

60

kHz

%

-

Frequency spread

1.0

1, 2

Notes:

1. SYSCLK frequencies that result from frequency spreading and the resulting core frequency must meet the minimum and

maximum specifications given in Table 14.

2. Maximum spread-spectrum frequency may not result in exceeding any maximum operating frequency of the device.

3. At recommended operating conditions with OVDD = 1.8 V, see Table 3.

CAUTION

The processor's minimum and maximum SYSCLK and core/

platform/DDR frequencies must not be exceeded regardless of

the type of clock source. Therefore, systems in which the

processor is operated at its maximum rated core/platform/DDR

frequency should avoid violating the stated limits by using

down-spreading only.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

93

Electrical characteristics

3.6.3 Real-time clock (RTC) timing

The RTC timing input is sampled by the platform clock. The output of the sampling latch

is then used as an input to the counters of the MPIC and the time base unit of the core;

there is no need for jitter specification. The minimum period of the RTC signal should be

greater than or equal to 16x the period of the platform clock. There is no minimum RTC

frequency; RTC may be grounded if not needed.

3.6.4 Gigabit Ethernet reference clock timing

This table provides the Ethernet gigabit reference clock DC specifications.

Table 17. ECn_GTX_CLK125 DC electrical characteristics ¹

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Input high

voltage

V_IH

V_IL

C_IN

I_IN

1.7

-

V

2

-

Input low

voltage

0.7

6

V

Input

capacitance

-

pF

μA

Input current

(LV_IN= 0 V or

-50

50

3

LV_IN= LV_DD

1. At recommended operating conditions with LV_DD= 2.5 V

2. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

3. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

)

This table provides the Ethernet gigabit reference clocks AC timing specifications.

Table 18. ECn_GTX_CLK125 AC timing specifications ¹

Parameter/Condition

ECn_GTX_CLK125 frequency

ECn_GTX_CLK125 cycle time

ECn_GTX_CLK125 rise and fall time

LV_DD= 2.5 V

Symbol

t_G125

Min

Typical

Max

Unit

Notes

125 - 100 ppm 125

125 + 100 ppm MHz

-

t_G125

-

8

-

ns

t_G125R/t_G125F

0.75

2

3

ECn_GTX_CLK125 duty cycle

1000Base-T for RGMII

t_G125H/t_G125

47

-

53

%

ECn_GTX_CLK125 jitter

-

150

ps

1. At recommended operating conditions with LV_DD= 2.5 V 125 mV.

2. Rise and fall times for ECn_GTX_CLK125 are measured from 0.5 and 2.0 V for LV_DD= 2.5 V.

3. ECn_GTX_CLK125 is used to generate the GTX clock for the Ethernet transmitter with 2% degradation. The

ECn_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle

generated by the GTX_CLK. See RGMII AC timing specifications for duty cycle for 10Base-T and 100Base-T reference clock.

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3.6.5 DDR clock timing

This section provides the DDR clock DC and AC timing specifications.

3.6.5.1 DDR clock DC timing specifications

This table provides the DDR clock (DDRCLK) DC specifications.

Table 19. DDRCLK DC electrical characteristics³

Parameter

Input high voltage

Symbol

Min

Typical

Max

Unit

Notes

V_IH

V_IL

C_IN

I_IN

1.25

-

V

1

-

Input low voltage

Input capacitance

-

0.6

V

-

11

-

pF

μA

Input current (OV_IN= 0 V or OV_IN

OV_DD)

=

-50

50

2

Note:

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol OV_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3. At recommended operating conditions with OV_DD= 1.8 V, see Table 3.

3.6.5.2 DDR clock AC timing specifications

This table provides the DDR clock (DDRCLK) AC timing specifications.

Table 20. DDRCLK AC timing specifications⁵

Parameter/Condition

DDRCLK frequency

Symbol

f_DDRCLK

Min

Typ

Max

Unit

MHz

Notes

66.7

7.5

40

1

-

133.3

15

1, 2

2

DDRCLK cycle time

DDRCLK duty cycle

DDRCLK slew rate

t_DDRCLK

ns

t_KHK/ t_DDRCLK

60

%

-

4

V/ns

ps

3

DDRCLK peak period jitter

-

150

500

-

DDRCLK jitter phase noise at -56 dBc -

-

KHz

V

4

AC Input Swing voltage

ΔV_AC

0.6 x OV_DD

1 x OV_DD

6

Notes:

1. Caution: The relevant clock ratio settings must be chosen such that the resulting DDRCLK frequency do not exceed their

respective maximum or minimum operating frequencies.

2. Measured at the rising edge and/or the falling edge at OV_DD/2.

3. Slew rate as measured from 0.35 x OV_DDto 0.65 x OV_DD

.

4. Phase noise is calculated as FFT of TIE jitter.

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Parameter/Condition

Table 20. DDRCLK AC timing specifications⁵

Symbol

Min

Typ

Max

Unit

Notes

5. At recommended operating conditions with OV_DD= 1.8V, see Table 3.

6. AC swing measured relative to half OV_DDor VIH and VIL have equal absolute offset from OV_DD/2, So, Swing = (VIH-VIL)/

OVDD and ΔV_AC= Swing x OV_DD

.

3.6.6 Other input clocks

A description of the overall clocking of this device is available in the chip reference

manual in the form of a clock subsystem block diagram. For information about the input

clock requirements of functional modules sourced external of the chip, such as SerDes,

Ethernet management, eSDHC, IFC, see the specific interface section.

3.7 RESET initialization

This section describes the AC electrical specifications for the RESET initialization timing

requirements. This table describes the AC electrical specifications for the RESET

initialization timing.

Table 21. RESET Initialization timing specifications

Parameter/Condition

Required assertion time of PORESET_B

Min

Max

Unit

Notes

1

-

ms

1

Required input assertion time of HRESET_B

Maximum rise/fall time of PORESET_B signal

32

-

SYSCLKs

SYSCLK

2, 3

4

1

Maximum rise/fall time of HRESET_B signal

-

4

-

SYSCLK

μs

4

-

PLL input setup time with stable SYSCLK before HRESET_B negation 100

Input setup time for POR configs with respect to negation of

PORESET_B

4

2

-

SYSCLKs

2

Input hold time for all POR configs with respect to negation of

PORESET_B

-

Maximum valid-to-high impedance time for actively driven POR

configs with respect to negation of PORESET_B

5

1. PORESET_B must be driven asserted before the core and platform power supplies are powered up.

2. SYSCLK is the primary clock input for the chip.

3. The device asserts HRESET_B as an output when PORESET_B is asserted to initiate the power-on reset process. The

device releases HRESET_B sometime after PORESET_B is deasserted. The exact sequencing of HRESET_B deassertion is

documented in section "Power-On Reset Sequence" in the chip reference manual.

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Table 21. RESET Initialization timing specifications

Parameter/Condition

Min

Max

Unit

Notes

4. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing. For example On

table 1, notes 6 and 7, recommends a week pull up resistor for HRESET signal pin in the range of 2K to 10K Ohms, But PCB

designers have to reduce the pull up resistor ( min of 280 Ohms) or in addition use bidirectional level shifter to comply with

maximum rise/fall time requirement for HRESET if this pin is too loaded.

This table provides the PLL lock times.

Table 22. PLL lock times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times (Core, platform, DDR only)

-

100

μs

-

3.8 DDR3 and DDR3L SDRAM controller

This section describes the DC and AC electrical specifications for the DDR3 and DDR3L

SDRAM controller interface. Note that the required GV_DD(typ) voltage is 1.5 V when

interfacing to DDR3 SDRAM and the GV_DD(typ) voltage is 1.35 V when interfacing to

DDR3L SDRAM.

NOTE

When operating at a DDR data rate of 1866 MT/s, only one

dual-ranked module per memory controller is supported.

3.8.1 DDR3 and DDR3L SDRAM interface DC electrical

characteristics

This table provides the recommended operating conditions for the DDR SDRAM

controller when interfacing to DDR3 SDRAM.

Table 23. DDR3 SDRAM interface DC electrical characteristics (GV_DD= 1.5 V)^{1, 7}

Parameter

I/O reference voltage

Symbol

Dn_MV_REF

V_IH

Min

Max

Unit

Note

2, 3, 4

0.49 x GV_DD

0.51 x GV_DD

V

Input high voltage

Input low voltage

I/O leakage current

Notes:

Dn_MV_REF+ 0.100 GV_DD

V

5

6

V_IL

GND

-100

Dn_MV_REF- 0.100

100

V

I_OZ

μA

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Table 23. DDR3 SDRAM interface DC electrical characteristics (GV_DD= 1.5 V)^{1, 7}

Parameter

Symbol

Min

Max

Unit

Note

1. GV_DDis expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's

voltage supply may or may not be from the same source.

2. Dn_MV_REFis expected to be equal to 0.5 x GV_DDand to track GV_DDDC variations as measured at the receiver. Peak-to-

peak noise on Dn_MV_REFmay not exceed the Dn_MV_REFDC level by more than 1% of GV_DD(i.e. 15 mV).

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be

equal to Dn_MV_REFwith a min value of Dn_MV_REF- 0.04 and a max value of Dn_MV_REF+ 0.04. V_TTshould track variations in

the DC level of Dn_MV_REF

.

4. The voltage regulator for Dn_MV_REFmust meet the specifications stated in Table 25.

5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.

6. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

7. For recommended operating conditions, see Table 3.

.

This table provides the recommended operating conditions for the DDR SDRAM

controller when interfacing to DDR3L SDRAM.

Table 24. DDR3L SDRAM interface DC electrical characteristics (GV_DD= 1.35 V)^{1, 7}

Parameter

I/O reference voltage

Symbol

Dn_MV_REF

V_IH

Min

Max

Unit

Note

2, 3, 4

0.49 x GV_DD

0.51 x GV_DD

V

Input high voltage

Input low voltage

I/O leakage current

Notes:

Dn_MV_REF+ 0.090 GV_DD

V

5

6

V_IL

GND

-100

Dn_MV_REF- 0.090

100

V

I_OZ

μA

1. GV_DDis expected to be within 50 mV of the DRAM's voltage supply at all times. The DRAM's and memory controller's

voltage supply may or may not be from the same source.

2. Dn_MV_REFis expected to be equal to 0.5 x GV_DDand to track GV_DDDC variations as measured at the receiver. Peak-to-

peak noise on Dn_MV_REFmay not exceed the Dn_MV_REFDC level by more than 1% of GV_DD(i.e. 13.5mV).

3. V_TTis not applied directly to the device. It is the supply to which far end signal termination is made, and it is expected to be

equal to Dn_MV_REFwith a min value of Dn_MV_REF- 0.04 and a max value of Dn_MV_REF+ 0.04. V_TTshould track variations in

the DC level of Dn_MV_REF

.

4. The voltage regulator for Dn_MV_REFmust meet the specifications stated in Table 25.

5. Input capacitance load for DQ, DQS, and DQS_B are available in the IBIS models.

6. Output leakage is measured with all outputs disabled, 0 V ≤ V_OUT≤ GV_DD

7. For recommended operating conditions, see Table 3.

.

This table provides the current draw characteristics for Dn_MV_REF

.

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1

Table 25. Current draw characteristics for Dn_MV_REF

Parameter

Symbol

Min

Max

Unit

Notes

Current draw for DDR3 SDRAM for

Dn_MV_REF

I_{Dn_MVREF}

-

500

μA

-

Current draw for DDR3L SDRAM for

I_{Dn_MVREF}

Dn_MV_REF

Note:

1. For recommended operating conditions, see Table 3.

3.8.2 DDR3 and DDR3L SDRAM interface AC timing specifications

This section provides the AC timing specifications for the DDR SDRAM controller

interface. The DDR controller supports DDR3 and DDR3L memories. Note that the

required GV_DD(typ) voltage is 1.5 V when interfacing to DDR3 SDRAM and the

required GV_DD(typ) voltage is 1.35 V when interfacing to DDR3L SDRAM.

3.8.2.1 DDR3 and DDR3L SDRAM interface input AC timing specifications

This table provides the input AC timing specifications for the DDR controller when

interfacing to DDR3 SDRAM.

Table 26. DDR3 and DDR3L SDRAM interface input AC timing specifications³

Parameter

Controller Skew for MDQS-MDQ/MECC

1866 MT/s data rate

Symbol

t_CISKEW

Min

Max

Unit

Notes

ps

1

-93

93

1600 MT/s data rate

-112

-125

-142

-170

112

125

142

170

1333 MT/s data rate

1200 MT/s data rate

1066 MT/s data rate

Tolerated Skew for MDQS-MDQ/MECC

1866 MT/s data rate

t_DISKEW

ps

2

-175

-200

-250

-275

-300

175

200

250

275

300

1600 MT/s data rate

1333 MT/s data rate

1200 MT/s data rate

1066 MT/s data rate

1. t_CISKEWrepresents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that

is captured with MDQS[n]. This must be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t_DISKEW.This can be

determined by the following equation: t_DISKEW= (T ꢀ 4 - abs(t_CISKEW)) where T is the clock period and abs(t_CISKEW) is the

absolute value of t_CISKEW

.

3. For recommended operating conditions, see Table 3.

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This figure shows the DDR3 and DDR3L SDRAM interface input timing diagram.

MCK[n]_B

MCK[n]

t_MCK

MDQS[n]

t_DISKEW

D0

D1

MDQ[x]

t_DISKEW

Figure 9. DDR3 and DDR3L SDRAM Interface Input Timing Diagram

3.8.2.2 DDR3 and DDR3L SDRAM interface output AC timing

specifications

This table contains the output AC timing targets for the DDR3 SDRAM interface.

Table 27. DDR3 and DDR3L SDRAM interface output AC timing specifications⁷

Parameter

MCK[n] cycle time

Symbol¹

Min

Max

Unit

Notes

t_MCK

0.938

2

ns

2

3

ADDR/CMD output setup with respect to MCK t_DDKHAS

1866 MT/s data rate

0.410

0.495

0.606

0.675

0.744

-

1600 MT/s data rate

1333 MT/s data rate

1200 MT/s data rate

1066 MT/s data rate

ADDR/CMD output hold with respect to MCK t_DDKHAX

1866MT/s data rate

ns

3

0.390

0.495

0.606

0.675

0.744

-

1600 MT/s data rate

1333 MT/s data rate

1200 MT/s data rate

1066 MT/s data rate

Table continues on the next page...

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Table 27. DDR3 and DDR3L SDRAM interface output AC timing specifications⁷(continued)

Parameter

MCK to MDQS Skew

Symbol¹

Min

Max

Unit

Notes

t_DDKHMH

ns

4

> 1600 MT/s data rate

> 1066 MT/s data rate, ≤ 1600 MT/s data rate

MDQ/MECC/MDM output Data eye

1866 MT/s data rate

-0.150

-0.245

0.150

0.245

4, 6

5

t_DDKXDEYE

0.350

0.400

0.500

0.550

0.600

-

1600 MT/s data rate

1333 MT/s data rate

1200 MT/s data rate

1066 MT/s data rate

MDQS preamble

t_DDKHMP

t_DDKHME

0.9 x t_MCK

0.4 x t_MCK

ns

-

MDQS postamble

0.6 x t_MCK

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. Output hold time can be read as DDR timing (DD)

from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t_DDKHAS

symbolizes DDR timing (DD) for the time t_MCKmemory clock reference (K) goes from the high (H) state until outputs (A) are

setup (S) or output valid time.

2. All MCK/MCK_B and MDQS/MDQS_B referenced measurements are made from the crossing of the two signals.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK_B, MCS_B, and MDQ/MECC/MDM/MDQS.

4. Note that t_DDKHMHfollows the symbol conventions described in note 1. For example, t_DDKHMHdescribes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t_DDKHMHcan be modified through

control of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the

same delay as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these two

parameters have been set to the same adjustment value. See the chip reference manual for a description and explanation of

the timing modifications enabled by the use of these bits.

5. Available eye for data (MDQ), ECC (MECC), and data mask (MDM) outputs at the pin of the processor. Memory controller

will center the strobe (MDQS) in the available data eye at the DRAM (end point) during the initialization.

6. Note that for data rates of 1200 MT/s or higher, it is required to program the start value of the DQS adjust for write leveling.

7. For recommended operating conditions, see Table 3.

NOTE

For the ADDR/CMD setup and hold specifications in Table 27,

it is assumed that the clock control register is set to adjust the

memory clocks by ½ applied cycle.

This figure shows the DDR3 and DDR3L SDRAM interface output timing for the MCK

to MDQS skew measurement (t_DDKHMH).

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MCK[n]_B

MCK[n]

t

MCK

t

DDKHMH(max)

MDQS

t

DDKHMH(min)

Figure 10. t_DDKHMHtiming diagram

This figure shows the DDR3 and DDR3L SDRAM output timing diagram.

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MCK_B

MCK

t_MCK

t_DDKHAS

t_DDKHAX

NOOP

ADDR/CMD

Write A0

t_DDKHMP

t_DDKHMH

MDQS[n]

MDQ[x]

t_DDKHME

D0

t_DDKXDEYE

D1

t_DDKXDEYE

Figure 11. DDR3 and DDR3L output timing diagram

3.9 eSPI interface

This section describes the DC and AC electrical specifications for the eSPI interface.

3.9.1 eSPI DC electrical characteristics

This table provides the DC electrical characteristics for the eSPI interface operating at

OV_DD= 1.8 V.

Table 28. eSPI DC electrical characteristics (1.8 V)³

Parameter

Symbol

V_IH

Min

1.25

Max

Unit

Notes

Input high voltage

Input low voltage

-

V

1

2

-

V_IL

I_IN

-

0.6

50

-

V

Input current (V_IN= 0 V or V_IN= OV_DD

)

-50

1.35

μA

V

Output high voltage

V_OH

Table continues on the next page...

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Table 28. eSPI DC electrical characteristics (1.8 V)³(continued)

Parameter

Symbol

Min

Max

Unit

Notes

(OV_DD= min, I_OH= -0.5 mA)

Output low voltage

(OV_DD= min, I_OL= 0.5 mA)

Notes:

V_OL

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.9.2 eSPI AC timing specifications

This table provides the eSPI input and output AC timing specifications.

Table 29. eSPI AC timing specifications³

Parameter/Condition

Symbol ²

Min

Max

Unit Notes

SPI_MOSI output-Master data (internal clock) t_NIKHOX

hold time

n1 + ( t_{PLATFORM_CLK}

SPMODE[HO_ADJ])

*

-

ns

1, 2, 4

SPI_MOSI output-Master data (internal clock) t_NIKHOV

delay

-

n2 + ( t_{PLATFORM_CLK *}ns

SPMODE[HO_ADJ])

1, 2, 4

SPI_CS outputs-Master data (internal clock) t_NIKHOX2

hold time

0

-

ns

1

-

SPI_CS outputs-Master data (internal clock) t_NIKHOV2

delay

-

6.0

SPI inputs-Master data (internal clock) input t_NIIVKH

setup time

3.0

0

-

SPI inputs-Master data (internal clock) input t_NIIXKH

hold time

-

Clock-high time

Clock-low time

Notes:

t_NIKCKH

t_NIKCKL

4

-

ns

-

1. See the chip reference manual for details about the SPMODE register.

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

3. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state) (reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_NIKHOVsymbolizes the NMSI outputs

internal timing (NI) for the time t_SPImemory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).

4. n1 and n2 values are -1.0 and 1.0 respectively.

This figure provides the AC test load for the eSPI.

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Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 12. eSPI AC test load

This figure provides the eSPI clock output timing diagram.

Figure 13. eSPI clock output timing diagram

This figure represents the AC timing from Table 29 in master mode (internal clock). Note

that although the specifications generally reference the rising edge of the clock, these AC

timing diagrams also apply when the falling edge is the active edge. Also, note that the

clock edge is selectable on eSPI.

1

SPICLK (output)

t_NIIXKH

t_NIIVKH

Input Signals:

t_NIKHOX

t_NIKHOV

Output Signals:

t_NIKHOX2

t_NIKHOV2

Output Signals:

1

SPI_CS[0:3]

Figure 14. eSPI AC timing in master mode (internal clock) diagram

1. SPICLK appears on the interface only after CS assertion.

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3.10 DUART interface

This section describes the DC and AC electrical specifications for the DUART interface.

3.10.1 DUART DC electrical characteristics

This table provides the DC electrical characteristics for the DUART interface at DV_DD

2.5 V.

=

Table 30. DUART DC electrical characteristics(2.5 V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

1.7

-

V

1

2

-

0.7

50

-

V

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

-50

2.0

-

μA

V

Output high voltage (DV_DD= min, I_OH= -1 mA)

Output low voltage (DV_DD= min, I_OL= 1 mA)

Notes:

V_OH

V_OL

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_INrepresents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the DUART interface at DV_DD

1.8 V.

=

Table 31. DUART DC electrical characteristics(1.8 V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

1.25

-

V

1

2

-

0.6

50

-

V

Input current (DV_IN= 0 V or DV_IN= DV_DD

)

-50

1.35

-

μA

V

Output high voltage (DV_DD= min, I_OH= -0.5 mA)

Output low voltage (DV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max DV_INrespective values found in Table 3.

2. The symbol DV_INrepresents the input voltage of the supply. It is referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

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3.10.2 DUART AC electrical specifications

This table provides the AC timing parameters for the DUART interface.

Table 32. DUART AC timing specifications

Parameter/Condition

Minimum baud rate

Value

f_PLAT/(2 x 1,048,576)

f_PLAT/(2 x 16)

Unit

Notes

baud

1, 3

1, 2

Maximum baud rate

Notes:

1. f_PLATrefers to the internal platform clock.

2. The actual attainable baud rate is limited by the latency of interrupt processing.

3. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values

are sampled each 16^thsample.

3.11 Ethernet interface, Ethernet management interface 1 and 2,

IEEE Std 1588^™

This section provides the AC and DC electrical characteristics for the Ethernet controller

and the Ethernet management interfaces.

3.11.1 SGMII electrical specifications

See SGMII interface.

3.11.2 RGMII electrical specifications

This section discusses the electrical characteristics for the RGMII interface.

3.11.2.1 RGMII DC electrical characteristics

This table shows the DC electrical characteristics for the RGMII interface.

Table 33. RGMII DC electrical characteristics(LV_DD= 2.5 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.70

-

V

1

2

-

V_IL

I_IN

0.70

50

V

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

-50

2.00

μA

V

Output high voltage (LV_DD= min, I_OH= -1.0 mA)

V_OH

LV_DD+ 0.3

Table continues on the next page...

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Table 33. RGMII DC electrical characteristics(LV_DD= 2.5 V)³(continued)

Parameter

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

Symbol

V_OL

Min

Max

Unit

Notes

GND - 0.3

0.40

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.11.2.2 RGMII AC timing specifications

This table presents the RGMII AC timing specifications.

Table 34. RGMII AC timing specifications (LV_DD= 2.5 V)⁸

Parameter/Condition

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

Symbol¹

t_{SKRGT_TX}

t_{SKRGT_RX}

Min

-750

Typ

Max

1250

Unit

Notes

0

-

ps

ns

7,9

1.0

2.6

2,10

RGMII RX_CLK Clock period duration

Duty cycle for 10BASE-T and 100BASE-TX

Duty cycle for Gigabit

t_RGT

7.2

40

45

-

8.0

50

-

8.8

60

ns

%

3

t_RGTH/t_RGT

t_RGTR

3, 4

-

55

%

Rise time (20%-80%)

0.75

ns

5, 6

Fall time (20%-80%)

t_RGTF

-

Notes:

1. In general, the clock reference symbol representation for this section is based on the symbols RGT to represent RGMII

timing. Note that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols

representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns

is added to the associated clock signal. Many PHY vendors already incorporate the necessary delay inside their device. If so,

additional PCB delay is probably not needed.

3. For 10 and 100 Mbps, t_RGTscales to 400 ns 40 ns and 40 ns 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as

long as the minimum duty cycle is not violated and stretching occurs for no more than three t_RGTof the lowest speed

transitioned between.

5. Applies to inputs and outputs.

6. System/board must be designed to ensure this input requirement to the chip is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

7. The frequency of ECn_RX_CLK (input) should not exceed the frequency of ECn_GTX_CLK (output) by more than 300

ppm.

8. For recommended operating conditions, see Table 3.

9. IEEE spec mandates tSKRGT_TX = +- 0.5ns. Per erratum A-005177 we see tSKRGT_TX has a wider output skew range

from -0.75ns to 1.25ns which is larger than the spec asks for. If can not cope with this wide skew then use RGMII at 100

Mbps or 10 Mbps (which allows larger maximum RX skews) or terminate 1000 Mbps RGMII links with PHYs that

accommodate larger RX skews or terminate to a second Rev2 device.

10. This device has better input clock to data skew tSKRGT_RX tolerance (1ns to 3.5ns) than spec (1ns to 2.6ns) requires.

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This figure shows the RGMII AC timing and multiplexing diagrams.

t

RGT

t

RGTH

GTX_CLK

output

t

SKRGT_TX

t

SKRGT_TX

TXD[7:4][3:0]

output

TXD[3:0]

TXEN

TXD[7:4]

TXERR

TX_CTL

output

RXD[7:4][3:0]

input

RXD[3:0]

RXDV

RXD[7:4]

RXERR

RX_CTL

input

t

SKRGT_RX

t

SKRGT_RX

RX_CLK

input

t

RGTH

t

RGT

Figure 15. RGMII AC timing and multiplexing diagrams

Warning

NXP guarantees timings generated from the MAC. Board

designers must ensure delays needed at the PHY or the MAC.

3.11.3 Ethernet management interface (EMI)

This section discusses the electrical characteristics for the EMI1 and EMI2 interfaces.

Frame Manager 2’s external GE MDIO configures external GE PHYs connected to EMI1

pins. Frame Manager 2’s external 10GE MDIO configures external XAUI, XFI and

HiGig/HiGig2 PHYs connected to EMI2 pins.

The EMI1 interface timing is compatible with IEEE Std 802.3^™clause 22 and EMI2

interface timing is compatible with IEEE Std 802.3^™clause 45. The External MDIO

interfaces on FM1 are not available for use.

3.11.3.1 Ethernet management interface 1 DC electrical characteristics

The DC electrical characteristics for EMI1_MDIO and EMI1_MDC are provided in this

section.

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Table 35. Ethernet management interface 1 DC electrical characteristics (LV_DD= 2.5 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.70

-

V

1

2

-

V_IL

0.70

50

V

Input current (LV_IN=0V or LV_IN=LV_DD

)

I_IN

-50

2.00

μA

V

Output high voltage (LV_DD= min, I_OH= -1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

Notes:

V_OH

V_OL

LV_DD+ 0.3

0.40

GND - 0.3

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol VIN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

Table 36. DC electrical characteristics (1.8 V)

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.25

-

V

1

2

-

V_IL

0.60

50

-

V

Input current (LV_IN= 0V or LV_IN=LV_DD

)

I_IN

-50

1.35

-

μA

V

Output high voltage (LV_DD= min, I_OH= -0.5 mA)

Output low voltage (LV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

0.40

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_IN/QV_INvalues found in Table 3.

2. The symbol VIN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3.11.3.2 Ethernet management interface 2 DC electrical characteristics

Ethernet management interface 2 pins function as open drain I/Os. The interface

conforms to 1.2 V nominal voltage levels. The DC electrical characteristics for

EMI2_MDIO and EMI2_MDC are provided in this section.

Table 37. Ethernet management interface 2 DC electrical characteristics (1.2 V)¹

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

0.84

-

V

-

V_IL

-

0.36

0.2

10

V

Output low voltage (I_OL= 5.5 mA)

Input capacitance

Notes:

V_OL

C_IN

V

pF

1. For recommended operating conditions, see Table 3.

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3.11.3.3 Ethernet management interface 1 AC electrical specifications

This table provides the Ethernet management interface 1 AC timing specifications.

Table 38. Ethernet management interface 1 AC timing specifications⁶

Parameter/Condition

MDC frequency (1/T_{MDC_ClK}

MDC clock pulse width high

Symbol¹

Min

Typ

Max

Unit

MHz

ns

Notes

)

f_MDC

—

2.5

—

2

t_MDCH

160

—

MDC to MDIO

delay

Rev1

t_MDKHDX

(Y x t_{enet_clk}) -

3,

(Y x t_{enet_clk}) + ns

3,

3, 4, 5

4

MDIO_CFG[

EHOLD] = 0

Y = 2 x

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[

NEG] = 0

Rev2

t_MDKHDX

(Y x t_{enet_clk}) -

3,

—

(Y x t_{enet_clk}) + ns

3,

MDIO_CFG[

NEG] = 0

Y = 2 x

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[

EHOLD] = 0

Rev2

(Y x t_{enet_clk}) -

3,

(Y x t_{enet_clk}) + ns

3,

MDIO_CFG[

NEG] = 0

Y = 8 x

MDIO_CFG[M

DIO_HOLD]

+1

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[

EHOLD] = 1

Rev2

(Y x T_{MDC_ClK}

- 3,

)

(Y x T_{MDC_ClK}

+ 3,

)

ns

MDIO_CFG[

NEG] = 1

Y = ½

—

MDIO to MDC setup time

MDIO to MDC hold time

Notes:

t_MDDVKH

t_MDDXKH

9

0

—

ns

—

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes management

data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time.

2. This parameter is dependent on the Ethernet clock frequency. (MDIO_CFG [MDIO_CLK_DIV] field determines the clock

frequency of the MgmtClk Clock MDIO_MDC).

3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods 3 ns. For

example, in default rev1 silicon, with an Ethernet clock of 400 MHz, the min/max delay is = (Y x t_{enet_clk}

1/400 M) 3 ns = 12.5 ns 3 ns.

)

3 ns = ((2 x 2 + 1) x

Default values for Rev 1: silicon:

• MDIO_CFG[MDIO_HOLD]= 3’b010 which selects Y = 2 x 2 + 1 = 5 tenet_clk cycles.

• MDIO_CFG[NEG] = 0, in Rev 1, NEG bit field was not visible.

• MDIO_CFG[EHOLD] = 0, in Rev 1, NEG bit field was not visible.

Default values for Rev 2 silicon:

• MDIO_CFG[MDIO_HOLD]= 3’b010, since MDIO_CFG[NEG] = 1 then Y = ½.

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Table 38. Ethernet management interface 1 AC timing specifications⁶

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

• MDIO_CFG[NEG] = 1

• MDIO_CFG[EHOLD] = 0

• For Rev 1 silicon: Y = 2 x MDIO_CFG[MDIO_HOLD] + 1

• For Rev 2 silicon:

• If MDIO_CFG[EHOLD] = 0 and MDIO_CFG[NEG] = 0 then Y = 2 x MDIO_CFG[MDIO_HOLD] + 1

• If MDIO_CFG[EHOLD] = 1 and MDIO_CFG[NEG] = 0 then Y = 8 x MDIO_CFG[MDIO_HOLD] + 1

• If MDIO_CFG[NEG] = 1 then Y = ½ . Thus, Y is not affected by MDIO_CFG[HOLD] and MDIO_CFG[EHOLD]

when MDIO_CFG[NEG] = 1. For example, in this case, if MDC clock = 2.5 MHz, then min/max of t_MDKHDXdelay

is = Y * T_{MDC_ClK}3 ns = ½ x 1/2.5 M 3 ns = 200 ns 3 ns.

4. t_MDKHDXtransition:

• For Rev 1 silcon: t_MDKHDXis MDC positive edge to MDIO transition.

• For Rev 2 silicon:

• If MDIO_CFG[NEG] = 0 then t_MDKHDXis MDC positive edge to MDIO transition.

• If MDIO_CFG[NEG] = 1 then t_MDKHDXis MDC negative edge to MDIO transition.

• The default value of MDIO_CFG [MDIO_CLK_DIV] is 0 which means no MDIO clock is available. Recommended

to configure this field in PBL.

5. t_{enet_clk}is the Ethernet clock period derived from Frame Manager clock, FM clock. t_{enet_clk}=1/FM_clock.

6. For recommended operating conditions, see Table 3.

3.11.3.4 Ethernet management interface 2 AC electrical characteristics

This table provides the Ethernet management interface 2 AC timing specifications.

Table 39. Ethernet management interface 2 AC timing specifications⁶

Parameter/Condition

MDC frequency (1/T_{MDC_ClK}

MDC clock pulse width high

Symbol¹

Min

Typ

Max

Unit

MHz

ns

Notes

)

f_MDC

—

2.5

—

2

t_MDCH

160

—

MDC to MDIO

delay

Rev1

t_MDKHDX

(Y x t_{enet_clk}) -

3,

(Y x t_{enet_clk}) + ns

3,

3, 4, 5

MDIO_CFG[

EHOLD] = 0

Y = 2 x

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[

NEG] = 0

Rev2

t_MDKHDX

(Y x t_{enet_clk}) -

3,

—

(Y x t_{enet_clk}) + ns

3,

MDIO_CFG[

NEG] = 0

Y = 2 x

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[

EHOLD] = 0

Rev2

t_MDKHDX

(Y x t_{enet_clk}) -

3,

-

(Y x t_{enet_clk}) + ns

3,

MDIO_CFG[

NEG] = 0

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Table 39. Ethernet management interface 2 AC timing specifications⁶(continued)

Parameter/Condition

MDIO_CFG[

Symbol¹

Min

Y = 8 x

Typ

Max

Y = 8 x

Unit

Notes

EHOLD] = 1

MDIO_CFG[M

DIO_HOLD] +

1

MDIO_CFG[M

DIO_HOLD]

+1

Rev2

t_MDKHDX

(Y x T_{MDC_ClK}

- 3,

)

—

(Y x T_{MDC_ClK}) ns

+ 3,

4

MDIO_CFG[

NEG] = 1

Y = ½

MDIO to MDC setup time

t_MDDVKH

t_MDDXKH

8

0

—

ns

7

MDIO to MDC hold time

—

Notes:

1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_MDKHDXsymbolizes management

data timing (MD) for the time t_MDCfrom clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.

Also, t_MDDVKHsymbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state

(V) relative to the t_MDCclock reference (K) going to the high (H) state or setup time.

2. This parameter is dependent on the Ethernet clock frequency (MDIO_CFG [MDIO_CLK_DIV] field determines the clock

frequency of the MgmtClk Clock MDIO_MDC).

3. This parameter is dependent on the Ethernet clock frequency. The delay is equal to Y x Ethernet clock periods 3 ns. For

example, in default rev1 silicon, with an Ethernet clock of 400 MHz, the min/max delay is = (Y x t_{enet_clk}) = ((2 x 2 + 1) x

1/400M) 3 ns = 12.5 ns 3 ns.

Default values for Rev 1: silicon:

• MDIO_CFG[MDIO_HOLD] = 3’b010, which selects Y = 2 x 2 + 1 = 5 tenet_clk cycles.

• MDIO_CFG[NEG] = 0, in Rev 1, NEG bit field was not visible.

• MDIO_CFG[EHOLD] = 0, in Rev 1, NEG bit field was not visible.

Default values for Rev 2 silicon:

• MDIO_CFG[MDIO_HOLD] = 3’b010, since MDIO_CFG[NEG] = 1 then Y = ½.

• MDIO_CFG[NEG] = 1

• MDIO_CFG[EHOLD] = 0

• For Rev 1 silicon: Y = 2 x MDIO_CFG[MDIO_HOLD] + 1

• For Rev 2 silicon:

• If MDIO_CFG[EHOLD] = 0 and MDIO_CFG[NEG] = 0 then Y = 2 x MDIO_CFG[MDIO_HOLD] + 1

• If MDIO_CFG[EHOLD] = 1 and MDIO_CFG[NEG] = 0 then Y = 8 x MDIO_CFG[MDIO_HOLD] + 1

• If MDIO_CFG[NEG] = 1 then Y = ½ . Thus Y is not affected by MDIO_CFG[HOLD] and MDIO_CFG[EHOLD]

when MDIO_CFG[NEG]=1. For example in this case If MDC clock = 2.5 MHz, then min/max of t_MDKHDXdelay is =

Y * T_{MDC_ClK}3 ns = ½ x 1/2.5 M 3ns = 200 ns 3 ns.

4. t_MDKHDXtransition:

• For Rev 1 silcon: t_MDKHDXis MDC positive edge to MDIO transition.

• For Rev 2 silicon:

• If MDIO_CFG[NEG] = 0 then t_MDKHDXis MDC positive edge to MDIO transition.

• If MDIO_CFG[NEG]= 1 then t_MDKHDXis MDC negative edge to MDIO transition.

• The default value of MDIO_CFG [MDIO_CLK_DIV] is 0, which means no MDIO clock is available. Recommended

to configure this field in PBL.

5. t_{enet_clk}is the Ethernet clock period derived from Frame Manager clock (FM clock). t_{enet_clk}= 1/FM_clock.

6. For recommended operating conditions, see Table 3.

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Table 39. Ethernet management interface 2 AC timing specifications⁶

Parameter/Condition

Symbol¹

Min

Typ

Max

Unit

Notes

7. The actual setup time varies with the MDC slew rate. For a 180 Ω MDC pull-up and 470 pF load, the setup time is

expected to be 68 ns measured at 50% points. To ensure setup time is met, the EMI2 clock frequency may need to be

reduced from the default setting by selecting a larger clock divide via configuration of MDIO_CFG[MDIO_CLK_DIV]

associated with EMI2.

This figure shows the Ethernet management interface timing diagram.

t_MDC

MDC

t_MDCH

MDIO

(Input)

t_MDDVKH

t_MDDXKH

MDIO

(Output)

Rev 1

t_MDKHDX

MDIO

(Output)

Rev 2

t_MDKHDX

Figure 16. Ethernet management interface timing diagram

3.11.4 IEEE 1588 electrical specifications

3.11.4.1 IEEE 1588 DC electrical characteristics

This table shows IEEE 1588 DC electrical characteristics when operating at LV_DD= 2.5

V supply.

Table 40. IEEE 1588 DC electrical characteristics(LV_DD= 2.5 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

1.70

-

V

1

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Table 40. IEEE 1588 DC electrical characteristics(LV_DD= 2.5 V)³(continued)

Parameter

Symbol

Min

Max

Unit

Notes

Input low voltage

Input current (LV_IN= 0 V or LV_IN= LV_DD

V_IL

I_IN

-

0.70

50

V

1

2

-

)

-50

2.00

μA

V

Output high voltage (LV_DD= min, I_OH= -1.0 mA)

Output low voltage (LV_DD= min, I_OL= 1.0 mA)

V_OH

V_OL

LV_DD+ 0.3

0.40

GND - 0.3

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table shows IEEE 1588 DC electrical characteristics when operating at LV_DD= 1.8

V supply.

Table 41. IEEE 1588 DC electrical characteristics(LV_DD= 1.8 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.25

-

V

1

2

-

V_IL

0.6

50

V

Input current (LV_IN= 0 V or LV_IN= LV_DD

)

I_IN

-50

1.35

μA

V

Output high voltage (LV_DD= min, I_OH= -0.5 mA)

Output low voltage (LV_DD= min, I_OL= 0.5 mA)

V_OH

V_OL

LV_DD+ 0.3

0.40

GND - 0.3

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3.

2. The symbol LV_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.11.4.2 IEEE 1588 AC specifications

This table provides the IEEE 1588 AC timing specifications.

Table 42. IEEE 1588 AC timing specifications³

Parameter/Condition

TSEC_1588_CLK_IN clock period

TSEC_1588_CLK_IN duty cycle

Symbol

t_T1588CLK

t_T1588CLKH

t_T1588CLK

TSEC_1588_CLK_IN peak-to-peak jitter t_T1588CLKINJ

Min

Typ

Max

Unit

ns

Notes

6

-

/

40

50

60

%

-

250

2.0

ps

ns

-

Rise time TSEC_1588_CLK_IN (20%

-80%)

t_T1588CLKINR

t_T1588CLKINF

t_T1588CLKOUT

1.0

-

Fall time TSEC_1588_CLK_IN (80%

-20%)

1.0

-

2.0

-

ns

-

TSEC_1588_CLK_OUT clock period

2 x t_T1588CLK

2

Table continues on the next page...

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Table 42. IEEE 1588 AC timing specifications³(continued)

Parameter/Condition

Symbol

t_T1588CLKOTH

t_T1588CLKOUT

Min

Typ

Max

Unit

Notes

TSEC_1588_CLK_OUT duty cycle

/

30

50

-

70

%

-

TSEC_1588_PULSE_OUT1/2,

TSEC_1588_ALARM_OUT1/2 hold time

TSEC_1588_TRIG_IN1/2 pulse width

Notes:

t_T1588OV

0.5

4.0

ns

t_T1588TRIGH

2 x t_T1588CLK

-

1

1. It needs to be at least two times the clock period of the clock selected by TMR_CTRL[CKSEL]. See the chip reference

manual for a description of TMR_CTRL registers.

2. There are 3 input clock sources for 1588 i.e. TSEC_1588_CLK_IN, RTC, and MAC clock / 2 in rev1 silicon and MAC clock

in rev2 silicon.

3. For recommended operating conditions, see Table 3.

This figure shows the data and command output AC timing diagram.

t_T1588CLKOUT

t_T1588CLKOUTH

TSEC_1588_CLK_OUT

t_T1588OV

TSEC_1588_PULSE_OUT1/2

TSEC_1588_ALARM_OUT1/2

Note: The output delay is counted starting at the rising edge if t_T1588CLKOUTis non-inverting.

Otherwise, it is counted starting at the falling edge.

Figure 17. IEEE 1588 output AC timing

This figure shows the data and command input AC timing diagram.

t_T1588CLK

TSEC_1588_CLK_IN

t_T1588CLKH

TSEC_1588_TRIG_IN1/2

t_T1588TRIGH

Figure 18. IEEE 1588 input AC timing

3.12 USB interface

This section provides the AC and DC electrical specifications for the USB interface.

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3.12.1 USB DC electrical characteristics

This table provides the DC electrical characteristics for the USB interface at USB_HV_DD

= 3.3 V.

Table 43. USB DC electrical characteristics (USB_HV_DD= 3.3 V) ³

Parameter

Symbol

Min

Max

Unit

Notes

1, 4

Input high voltage

Input low voltage

V_IH

V_IL

I_IN

2.0

-

V

0.8

1, 4

2, 4

Input current (USB_HV_IN= 0 V or USB_HV_IN=

USB_HV_DD

-100

+100

μA

)

Output high voltage (USB_HV_DD= min, I_OH= -2 mA)

Output low voltage (USB_HV_DD= min, I_OL= 2 mA)

Notes:

V_OH

V_OL

2.8

-

V

5

0.3

1. The min V_ILand max V_IHvalues are based on the respective min and max USB_HV_INvalues found in Table 3.

2. The symbol USB_HV_IN, in this case, represents the USB_HV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

4. These specifications only apply to the following pins: USB1_PWRFAULT, USB2_PWRFAULT, USB1_UDM (full-speed

mode), USB2_UDM (full-speed mode), USB1_UDP (full-speed mode), and USB2_UDP (full-speed mode).

5. This specification only applies to USB1_DRVVBUS and USB2_DRVVBUS pins.

This table provides the DC electrical characteristics for the USBCLK at OV_DD= 1.8 V.

Table 44. USBCLK DC electrical characteristics (1.8 V)³

Parameter

Symbol

Min

Max

Unit

Notes

Input high voltage V_IH

1.25

-

V

1

2

Input low voltage

V_IL

0.6

50

V

Input current (V_IN= I_IN

-50

μA

0 V or V_IN= OV_DD

)

Notes:

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

3.12.2 USB AC timing specifications

This section describes the AC timing specifications for the on-chip USB PHY. See

Chapter 7 in the Universal Serial Bus Revision 2.0 Specification for more information.

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This table provides the USB clock input (USBCLK) AC timing specifications.

Table 45. USBCLK AC timing specifications¹

Parameter/Condition

Symbol

Condition

Min Typ Max

Unit

MHz

Notes

USBCLK Frequency

f_{USB_CLK_IN}

-

24

-

USBCLK Rise/Fall time t_USRF

Measured between 10% and 90%

-

6

ns

%

2

-

USBCLK frequency

tolerance

t_{CLK_TOL}

t_{CLK_DUTY}

t_{CLK_PJ}

-0.005 0

0.005

USBCLK duty cycle

Measured at rising edge and/or failing edge 40

at OV_DD/2

50

-

60

5

%

-

USBCLK total input

jitter/time interval error

RMS value measured with a second-order,

band-pass filter of 500 kHz to 4 MHz

bandwidth at 10^-12BER

-

ps

Notes:

1. For recommended operating conditions, see Table 3

2. System/board must be designed to ensure the input requirement to the device is achieved. Proper device operation is

guaranteed for inputs meeting this requirement by design, simulation, characterization, or functional testing.

3.13 Integrated flash controller

This section describes the DC and AC electrical specifications for the integrated flash

controller.

3.13.1 Integrated flash controller DC electrical characteristics

This table provides the DC electrical characteristics for the integrated flash controller

when operating at OV_DD= 1.8 V.

Table 46. Integrated flash controller DC electrical characteristics (1.8 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Note

V_IH

V_IL

I_IN

1.25

-

V

1

2

Input low voltage

Input current

0.6

50

V

-50

μA

(V_IN= 0 V or V_IN= OV_DD

Output high voltage

)

V_OH

1.6

-

V

-

(OV_DD= min, I_OH= -0.5 mA)

Output low voltage

V_OL

0.32

(OV_DD= min, I_OL= 0.5 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol referenced in Recommended operating conditions.

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Table 46. Integrated flash controller DC electrical characteristics (1.8 V)³

Parameter

Symbol

Min

Max

Unit

Note

3. For recommended operating conditions, see Table 3.

3.13.2 Integrated flash controller AC timing specification

This section describes the AC timing specifications for the integrated flash controller.

3.13.2.1 Test condition

This figure provides the AC test load for the integrated flash controller.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 19. Integrated flash controller AC test load

3.13.2.2 Integrated flash controller AC timing specifications

All output signal timings are relative to the falling edge of any IFC_CLK. The external

circuit must use the rising edge of the IFC_CLKs to latch the data.

All input timings are relative to the rising edge of IFC_CLKs.

This table describes the timing specifications of the integrated flash controller interface.

Table 47. Integrated flash controller timing specifications (OV_DD= 1.8 V)⁵

Parameter/Condition

Symbol¹

Min

Max

Unit

ns

Notes

IFC_CLK cycle time

IFC_CLK duty cycle

t_IBK

10

45

0

-

t_IBKH/ t_IBK

t_IBKSKEW

t_IBIVKH

55

%

IFC_CLK[n] skew to IFC_CLK[m]

Input setup

75

ps

ns

2

-

4

-

Input hold

t_IBIXKH

1

-

Output delay

t_IBKLOV

t_IBKLOX

-

1.5

-

Output hold

-2

4

Table continues on the next page...

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Table 47. Integrated flash controller timing specifications (OV_DD= 1.8 V)⁵(continued)

Parameter/Condition

Symbol¹

Min

Max

Unit

ns

Notes

IFC_CLK to output high impedance for AD

t_IBKLOZ

-

2

3

1. All signals are measured from OV_DD/2 of rising/falling edge of IFC_CLK to OV_DD/2 of the signal in question.

2. Skew measured between different IFC_CLK signals at OV_DD/2.

3. For purposes of active/float timing measurements, the high impedance or off state is defined to be when the total current

delivered through the component pin is less than or equal to the leakage current specification.

4. Here the negative sign means output transit happens earlier than the falling edge of IFC_CLK.

5. For recommended operating conditions, see Table 3.

This figure shows the AC timing diagram.

IFC_CLK[m]

t

IBIXKH

IBIVKL

t

IBIVKH

Input signals

t

IBKLOV

t

IBKLOX

Output signals

t

IBKLOZ

t

IBKLOX

AD (data phase)

Figure 20. Integrated flash controller signals

The figure above applies to all the controllers that IFC supports.

• For input signals, the AC timing data is used directly for all controllers.

• For output signals, each type of controller provides its own unique method to control

the signal timing. The final signal delay value for output signals is the programmed

delay plus the AC timing delay.

This figure shows how the AC timing diagram applies to GPCM. The same principle also

applies to other controllers of IFC.

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IFC_CLK

AD

Address

Read data

Write data

t

+ t

eahc IBKLOV

t

+ t

eadc IBKLOV

AVD

t

+ t

acse IBKLOV

CE_B

t

+ t

aco IBKLOV

t

+ t

OE_B

WE_B

BCTL

rad IBKLOV

t

+ t

ch IBKLOV

t

+ t

cs IBKLOV

t

+ t

wp IBKLOV

Read

Write

Figure 21. GPCM output timing diagram^{1, 2}

Notes for figure:

1. t_aco, t_rad,t_eahc,t_eadc, t_acse, t_cs, t_ch,t_wpare programmable. See the chip reference manual.

2. For output signals, each type of controller provides its own unique method to control

the signal timing. The final signal delay value for output signals is the programmed delay

plus the AC timing delay.

3.14 Enhanced secure digital host controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC interface.

3.14.1 eSDHC DC electrical characteristics

This table provides the DC electrical characteristics for the eSDHC interface.

Table 48. eSDHC interface DC electrical characteristics (dual-voltage cards)³

Parameter

Input high voltage

Symbol

Min

0.7 x OV_DD

Max

Unit

Notes

V_IH

V_IL

-

V

1

-

Input low voltage

-

0.3 x OV_DD

V

I/O leakage current

I_IN/I_OZ

-50

50

-

μA

V

Output high voltage (I_OH= -100 μA at V_OH

OV_DDmin)

OV_DD- 0.2 V

-

Output low voltage (I_OL= 100 μA at

OV_DDmin)

V_OL

-

0.2

V

-

Table continues on the next page...

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Table 48. eSDHC interface DC electrical characteristics (dual-voltage cards)³(continued)

Parameter

Symbol

Min

OV_DD- 0.2 V

-

Max

Unit

Notes

Output high voltage (I_OH= -100 μA)

Output low voltage (I_OL= 2 mA)

V_OH

V_OL

-

V

2

0.3

1. The min V_ILand V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. Open-drain mode is for MMC cards only.

3. For recommended operating conditions, see Table 3.

3.14.2 eSDHC AC timing specifications

This table provides the eSDHC AC timing specifications as defined in Figure 22.

Table 49. eSDHC AC timing specifications⁶

Parameter/Condition

SD_CLK clock frequency:

Symbol¹

Min

Max

25/50

Unit

MHz

Notes

f_SHSCK

0

2, 4

SD/SDIO Full-speed/high-speed mode

MMC Full-speed/high-speed mode

20/52

SD_CLK clock low time-Full-speed/High-speed mode

SD_CLK clock high time-Full-speed/High-speed mode

SD_CLK clock rise and fall times

t_SHSCKL

t_SHSCKH

t_SHSCKR/

t_SHSCKF

t_SHSIVKH

t_SHSIXKH

t_SHSKHOX

t_SHSKHOV

10/7

-

ns

4

-

3

Input setup times: SD_CMD, SD_DATx, SD_CD to SD_CLK

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

Output hold time: SD_CLK to SD_CMD, SD_DATx valid

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

Notes:

2.5

-3

-

ns

3, 4, 5

4, 5

-

4, 5

-

3

4, 5

1. The symbols used for timing specifications herein follow the pattern of t_{(first three letters of functional block)(signal)(state) (reference)(state)}

for inputs and t_{(first three letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_FHSKHOVsymbolizes eSDHC

high-speed mode device timing (SHS) clock reference (K) going to the high (H) state, with respect to the output (O) reaching

the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters representing

the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F

(fall).

2. In full-speed mode, the clock frequency value can be 0-25 MHz for an SD/SDIO card and 0-20 MHz for an MMC card. In

high-speed mode, the clock frequency value can be 0-50 MHz for an SD/SDIO card and 0-52 MHz for an MMC card.

3. To satisfy setup timing, one-way board-routing delay between Host and Card, on SD_CLK, SD_CMD, and SD_DATx

should not exceed 1 ns for any high speed MMC card. For any high speed or default speed mode SD card, the one way

board routing delay between Host and Card, on SD_CLK, SD_CMD, and SD_DATx should not exceed 1.5ns.

4. C_CARD≤ 10 pF, (1 card), and C_L= C_BUS+ C_HOST+ C_CARD≤ 40 pF.

5. The parameter values apply to both full-speed and high-speed modes.

6. For recommended operating conditions, see Table 3.

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This figure provides the eSDHC clock input timing diagram.

eSDHC

external clock

VM

operational mode

t_SHSCKL

t_SHSCKH

t_SHSCK

t_SHSCKR

t_SHSCKF

VM = Midpoint voltage (OV_DD/2)

Figure 22. eSDHC clock input timing diagram

This figure provides the data and command input/output timing diagram.

VM

SDHC_CLK

external clock

t_SHSIVKH

t_SHSIXKH

SDHC_DAT/CMD inputs

SDHC_DAT/CMD outputs

t_SHSKHOX

t_SHSKHOV

VM = Midpoint voltage (OV_DD/2)

Figure 23. eSDHC data and command input/output timing diagram referenced to clock

3.15 Multicore programmable interrupt controller (MPIC)

This section describes the DC and AC electrical specifications for the multicore

programmable interrupt controller.

3.15.1 MPIC DC specifications

This figure provides the DC electrical characteristics for the MPIC interface.

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Table 50. MPIC DC electrical characteristics (OV_DD= 1.8 V)³

Parameter

Symbol

V_IH

Min

Max

Unit

Notes

Input high voltage

1.25

-

V

1

2

-

Input low voltage

V_IL

0.6

50

-

V

Input current (OV_IN= 0 V or OV_IN= OV_DD

)

I_IN

-50

1.35

-

μA

V

Output high voltage (OV_DD= min, I_OH= -0.5 mA)

Output low voltage (OV_DD= min, I_OL= 0.5 mA)

Note:

V_OH

V_OL

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the min and max OV_INrespective values found in Table 3.

2. The symbol OV_IN, in this case, represents the OV_INsymbol referenced in Table 3.

3. For recommended operating conditions, see Table 3.

3.15.2 MPIC AC timing specifications

This table provides the MPIC input and output AC timing specifications.

Table 51. MPIC Input AC timing specifications²

Parameter/Condition

Symbol

t_PIWID

Min

Max

Unit

Notes

MPIC inputs-minimum pulse width

3

-

SYSCLKs

1

1. MPIC inputs and outputs are asynchronous to any visible clock. MPIC outputs must be synchronized before use by any

external synchronous logic. MPIC inputs are required to be valid for at least t_PIWIDns to ensure proper operation when

working in edge triggered mode.

2. For recommended operating conditions, see Table 3.

3.16 JTAG controller

This section describes the DC and AC electrical specifications for the IEEE 1149.1

(JTAG) interface.

3.16.1 JTAG DC electrical characteristics

This table provides the JTAG DC electrical characteristics.

Table 52. JTAG DC electrical characteristics (OV_DD= 1.8V)³

Parameter

Symbol

V_IH

V_IL

Min

Max

Unit

Notes

Input high voltage

Input low voltage

1.25

-

V

1

0.6

Table continues on the next page...

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Table 52. JTAG DC electrical characteristics (OV_DD= 1.8V)³(continued)

Parameter

Symbol

Min

Max

Unit

Notes

Input current (OV_IN= 0 V or OV_IN= OV_DD

)

I_IN

-100

1.35

-

50

-

μA

V

2, 4

Output high voltage (OV_DD= min, I_OH= -0.5 mA)

Output low voltage (OV_DD= min, I_OL= 0.5 mA)

Notes:

V_OH

V_OL

-

0.4

V

1. The min V_ILand max V_IHvalues are based on the respective min and max OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the OV_INsymbol found in Table 3.

3. For recommended operating conditions, see Table 3.

4. TMI, TMS, and TRST_B have internal pull-ups per the IEEE Std. 1149.1 specification.

3.16.2 JTAG AC timing specifications

This table provides the JTAG AC timing specifications as defined in Figure 24 through

Figure 27.

Table 53. JTAG AC timing specifications⁴

Parameter/Condition

JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST_B assert time

Symbol¹

Min

Max

Unit

MHz

Notes

f_JTG

0

33.3

5

t_JTG

30

15

0

-

ns

6

t_JTKHKL

t_JTGR/t_JTGF

t_TRST

-

7

2

-

8

25

4.5

11

-

2

Input setup times

t_JTDVKH

t_JTDXKH

t_JTKLDV

-

9

Input hold times

-

10

Output valid times

Boundary-scan data

TDO

15

10

-

3, 11, 12

-

Output hold times

t_JTKLDX

0

ns

3

Notes:

1. The symbols used for timing specifications follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for inputs

and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_JTDVKHsymbolizes JTAG device timing (JT)

with respect to the time data input signals (D) reaching the valid state (V) relative to the t_JTGclock reference (K) going to the

high (H) state or setup time. Also, t_JTDXKHsymbolizes JTAG timing (JT) with respect to the time data input signals (D)

reaching the invalid state (X) relative to the t_JTGclock reference (K) going to the high (H) state. Note that in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2.TRST_B is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. All outputs are measured from the midpoint voltage of the falling edge of t_TCLKto the midpoint of the signal in question. The

output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays must be

added for trace lengths, vias, and connectors in the system.

4. For recommended operating conditions, see Table 3.

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Table 53. JTAG AC timing specifications⁴

Parameter/Condition

Symbol¹

Min

Max

Unit

Notes

5. TCK frequency can be as high as 100MHz for internal debug modes.

6. If TCK = 100 MHz then t_JTG= 10 nsec

7. If TCK = 100 MHz then t_JTKHKL= 5 nsec

8. If TCK = 100 MHz then t_JTGR/t_JTGF=<1 nsec

9. If TCK = 100 MHz then t_JTDVKH= 1.33 nsec

10. If TCK = 100 MHz then t_JTDXKH= 3.3 nsec

11. Due to value of tJTKLDV, after Update-IR or Update-DR transitions for EXTEST* or CLAMP instructions, a transition

through the optional Run-Test-Idle state is recommended to allow for board level propagation and setup times of observation

points.

12. DDR output pins when transitioning from a tristate to driving a logic 1 or 0 can require up to 24ns. Use of Run-Test Idle

state is recommended after Update-IR or Update-DR TAP states.

This figure provides the AC test load for TDO and the boundary-scan outputs of the

device.

Output

OV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 24. AC test load for the JTAG interface

This figure provides the JTAG clock input timing diagram.

VM

JTAG external clock

t_JTGR

t_JTKHKL

t_JTGF

t_JTG

VM = Midpoint voltage (OV_DD/2)

Figure 25. JTAG clock input timing diagram

This figure provides the TRST_B timing diagram.

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TRST_B

VM

t_TRST

VM = Midpoint voltage (OV_DD/2)

Figure 26. TRST_B timing diagram

This figure provides the boundary-scan timing diagram.

JTAG External Clock

VM

t_JTDVKH

t_JTDXKH

Boundary Data Inputs

Input Data Valid

t_JTKLDV

t_JTKLDX

Boundary Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV_DD/2)

Figure 27. Boundary-scan timing diagram

3.17 I²C interface

This section describes the DC and AC electrical characteristics for the I²C interface.

3.17.1 I²C DC electrical characteristics

This table provides the DC electrical characteristics for the I²C interfaces operating at

2.5V.

Table 54. I²C DC electrical characteristics (DV_DD= 2.5V)⁵

Parameter

Symbol

V_IH

Table continues on the next page...

Min

Max

Unit

Notes

Input high voltage

1.7

-

V

1

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Table 54. I²C DC electrical characteristics (DV_DD= 2.5V)⁵(continued)

Parameter

Symbol

V_IL

Min

Max

0.7

Unit

Notes

Input low voltage

-

V

1

2

3

4

Output low voltage (DV_DD= min, I_OL= 3 mA)

V_OL

0

0.4

50

V

Pulse width of spikes which must be suppressed by the input filter

t_I2KHKL

I_OZ

0

ns

Leakage Input current at each I/O pin (input voltage is between 0.1 x

DV_DDand 0.9 x DV_DD(max)

-50

μA

Capacitance for each I/O pin

C_I

-

10

pF

-

Notes:

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3.

2. See the chip reference manual for information about the digital filter used.

3. I/O pins obstruct the SDA and SCL lines if DV_DDis switched off.

4. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the I²C interfaces operating at

1.8V.

Table 55. I²C DC electrical characteristics (DV_DD= 1.8V)⁵

Parameter

Symbol

V_IH

Min

1.25

Max

Unit

Notes

Input high voltage

Input low voltage

-

V

1

2

V_IL

-

0.6

Output low voltage (DV_DD= min, I_OL= 3 mA)

V_OL

0

0.36

Pulse width of spikes which must be suppressed by the input filter

t_I2KHKL

I_OZ

0

50

ns

3

4

Leakage Input current each I/O pin (input voltage is between 0.1 x

DV_DDand 0.9 x DV_DD(max)

-50

μA

Capacitance for each I/O pin

C_I

-

10

pF

-

Notes:

1. The min V_ILand max V_IHvalues are based on the respective min and max DV_INvalues found in Table 3.

2. See the chip reference manual for information about the digital filter used.

3. I/O pins obstruct the SDA and SCL lines if DV_DDis switched off.

4. For recommended operating conditions, see Table 3.

3.17.2 I²C AC timing specifications

This table provides the AC timing parameters for the I²C interfaces.

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Table 56. I²C AC timing specifications⁵

Parameter/Condition

Symbol¹

Min

Max

Unit

kHz

Notes

SCL clock frequency

f_I2C

0

400

—

2

Low period of the SCL clock

t_I2CL

1.3

0.6

μs

—

High period of the SCL clock

t_I2CH

—

Setup time for a repeated START condition

t_I2SVKH

—

Hold time (repeated) START condition (after this period, the first t_I2SXKL

clock pulse is generated)

—

Data setup time

t_I2DVKH

t_I2DXKL

t_I2OVKL

t_I2PVKH

t_I2KHDX

V_NL

100

—

0.9

—

ns

μs

V

—

3

Data input hold time:

Data output delay time

—

4

Setup time for STOP condition

Bus free time between a STOP and START condition

0.6

1.3

—

Noise margin at the LOW level for each connected device

(including hysteresis)

0.1 x OV_DD

0.2 x OV_DD

—

Noise margin at the HIGH level for each connected device

(including hysteresis)

V_NH

Cb

—

V

—

Capacitive load for each bus line

400

pF

Notes:

1. The symbols used for timing specifications herein follow the pattern t_{(first two letters of functional block)(signal)(state)(reference)(state)}for

inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)}for outputs. For example, t_I2DVKHsymbolizes I²C timing (I2) with

respect to the time data input signals (D) reaching the valid state (V) relative to the t_I2Cclock reference (K) going to the high

(H) state or setup time. Also, t_I2SXKLsymbolizes I²C timing (I2) for the time that the data with respect to the START condition

(S) went invalid (X) relative to the t_I2Cclock reference (K) going to the low (L) state or hold time. Also, t_I2PVKHsymbolizes I²C

timing (I2) for the time that the data with respect to the STOP condition (P) reaches the valid state (V) relative to the t_I2Cclock

reference (K) going to the high (H) state or setup time.

2. The requirements for I²C frequency calculation must be followed. See Determining the I²C Frequency Divider Ratio for

SCL (AN2919).

3. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the V_IHminof the SCL

signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of a START or STOP

condition. When the chip acts as the I²C bus master while transmitting, it drives both SCL and SDA. As long as the load on

SCL and SDA are balanced, the chip does not generate an unintended START or STOP condition. Therefore, the 300 ns

SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for the

chip as transmitter, see Determining the I²C Frequency Divider Ratio for SCL (AN2919).

4. The maximum t_I2OVKLhas to be met only if the device does not stretch the LOW period (t_I2CL) of the SCL signal.

5. For recommended operating conditions, see Table 3.

This figure provides the AC test load for the I²C.

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Output

DV_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 28. I²C AC test load

This figure shows the AC timing diagram for the I²C bus.

SDA

t_I2KHKL

t_I2DVKH

t_I2KHDX

t_I2SXKL

t_I2CL

SCL

t_I2CH

t_I2SVKH

t_I2PVKH

t_I2SXKL

t_I2DXKL, t_I2OVKL

P

S

Sr

Figure 29. I²C Bus AC timing diagram

3.18 GPIO interface

This section describes the DC and AC electrical characteristics for the GPIO interface.

3.18.1 GPIO DC electrical characteristics

This table provides the DC electrical characteristics for GPIO pins operating at LV_DD

2.5 V.

=

Table 57. GPIO DC electrical characteristics (2.5 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

1.7

-

V

1

2

-

Input low voltage

0.7

50

-

V

Input current (V_IN= 0 V or V_IN= LV_DD)

Output high voltage

-50

2.0

μA

V

V_OH

(LV_DD= min, I_OH= -1 mA)

Table continues on the next page...

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Table 57. GPIO DC electrical characteristics (2.5 V)³(continued)

Parameter

Output low voltage

(LV_DD= min, I_OL= 1 mA)

Symbol

Min

Max

Unit

Notes

V_OL

-

0.4

V

-

1. The min V_ILand max V_IHvalues are based on the respective min and max LV_INvalues found in Table 3 .

2. The symbol V_IN, in this case, represents the LV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for GPIO pins operating at LV_DDor

OV_DD= 1.8 V.

Table 58. GPIO DC electrical characteristics (1.8 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

1.25

-

V

1

2

-

Input low voltage

0.6

50

-

V

Input current (V_IN= 0 V or V_IN= L/OV_DD

)

-50

1.35

μA

V

Output high voltage

V_OH

(L/OV_DD= min, I_OH= -0.5 mA)

Output low voltage

V_OL

-

0.4

V

-

(L/OV_DD= min, I_OL= 0.5 mA)

1. The min V_ILand max V_IHvalues are based on the respective min and max L/OV_INvalues found in Table 3.

2. The symbol V_IN, in this case, represents the L/OV_INsymbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

This table provides the DC electrical characteristics for the LP Trust pin,

LP_TMP_DETECT_B, operating at V_DDLP = 1 V.

Table 59. LP_TMP_DETECT_B Pin DC electrical characteristics (1 V)³

Parameter

Input high voltage

Symbol

Min

Max

Unit

Notes

V_IH

V_IL

I_IN

0.8 x V_{DD_LP}

-

V

1

2

Input low voltage

-

0.4 x V_{DD_LP}

V

Input current (V_{IN_LP}= 0 V or V_{IN_LP}

=

-50

50

μA

V_{DD_LP}

)

1. The min V_ILand max V_IHvalues are based on the respective min and max V_{DD_LP}values found in Table 3.

2. The symbol V_{IN_LP}, in this case, represents the V_{IN_LP}symbol referenced in Recommended operating conditions.

3. For recommended operating conditions, see Table 3.

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3.18.2 GPIO AC timing specifications

This table provides the GPIO input and output AC timing specifications.

Table 60. GPIO input AC timing specifications²

Parameter/Condition

GPIO inputs—minimum pulse width

Symbol

t_PIWID

Min

Unit

Notes

20

ns

1

Notes:

1. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any

external synchronous logic. GPIO inputs are required to be valid for at least t_PIWIDto ensure proper operation.

2. For recommended operating conditions, see Table 3.

This figure provides the AC test load for the GPIO.

Output

(L/O) V_DD/2

Z₀= 50 Ω

R_L= 50 Ω

Figure 30. GPIO AC test load

3.19 High-speed serial interfaces (HSSI)

The chip features a serializer/deserializer (SerDes) interface to be used for high-speed

serial interconnect applications. The SerDes interface can be used for PCI Express,

SATA, Serial RapidIO, XAUI, XFI, 10GBase-KR, Aurora, Interlaken LA, HiGig/

HiGig2, SGMII, 2.5x SGMII and QSGMII data transfers.

This section describes the common portion of SerDes DC electrical specifications: the

DC requirement for SerDes reference clocks. The SerDes data lane's transmitter (Tx) and

receiver (Rx) reference circuits are also shown.

3.19.1 Signal terms definition

The SerDes utilizes differential signaling to transfer data across the serial link. This

section defines the terms that are used in the description and specification of differential

signals.

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This figure shows how the signals are defined. For illustration purposes only, one SerDes

lane is used in the description. This figure shows the waveform for either a transmitter

output (SD_TXn and SD_TXn_B) or a receiver input (SD_RXn and SD_RXn_B). Each

signal swings between A volts and B volts where A > B.

SD_TXn or

SD_RXn

A Volts

V_cm= (A + B)/2

SD_TXn_B or

SD_RXn_B

B Volts

Differential swing, V_IDorV_OD= A - B

Differential peak voltage, V_DIFFp= |A - B|

Differential peak-to-peak voltage, V_DIFFpp=2 x V_DIFFp(not shown)

Figure 31. Differential voltage definitions for transmitter or receiver

Using this waveform, the definitions are as shown in the following list. To simplify the

illustration, the definitions assume that the SerDes transmitter and receiver operate in a

fully symmetrical differential signaling environment:

Single-Ended Swing

The transmitter output signals and the receiver input signals SD_TXn, SD_TXn_B,

SD_RXn and SD_RXn_B each have a peak-to-peak swing of A - B volts. This is also

referred as each signal wire's single-ended swing.

Differential Output Voltage, V_OD(or Differential Output Swing)

The differential output voltage (or swing) of the transmitter, V_OD, is defined as the

difference of the two complementary output voltages: V_{SD_TXn}- V_{SD_TXn_B.}The V_OD

value can be either positive or negative.

Differential Input Voltage, V_ID(or Differential Input Swing)

The differential input voltage (or swing) of the receiver, V_ID, is defined as the

difference of the two complementary input voltages: V_{SD_RXn}- V_{SD_RXn_B.}The V_ID

value can be either positive or negative.

Differential Peak Voltage, V_DIFFp

The peak value of the differential transmitter output signal or the differential receiver

input signal is defined as the differential peak voltage, V_DIFFp= |A - B| volts.

Differential Peak-to-Peak, V_DIFFp-p

Since the differential output signal of the transmitter and the differential input signal of

the receiver each range from A - B to -(A - B) volts, the peak-to-peak value of the

differential transmitter output signal or the differential receiver input signal is defined

as differential peak-to-peak voltage, V_DIFFp-p= 2 x V_DIFFp= 2 x |(A - B)| volts, which

is twice the differential swing in amplitude, or twice of the differential peak. For

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example, the output differential peak-to-peak voltage can also be calculated as V_TX-

_DIFFp-p= 2 x |V_OD|.

Differential Waveform

The differential waveform is constructed by subtracting the inverting signal

(SD_TXn_B, for example) from the non-inverting signal (SD_TXn, for example)

within a differential pair. There is only one signal trace curve in a differential

waveform. The voltage represented in the differential waveform is not referenced to

ground. See Figure 36 as an example for differential waveform.

Common Mode Voltage, V_cm

The common mode voltage is equal to half of the sum of the voltages between each

conductor of a balanced interchange circuit and ground. In this example, for SerDes

output, V_{cm_out}= (V_{SD_TXn}+ V_{SD_TXn_B}) ÷ 2 = (A + B) ÷ 2, which is the arithmetic

mean of the two complementary output voltages within a differential pair. In a system,

the common mode voltage may often differ from one component's output to the other's

input. It may be different between the receiver input and driver output circuits within

the same component. It is also referred to as the DC offset on some occasions.

To illustrate these definitions using real values, consider the example of a current mode

logic (CML) transmitter that has a common mode voltage of 2.25 V and outputs, TD and

TD_B. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak voltage swing

of each signal (TD or TD_B) is 500 mV p-p, which is referred to as the single-ended

swing for each signal. Because the differential signaling environment is fully symmetrical

in this example, the transmitter output's differential swing (V_OD) has the same amplitude

as each signal's single-ended swing. The differential output signal ranges between 500

mV and -500 mV. In other words, V_ODis 500 mV in one phase and -500 mV in the other

phase. The peak differential voltage (V_DIFFp) is 500 mV. The peak-to-peak differential

voltage (V_DIFFp-p) is 1000 mV p-p.

3.19.2 SerDes reference clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates

the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are

SD1_REF_CLK[1:2] and SD1_REF_CLK[1:2]_B for SerDes 1, SD2_REF_CLK[1:2]

and SD2_REF_CLK[1:2]_B for SerDes 2, SD3_REF_CLK[1:2] and

SD3_REF_CLK[1:2]_B for SerDes 3 and SD4_REF_CLK[1:2] and

SD4_REF_CLK[1:2]_B for SerDes 4.

SerDes 1-4 may be used for various combinations of the following IP blocks based on the

RCW Configuration field SRDS_PRTCLn:

• SerDes 1: SGMII (1.25 and 3.125 Gbaud), QSGMII (5 Gbps only), HiGig/HiGig2

(3.125 Gbps), HiGig/HiGig2 (3.75 Gbps) or XAUI (3.125 Gb/s)

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• SerDes 2: SGMII (1.25 and 3.125 Gbaud), QSGMII (5 Gbps only), XAUI (3.125

Gb/s), HiGig/HiGig2 (3.125 Gbps), HiGig/HiGig2 (3.75 Gbps), XFI (10.3125 Gb/s

only) or 10GBase-KR (10.3125 Gbaud only)

• SerDes 3: PEX1/2 (2.5, 5, and 8 GT/s), SRIO1(2.5, 3.125, and 5 Gbaud) or

Interlaken-LA(6.25)

• SerDes 4: PEX3/4 (2.5, 5, and 8 GT/s), SRIO2(2.5, 3.125, and 5 Gbaud), Aurora

(2.5, 3.125, and 5 Gbps) or SATA1/2 (1.5 and 3.0 Gbps)

The following sections describe the SerDes reference clock requirements and provide

application information.

3.19.2.1 SerDes spread-spectrum clock source recommendations

SDn_REF_CLKn/SDn_REF_CLKn_B are designed to work with spread-spectrum clock

for PCI Express protocol only with the spreading specification defined in Table 61. When

using spread-spectrum clocking for PCI Express, both ends of the link partners should

use the same reference clock. For best results, a source without significant unintended

modulation must be used.

For SATA protocol, the SerDes transmitter does not support spread-spectrum clocking.

The SerDes receiver does support spread-spectrum clocking on receive, which means the

SerDes receiver can receive data correctly from a SATA serial link partner using spread-

spectrum clocking

The spread-spectrum clocking cannot be used if the same SerDes reference clock is

shared with other non-spread-spectrum supported protocols. For example, if the spread-

spectrum clocking is desired on a SerDes reference clock for PCI Express and the same

reference clock is used for any other protocol such as SATA/SGMII/QSGMII/SRIO/

XAUI due to the SerDes lane usage mapping option, spread-spectrum clocking cannot be

used at all.

Table 61. SerDes spread-spectrum clock source recommendations ¹

Parameter

Min

Max

Unit

Notes

Frequency modulation

Frequency spread

30

+0

33

kHz

%

-

-0.5

2

1. At recommended operating conditions. See Table 3.

2. Only down-spreading is allowed.

3.19.2.2 SerDes reference clock receiver characteristics

This figure shows a receiver reference diagram of the SerDes reference clocks.

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Electrical characteristics

50 Ω

SDn_REF_CLKn

Input

amp

SDn_REF_CLKn_B

50 Ω

Figure 32. Receiver of SerDes reference clocks

The characteristics of the clock signals are as follows:

• The SerDes transceivers core power supply voltage requirements (SV_DDn) are as

specified in Recommended operating conditions.

• The SerDes reference clock receiver reference circuit structure is as follows:

• The SDn_REF_CLKn and SDn_REF_CLKn_B are internally AC-coupled

differential inputs as shown in Figure 32. Each differential clock input

(SDn_REF_CLKn or SDn_REF_CLKn_B) has on-chip 50 Ω termination to

SGNDn followed by on-chip AC-coupling.

• The external reference clock driver must be able to drive this termination.

• The SerDes reference clock input can be either differential or single-ended. See

the differential mode and single-ended mode descriptions below for detailed

requirements.

• The maximum average current requirement also determines the common mode

voltage range.

• When the SerDes reference clock differential inputs are DC coupled externally

with the clock driver chip, the maximum average current allowed for each input

pin is 8 mA. In this case, the exact common mode input voltage is not critical as

long as it is within the range allowed by the maximum average current of 8 mA

because the input is AC-coupled on-chip.

• This current limitation sets the maximum common mode input voltage to be less

than 0.4 V (0.4 V ÷ 50 Ω = 8 mA) while the minimum common mode input level

is 0.1 V above SGNDn. For example, a clock with a 50/50 duty cycle can be

produced by a clock driver with output driven by its current source from 0 mA to

16 mA (0-0.8 V), such that each phase of the differential input has a single-

ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.

• If the device driving the SDn_REF_CLKn and SDn_REF_CLKn_B inputs

cannot drive 50 Ω to SGNDn DC or the drive strength of the clock driver chip

exceeds the maximum input current limitations, it must be AC-coupled off-chip.

• The input amplitude requirement is described in detail in the following sections.

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3.19.2.3 DC-level requirement for SerDes reference clocks

The DC level requirement for the SerDes reference clock inputs is different depending on

the signaling mode used to connect the clock driver chip and SerDes reference clock

inputs, as described below:

• Differential Mode

• The input amplitude of the differential clock must be between 400 mV and 1600

mV differential peak-to-peak (or between 200 mV and 800 mV differential

peak). In other words, each signal wire of the differential pair must have a

single-ended swing of less than 800 mV and greater than 200 mV. This

requirement is the same for both external DC-coupled or AC-coupled

connection.

• For an external DC-coupled connection, as described in SerDes reference clock

receiver characteristics, the maximum average current requirements sets the

requirement for average voltage (common mode voltage) as between 100 mV

and 400 mV. Figure 33 shows the SerDes reference clock input requirement for

DC-coupled connection scheme.

200 mV < Input amplitude or differential peak < 800 mV

SDn_REF_CLKn

Vmax < 800mV

100 mV < Vcm < 400 mV

Vmin > 0 V

SDn_REF_CLKn_B

Figure 33. Differential reference clock input DC requirements (external DC-coupled)

• For an external AC-coupled connection, there is no common mode voltage

requirement for the clock driver. Because the external AC-coupling capacitor

blocks the DC level, the clock driver and the SerDes reference clock receiver

operate in different common mode voltages. The SerDes reference clock receiver

in this connection scheme has its common mode voltage set to SGNDn. Each

signal wire of the differential inputs is allowed to swing below and above the

common mode voltage (SGNDn). Figure 34 shows the SerDes reference clock

input requirement for AC-coupled connection scheme.

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Electrical characteristics

200 mV < Input amplitude or differential peak < 800 mV

SDn_REF_CLKn

Vmax < Vcm + 400 mV

Vcm

Vmin > Vcm - 400 mV

SDn_REF_CLK_B

Figure 34. Differential reference clock input DC requirements (external AC-coupled)

• Single-Ended Mode

• The reference clock can also be single-ended. The SDn_REF_CLKn input

amplitude (single-ended swing) must be between 400 mV and 800 mV peak-to-

peak (from V_MINto V_MAX) with SDn_REF_CLKn_B either left unconnected or

tied to ground.

• The SDn_REF_CLKn input average voltage must be between 200 and 400 mV.

Figure 35 shows the SerDes reference clock input requirement for single-ended

signaling mode.

• To meet the input amplitude requirement, the reference clock inputs may need to

be DC- or AC-coupled externally. For the best noise performance, the reference

of the clock could be DC- or AC-coupled into the unused phase

(SDn_REF_CLKn_B) through the same source impedance as the clock input

(SDn_REF_CLKn) in use.

400 mV < SD_REF_CLKn input amplitude < 800 mV

SDn_REF_CLKn

0 V

SDn_REF_CLKn_B

Figure 35. Single-ended reference clock input DC requirements

3.19.2.4 AC requirements for SerDes reference clocks

This table lists the AC requirements for SerDes reference clocks for protocols running at

data rates up to 8 Gb/s.

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Electrical characteristics

This includes PCI Express (2.5, 5, 8 GT/s), SGMII (1.25 Gbaud), 2.5x SGMII

(3.125 Gbaud), QSGMII (5 Gbps), Serial RapidIO (2.5, 3.125, 5 Gbaud), Aurora (2.5,

3.125, 5 Gbps), HiGig/HiGig2 (3.125 Gbps), HiGig/HiGig2 (3.75 Gbps), XAUI

(3.125 Gb/s) and Interlaken-LA (6.25 Gbps) SerDes reference clocks to be guaranteed by

the customer's application design.

Table 62. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SnV_DD= 1.0 V)

1

Parameter

Symbol

t_{CLK_REF}

Min

Typ

Max

Unit

MHz

Notes

SDn_REF_CLKn/ SDn_REF_CLKn_B frequency

range

-

100/125/156.25

-

2

SDn_REF_CLKn/ SDn_REF_CLKn_B clock

frequency tolerance

t_{CLK_TOL}

t_{CLK_DUTY}

t_{CLK_DJ}

-300

-100

40

-

300

100

60

ppm

%

3, 12

SDn_REF_CLKn/ SDn_REF_CLKn_B clock

frequency tolerance

-

4, 12

SDn_REF_CLKn/ SDn_REF_CLKn_B reference

clock duty cycle

50

-

5

-

SDn_REF_CLKn/ SDn_REF_CLKn_B max

deterministic peak-to-peak jitter at 10^-6BER

42

ps

SDn_REF_CLKn/ SDn_REF_CLKn_B total reference t_{CLK_TJ}

clock jitter at 10^-6BER (peak-to-peak jitter at refClk

input)

-

86

ps

6

SDn_REF_CLKn/ SDn_REF_CLKn_B 10 kHz to 1.5 t_{REFCLK-LF-RMS}

MHz RMS jitter

-

3

ps

RMS

7

8

9

5

SDn_REF_CLKn/ SDn_REF_CLKn_B > 1.5 MHz to t_{REFCLK-HF-RMS}

Nyquist RMS jitter

-

3.1

1

ps

RMS

SDn_REF_CLKn/ SDn_REF_CLKn_B RMS

reference clock jitter

t_{REFCLK-RMS-DC}

-

ps

RMS

SDn_REF_CLKn/ SDn_REF_CLKn_B rising/falling

edge rate

t_{CLKRR/ CLKFR}

t

1

4

V/ns

Differential input high voltage

-

V_CM

+200 m

V

-

mV

Differential input low voltage

-

V_CM-20 mV

0 mV

5

Rising edge rate (SDn_REF_CLKn) to falling edge

rate (SDn_REF_CLKn) matching

Rise-Fall

Matching

-

20

%

10, 11

1. For recommended operating conditions, see Table 3.

2. Caution: Only 100, 125 and 156.25 have been tested.In-between values do not work correctly with the rest of the system.

3. For PCI Express (2.5, 5, 8 GT/s)

4. For SGMII, 2.5x SGMII, QSGMII, sRIO, HiGig/HiGig2, XAUI, Interlaken-LA, Aurora

5. Measurement taken from differential waveform. VCM is the common mode voltage.

6. Limits from PCI Express CEM Rev 2.0

7. For PCI Express-5 GT/s, per PCI Express base specification rev 3.0

8. For PCI-Express-8 GT/s, per PCI-Express base specification rev 3.0

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Table 62. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SnV_DD= 1.0 V)

1

Parameter

Symbol

Min

Typ

Max

Unit

Notes

9. Measured from -200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLKn minus

SDn_REF_CLKn_B). The signal must be monotonic through the measurement region for rise and fall time. The 400 mV

measurement window is centered on the differential zero crossing. See Figure 36.

10. Measurement taken from single-ended waveform

11. Matching applies to rising edge for SDn_REF_CLKn and falling edge rate for SDn_REF_CLKn_B. It is measured using a

200 mV window centered on the median cross point where SDn_REF_CLKn rising meets SDn_REF_CLKn_B falling. The

median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The

rise edge rate of SDn_REF_CLKn must be compared to the fall edge rate of SDn_REF_CLKn_B, the maximum allowed

difference should not exceed 20% of the slowest edge rate. See Figure 37.

12. When 2 or more protocols share the same PLL on a SerDes module, the tightest SDn_REF_CLKn/ SDn_REF_CLKn_B

clock frequency tolerance must be followed.

This table lists the AC requirements for SerDes reference clocks for protocols running at

data rates greater than 8 Gb/s.

This includes XFI (10.3125 Gb/s) and 10GBase-KR (10.3125 GBd) SerDes reference

clocks to be guaranteed by the customer's application design.

Table 63. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SV_DDn = 1.0 V)

1

Parameter

Symbol

Min

Typ

156.25/

Max

Unit

MHz

Notes

SDn_REF_CLKn/ SDn_REF_CLKn_B frequency range

t_{CLK_REF}

-

2

161.1328135

SDn_REF_CLKn/ SDn_REF_CLKn_B clock frequency

tolerance

t_{CLK_TOL}

-100

-

100

60

ppm

%

5

3

SDn_REF_CLKn/ SDn_REF_CLKn_B reference clock duty t_{CLK_DUTY}40

cycle

50

-

SDn_REF_CLKn/ SDn_REF_CLKn_B single side band

noise

@1 kHz

-

-85

dBC/Hz 4

SDn_REF_CLKn/ SDn_REF_CLKn_B single side band

noise

@10 kHz

-

-108

-128

-138

0.8

SDn_REF_CLKn/ SDn_REF_CLKn_B single side band

noise

@100 kH

z

-

SDn_REF_CLKn/ SDn_REF_CLKn_B single side band

noise

@1 MHz

-

SDn_REF_CLKn/ SDn_REF_CLKn_B single side band

noise

@10 MHz -

-

SDn_REF_CLKn/ SDn_REF_CLKn_B random jitter

(1.2 MHz to 15 MHz)

t_{CLK_RJ}

-

ps

-

SDn_REF_CLKn/ SDn_REF_CLKn_B total reference clock t_{CLK_TJ}

jitter at 10^-12BER (1.2 MHz to 15 MHz)

-

11

ps

SDn_REF_CLKn/ SDn_REF_CLKn_B spurious noise

(1.2 MHz to 15 MHz)

-

-75

dBC

Table continues on the next page...

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Electrical characteristics

Table 63. SDn_REF_CLKn and SDn_REF_CLKn_B input clock requirements (SV_DDn = 1.0 V)

¹(continued)

Parameter

Differential input high voltage

Symbol

Min

V_CM

+200 m

V

Typ

Max

Unit

mV

Notes

-

6

Differential input low voltage

-

V_CM-20 mV

0 mV

6

Rising edge rate (SDn_REF_CLKn) to falling edge rate

(SDn_REF_CLKn) matching

Rise-Fall

Matching

-

20

%

7, 8

1. For recommended operating conditions, see Table 3.

2. Caution: Only 156.25 and 161.1328135 have been tested. In-between values do not work correctly with the rest of the

system.

3. Measurement taken from differential waveform.

4. Per XFP Spec. Rev 4.5, the Module Jitter Generation spec at XFI Optical Output is 10mUI (RMS) and 100 mUI (p-p). In the

CDR mode the host is contributing 7 mUI (RMS) and 50 mUI (p-p) jitter.

5. When 2 or more protocols share the same PLL on a SerDes module, the tightest SDn_REF_CLKn/ SDn_REF_CLKn_B

clock frequency tolerance must be followed.

6. Measurement taken from differential waveform. VCM is the common mode voltage.

7. Measurement taken from single-ended waveform .

8. Matching applies to rising edge for SDn_REF_CLKn and falling edge rate for SDn_REF_CLKn_B. It is measured using a

200 mV window centered on the median cross point where SDn_REF_CLKn rising meets SDn_REF_CLKn_B falling. The

median cross point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The

rise edge rate of SDn_REF_CLKn must be compared to the fall edge rate of SDn_REF_CLKn_B, the maximum allowed

difference should not exceed 20% of the slowest edge rate. See Figure 37.

Rise-edge rate

Fall-edge rate

V_IH= + 200 mV

0.0 V

V_IL= - 200 mV

SDn_REF_CLKn

SDn_REF_CLKn_B

Figure 36. Differential measurement points for rise and fall time

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Electrical characteristics

SDn_REF_CLKn_B

T

RISE

FALL

V_{CROSS MEDIAN}+ 100 mV

V_{CROSS MEDIAN}

V_{CROSS MEDIAN}- 100 mV

SDn_REF_CLKn

Figure 37. Single-ended measurement points for rise and fall time matching

3.19.3 SerDes transmitter and receiver reference circuits

This figure shows the reference circuits for SerDes data lane's transmitter and receiver.

SDn_TXn

SDn_RXn

50 Ω

Transmitter

100 Ω

Receiver

SDn_TXn_B

SDn_RXn_B

Figure 38. SerDes transmitter and receiver reference circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol

section below based on the application usage:

• PCI Express

• Serial RapidIO (sRIO)

• XAUI interface

• Aurora interface

• Serial ATA (SATA) interface

• SGMII interface

• QSGMII interface

• HiGig/HiGig2 interface

• XFI interface

• Interlaken interface

Note that external AC-coupling capacitor is required for the above serial transmission

protocols with the capacitor value defined in the specification of each protocol section.

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3.19.4 PCI Express

This section describes the clocking dependencies, DC and AC electrical specifications for

the PCI Express bus.

3.19.4.1 Clocking dependencies

The ports on the two ends of a link must transmit data at a rate that is within 600 parts per

million (ppm) of each other at all times. This is specified to allow bit rate clock sources

with a 300 ppm tolerance.

3.19.4.2 PCI Express clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

SerDes 3-4 (SD[3:4]_REF_CLK[1:2] and SD[3:4]_REF_CLK[1:2]_B) may be used for

various SerDes PCI Express configurations based on the RCW Configuration field

SRDS_PRTCL. PCI Express is not supported on SerDes 1 and 2.

NOTE

PCI Express operating in x8 mode is only supported at 2.5 and

5.0 GT/s.

For more information on these specifications, see SerDes reference clocks.

3.19.4.3 PCI Express DC physical layer specifications

This section contains the DC specifications for the physical layer of PCI Express on this

chip.

3.19.4.3.1 PCI Express DC physical layer transmitter specifications

This section discusses the PCI Express DC physical layer transmitter specifications for

2.5 GT/s, 5 GT/s and 8 GT/s.

This table defines the PCI Express 2.0 (2.5 GT/s) DC specifications for the differential

output at all transmitters. The parameters are specified at the component pins.

Table 64. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XV_DD

= 1.35 V or 1.5 V)¹

Parameter

Symbol

Min Typical Max Units

800 1000 1200 mV

Notes

Differential peak-to-peak

output voltage

V_TX-DIFFp-p

V_TX-DIFFp-p= 2 x │ V_TX-D+- V_TX-D-│

Table continues on the next page...

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Table 64. PCI Express 2.0 (2.5 GT/s) differential transmitter output DC specifications (XV_DD

= 1.35 V or 1.5 V)¹(continued)

Parameter

Symbol

Min Typical Max Units

Notes

De-emphasized differential V_TX-DE-RATIO3.0

output voltage (ratio)

3.5

4.0

dB

Ratio of the V_TX-DIFFp-pof the second and

following bits after a transition divided by the V_TX-

_DIFFp-pof the first bit after a transition.

DC differential transmitter Z_TX-DIFF-DC80

impedance

100

50

120

60

Ω

Transmitter DC differential mode low Impedance

Transmitter DC impedance Z_TX-DC

40

Required transmitter D+ as well as D- DC

Impedance during all states

Notes:

1. For recommended operating conditions, see Table 3.

This table defines the PCI Express 2.0 (5 GT/s) DC specifications for the differential

output at all transmitters. The parameters are specified at the component pins.

Table 65. PCI Express 2.0 (5 GT/s) differential transmitter output DC specifications (XV_DD

1.35 V or 1.5 V)¹

=

Parameter

Symbol

V_TX-DIFFp-p

Min Typical Max Units

Notes

Differential peak-to-peak

output voltage

800

1000

1200 mV

V_TX-DIFFp-p= 2 x │ V_TX-D+- V_TX-D-

│

Low power differential

peak-to-peak output

voltage

V_{TX-DIFFp-p_low}

400

500

1200 mV

V_TX-DIFFp-p= 2 x │ V_TX-D+- V_TX-D-

De-emphasized differential V_{TX-DE-RATIO-3.5dB}3.0

output voltage (ratio)

3.5

6.0

4.0

6.5

dB

Ratio of the V_TX-DIFFp-pof the second and

following bits after a transition divided by the

V_TX-DIFFp-pof the first bit after a transition.

De-emphasized differential V_{TX-DE-RATIO-6.0dB}5.5

output voltage (ratio)

Ratio of the V_TX-DIFFp-pof the second and

following bits after a transition divided by the

V_TX-DIFFp-pof the first bit after a transition.

DC differential transmitter Z_TX-DIFF-DC

impedance

80

40

100

50

120

60

Ω

Transmitter DC differential mode low

impedance

Transmitter DC

Impedance

Z_TX-DC

Required transmitter D+ as well as D- DC

impedance during all states

Notes:

1. For recommended operating conditions, see Table 3.

This table defines the PCI Express 3.0 (8 GT/s) DC specifications for the differential

output at all transmitters. The parameters are specified at the component pins.

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Table 66. PCI Express 3.0 (8 GT/s) differential transmitter output DC specifications (XV_DD

1.35 V or 1.5 V)³

=

Parameter

Symbol

Min Typical Max

Units

Notes

Full swing transmitter

voltage with no TX Eq

V_TX-FS-NO-EQ

800

-

1300 mVp-p See Note 1.

Reduced swing

transmitter voltage with

no TX Eq

V_TX-RS-NO-EQ

400

-

1300 mV

See Note 1.

De-emphasized

differential output voltage

(ratio)

V_{TX-DE-RATIO-3.5dB}3.0

3.5

6.0

4.0

6.5

dB

-

De-emphasized

differential output voltage

(ratio)

V_{TX-DE-RATIO-6.0dB}5.5

Minimum swing during

EIEOS for full swing

V_TX-EIEOS-FS

V_TX-EIEOS-RS

250

232

80

-

mVp-p See Note 2

Minimum swing during

EIEOS for reduced swing

-

DC differential transmitter Z_TX-DIFF-DC

impedance

100

50

120

60

Ω

Transmitter DC differential mode low

impedance

Transmitter DC

Impedance

Z_TX-DC

40

Required transmitter D+ as well as D- DC

impedance during all states

Notes:

1. Voltage measurements for V_TX-FS-NO-EQand V_TX-RS-NO-EQare made using the 64-zeroes/64-ones pattern in the compliance

pattern.

2. Voltage limits comprehend both full swing and reduced swing modes. The transmitter must reject any changes that would

violate this specification. The maximum level is covered in the V_TX-FS-NO-EQmeasurement which represents the maximum

peak voltage the transmitter can drive. The V_TX-EIEOS-FSand V_TX-EIEOS-RSvoltage limits are imposed to guarantee the EIEOS

threshold of 175 mV_P-Pat the receiver pin. This parameter is measured using the actual EIEOS pattern that is part of the

compliance pattern and then removing the ISI contribution of the breakout channel.

3. For recommended operating conditions, see Table 3.

3.19.4.4 PCI Express DC physical layer receiver specifications

This section discusses the PCI Express DC physical layer receiver specifications for 2.5

GT/s, 5 GT/s and 8 GT/s.

This table defines the DC specifications for the PCI Express 2.0 (2.5 GT/s) differential

input at all receivers. The parameters are specified at the component pins.

Table 67. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁴

Parameter

Symbol

V_RX-DIFFp-p

Min

Typ

Max Units

Notes

Differential input peak-to-peak

voltage

120 1000

1200 mV

V_RX-DIFFp-p= 2 x |V_RX-D+- V_RX-D-| See

Note 1.

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Table 67. PCI Express 2.0 (2.5 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁴(continued)

Parameter

Symbol

Min

80

Typ

100

Max Units

Notes

DC differential input impedance

Z_RX-DIFF-DC

120

Ω

Receiver DC differential mode

impedance. See Note 2

DC input impedance

Z_RX-DC

40

50

-

60

Ω

Required receiver D+ as well as D- DC

Impedance (50 20% tolerance). See

Notes 1 and 2.

Powered down DC input impedance Z_{RX-HIGH-IMP-DC}50

-

kΩ

Required receiver D+ as well as D- DC

Impedance when the receiver

terminations do not have power. See

Note 3.

Electrical idle detect threshold

V_RX-IDLE-DET-

65

-

175 mV

V_{RX-IDLE-DET-DIFFp-p}= 2 x |V_RX-D+-V_RX-

|

DIFFp-p

D-

Measured at the package pins of the

receiver

Notes:

1. Measured at the package pins with a test load of 50Ω to GND on each pin.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This

helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must

be measured at 300 mV above the receiver ground.

4. For recommended operating conditions, see Table 3.

This table defines the DC specifications for the PCI Express 2.0 (5 GT/s) differential

input at all receivers. The parameters are specified at the component pins.

Table 68. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁴

Parameter

Symbol

Min

Typ

Max Units

Notes

Differential input peak-to-peak voltage V_RX-DIFFp-p

120 1000

1200 mV

V_RX-DIFFp-p= 2 x |V_RX-D+- V_RX-D-

See Note 1.

|

DC differential input impedance

DC input impedance

Z_RX-DIFF-DC

Z_RX-DC

80

40

100

50

120

60

Ω

Receiver DC differential mode

impedance. See Note 2

Required receiver D+ as well as D-

DC Impedance (50 20%

tolerance). See Notes 1 and 2.

Powered down DC input impedance

Electrical idle detect threshold

Z_{RX-HIGH-IMP-DC}50

-

kΩ

Required receiver D+ as well as D-

DC Impedance when the receiver

terminations do not have power.

See Note 3.

V_RX-IDLE-DET-

65

175 mV

V_{RX-IDLE-DET-DIFFp-p}= 2 x |V_RX-D+

V_RX-D-

-

|

DIFFp-p

Measured at the package pins of

the receiver

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Table 68. PCI Express 2.0 (5 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁴(continued)

Parameter

Symbol

Min

Typ

Max Units

Notes

Notes:

1. Measured at the package pins with a test load of 50 Ω to GND on each pin.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This

helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must

be measured at 300 mV above the receiver ground.

4. For recommended operating conditions, see Table 3.

This table defines the DC specifications for the PCI Express 3.0 (8 GT/s) differential

input at all receivers. The parameters are specified at the component pins.

Table 69. PCI Express 3.0 (8 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁶

Parameter

Symbol

Min

80

Typ

100

Max Units

Notes

DC differential input impedance

Z_RX-DIFF-DC

120

Ω

Receiver DC differential mode

impedance. See Note 2

DC input impedance

Z_RX-DC

40

50

-

60

Ω

Required receiver D+ as well as D-

DC Impedance (50 20%

tolerance). See Notes 1 and 2.

Powered down DC input impedance

Z_{RX-HIGH-IMP-DC}50

-

kΩ

Required receiver D+ as well as D-

DC Impedance when the receiver

terminations do not have power.

See Note 3.

Generator launch voltage

Eye height (-20dB Channel)

Eye height (-12dB Channel)

Eye height (-3dB Channel)

Electrical idle detect threshold

V_RX-LAUNCH-8G

V_RX-SV-8G

-

800

-

mV

Measured at TP1 per PCI Express

base spec. rev 3.0

25

50

200

65

-

Measured at TP2P per PCI Express

base spec. rev 3.0. See Notes 4, 5

V_RX-SV-8G

Measured at TP2P per PCI Express

base spec. rev 3.0. See Notes 4, 5

V_RX-SV-8G

Measured at TP2P per PCI Express

base spec. rev 3.0. See Notes 4, 5

V_RX-IDLE-DET-

175 mV

V_{RX-IDLE-DET-DIFFp-p}= 2 x |V_RX-D+

V_RX-D-

-

|

DIFFp-p

Measured at the package pins of

the receiver

Notes:

1. Measured at the package pins with a test load of 50Ω to GND on each pin.

2. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)

there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.

3. The receiver DC common mode impedance that exists when no power is present or fundamental reset is asserted. This

helps ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must

be measured at 300 mV above the receiver ground.

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Table 69. PCI Express 3.0 (8 GT/s) differential receiver input DC specifications (SV_DD= 1.0

V)⁶

Parameter

Symbol

Min

Typ

Max Units

Notes

4. V_RX-SV-8Gis tested at three different voltages to ensure the receiver device under test is capable of equalizing over a range

of channel loss profiles. The "SV" in the parameter names refers to stressed voltage.

5. V_RX-SV-8Gis referenced to TP2P and is obtained after post processing data captured at TP2.

6. For recommended operating conditions, see Table 3.

3.19.4.5 PCI Express AC physical layer specifications

This section contains the AC specifications for the physical layer of PCI Express on this

device.

3.19.4.5.1 PCI Express AC physical layer transmitter specifications

This section discusses the PCI Express AC physical layer transmitter specifications for

2.5 GT/s, 5 GT/s and 8 GT/s.

This table defines the PCI Express 2.0 (2.5 GT/s) AC specifications for the differential

output at all transmitters. The parameters are specified at the component pins. The AC

timing specifications do not include RefClk jitter.

Table 70. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications⁴

Parameter

Unit interval

Symbol

Min

Typ

Max

Units

Notes

UI

399.88 400 400.12 ps

Each UI is 400 ps 300 ppm. UI does not

account for spread-spectrum clock dictated

variations.

Minimum transmitter eye

width

T_TX-EYE

0.75

-

UI

The maximum transmitter jitter can be

derived as T_{TX-MAX-JITTER}= 1 - T_TX-EYE

=

0.25 UI. Does not include spread-spectrum

or RefCLK jitter. Includes device random

jitter at 10^-12

.

See Notes 1 and 2.

Maximum time between the T_{TX-EYE-MEDIAN-}

jitter median and maximum

deviation from the median

-

0.125 UI

Jitter is defined as the measurement

variation of the crossing points (V_TX-DIFFp-p

0 V) in relation to a recovered transmitter

UI. A recovered transmitter UI is calculated

over 3500 consecutive unit intervals of

sample data. Jitter is measured using all

edges of the 250 consecutive UI in the

center of the 3500 UI used for calculating

the transmitter UI. See Notes 1 and 2.

=

to- MAX-JITTER

AC coupling capacitor

C_TX

75

-

200

nF

All transmitters must be AC coupled. The

AC coupling is required either within the

media or within the transmitting component

itself. See Note 3.

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Table 70. PCI Express 2.0 (2.5 GT/s) differential transmitter output AC specifications⁴

(continued)

Parameter

Symbol

Min

Typ

Max

Units

Notes

Notes:

1. Specified at the measurement point into a timing and voltage test load as shown in Figure 40 and measured over any 250

consecutive transmitter UIs.

2. A T_TX-EYE= 0.75 UI provides for a total sum of deterministic and random jitter budget of T_{TX-JITTER-MAX}= 0.25 UI for the

transmitter collected over any 250 consecutive transmitter UIs. The T_{TX-EYE-MEDIAN-to-MAX-JITTER}median is less than half of the

total transmitter jitter budget collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the

same as the mean. The jitter median describes the point in time where the number of jitter points on either side is

approximately equal as opposed to the averaged time value.

3. The chip's SerDes transmitter does not have C_TXbuilt-in. An external AC coupling capacitor is required.

4. For recommended operating conditions, see Table 3.

This table defines the PCI Express 2.0 (5 GT/s) AC specifications for the differential

output at all transmitters. The parameters are specified at the component pins. The AC

timing specifications do not include RefClk jitter.

Table 71. PCI Express 2.0 (5 GT/s) differential transmitter output AC specifications³

Parameter

Unit Interval

Symbol

Min

Typ

Max Units

Notes

UI

199.94 200.00 200.06 ps

Each UI is 200 ps 300 ppm. UI does not

account for spread-spectrum clock dictated

variations.

Minimum transmitter eye width T_TX-EYE

0.75

-

UI

The maximum transmitter jitter can be

derived as: T_{TX-MAX-JITTER}= 1 - T_TX-EYE

0.25 UI.

=

See Note 1.

-

Transmitter RMS deterministic T_TX-HF-DJ-DD

jitter > 1.5 MHz

-

0.15

200

ps

AC coupling capacitor

C_TX

75

nF

All transmitters must be AC coupled. The

AC coupling is required either within the

media or within the transmitting component

itself. See Note 2.

Notes:

1. Specified at the measurement point into a timing and voltage test load as shown in Figure 40 and measured over any 250

consecutive transmitter UIs.

2. The chip's SerDes transmitter does not have C_TXbuilt-in. An external AC coupling capacitor is required.

3. For recommended operating conditions, see Table 3.

This table defines the PCI Express 3.0 (8 GT/s) AC specifications for the differential

output at all transmitters. The parameters are specified at the component pins. The AC

timing specifications do not include RefClk jitter.

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Table 72. PCI Express 3.0 (8 GT/s) differential transmitter output AC specifications⁴

Parameter

Unit Interval

Symbol

Min

Typ

Max

Units

Notes

UI

124.9625 125.00 125.0375 ps

Each UI is 125 ps 300 ppm. UI does

not account for spread-spectrum clock

dictated variations.

Transmitter uncorrelated total T_TX-UTJ

jitter

-

31.25

12

ps p-p -

Transmitter uncorrelated

deterministic jitter

T_TX-UDJ-DD

ps p-p -

Total uncorrelated pulse width T_TX-UPW-TJ

jitter (PWJ)

24

ps p-p See Note 1, 2

Deterministic data dependent T_TX-UPW-DJDD

jitter (DjDD) uncorrelated

10

pulse width jitter (PWJ)

Data dependent jitter

AC coupling capacitor

T_TX-DDJ

C_TX

-

18

ps p-p See Note 2

176

265

nF

All transmitters must be AC coupled.

The AC coupling is required either

within the media or within the

transmitting component itself. See

Note 3.

Notes:

1. PWJ parameters shall be measured after data dependent jitter (DDJ) separation.

2. Measured with optimized preset value after de-embedding to transmitter pin.

3. The chip's SerDes transmitter does not have C_TXbuilt-in. An external AC coupling capacitor is required.

4. For recommended operating conditions, see Table 3.

3.19.4.5.2 PCI Express AC physical layer receiver specifications

This section discusses the PCI Express AC physical layer receiver specifications for 2.5

GT/s, 5 GT/s and 8 GT/s.

This table defines the AC specifications for the PCI Express 2.0 (2.5 GT/s) differential

input at all receivers. The parameters are specified at the component pins. The AC timing

specifications do not include RefClk jitter.

Table 73. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications⁴

Parameter

Unit Interval

Symbol

Min

Typ

Max

Units

Notes

UI

399.88 400.00 400.12 ps

Each UI is 400 ps 300 ppm. UI does not

account for spread-spectrum clock

dictated variations.

Minimum receiver eye width T_RX-EYE

0.4

-

UI

The maximum interconnect media and

transmitter jitter that can be tolerated by

the receiver can be derived as T_RX-MAX-

_JITTER= 1 - T_RX-EYE= 0.6 UI.

See Notes 1 and 2.

Table continues on the next page...

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Table 73. PCI Express 2.0 (2.5 GT/s) differential receiver input AC specifications⁴

(continued)

Parameter

Symbol

Min

Typ

Max

0.3

Units

UI

Notes

Maximum time between the T_{RX-EYE-MEDIAN-}

jitter median and maximum

deviation from the median.

-

Jitter is defined as the measurement

variation of the crossing points (V_RX-DIFFp-p

= 0 V) in relation to a recovered

to-MAX-JITTER

transmitter UI. A recovered transmitter UI

is calculated over 3500 consecutive unit

intervals of sample data. Jitter is

measured using all edges of the 250

consecutive UI in the center of the 3500

UI used for calculating the transmitter UI.

See this table notes.

Notes:

1. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 40 must be used

as the receiver device when taking measurements. If the clocks to the receiver and transmitter are not derived from the same

reference clock, the transmitter UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.

2. A T_RX-EYE= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and

interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter

distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget

collected over any 250 consecutive transmitter UIs. It must be noted that the median is not the same as the mean. The jitter

median describes the point in time where the number of jitter points on either side is approximately equal as opposed to the

averaged time value. If the clocks to the receiver and transmitter are not derived from the same reference clock, the

transmitter UI recovered from 3500 consecutive UI must be used as the reference for the eye diagram.

3. It is recommended that the recovered transmitter UI is calculated using all edges in the 3500 consecutive UI interval with a

fit algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental

and simulated data.

4. For recommended operating conditions, see Table 3.

5. The TRX-EYE-MEDIAN-to-MAX-JITTER for common and separated reference clock architecture.

6. If spread spectrum clocking is desired, common clock receiver architecture must be used.

7. The AC specifications do not include Refclk jitter.

This table defines the AC specifications for the PCI Express 2.0 (5 GT/s) differential

input at all receivers. The parameters are specified at the component pins. The AC timing

specifications do not include RefClk jitter.

Table 74. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications¹

Parameter

Symbol

Min

199.40

Typ

200.00

Max

200.06

Units

ps

Notes

1, 2

Unit Interval

Max receiver inherent timing error

UI

T_RX-TJ-CC

-

0.4

UI

3, 5, 6

4, 5, 6

Max receiver inherent deterministic timing T_RX-DJ-DD-CC

error

0.30

Note:

1. Each UI is 200 ps 300 ppm. UI does not account for spread-spectrum clock dictated variations.

2. For recommended operating conditions, see Table 3.

3. The maximum inherent total timing error for common and separated RefClk receiver architecture.

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Table 74. PCI Express 2.0 (5 GT/s) differential receiver input AC specifications¹

Parameter

Symbol

Min

Typ

Max

Units

Notes

4. The maximum inherent deterministic timing error for common and separated RefClk receiver architecture.

5. If spread spectrum clocking is desired, common clock must be used.

6. The AC specifications do not include Refclk jitter.

This table defines the AC specifications for the PCI Express 3.0 (8 GT/s) differential

input at all receivers. The parameters are specified at the component pins. The AC timing

specifications do not include RefClk jitter.

Table 75. PCI Express 3.0 (8 GT/s) differential receiver input AC specifications⁵

Parameter

Unit Interval

Symbol

Min

Typ

Max

Units

Notes

UI

124.9625 125.00 125.0375 ps

Each UI is 125 ps 300 ppm. UI

does not account for spread-

spectrum clock dictated variations.

See Note 1.

Eye Width at TP2P

T_RX-SV-8G

0.3

-

0.35

UI

See Note 1

Differential mode interference V_{RX-SV-DIFF-8G}

14

-

mV

Frequency = 2.1GHz. See Note 2.

Sinusoidal Jitter at 100 MHz

Random Jitter

T_RX-SV-SJ-8G

T_RX-SV-RJ-8G

0.1

2.0

UI p-p Fixed at 100 MHz. See Note 3.

ps Random jitter spectrally flat before

RMS filtering. See Note 4.

-

Note:

1. T_RX-SV-8Gis referenced to TP2P and obtained after post processing data captured at TP2. T_RX-SV-8Gincludes the effects of

applying the behavioral receiver model and receiver behavioral equalization.

2. V_{RX-SV-DIFF-8G}voltage may need to be adjusted over a wide range for the different loss calibration channels.

3. The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency as shown in Figure 39.

4. Random jitter (Rj) is applied over the following range: The low frequency limit may be between 1.5 and 10 MHz, and the

upper limit is 1.0 GHz. See Figure 39 for details. Rj may be adjusted to meet the 0.3 UI value for T_RX-SV-8G

.

5. For recommended operating conditions, see Table 3.

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0.03 MHz

100 MHz

Sj sweep range

1.0 UI

0.1 UI

20 dB

decade

Sj

Rj

~ 3.0 ps RMS

0.01 MHz

0.1 MHz

1.0 MHz

10 MHz

100 MHz

1000 MHz

Figure 39. Swept sinusoidal jitter mask

3.19.4.6 Test and measurement load

The AC timing and voltage parameters must be verified at the measurement point. The

package pins of the device must be connected to the test/measurement load within 0.2

inches of that load, as shown in the following figure.

NOTE

The allowance of the measurement point to be within 0.2 inches

of the package pins is meant to acknowledge that package/

board routing may benefit from D+ and D- not being exactly

matched in length at the package pin boundary. If the vendor

does not explicitly state where the measurement point is

located, the measurement point is assumed to be the D+ and D-

package pins.

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D + package pin

C = C_TX

Transmitter

silicon

+ package

C = C_TX

D - package pin

R = 50 Ω

Figure 40. Test/measurement load

3.19.5 Serial RapidIO (sRIO)

This section describes the DC and AC electrical specifications for the serial RapidIO

interface of the LP-Serial physical layer. The electrical specifications cover both single

and multiple-lane links. Two transmitters (short run and long run) and a single receiver

are specified for each of three baud rates: 2.50, 3.125 and 5 GBaud.

Two transmitter specifications allow for solutions ranging from simple board-to-board

interconnect to driving two connectors across a backplane. A single receiver specification

is given that accepts signals from both the short run and long run transmitter

specifications.

The short run transmitter must be used mainly for chip-to-chip connections on either the

same printed circuit board or across a single connector. This covers the case where

connections are made to a mezzanine (daughter) card. The minimum swings of the short

run specification reduce the overall power used by the transceivers.

The long run transmitter specifications use larger voltage swings that are capable of

driving signals across backplanes. This allows a user to drive signals across two

connectors and a backplane.

All unit intervals are specified with a tolerance of 100 ppm. The worst case frequency

difference between any transmit and receive clock is 200 ppm.

To ensure interoperability between drivers and receivers of different vendors and

technologies, AC coupling at the receiver input must be used.

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3.19.5.1 Signal definitions

This section defines the terms used in the description and specification of the differential

signals used by the LP-Serial links. The following figure shows how the signals are

defined. The figures show waveforms for either a transmitter output (TD and TD_B) or a

receiver input (RD and RD_B). Each signal swings between A volts and B volts where A

> B. Using these waveforms, the definitions are as follows:

• The transmitter output signals and the receiver input signals-TD, TD_B, RD, and

RD_B-each have a peak-to-peak swing of A - B volts.

• The differential output signal of the transmitter, V_OD, is defined as V_TD- V_{TD_B}

• The differential input signal of the receiver, V_ID, is defined as V_RD- V_{RD_B}

• The differential output signal of the transmitter and the differential input signal of the

receiver each range from A - B to -(A - B) volts

• The peak value of the differential transmitter output signal and the differential

receiver input signal is A - B volts.

• The peak-to-peak value of the differential transmitter output signal and the

differential receiver input signal is 2 x (A - B) volts.

TD or RD

A volts

TD or RD

B volts

Differential peak-to-peak = 2 x (A - B)

Figure 41. Differential peak-to-peak voltage of transmitter or receiver

To illustrate these definitions using real values, consider the case of a CML (current

mode logic) transmitter that has a common mode voltage of 2.25 V, and each of its

outputs TD and TD_B, has a swing that goes between 2.5 V and 2.0 V. Using these

values, the peak-to-peak voltage swing of the signals TD and TD_B is 500 mV p-p. The

differential output signal ranges between 500 mV and -500 mV. The peak differential

voltage is 500 mV. The peak-to-peak differential voltage is 1000 mV p-p.

3.19.5.2 Equalization

With the use of high-speed serial links, the interconnect media causes degradation of the

signal at the receiver and produces effects such as inter-symbol interference (ISI) or data-

dependent jitter. This loss can be large enough to degrade the eye opening at the receiver

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beyond what is allowed in the specification. To negate a portion of these effects,

equalization can be used. The most common equalization techniques that can be used are

as follows:

• Pre-emphasis on the transmitter

• A passive high-pass filter network placed at the receiver, often referred to as passive

equalization.

• The use of active circuits in the receiver, often referred to as adaptive equalization.

3.19.5.3 Serial RapidIO clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

SerDes 3 and SerDes 4 (SD[3:4]_REF_CLK[1:2] and SD[3:4]_REF_CLK[1:2]_B) may

be used for various SerDes serial RapidIO configurations based on the RCW

Configuration field SRDS_PRTCL. Serial RapidIO is not supported on SerDes 1 and 2.

The ref clock frequency tolerance spec is 100ppm.

For more information on these specifications, see SerDes reference clocks.

3.19.5.4 DC requirements for serial RapidIO

This section explains the DC requirements for the serial RapidIO interface.

3.19.5.4.1 DC serial RapidIO transmitter specifications

This table defines the transmitter DC specifications for serial RapidIO operating at 2.5

and 3.125 GBaud.

Table 76. Serial RapidIO transmitter DC specifications-2.5 GBaud, 3.125 GBaud²

Parameter

Symbol

V_DIFFPP

Min

800

500

Typ

Max

1600

Unit

mV p-p

Ω

Notes

Long-run differential output voltage

Short-run differential output voltage

-

V_DIFFPP

1000

120

DC Differential transmitter impedance Z_TX-DIFF-DC80

100

Transmitter DC differential

impedance

Notes:

1. Voltage relative to COMMON of either signal comprising a differential pair

2. For recommended operating conditions, see Table 3.

This table defines the transmitter DC specifications for serial RapidIO operating at 5

GBaud.

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Table 77. Serial RapidIO transmitter DC specifications-5 GBaud¹

Parameter

Long-run differential output voltage

Short-run differential output voltage

Symbol

Min

800

Typ

Max

1200

Unit

mV

Notes

V_DIFF

-

400

3

750

4

mV

dB

Long-run de-emphasized differential output voltage (ratio) V_{TX-DE-RATIO-3.5dB}

3.5

6.0

100

Long-run de-emphasized differential output voltage (ratio) V_{TX-DE-RATIO-6.0dB}5.5

6.5

dB

Ω

-

Differential resistance

T_RD

80

120

Notes:

1. For recommended operating conditions, see Table 3.

3.19.5.4.2 DC serial RapidIO receiver specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tables of

this section.

Receiver input impedance results in a differential return loss better than 10 dB and a

common mode return loss better than 6 dB from 100 MHz to (0.8) x (Baud Frequency).

This includes contributions from on-chip circuitry, the chip package, and any off-chip

components related to the receiver. AC coupling components are included in this

requirement. The reference impedance for return loss measurements is 100-Ω resistive for

differential return loss and 25-Ω resistive for common mode.

This table defines the receiver DC specifications for serial RapidIO operating at 2.5 and

3.125 GBaud.

Table 78. Serial RapidIO receiver DC specifications-2.5 GBaud, 3.125 GBaud²

Parameter

Differential input voltage

Symbol

V_IN

Z_RX-DIFF-DC80

Min

Typ

Max

1600

120

Unit

Notes

200

-

mV p-p 1

DC differential receiver input impedance

100

Ω

Receiver DC differential

impedance

Notes:

1. Measured at the receiver

2. For recommended operating conditions, see Table 3.

This table defines the receiver DC specifications for serial RapidIO operating at 5

GBaud.

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Table 79. Serial RapidIO receiver DC specifications-5 GBaud²

Parameter

Symbol

V_DIFF

Min

Typ

Max

1200

Unit

Notes

Long-run differential input voltage

-

mV

1

Short-run differential input voltage

Differential resistance

V_DIFF

R_RD

125

80

-

1200

120

mV

Ω

1

-

Notes:

1. Measured at the receiver.

2. For recommended operating conditions, see Table 3.

3.19.5.5 AC requirements for serial RapidIO

This section explains the AC requirements for the serial RapidIO interface.

3.19.5.5.1 AC requirements for serial RapidIO transmitter

This table defines the transmitter AC specifications for the serial RapidIO operating at

2.5 and 3.125 GBaud. The AC timing specifications do not include RefClk jitter.

Table 80. Serial RapidIO transmitter, 2.5 GBaud and 3.125 GBaud, AC timing specifications¹

Parameter

Symbol

Min

Typical

Max

Unit

UI p-p

Deterministic jitter

Total jitter

J_D

J_T

UI

-

0.17

0.35

-

Unit Interval: 2.5 GBaud

Unit Interval: 3.125 GBaud

Notes:

400 - 100ppm

320 - 100ppm

400

320

400 + 100ppm ps

320 + 100ppm ps

1. For recommended operating conditions, see Table 3.

This table defines the transmitter AC specifications for the serial RapidIO operating at 5

GBaud, short range. The AC timing specifications do not include RefClk jitter.

Table 81. Serial RapidIO transmitter, 5 GBaud, AC timing specifications¹

Parameter

Symbol

T_BAUD

Min

Typical

Max

Unit

Baud rate

5.000 - 100ppm 5.000

5.000 +

GBaud

100ppm

0.155

0.30

Uncorrelated high probability jitter

T_UHPJ

T_J

-

UI p-p

Total jitter

Notes:

1. For recommended operating conditions, see Table 3.

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This table defines the receiver AC specifications for serial RapidIO operating at 2.5 and

3.125 GBaud. The AC timing specifications do not include RefClk jitter.

Table 82. Serial RapidIO receiver, 2.5 GBaud and 3.125 GBaud, AC timing specifications³

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Deterministic jitter tolerance

J_D

-

0.37

0.55

UI p-p

1

Combined deterministic and random

jitter tolerance

J_DR

UI p-p

Total jitter tolerance²

J_T

-

0.65

10^-12

UI p-p

-

1

-

Bit error rate

BER

UI

Unit Interval: 2.5 GBaud

Unit Interval: 3.125 GBaud

Notes:

400 - 100ppm 400

320 - 100ppm 320

400 + 100ppm ps

320 + 100ppm ps

-

UI

-

1. Measured at receiver

2. Total jitter is composed of three components: deterministic jitter, random jitter and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 42. The sinusoidal jitter component

is included to ensure margin for low-frequency jitter, wander, noise, crosstalk, and other variable system effects.

3. For recommended operating conditions, see Table 3.

This figure shows the single-frequency sinusoidal jitter limits for 2.5 GBaud and 3.125

GBaud rates.

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8.5 UI p-p

Sinuosidal

Jitter

20 dB/dec

Amplitude

0.10 UI p-p

20 MHz

baud/142000

baud/1667

Frequency

Figure 42. Single-frequency sinusoidal jitter limits, substitute the baud parameter in this

figure by either 2.5G or 3.125G.

This table defines the receiver AC specifications for serial RapidIO operating at 5

GBaud. The AC timing specifications do not include RefClk jitter.

Table 83. Serial RapidIO receiver, 5G Baud, AC timing specifications¹

Parameter

Receiver baud rate

Symbol

R_BAUD

R_GJ

Min

Typical

Max

Unit

Notes

5.000 - 100ppm 5.000

5.000 + 100ppm Gbaud

-

Long-run Gaussian jitter

-

0.2

UI p-p

2

Long-Run Uncorrelated bounded high

probability jitter

R_UHPJ

0.12

2, 3

2, 4

Long-run correlated bounded high probability R_CBHPJ

jitter

-

0.63

0.30

UI p-p

Short-run correlated bounded high probability R_CBHPJ

jitter

Long-run bounded high probability jitter

Short-run bounded high probability jitter

Sinusoidal jitter, maximum

R_BHPJ

R_SJ-max

R_SJ-hf

R_Tj

-

0.75

0.45

5.00

0.05

0.95

UI p-p

3, 4

-

Sinusoidal jitter, high frequency

-

Long-run total jitter (does not include

sinusoidal jitter)

3, 4

Short-run total jitter (does not include

sinusoidal jitter)

R_Tj

-

0.60

UI p-p

3, 4

Table continues on the next page...

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Table 83. Serial RapidIO receiver, 5G Baud, AC timing specifications¹(continued)

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Notes:

1. For recommended operating conditions, see Table 3.

2. The AC specifications do not include Refclk jitter.

3. The jitter (R_UHPJ) is Bounded High Probability Jitter and is commonly caused by crosstalk coupling and can have periodic

and bounded PRBS jitter subcomponents.

4. The jitter (R_CBHPJ) and amplitude have to be correlated, for example by a PCB trace.

This figure shows the single-frequency sinusoidal jitter limits for 5 GBaud rate.

5 UI p-p

Sinuosidal

Jitter

20 dB/dec

Amplitude

0.05 UI p-p

20 MHz

35.2 kHz

3 MHz

Frequency

Figure 43. Single-frequency sinusoidal jitter limits

3.19.6 XAUI interface

This section describes the DC and AC electrical specifications for the XAUI bus.

3.19.6.1 XAUI DC electrical characteristics

This section discusses the XAUI DC electrical characteristics for the clocking signals,

transmitter, and receiver.

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3.19.6.1.1 DC requirements for XAUI SDn_REF_CLKn and SDn_REF_CLKn_B

Only SerDes 1-2 (SD[1:2]_REF_CLK[1:2] and SD[1:2]_REF_CLK[1:2]_B) may be used

for various SerDes XAUI configurations based on the RCW Configuration field

SRDS_PRTCL. The ref clock frequency tolerance spec is 100ppm.

For more information on these specifications, see SerDes reference clocks.

3.19.6.1.2 XAUI transmitter DC electrical characteristics

This table defines the XAUI transmitter DC electrical characteristics.

Table 84. XAUI transmitter DC electrical characteristics (XV_DD= 1.35V or 1.5V)¹

Parameter

Symbol

V_DIFFPP

Min

800

Typical

1000

Max

1600

Unit

Notes

Differential output voltage

mV p-p

-

DC Differential transmitter impedance Z_TX-DIFF-DC80

100

120

Ω

3

1. For recommended operating conditions, see Table 3.

2. Absolute output voltage limit

3. Transmitter DC differential impedance

3.19.6.1.3 XAUI receiver DC electrical characteristics

This table defines the XAUI receiver DC electrical characteristics.

Table 85. XAUI receiver DC timing specifications (SV_DD= 1.0 V)¹

Parameter

Symbol

V_IN

Min

200

Typical

Max

1600

Unit

Notes

Differential input voltage

-

mV p-p

2

3

DC Differential receiver input

impedance

Z_RX-DIFF-DC80

100

120

Ω

1. For recommended operating conditions, see Table 3.

2. Measured at the receiver.

3. Receiver DC differential impedance

3.19.6.2 XAUI AC timing specifications

This section explains the AC requirements for the XAUI interface.

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3.19.6.2.1 XAUI transmitter AC timing specifications

This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not

included.

Table 86. XAUI transmitter AC timing specifications ¹

Parameter

Deterministic jitter

Symbol

Min

Typical

Max

Unit

UI p-p

J_D

J_T

UI

-

0.17

0.35

Total jitter

Unit Interval: 3.125 Gb/s

320 - 100 ppm

320

320 + 100 ppm ps

1. For recommended operating conditions, see Table 3.

3.19.6.2.2 XAUI receiver AC timing specifications

This table defines the receiver AC specifications for XAUI. RefClk jitter is not included.

Table 87. XAUI receiver AC timing specifications³

Parameter

Symbol

J_D

Min

Typical

Max

Unit

UI p-p

Notes

Deterministic jitter tolerance

-

0.37

0.55

1

Combined deterministic and random

jitter tolerance

J_DR

J_T

UI p-p

Total jitter tolerance

-

0.65

UI p-p

-

1, 2

Bit error rate

BER

UI

10^-12

-

Unit Interval: 3.125 Gb/s

Notes:

320 - 100 ppm 320

320 + 100 ppm ps

1. Measured at receiver.

2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk, and other variable system effects.

3. For recommended operating conditions, see Table 3.

3.19.7 Aurora interface

This section describes the Aurora clocking requirements and its DC and AC electrical

characteristics.

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3.19.7.1 Aurora clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

Only SerDes 4 (SD4_REF_CLK[1:2] and SD4_REF_CLK[1:2]_B) may be used for

SerDes Aurora configurations based on the RCW Configuration field SRDS_PRTCL.

The ref clock frequency tolerance spec is 100ppm. Aurora is not supported on SerDes

1-3.

For more information on these specifications, see SerDes reference clocks.

3.19.7.2 Aurora DC electrical characteristics

This section describes the DC electrical characteristics for the Aurora interface.

3.19.7.2.1 Aurora transmitter DC electrical characteristics

This table defines the Aurora transmitter DC electrical characteristics.

Table 88. Aurora transmitter DC electrical characteristics (XV_DD= 1.35 V or 1.5 V) ¹

Parameter

Symbol

V_DIFFPP

Min

Typical

1000

Max

Unit

mV p-p

Differential output voltage

800

80

1600

120

DC Differential transmitter impedance

Z_TX-DIFF-DC

100

Ω

1. For recommended operating conditions, see Table 3.

3.19.7.2.2 Aurora receiver DC electrical characteristics

This table defines the Aurora receiver DC electrical characteristics for the Aurora

interface.

Table 89. Aurora receiver DC electrical characteristics (SV_DD= 1.0V)¹

Parameter

Symbol

V_IN

Z_RX-DIFF-DC80

Min

Typical

Max

1600

120

Unit

mV p-p

Ω

Notes

Differential input voltage

200

-

2

3

DC Differential receiver impedance

100

Notes:

1. For recommended operating conditions, see Table 3.

2. Measured at receiver

3. DC Differential receiver impedance

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3.19.7.3 Aurora AC timing specifications

This section describes the AC timing specifications for Aurora.

3.19.7.3.1 Aurora transmitter AC timing specifications

This table defines the Aurora transmitter AC timing specifications. RefClk jitter is not

included.

Table 90. Aurora transmitter AC timing specifications¹

Parameter

Deterministic jitter

Symbol

Min

Typical

Max

Unit

UI p-p

J_D

J_T

UI

-

0.17

0.35

Total jitter

Unit interval: 2.5 Gbps

Unit interval: 3.125 Gbps

Unit interval: 5.0 Gbps

Notes:

400 - 100 ppm

320 - 100 ppm

200 - 100 ppm

400

320

200

400 + 100 ppm ps

320 + 100 ppm ps

200 + 100 ppm ps

1. For recommended operating conditions, see Table 3.

3.19.7.3.2 Aurora receiver AC timing specifications

This table defines the Aurora receiver AC timing specifications. RefClk jitter is not

included.

Table 91. Aurora receiver AC timing specifications³

Parameter

Symbol

J_D

Min

Typical

Max

Unit

UI p-p

Notes

Deterministic jitter tolerance

-

0.37

0.55

1

Combined deterministic and random

jitter tolerance

J_DR

J_T

UI p-p

Total jitter tolerance

-

0.65

UI p-p

-

1, 2

Bit error rate

BER

UI

10^-12

-

Unit Interval: 2.5 Gbps

Unit Interval: 3.125 Gbps

Unit Interval: 5.0 Gbps

Notes:

400 - 100 ppm 400

320 - 100 ppm 320

200 - 100 ppm 200

400 + 100 ppm ps

320 + 100 ppm ps

200 + 100 ppm ps

UI

1. Measured at receiver

2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 42. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

3. For recommended operating conditions, see Table 3.

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3.19.8 Serial ATA (SATA) interface

This section describes the DC and AC electrical specifications for the serial ATA

(SATA) interface.

3.19.8.1 SATA DC electrical characteristics

This section describes the DC electrical characteristics for SATA.

3.19.8.1.1 SATA DC transmitter output characteristics

This table provides the differential transmitter output DC characteristics for the SATA

interface at Gen1i/1m or 1.5 Gbps transmission.

Table 92. Gen1i/1m 1.5G transmitter DC specifications (XV_DD= 1.35 V or 1.5 V)³

Parameter

Symbol

Min

Typ

Max

Units

Notes

Tx differential output voltage

V_{SATA_TXDIFF}

400

85

500

100

600

115

mV p-p

1

2

Tx differential pair impedance

Notes:

Z_{SATA_TXDIFFIM}

Ω

1. Terminated by 50 Ω load

2. DC impedance

3. For recommended operating conditions, see Table 3.

This table provides the differential transmitter output DC characteristics for the SATA

interface at Gen2i/2m or 3.0 Gbps transmission.

Table 93. Gen 2i/2m 3G transmitter DC specifications (XV_DD= 1.35 V or 1.5 V)²

Parameter

Symbol

Min

Typ

Max

Units

Notes

Transmitter differential output voltage

V_{SATA_TXDIFF}

400

85

-

700

115

mV p-p

1

-

Transmitter differential pair impedance

Notes:

Z_{SATA_TXDIFFIM}

100

Ω

1. Terminated by 50 Ω load.

2. For recommended operating conditions, see Table 3.

3.19.8.1.2 SATA DC receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbps differential receiver input DC

characteristics for the SATA interface.

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Table 94. Gen1i/1m 1.5 G receiver input DC specifications (SV_DD= 1.0 V)³

Parameter

Symbol

Min

Typical

Max

Units

mV p-p

Ω

Notes

Differential input voltage

V_{SATA_RXDIFF}

240

85

500

100

120

600

115

240

1

2

-

Differential receiver input impedance Z_{SATA_RXSEIM}

OOB signal detection threshold

V_{SATA_OOB}

50

mV p-p

Notes:

1. Voltage relative to common of either signal comprising a differential pair

2. DC impedance

3. For recommended operating conditions, see Table 3.

This table provides the Gen2i/2m or 3 Gbps differential receiver input DC characteristics

for the SATA interface.

Table 95. Gen2i/2m 3 G receiver input DC specifications (SV_DD= 1.0 V)³

Parameter

Differential input voltage

Differential receiver input impedance

OOB signal detection threshold

Notes:

Symbol

V_{SATA_RXDIFF}

Z_{SATA_RXSEIM}

V_{SATA_OOB}

Min

Typical

Max

Units

mV p-p

Notes

240

85

-

750

115

240

1

2

100

120

Ω

75

mV p-p

1. Voltage relative to common of either signal comprising a differential pair

2. DC impedance

3. For recommended operating conditions, see Table 3.

3.19.8.2 SATA AC timing specifications

This section discusses the SATA AC timing specifications.

3.19.8.2.1 AC requirements for SATA REF_CLK

The AC requirements for the SATA reference clock listed in this table are to be

guaranteed by the customer's application design. SATA does not support TX Spread

Spectrum Clock as it is an optional requirement in protocol. However T4 SATA supports

RX spread spectrum data as it is required in the SATA standard that all SATA Receivers

handle spread spectrum. SerDes can receive spread spectrum without affecting other

protocols since this doesn’t affect SerDes PLL.

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Table 96. SATA reference clock input requirements⁶

Parameter

Symbol

Min

Typ

Max

Unit

MHz

Notes

SDn_REF_CLKn/SDn_REF_CLKn_B

frequency range

t_{CLK_REF}

-

100/125

-

1

-

SDn_REF_CLKn/SDn_REF_CLKn_B clock

frequency tolerance

t_{CLK_TOL}

-350

40

-

+350

60

ppm

%

SDn_REF_CLKn/SDn_REF_CLKn_B reference t_{CLK_DUTY}

clock duty cycle

50

-

5

2

SDn_REF_CLKn/SDn_REF_CLKn_B cycle-to- t_{CLK_CJ}

cycle clock jitter (period jitter)

100

+50

ps

SDn_REF_CLKn/SDn_REF_CLKn_B total

t_{CLK_PJ}

-50

-

ps

2, 3, 4

reference clock jitter, phase jitter (peak-to-peak)

Notes:

1. Caution: Only 100 and 125MHz have been tested. In-between values do not work correctly with the rest of the system.

2. At RefClk input

3. In a frequency band from 150 kHz to 15 MHz at BER of 10^-12

4. Total peak-to-peak deterministic jitter must be less than or equal to 50 ps.

5. Measurement taken from differential waveform

6. For recommended operating conditions, see Table 3.

3.19.8.3 AC transmitter output characteristics

This table provides the differential transmitter output AC characteristics for the SATA

interface at Gen1i/1m or 1.5 Gbps transmission. The AC timing specifications do not

include RefClk jitter.

Table 97. Gen1i/1m 1.5 G transmitter AC specifications²

Parameter

Channel speed

Symbol

t_{CH_SPEED}

Min

Typ

Max

Units

Gbps

Notes

-

1.5

-

Unit Interval

T_UI

666.4333

666.6667

670.2333

0.355

0.47

ps

Total jitter data-data 5 UI

Total jitter, data-data 250 UI

Deterministic jitter, data-data 5 UI

Deterministic jitter, data-data 250 UI

Notes:

U_{SATA_TXTJ5UI}

U_{SATA_TXTJ250UI}

U_{SATA_TXDJ5UI}

U_{SATA_TXDJ250UI}

-

UI p-p

1

0.175

0.22

1. Measured at transmitter output pins peak to peak phase variation, random data pattern

2. For recommended operating conditions, see Table 3.

This table provides the differential transmitter output AC characteristics for the SATA

interface at Gen2i/2m or 3.0 Gbps transmission. The AC timing specifications do not

include RefClk jitter.

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Table 98. Gen 2i/2m 3 G transmitter AC specifications²

Parameter

Channel speed

Symbol

t_{CH_SPEED}

Min

Typ

Max

Units

Gbps

Notes

-

3.0

-

Unit Interval

T_UI

333.2167

333.3333

335.1167

0.37

ps

Total jitter f_C3dB= f_BAUDꢀ 500

Total jitter f_C3dB= f_BAUDꢀ 1667

U_{SATA_TXTJfB/500}

U_{SATA_TXTJfB/1667}

-

UI p-p

1

0.55

Deterministic jitter, f_C3dB= f_BAUDꢀ 500 U_{SATA_TXDJfB/500}

0.19

Deterministic jitter, f_C3dB= f_BAUD

1667

ꢀ

U_{SATA_TXDJfB/1667}

0.35

Notes:

1. Measured at transmitter output pins peak-to-peak phase variation, random data pattern

2. For recommended operating conditions, see Table 3.

3.19.8.4 AC differential receiver input characteristics

This table provides the Gen1i/1m or 1.5 Gbps differential receiver input AC

characteristics for the SATA interface. The AC timing specifications do not include

RefClk jitter.

Table 99. Gen 1i/1m 1.5G receiver AC specifications²

Parameter

Symbol

Min

Typical

Max

670.2333

0.43

Units

ps

Notes

Unit Interval

T_UI

666.4333

666.6667

-

Total jitter data-data 5 UI

U_{SATA_RXTJ5UI}

U_{SATA_RXTJ250UI}

U_{SATA_RXDJ5UI}

-

UI p-p

1

Total jitter, data-data 250 UI

Deterministic jitter, data-data 5 UI

0.60

0.25

Deterministic jitter, data-data 250 UI U_{SATA_RXDJ250UI}

Notes:

0.35

1. Measured at receiver.

2. For recommended operating conditions, see Table 3.

This table provides the differential receiver input AC characteristics for the SATA

interface at Gen2i/2m or 3.0 Gbps transmission. The AC timing specifications do not

include RefClk jitter.

Table 100. Gen 2i/2m 3G receiver AC specifications²

Parameter

Symbol

Min

Typical

Max

335.1167

0.60

Units

ps

Notes

Unit Interval

T_UI

U_{SATA_RXTJfB/500}

U_{SATA_RXTJfB/1667}

333.2167

333.3333

-

Total jitter f_C3dB= f_BAUDꢀ 500

Total jitter f_C3dB= f_BAUDꢀ 1667

-

UI p-p

1

0.65

Deterministic jitter, f_C3dB= f_BAUDꢀ 500 U_{SATA_RXDJfB/500}

0.42

Table continues on the next page...

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Table 100. Gen 2i/2m 3G receiver AC specifications²(continued)

Parameter

Symbol

Min

Typical

Max

Units

UI p-p

Notes

Deterministic jitter, f_C3dB= f_BAUDꢀ 1667 U_{SATA_RXDJfB/1667}

Notes:

-

0.35

1

1. Measured at receiver

2. For recommended operating conditions, see Table 3.

3.19.9 SGMII interface

Each SGMII port features a 4-wire AC-coupled serial link from the SerDes interface of

the chip, as shown in Figure 44, where C_TXis the external (on board) AC-coupled

capacitor. Each SerDes transmitter differential pair features 100-Ω output impedance.

Each input of the SerDes receiver differential pair features 50-Ω on-die termination to

XGNDn. The reference circuit of the SerDes transmitter and receiver is shown in Figure

38.

3.19.9.1 SGMII clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

When operating in SGMII mode, the ECn_GTX_CLK125 clock is not required for this

port. Instead, a SerDes reference clock is required on SD[1:2]_REF_CLK[1:2] and

SD[1:2]_REF_CLK[1:2]_Bpins. SerDes 1-2 may be used for SerDes SGMII

configurations based on the RCW Configuration field SRDS_PRTCL.

For more information on these specifications, see SerDes reference clocks.

3.19.9.2 SGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface.

3.19.9.2.1 SGMII and SGMII 2.5x transmit DC specifications

This table describes the SGMII SerDes transmitter AC-coupled DC electrical

characteristics. Transmitter DC characteristics are measured at the transmitter outputs

(SDn_TXn and SDn_TXn_B)as shown in Figure 45.

Table 101. SGMII DC transmitter electrical characteristics (XV_DD= 1.35 V or 1.5 V)⁴

Parameter

Symb

ol

Min

Typ

Max

Unit

Notes

Output high voltage

V_OH

-

1.5 x │V_OD

│

-max

mV

1

Table continues on the next page...

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Table 101. SGMII DC transmitter electrical characteristics (XV_DD= 1.35 V or 1.5 V)⁴

(continued)

Parameter

Symb

ol

Min

Typ

Max

Unit

Notes

Output low voltage

V_OL

│V_OD

│_-min/2

-

mV

1

Output differential

voltage^{2, 3}

│V_OD

│

320

500

725

SRDSxLNmTECR0 [AMP_RED] =

6b000000

(XV_DD-Typat 1.35 V and

1.5 V)

293.8

266.9

240.6

213.1

186.9

160.0

40

459.0 665.6

417.0 604.7

376.0 545.2

333.0 482.9

292.0 423.4

250.0 362.5

SRDSxLNmTECR0 [AMP_RED] =

6b000001

SRDSxLNmTECR0 [AMP_RED] =

6b000011

SRDSxLNmTECR0 [AMP_RED] =

6b000010

SRDSxLNmTECR0 [AMP_RED] =

6b000110 (Default)

SRDSxLNmTECR0 [AMP_RED] =

6b000111

SRDSxLNmTECR0 [AMP_RED] =

6b010000

Output impedance

(single ended)

R_O

50

60

Ω

-

Notes:

1. This does not align to DC-coupled SGMII.

2. │V_OD│ = │V_{SD_TXn}- V_{SD_TXn_B}│. │V_OD│ is also referred to as output differential peak voltage. V_TX-DIFFp-p= 2 x │V_OD

│

.

3. The │V_OD│ value shown in the Typ column is based on the condition of XVDD_SRDSn-Typ = 1.35 V or 1.5 V, no common

mode offset variation. SerDes transmitter is terminated with 100-Ω differential load between SDn _TXn and SDn_TXn_B.

4. For recommended operating conditions, see Table 3.

This figure shows an example of a 4-wire AC-coupled SGMII serial link connection.

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SDn_RXn

SDn_TXn

C_TX

50 Ω

Transmitter

Receiver

100 Ω

C_TX

SDn_TXn_B

SDn_RXn

SDn_RXn_B

50 Ω

SGMII

SerDes Interface

SDn_TXn

C_TX

50 Ω

Receiver

Transmitter

100 Ω

C_TX

SDn_RXn_B

SDn_TXn_B

50 Ω

Figure 44. 4-wire AC-coupled SGMII serial link connection example

This figure shows the SGMII transmitter DC measurement circuit.

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SGMII

SerDes Interface

SDn_TXn

50 Ω

Transmitter

V_OD

100 Ω

50 Ω

SDn_TXn_B

Figure 45. SGMII transmitter DC measurement circuit

This table defines the SGMII 2.5x transmitter DC electrical characteristics for 3.125

GBaud.

Table 102. SGMII 2.5x transmitter DC electrical characteristics (XV_DD= 1.35 V or 1.5 V)¹

Parameter

Symbo Min

l

Typical

Max Unit

Notes

Output differential voltage │V_OD

│

400

80

-

600

120

mV

Ω

SRDSxLNmTECR0 [AMP_RED] = 6b000000

-

Output impedance

(differential)

R_O

100

Notes:

1. For recommended operating conditions, see Table 3.

3.19.9.2.2 SGMII and SGMII 2.5x DC receiver electrical characteristics

This table lists the SGMII DC receiver electrical characteristics. Source synchronous

clocking is not supported. Clock is recovered from the data.

Table 103. SGMII DC receiver electrical characteristics (SV_DD= 1.0V)⁴

Parameter

DC input voltage range

Input differential voltage

Symbol

Min

Typ

Max

Unit Notes

-

N/A

100

-

1

SRDSxLNmGCR1

[REIDL_TH] = 001

V_{RX_DIFFp-p}

-

1200

mV

2

Table continues on the next page...

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Table 103. SGMII DC receiver electrical characteristics (SV_DD= 1.0V)⁴(continued)

Parameter

Symbol

Min

Typ

Max

Unit Notes

SRDSxLNmGCR1

[REIDL_TH] = 100

175

30

-

Loss of signal threshold

SRDSxLNmGCR1

[REIDL_TH] = 001

V_LOS

100

175

120

mV

3

-

SRDSxLNmGCR1

[REIDL_TH] = 100

65

Receiver differential input impedance

Notes:

Z_{RX_DIFF}

80

Ω

1. Input must be externally AC coupled.

2. V_{RX_DIFFp-p}is also referred to as peak-to-peak input differential voltage.

3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. See PCI

Express DC physical layer receiver specifications, and PCI Express AC physical layer receiver specifications, for further

explanation.

4. For recommended operating conditions, see Table 3.

This table defines the SGMII 2.5x receiver DC electrical characteristics for 3.125 GBaud.

Table 104. SGMII 2.5x receiver DC timing specifications (SV_DD= 1.0V)¹

Parameter

Input differential voltage

Loss of signal threshold

Receiver differential input impedance

Notes:

Symbol

Min

Typical

Max

Unit

Notes

V_{RX_DIFFp-p}200

-

1200

200

mV

Ω

-

V_LOS

75

80

Z_{RX_DIFF}

120

1. For recommended operating conditions, see Table 3.

3.19.9.3 SGMII AC timing specifications

This section discusses the AC timing specifications for the SGMII interface.

3.19.9.3.1 SGMII and SGMII 2.5x transmit AC timing specifications

This table provides the SGMII and SGMII 2.5x transmit AC timing specifications. A

source synchronous clock is not supported. The AC timing specifications do not include

RefClk jitter.

Table 105. SGMII transmit AC timing specifications⁴

Parameter

Symbol

Min

Typ

Max

Unit

Notes

Unit Interval: 1.25 GBaud (SGMII)

UI

800 - 100 ppm 800

320 - 100 ppm 320

800 + 100 ppm ps

320 + 100 ppm ps

1

Unit Interval: 3.125 GBaud (2.5x SGMII]) UI

Table continues on the next page...

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Table 105. SGMII transmit AC timing specifications⁴(continued)

Parameter

Deterministic jitter

Symbol

JD

Min

Typ

Max

Unit

UI p-p

Notes

-

0.17

0.35

200

-

Total jitter

JT

-

UI p-p

nF

2

3

AC coupling capacitor

C_TX

10

Notes:

1. Each UI is 800 ps 100 ppm or 320 ps 100 ppm.

2. See Figure 42 for single frequency sinusoidal jitter measurements.

3. The external AC coupling capacitor is required. It is recommended that it be placed near the device transmitter outputs.

4. For recommended operating conditions, see Table 3.

3.19.9.3.2 SGMII AC measurement details

Transmitter and receiver AC characteristics are measured at the transmitter outputs

(SDn_TXn and SDn_TXn_B) or at the receiver inputs (SDn_RXn and SDn_RXn_B)

respectively, as depicted in this figure.

D + package pin

C = C_TX

Transmitter

silicon

+ package

C = C_TX

D - package pin

R = 50 Ω

Figure 46. SGMII AC test/measurement load

3.19.9.3.3 SGMII and SGMII 2.5x receiver AC timing Specification

This table provides the SGMII and SGMII 2.5x receiver AC timing specifications. The

AC timing specifications do not include RefClk jitter. Source synchronous clocking is not

supported. Clock is recovered from the data.

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Table 106. SGMII Receive AC timing specifications³

Parameter

Deterministic jitter tolerance

Symbol

J_D

Min

Typ

Max

Unit

Notes

-

0.37

0.55

0.65

10^-12

UI p-p

1

Combined deterministic and random jitter tolerance J_DR

UI p-p

-

Total jitter tolerance

J_T

1, 2

Bit error ratio

BER

UI

-

Unit Interval: 1.25 GBaud (SGMII)

Unit Interval: 3.125 GBaud (2.5x SGMII])

Notes:

800 - 100 ppm 800

320 - 100 ppm 320

800 + 100 ppm ps

320 + 100 ppm ps

1

UI

1. Measured at receiver

2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 42. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

3. For recommended operating conditions, see Table 3.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in

the unshaded region of Figure 43.

3.19.10 QSGMII interface

This section describes the QSGMII clocking and its DC and AC electrical characteristics.

3.19.10.1 QSGMII clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

The ref clock frequency tolerance spec is 100ppm. For more information on these

specifications, see SerDes reference clocks.

3.19.10.2 QSGMII DC electrical characteristics

This section discusses the electrical characteristics for the SGMII interface.

3.19.10.2.1 QSGMII transmitter DC specifications

This table describes the QSGMII SerDes transmitter AC-coupled DC electrical

characteristics. Transmitter DC characteristics are measured at the transmitter outputs

(SDn_TXn and SDn_TXn_B).

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Table 107. QSGMII DC transmitter electrical characteristics (XV_DD= 1.35V or 1.5V)¹

Parameter

Symbol

Min

Typ

Max

Unit

mV

Notes

Output differential voltage

V_DIFF

400

80

-

900

120

-

Differential resistance

T_RD

100

Ω

Notes:

1. For recommended operating conditions, see Table 3.

3.19.10.2.2 QSGMII DC receiver electrical characteristics

This table defines the QSGMII receiver DC electrical characteristics.

Table 108. QSGMII receiver DC timing specifications (SV_DD= 1.0V)¹

Parameter

Input differential voltage

Differential resistance

Notes:

Symbol

V_DIFF

R_RDIN

Min

Typical

Max

Unit

Notes

100

80

-

900

120

mV

Ω

-

100

1. For recommended operating conditions, see Table 3.

3.19.10.3 QSGMII AC timing specifications

This section discusses the AC timing specifications for the QSGMII interface.

3.19.10.3.1 QSGMII transmit AC timing specifications

This table provides the QSGMII transmitter AC timing specifications.

Table 109. QSGMII transmit AC timing specifications¹

Parameter

Transmitter baud rate

Symbol

T_BAUD

T_UHPJ

J_T

Min

Typ

Max

5.000 + 100 ppm

0.15

Unit

Gbps

Notes

5.000 - 100 ppm 5.000

-

Uncorrelated high probability jitter

Total jitter tolerance

Notes:

-

UI p-p

0.30

1. For recommended operating conditions, see Table 3.

3.19.10.3.2 QSGMII receiver AC timing Specification

This table provides the QSGMII receiver AC timing specifications.

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Electrical characteristics

Table 110. QSGMII receive AC timing specifications²

Parameter

Symbol

R_BAUD

R_DJ

Min

Typ

Max

Unit

Notes

Receiver baud rate

5.000 - 100 ppm 5.000

5.000 + 100 ppm Gbps

-

Uncorrelated bounded high probability jitter

Correlated bounded high probability jitter

Bounded high probability jitter

Sinusoidal jitter, maximum

-

0.15

0.30

0.45

5.00

0.05

0.60

UI p-p

R_CBHPJ

R_BHPJ

R_SJ-max

R_SJ-hf

R_Tj

1

-

Sinusoidal jitter, high frequency

Total jitter (does not include sinusoidal jitter)

Notes:

-

1. The jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PCB trace.

2. For recommended operating conditions, see Table 3.

The sinusoidal jitter may have any amplitude and frequency in the unshaded region of

this figure.

5 UI p-p

Sinuosidal

Jitter

20 dB/dec

Amplitude

0.05 UI p-p

20 MHz

35.2 kHz

3 MHz

Frequency

Figure 47. QSGMII single-frequency sinusoidal jitter limits

3.19.11 HiGig/HiGig2 interface

This section describes the HiGig/HiGig2 clocking requirements and its DC and AC

electrical characteristics.

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3.19.11.1 HiGig/HiGig2 clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

Only SerDes 1 and 2 (SD[1:2]_REF_CLK[1:2] and SD[1:2]_REF_CLK[1:2]_B) may be

used for SerDes HiGig/HiGig2 configurations based on the RCW Configuration field

SRDS_PRTCL. The ref clock frequency tolerance spec is 100ppm.

For more information on these specifications, see SerDes reference clocks.

3.19.11.2 HiGig/HiGig2 DC electrical characteristics

This section describes the DC electrical characteristics for HiGig/HiGig2.

3.19.11.2.1 HiGig/HiGig2 transmitter DC electrical characteristics

This table defines the HiGig/HiGig2 transmitter DC electrical characteristics.

Table 111. HiGig/HiGig2 transmitter DC electrical characteristics (XV_DD= 1.35V or 1.5V)²

Parameter

Symbol

V_DIFFPP

Min

Typical

Max

1600

Unit

Notes

Differential output voltage

800

1000

mV p-p

-

DC Differential transmitter impedance

Z_TX-DIFF-DC80

100

120

Ω

Transmitter DC

differential impedance

Notes:

1. Absolute output voltage limit

2. For recommended operating conditions, see Table 3.

3.19.11.2.2 HiGig/HiGig2 receiver DC electrical characteristics

This table defines the HiGig/HiGig2 receiver DC electrical characteristics.

Table 112. HiGig/HiGig2 receiver DC electrical characteristics (SV_DD= 1.0V)²

Parameter

Symbol

V_IN

Z_RX-DIFF-DC80

Min

Typical

Max

1600

120

Unit

mV p-p

Ω

Notes

Differential input voltage

200

-

1

DC Differential receiver impedance

100

DC Differential receiver

impedance

1. Measured at receiver

2. For recommended operating conditions, see Table 3.

3.19.11.3 HiGig/HiGig2 AC timing specifications

This section describes the AC timing specifications for HiGig/HiGig2.

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Electrical characteristics

3.19.11.3.1 HiGig/HiGig2 transmitter AC timing specifications

This table defines the HiGig/HiGig2 transmitter AC timing specifications. RefClk jitter is

not included.

Table 113. HiGig/HiGig2 transmitter AC timing specifications¹

Parameter

Deterministic jitter

Total jitter

Symbol

Min

Typical

Max

Unit

UI p-p

J_D

J_T

-

0.17

0.35

UI p-p

ps

Unit Interval: 3.125 Gbps (HiGig/HiGig2) UI

320 - 100 ppm

320

320 + 100 ppm

Unit Interval: 3.75 Gbps (HiGig/HiGig2)

UI

266.66 - 100 ppm 266.66

266.66 + 100

ppm

ps

Notes:

1. For recommended operating conditions, see Table 3.

3.19.11.3.2 HiGig/HiGig2 receiver AC timing specifications

This table defines the HiGig/HiGig2 receiver AC timing specifications. RefClk jitter is

not included.

Table 114. HiGig/HiGig2 receiver AC timing specifications³

Parameter

Symbol

J_D

Min

Typical

Max

Unit

UI p-p

Notes

Deterministic jitter tolerance

-

0.37

0.55

1

Combined deterministic and random

jitter tolerance

J_DR

UI p-p

Total jitter tolerance

J_T

UI

-

0.65

1, 2

-

Unit Interval: 3.125 Gbps (HiGig/

HiGig2)

320 - 100ppm 320

320 + 100ppm ps

Unit Interval: 3.75 Gbps (HiGig/HiGig2) UI

266.66 -

100ppm

266.66

266.66 +

100ppm

ps

-

1. Measured at receiver

2. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 43. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

3. For recommended operating conditions, see Table 3.

3.19.12 XFI interface

This section describes the XFI clocking requirements and its DC and AC electrical

characteristics.

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3.19.12.1 XFI clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

Only SerDes 2 (SD2_REF_CLK[1:2] and SD2_REF_CLK[1:2]_B) may be used for

SerDes XFI configurations based on the RCW Configuration field SRDS_PRTCL.

The ref clock frequency tolerance spec is 100ppm. For more information on these

specifications, see SerDes reference clocks.

3.19.12.2 XFI DC electrical characteristics

This section describes the DC electrical characteristics for XFI.

3.19.12.2.1 XFI transmitter DC electrical characteristics

This table defines the XFI transmitter DC electrical characteristics.

Table 115. XFI transmitter DC electrical characteristics (XV_DD= 1.35V or 1.5V)¹

Parameter

Symbol

V_TX-DIFF

Min

Typical

Max

Unit

Notes

Output differential voltage

360

0.6

-

770

1.6

mV

dB

-

De-emphasized differential output

voltage (ratio)

V_TX-DE-

1.1

3.5

4.6

6.0

9.5

100

RATIO-1.14dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

3

4

dB

Ω

-

RATIO-3.5dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

4.1

5.5

9

5.1

6.5

10

RATIO-4.66dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

RATIO-6.0dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

RATIO-9.5dB

Differential resistance

Notes:

T_RD

80

120

1. For recommended operating conditions, see Table 3.

3.19.12.2.2 XFI receiver DC electrical characteristics

This table defines the XFI receiver DC electrical characteristics.

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Table 116. XFI receiver DC electrical characteristics (SV_DD= 1.0V)²

Parameter

Input differential voltage

Differential resistance

1. Measured at receiver

Symbol

V_RX-DIFF

R_RD

Min

Typical

Max

Unit

Notes

110

80

-

1050

120

mV

Ω

1

-

100

2. For recommended operating conditions, see Table 3.

3.19.12.3 XFI AC timing specifications

This section describes the AC timing specifications for XFI.

3.19.12.3.1 XFI transmitter AC timing specifications

This table defines the XFI transmitter AC timing specifications. RefClk jitter is not

included.

Table 117. XFI transmitter AC timing specifications¹

Parameter

Transmitter baud rate

Symbol

T_BAUD

Min

Typical

Max

Unit

10.3125 - 100ppm 10.3125

10.3125 +

100ppm

-

Gb/s

ps

Unit Interval

Deterministic jitter

Total jitter

UI

D_J

T_J

-

96.96

-

0.155

0.30

UI p-p

Notes:

1. For recommended operating conditions, see Table 3.

3.19.12.3.2 XFI receiver AC timing specifications

This table defines the XFI receiver AC timing specifications. RefClk jitter is not

included.

Table 118. XFI receiver AC timing specifications³

Parameter

Receiver baud rate

Symbol

R_BAUD

Min

Typical

10.3125

Max

Unit

Gb/s

Notes

10.3125 -

100ppm

10.3125 +

100ppm

-

Unit Interval

UI

-

96.96

-

ps

-

Total non-EQJ jitter

Total jitter tolerance

T_NON-EQJ

T_J

-

0.45

0.65

UI p-p

1

1, 2

Table continues on the next page...

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NXP Semiconductors

Electrical characteristics

Table 118. XFI receiver AC timing specifications³(continued)

Parameter

Symbol

Min

Typical

Max

Unit

Notes

1. The total jitter (T_J) consists of Random Jitter (R_J), Duty Cycle Distortion (DCD), Periodic Jitter (P_J), and Inter symbol

Interference (ISI). Non-EQJ jitter can include duty cycle distortion (DCD), random jitter (R_J), and periodic jitter (P_J). Non-EQJ

jitter is uncorrelated to the primary data stream with exception of the DCD and so cannot be equalized by the receiver under

test. It can exhibit a wide spectrum. Non - EQJ = T_J- ISI = R_J+ DCD + P_J

2. The XFI channel has a loss budget of 9.6 dB @5.5GHz. The channel loss including connector @ 5.5GHz is 6dB. The

channel crosstalk and reflection margin is 3.6dB. Manual tuning of TX Equalization and amplitude will be required for

performance optimization.

3. For recommended operating conditions, see Table 3.

This figure shows the sinusoidal jitter tolerance of XFI receiver.

1.13x 0.2 + 0.1 , f in MHz

f

-20 dB/Dec

0.17

0.05

40

0.04

4

8

27.2

Frequency (MHz)

Figure 48. XFI host receiver input sinusoidal jitter tolerance

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

183

Electrical characteristics

3.19.13 10GBase-KR interface

This section describes the 10GBase-KR clocking requirements and its DC and AC

electrical characteristics.

3.19.13.1 10GBase-KR clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

Only SerDes 2 (SD2_REF_CLK[1:2] and SD2_REF_CLK[1:2]_B) may be used for

SerDes 10GBase-KR configurations based on the RCW Configuration field

SRDS_PRTCL. . The ref clock frequency tolerance spec is 100ppm.

For more information on these specifications, see SerDes reference clocks .

3.19.13.2 10GBase-KR DC electrical characteristics

This section describes the DC electrical characteristics for 10GBase-KR.

3.19.13.2.1 10GBase-KR transmitter DC electrical characteristics

This table defines the 10GBase-KR transmitter DC electrical characteristics.

Table 119. 10GBaseKR transmitter DC electrical characteristics (XV_DD= 1.35V or 1.5V)¹

Parameter

Symbol

V_TX-DIFF

Min

Typical

Max

Unit

Notes

Output differential voltage

800

0.6

-

1200

1.6

mV

dB

-

De-emphasized differential output

voltage (ratio)

V_TX-DE-

1.1

3.5

4.6

6.0

9.5

100

RATIO-1.14dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

3

4

dB

Ω

-

RATIO-3.5dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

4.1

5.5

9

5.1

6.5

10

RATIO-4.66dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

RATIO-6.0dB

De-emphasized differential output

voltage (ratio)

V_TX-DE-

RATIO-9.5dB

Differential resistance

T_RD

80

120

1. For recommended operating conditions, see Table 3.

3.19.13.2.2 10GBase-KR receiver DC electrical characteristics

This table defines the 10GBase-KR receiver DC electrical characteristics.

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NXP Semiconductors

Electrical characteristics

Table 120. 10GBase-KR receiver DC electrical characteristics (XV_DD= 1.35V or 1.5V)¹

Parameter

Input differential voltage

Differential resistance

Symbol

V_RX-DIFF

R_RD

Min

Typical

Max

Unit

Notes

-

1200

120

mV

Ω

-

80

1. For recommended operating conditions, see Table 3.

3.19.13.3 10GBase-KR AC timing specifications

This section describes the AC timing specifications for 10GBase-KR.

3.19.13.3.1 10GBase-KR transmitter AC timing specifications

This table defines the 10GBase-KR transmitter AC timing specifications. RefClk jitter is

not included.

Table 121. 10GBase-KR transmitter AC timing specifications¹

Parameter

Transmitter baud rate

Symbol

T_BAUD

Min

Typical

10.3125

Max

Unit

10.3125 - 100

ppm

10.3125 + 100

ppm

GBd

Deterministic jitter

Total jitter

D_J

T_J

-

0.155

0.30

UI p-p

1. For recommended operating conditions, see Table 3.

3.19.13.3.2 10GBase-KR receiver AC timing specifications

This table defines the 10GBase-KR receiver AC timing specifications. RefClk jitter is not

included.

Table 122. 10GBase-KR receiver AC timing specifications^4,3

Parameter

Receiver baud rate

Symbol

R_BAUD

Min

Typical

Max

Unit

Notes

10.3125 - 100 10.3125

ppm

10.3125 + 100 GBd

ppm

-

Random jitter

R_J

-

0.130

0.115

0.035

1.0

UI p-p

1

Sinusodial jitter, maximum

Duty cycle distortion

Total jitter

S_J-max

D_CD

T_J

UI p-p

1

1,2

1. The AC specifications do not include Refclk jitter.

2. The Total applied Jitter Tj = ISI + Rj + DCD + Sj-max where ISI is jitter due to frequency dependent loss.

3. TX Equalization and amplitude tuning is through software for performance optimization, as in Freescale provided SDKs.

4. For recommended operating conditions, see Table 3.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

185

Electrical characteristics

3.19.14 Interlaken interface

This section describes the Interlaken clocking requirements and its DC and AC electrical

characteristics.

3.19.14.1 Interlaken clocking requirements for SDn_REF_CLKn and

SDn_REF_CLKn_B

Only SerDes 3 (SD3_REF_CLK[1:2] and SD3_REF_CLK[1:2]_B) may be used for

SerDes Interlaken-LA configurations based on the RCW Configuration field

SRDS_PRTCL. The ref clock frequency tolerance spec is 100ppm.

For more information on these specifications, see SerDes reference clocks.

3.19.14.2 Interlaken-short reach DC electrical characteristics

This section describes the DC electrical characteristics for Interlaken-short reach.

3.19.14.2.1 Interlaken-short reach transmitter DC electrical characteristics

This table defines the Interlaken-short reach transmitter DC electrical characteristics.

Table 123. Interlaken-short reach transmitter DC electrical characteristics (XV_DD= 1.35V or

1.5V)¹

Parameter

Symbol

V_DIFF

Min

Typical

Max

Unit

Notes

Output differential voltage

400

80

-

750

120

mV

Ω

-

Differential resistance

T_RD

100

Notes:

1. For recommended operating conditions, see Table 3.

3.19.14.2.2 Interlaken-short reach receiver DC electrical characteristics

This table defines the Interlaken-short reach receiver DC electrical characteristics.

Table 124. Interlaken-short reach receiver DC electrical characteristics (SV_DD= 1.0V)¹

Parameter

Input differential voltage

Differential resistance

Notes:

Symbol

V_DIFF

R_RDIN

Min

Typical

Max

Unit

Notes

125

80

-

1200

120

mV

Ω

-

100

1. For recommended operating conditions, see Table 3.

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Electrical characteristics

3.19.14.3 Interlaken-short reach AC timing specifications

This section describes the AC timing specifications for Interlaken-short reach.

3.19.14.3.1 Interlaken-short reach transmitter AC timing specifications

This table defines the Interlaken-short reach transmitter AC timing specifications. RefClk

jitter is not included.

Table 125. Interlaken-short reach transmitter AC timing specifications¹

Parameter

Transmitter baud rate

Symbol

T_BAUD

Min

Typical

Max

Unit

3.125 - 100ppm 3.125

6.25 - 100 ppm 6.25

3.125 + 100ppm Gbps

6.25 + 100 ppm Gbps

Transmitter baud rate

Uncorrelated high probability jitter

Total jitter tolerance

Notes:

T_BAUD

T_UHPJ

T_J

-

0.155

0.30

UI p-p

1. For recommended operating conditions, see Table 3.

3.19.14.3.2 Interlaken-short reach receiver AC timing specifications

This table defines the Interlaken-short reach receiver AC timing specifications. RefClk

jitter is not included.

Table 126. Interlaken-short reach receiver AC timing specifications²

Parameter

Receiver baud rate

Symbol

R_BAUD

Min

Typical

Max

Unit

Gbps

Notes

3.125 - 100

ppm

3.125

3.125 + 100

ppm

-

Receiver baud rate

R_BAUD

R_UBHPJ

R_CBHPJ

R_BHPJ

6.25 - 100 ppm 6.25

6.25 + 100 ppm Gbps

-

Uncorrelated bounded high probability jitter

Correlated bounded high probability jitter

Bounded high probability jitter

Sinusoidal jitter, maximum

-

0.15

0.30

0.45

5.00

0.05

0.60

UI p-p

1

-

R_SJ-max

R_SJ-hf

-

Sinusoidal jitter, high frequency

-

Total jitter (does not include sinusoidal jitter) R_Tj

-

1. The jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PCB trace.

2. For recommended operating conditions, see Table 3.

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in

the unshaded region of this figure.

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NXP Semiconductors

187

Hardware design considerations

5 UI p-p

Sinuosidal

Jitter

20 dB/dec

Amplitude

0.05 UI p-p

20 MHz

baud/142000

baud/1667

Frequency

Figure 49. Single-frequency sinusoidal jitter limits

4 Hardware design considerations

4.1 System clocking

This section describes the PLL configuration of the chip.

4.1.1 PLL characteristics

Characteristics of the chip's PLLs include the following:

• There are five selectable core cluster PLLs which generate a clock for each core

cluster from the externally supplied SYSCLK input.

• Core cluster 1 (cores 0-3) can select from cluster group A PLL 1, 2 or 3 (CGA1,

2, 3 PLL)

• Core cluster 2 (cores 4-7) can select from cluster group A PLL 1, 2 or 3 (CGA1,

2, 3 PLL), not applicable to T4080 parts

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NXP Semiconductors

Hardware design considerations

• Core cluster 3 (cores 8-11) can select from cluster group B PLL 1 or 2 (CGB1, 2

PLL)

• The frequency ratio between each of the core cluster PLLs and SYSCLK is

selected using the configuration bits as described in Core cluster to SYSCLK

PLL ratio. The frequency for each core cluster 1-3 is selected using the

configuration bits as described in Table 131 and Table 132.

• The platform PLL generates the platform clock from the externally supplied

SYSCLK input. The frequency ratio between the platform and SYSCLK is selected

using the platform PLL ratio configuration bits as described in Platform to SYSCLK

PLL ratio.

• Cluster group A generates an asynchronous clock for PME from cluster group A

PLL 1 or cluster group A PLL 2. Described in Frame Manager (FMn) clock select.

• Cluster group B generates an asynchronous clock for FMan 1 and FMan 2 from the

platform PLL, cluster group B PLL 1, or cluster group B PLL 2. Described in Frame

Manager (FMn) clock select.

• The DDR block PLL generates an asynchronous DDR clock from the externally

supplied DDRCLK input. The frequency ratio is selected using the Memory

Controller Complex PLL multiplier/ratio configuration bits as described in DDR

controller PLL ratios.

• Each of the four SerDes blocks has 2 PLLs which generate a core clock from their

respective externally supplied SDn_REF_CLKn/SDn_REF_CLKn_B inputs. The

frequency ratio is selected using the SerDes PLL RCW configuration bits as

described in SerDes PLL ratio.

4.1.2 Clock ranges

This table provides the clocking specifications for the processor core, platform, memory,

and integrated flash controller.

Table 127. Processor, platform, and memory clocking specifications

Characteristic

Maximum processor core frequency

1500 MHz 1667 MHz 1800 MHz

Min Max Min Max Min Max

1000 1500 1000 1667 1000 1800

Unit

Notes

Core cluster group PLL frequency

Core cluster frequency

MHz

1, 2

See note 1500

2

See note 1667

2

See note 1800

2

MHz

2

Platform clock frequency

Memory bus clock frequency

IFC clock frequency

400

533

—

667

800

100

400

533

—

733

933.333 533

100

400

733

MHz

1, 7

1, 3, 4

5

933.333 MHz

100 MHz

—

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

189

Hardware design considerations

Table 127. Processor, platform, and memory clocking specifications (continued)

Characteristic

Maximum processor core frequency

1500 MHz 1667 MHz 1800 MHz

Min Max Min Max Min Max

Unit

Notes

PME

See note 500

6

See note 550

6

See note 550

6

MHz

6

8

FMn

450/667 667

450/667 733

1. Caution:The platform clock to SYSCLK ratio and core to SYSCLK ratio settings must be chosen such that the resulting

SYSCLK frequency, core frequency, and platform clock frequency do not exceed their respective maximum or minimum

operating frequencies.

2. The core cluster can run at cluster group PLL/1, PLL/2, or PLL/4. For the PLL/1 case, the minimum frequency is 1000

MHz. With a minimum cluster group PLL frequency of 1000 MHz, this results in a minimum allowable core cluster frequency

of 500 MHz for PLL/2. For the PLL/4 case, the minimum allowable core cluster frequency is platform clock frequency / 2. For

the case of the minimum platform frequency = 400 MHz, the minimum core cluster frequency is 200 MHz.

3. The memory bus clock speed is half the DDR3/DDR3L data rate. DDR3/3L memory bus clock frequency is limited to min =

533 MHz.

4. The memory bus clock speed is dictated by its own PLL.

5. The integrated flash controller (IFC) clock speed on IFC_CLK[0:2] is determined by the IFC module input clock (platform

clock / 2) divided by the IFC ratio programmed in CCR[CLKDIV]. See the chip reference manual for more information.

6. The PME minimum frequency is Platform Frequency / 2. For the case of the minimum platform frequency = 400 MHz, the

minimum PME frequency is 200 MHz.

7. The minimum platform frequency should meet the requirements in Minimum platform frequency requirements for high-

speed interfaces. For SRIO proper operations the FMAN minimum frequency has to be equal to 528 MHz.

8. If all MACs operate using RGMII or SGMII at 1.25 G, then the minimum required FMAN frequency is 450 MHz. Also, If any

MAC operates at a higher rate then the minimum FMAN is 667 MHZ.

4.1.2.1 DDR clock ranges

The DDR memory controller can run only in asynchronous mode, where the memory bus

is clocked with the clock provided on the DDRCLK input pin, which has its own

dedicated PLL.

This table provides the clocking specifications for the memory bus.

Table 128. Memory bus clocking specifications

Characteristic

Memory bus clock frequency

Notes:

Min

Max

933.3333

Unit

Notes

1, 2, 3

533

MHz

1. Caution: The platform clock to SYSCLK ratio and core to platform clock ratio settings must be chosen such that the

resulting SYSCLK frequency, core frequency, and platform frequency do not exceed their respective maximum or minimum

operating frequencies. See Platform to SYSCLK PLL ratio, and Core cluster to SYSCLK PLL ratio, and DDR controller PLL

ratios, for ratio settings.

2. The memory bus clock refers to the chip's memory controllers' Dn_MCK[0:3] and Dn_MCK[0:3]_B output clocks, running at

half of the DDR data rate.

3. The memory bus clock speed is dictated by its own PLL. See DDR controller PLL ratios.

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NXP Semiconductors

Hardware design considerations

4.1.3 Platform to SYSCLK PLL ratio

This table lists the allowed platform clock to SYSCLK ratios.

Because the DDR operates asynchronously, the memory-bus clock-frequency is

decoupled from the platform bus frequency.

For all valid platform frequencies supported on this chip, set the RCW Configuration

field SYS_PLL_CFG = 0b00.

Table 129. Platform to SYSCLK PLL ratios

Binary Value of SYS_PLL_RAT

Platform:SYSCLK Ratio

0_0011

0_0100

0_0101

0_0110

0_0111

0_1000

0_1001

0_1010

0_1011

0_1100

0_1101

0_1110

0_1111

1_0000

All Others

3:1

4:1

5:1

6:1

7:1

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

Reserved

4.1.4 Core cluster to SYSCLK PLL ratio

The clock ratio between SYSCLK and each of the core cluster PLLs is determined by the

binary value of the RCW Configuration field CGm_PLLn_RAT. This table describes the

supported ratios. For all valid core cluster frequencies supported on this chip, set the

RCW Configuration field CGn_PLL_CFG = 0b00.

This table lists the supported asynchronous core cluster to SYSCLK ratios.

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191

Hardware design considerations

Table 130. Core cluster PLL to SYSCLK ratios

Binary value of CGm_PLLn_RAT

00_1000

Core cluster:SYSCLK Ratio

8:1

00_1001

00_1010

00_1011

00_1100

00_1101

00_1110

00_1111

01_0000

01_0010

01_0100

01_0110

01_1001

01_1010

01_1011

All others

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

27:1

Reserved

4.1.5 Core complex PLL select

The clock frequency of each core cluster is determined by the binary value of the RCW

Configuration field Cn_PLL_SEL. These tables describe the selections available to each

core cluster, where each individual core cluster can select a frequency from their

respective tables.

NOTE

There is a restriction that requires that the frequency provided

to the e6500 core cluster after any dividers must always be

greater than half of the platform frequency. Special care must

be used when selecting the /2 or /4 outputs of a cluster PLL in

which this restriction is observed.

Table 131. Core cluster [1-2] PLL select

Binary Value of Cn_PLL_SEL for n = 1-2

Core cluster ratio

0000

0001

0010

0100

CGA PLL1/1

CGA PLL1/2

CGA PLL1/4

CGA PLL2/1

Table continues on the next page...

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192

NXP Semiconductors

Hardware design considerations

Table 131. Core cluster [1-2] PLL select (continued)

Binary Value of Cn_PLL_SEL for n = 1-2

Core cluster ratio

0101

CGA PLL2/2

CGA PLL2/4

CGA PLL3/1

CGA PLL3/2

CGA PLL3/4

Reserved

0110

1000

1001

1010

All Others

Table 132. Core cluster [3] PLL select

Binary Value of Cn_PLL_SEL for n = 3

Core cluster ratio

0000

CGB PLL1/1

CGB PLL1/2

CGB PLL1/4

CGB PLL2/1

CGB PLL2 2

CGB PLL2/4

Reserved

0001

0010

0100

0101

0110

All Others

4.1.6 DDR controller PLL ratios

The three DDR memory controller complexes operate asynchronous to the platform. All

DDR controllers operate at the same frequency configuration.

In asynchronous DDR mode, the DDR data rate to DDRCLK ratios supported are listed

in the following table. This ratio is determined by the binary value of the RCW

Configuration field MEM_PLL_RAT (bits 10-15).

The RCW Configuration field MEM_PLL_CFG (bits 8-9) must be set to

MEM_PLL_CFG = 0b00 for all valid DDR PLL reference clock frequencies supported

on this chip.

Table 133. DDR data Rate to DDRCLK ratios¹

Binary value of

MEM_PLL_RAT

Decimal values of

MEM_PLL_RAT

DDR data rate

to DDRCLK

Ratio value

Resulting DDR data-rate (MT/s)

Rev 1

Rev 2

Rev 1

Rev 2

Examples of DDRCLK frequency values that give

typical DDR data rata values at Ratio value

silicon

66.6667

MHz

100 MHz

125 MHz

133.333 MHz

00_1010

00_0101

10

5

10

1333.333

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

193

Hardware design considerations

Table 133. DDR data Rate to DDRCLK ratios¹(continued)

Binary value of

MEM_PLL_RAT

Decimal values of

MEM_PLL_RAT

DDR data rate

to DDRCLK

Ratio value

Resulting DDR data-rate (MT/s)

Rev 1

Rev 2

Rev 1

Rev 2

Examples of DDRCLK frequency values that give

typical DDR data rata values at Ratio value

silicon

66.6667

MHz

100 MHz

125 MHz

133.333 MHz

00_1100

00_1110

01_0000

01_0010

01_0100

00_0110

00_0111

00_1000

00_1001

00_1010

12

14

16

18

20

6

7

12

14

1500

1750

1600

1866.667

8

16

1066.667

1333.333

1600

1800

9

18

10

20

All Others All Others Reserved Reserved

Reserved

Notes:

1. This table shows examples of standard DDR data rate resulted from multiplying the MEM_PLL_RAT by some common

DDRCLK frequencies like 66.66MHZ, 100MHz, or 133MHZ. Customers can supply of course different DDRCLK frequency

from the common ones presented in this table and thus they have to pick up the correct MEM_PLL_RAT value that will give

them a common DDR data rate and always use a value for Rev2 silicon that is half of what is supposed to be given in Rev1

or simply in rev2 MEM_PLL_RAT = 0.5 * DDR data rate/ DDRCLK.

4.1.7 SerDes PLL ratio

The clock ratio between each of the three SerDes PLLs and their respective externally

supplied SDn_REF_CLKn/SDn_REF_CLKn_B inputs is determined by a set of RCW

Configuration fields-SRDS_PRTCL_Sn, SRDS_PLL_REF_CLK_SEL_Sn, and

SRDS_DIV_*_Sn-as shown in this table.

Table 134. Valid SerDes RCW encodings and reference clocks

SerDes protocol (given

lane)

Valid reference

clock

Legal setting for

SRDS_PRTCL_Sn

Legal setting

for

Legal setting for Notes

SRDS_DIV_*_Sn

frequency

SRDS_PLL_RE

F_CLK_SEL_Sn

High-speed serial and debug interfaces

PCI Express 2.5 GT/s

100 MHz

125 MHz

100 MHz

125 MHz

100 MHz

125 MHz

100 MHz

125 MHz

Any PCIe

0b0: 100 MHz

2b10: 2.5 G

2b01: 5.0 G

2b00: 8.0 G

0b1: 2.5 G

Don't care

1

-

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 125 MHz

(doesn't negotiate upwards)

PCI Express 5 GT/s

Any PCIe

(can negotiate up to 5 GT/s)

PCI Express 8 GT/s

Any PCIe

(can negotiate up to 8 GT/s)

Serial RapidIO 2.5 Gbaud

SRIO @ 2.5/5 Gbaud

SRIO @ 3.125 Gbaud

-

Serial RapidIO 3.125 Gbaud

-

Table continues on the next page...

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194

NXP Semiconductors

Hardware design considerations

Table 134. Valid SerDes RCW encodings and reference clocks (continued)

SerDes protocol (given

lane)

Valid reference

clock

Legal setting for

SRDS_PRTCL_Sn

Legal setting

for

Legal setting for Notes

SRDS_DIV_*_Sn

frequency

SRDS_PLL_RE

F_CLK_SEL_Sn

156.25 MHz

100 MHz

0b1: 156.25 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 125 MHz

0b1: 156.25 MHz

-

Serial RapidIO 5 Gbaud

SRIO @ 2.5/5 Gbaud

0b0: 5.0 G

Don't care

-

125 MHz

Interlaken Lookaside (6.25

Gbps)

125 MHz

Interlaken LA @ 6.25

Gbps

156.25 MHz

Interlaken Lookaside (10.3125 156.25 MHz

Interlaken LA @ 10.3125 0b0: 156.25 MHz Don't care

Gbps)

Gbps

161.1328125

0b1:

MHz

161.1328125

MHz

SATA (1.5 or 3 Gbps)

Debug (2.5 Gbps)

Debug (3.125 Gbps)

Debug (5 Gbps)

100 MHz

125 MHz

100 MHz

125 MHz

156.25 MHz

100 MHz

125 MHz

Any SATA

0b0: 100 MHz

0b1: 125 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 125 MHz

0b1: 156.25 MHz

0b0: 100 MHz

0b1: 125 MHz

Don't care

0b1: 2.5 G

Don't Care

0b0: 5.0 G

2

Aurora @ 2.5/5 Gbps

Aurora @ 3.125 Gbps

Aurora @ 2.5/5 Gbps

-

Networking interfaces

SGMII (1.25 Gbaud)

2.5x SGMII (3.125 Gbaud)

QSGMII (5.0 Gbps)

XAUI (3.125 Gb/s)

100 MHz

125 MHz

156.25 MHz

100 MHz

125 MHz

156.25 MHz

SGMII @ 1.25 Gbaud

0b0: 100 MHz

0b1: 125 MHz

0b0: 125 MHz

0b1: 156.25 MHz

0b0: 100 MHz

0b1: 125 MHz

0b0: 125 MHz

0b1: 156.25 MHz

0b0: 125 MHz

0b1: 156.25 MHz

0b0: 125 MHz

0b1: 156.25 MHz

Don't care

0b0: 5.0 G

Don't care

-

SGMII @ 3.125 Gbaud

Any QSGMII

XAUI @ 3.125 Gb/s

HiGig @ 3.125 Gbps

HiGig @ 3.75 Gbps

XFI @ 10.3125 Gbps

HiGig or HiGig2 (3.125 Gbps) 125 MHz

156.25 MHz

125 MHz

HiGig or HiGig2 (3.75 Gbps)

156.25 MHz

XFI (10.3125 Gbps)

0b0: 156.25 MHz Don't care

10GBase-KR (10.3125 GBd) 156.25 MHz

10GBase-KR @ 10.3125 0b0: 156.25 MHz Don't care

GBd

1. A spread-spectrum reference clock is permitted for PCI Express. However, if any other high-speed interfaces such as

sRIO, Interlaken, SATA, SGMII, SGMII 2.5x, QSGMII, XAUI, XFI, 10GBase-KR, HiGig/HiGig2 or Aurora are used

concurrently on the same SerDes bank, spread-spectrum clocking is not permitted.

2. SerDes lanes configured as SATA initially operate at 3.0 Gbps. 1.5 Gbps operation may later be enabled through the

SATA IP itself. It is possible for software to set each SATA at different rates.

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Hardware design considerations

4.1.8 Frame Manager (FMn) clock select

The following tables describe the clocking options that may be applied to each FM. The

clock selection is determined by the binary value of the RCW Clocking Configuration

fields HWA_CGB_M1_CLK_SEL and HWA_CGB_M2_CLK_SEL.

Table 135. Frame Manager (FMn) clock select

Binary value of

Frame Manager (FM1) clock select¹

Frame Manager (FM2) clock select¹

HWA_CGB_Mn_CLK_SEL

000b, 001b

Reserved

010b

Cluster group B PLL 1/2

Cluster group B PLL 1/3

Cluster group B PLL 1/4

Platform clock frequency/1

Cluster group B PLL 2/2

Reserved

Cluster group B PLL 2/2

Cluster group B PLL 2/3

Cluster group B PLL 2/4

Platform clock frequency/1

Cluster group B PLL 1/2

Cluster group B PLL 1/3

011b

100b

101b

110b

111b

1. For max frequency, see Table 127 .

4.1.9 Pattern Matching Engine (PME) clock select

The PME can be synchronous with or asynchronous to the platform, depending on

configuration.

This table describes the clocking options that may be applied to the PME. The clock

selection is determined by the binary value of the RCW Clocking Configuration field

HWA_CGA_M1_CLK_SEL.

Table 136. Pattern Matching Engine clock select

Binary Value of HWA_CGA_M1_CLK_SEL

PME Frequency ¹

Platform clock frequency/2 (synchronous mode)

Reserved

000b

001b

010b

011b

100b

101b

110b

111b

Note:

Cluster group A PLL 1/2 (Asynchronous mode)

Cluster group A PLL 1/3 (Asynchronous mode)

Cluster group A PLL 1/4 (Asynchronous mode)

Reserved

Cluster group A PLL 2/2 (Asynchronous mode)

Cluster group A PLL 2/3 (Asynchronous mode)

1. For asynchronous mode, max frequency, see Table 127.

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4.1.10 Frequency options

This section discusses interface frequency options.

4.1.10.1 SYSCLK and core cluster frequency options

This table shows the expected frequency options for SYSCLK and core cluster

frequencies.

Table 137. SYSCLK and core cluster frequency options

Core cluster: SYSCLK Ratio²

SYSCLK (MHz) ²

66.67

100.00

133.33

Core cluster Frequency (MHz)¹

8:1

1067

9:1

1200

1333

1467

1600

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

27:1

Notes:

1000

1100

1200

1400

1500

1600

1800

1000

1067

1200

1333

1467

1667

1800

1. Core cluster frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)

2. Example values.

4.1.10.2 SYSCLK and platform frequency options

This table shows the expected frequency options for SYSCLK and platform frequencies.

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Table 138. SYSCLK and platform frequency options

Platform: SYSCLK Ratio³

SYSCLK (MHz)³

66.67

100.00

Platform Frequency (MHz)¹

400

133.33

4:1

533

667

5:1

6:1

400²

600

700

7:1

8:1

533

600

667

733

9:1

10:1

11:1

12:1

Notes:

1. Platform frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)

2. A minimum platform clock frequency requirement is 528MHz if x4 SRIO is used.

3.Example values.

4.1.10.3 DDRCLK and DDR data rate frequency options

This table shows the expected frequency options for DDRCLK and DDR data rate

frequencies.

Table 139. DDRCLK and DDR data rate frequency options

DDR data rate: DDRCLK

Ratio²

DDRCLK (MHz)²

66.67

100.00 125.00

133.33

DDR Data Rate (MT/s)¹

10:1

1333

1600

1866

12:1

14:1

16:1

18:1

20:1

Notes:

1500

1750

1067

1333

1600

1800

1. DDR data rate values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. Example values.

4.1.10.4 SYSCLK and FMan frequency options

These table shows the expected frequency options for SYSCLK and FMan frequencies.

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Table 140. SYSCLK and FMan frequency options (clocked by CGB PLLn / 2)

Core cluster: SYSCLK Ratio³

SYSCLK (MHz)³

66.67

100.00

133.33

FMan Frequency (MHz)^{1, 2}

8:1

533

600

667

733

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

27:1

Notes:

500

550

600

700

750

500

533

600

667

733

1. FMan frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. For min frequency, see Table 127.

3. Example values.

Table 141. SYSCLK and FMan frequency options (clocked by CGB PLLn / 3)

Core cluster: SYSCLK Ratio³

SYSCLK (MHz)³

66.67

100.00

133.33

FMan Frequency (MHz)^{1, 2}

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

489

533

578

467

500

533

600

489

Table continues on the next page...

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Table 141. SYSCLK and FMan frequency options (clocked by CGB PLLn / 3)

(continued)

Core cluster: SYSCLK Ratio³

SYSCLK (MHz)³

66.67

100.00

133.33

FMan Frequency (MHz)^{1, 2}

25:1

556

578

600

26:1

27:1

Notes:

1. FMan frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed)

2. For min frequency, see Table 127

3. Example values.

Table 142. SYSCLK and FMan frequency options (clocked by CGB PLL1 / 4)

Core cluster: SYSCLK Ratio³

SYSCLK (MHz)³

66.67

100.00

133.33

FMan Frequency (MHz)^{1, 2}

8:1

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

27:1

Notes:

450

1. FMan frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. For min frequency, see Table 127.

3. Example values.

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Table 143. SYSCLK and FMan frequency options (clocked by platform frequency/1)

Platform: SYSCLK Ratio³

SYSCLK (MHz)³

66.67

100.00

133.33

FMan Frequency (MHz)^{1, 2}

4:1

533

667

5:1

6:1

600

700

7:1

8:1

533

600

667

733

9:1

10:1

11:1

12:1

Notes:

1. FMan frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. For min frequency, see Table 127.

3. Example values.

4.1.10.5 SYSCLK and PME frequency options

These table shows the expected frequency options for SYSCLK and PME frequencies.

Table 144. SYSCLK and PME frequency options (clocked by CGA PLLn / 2)

Core cluster: SYSCLK Ratio²

SYSCLK (MHz)²

66.67

100.00

133.33

PME Frequency (MHz)¹

8:1

533

600

9:1

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

500

550

600

500

533

600

Table continues on the next page...

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Table 144. SYSCLK and PME frequency options (clocked by CGA PLLn / 2)

(continued)

Core cluster: SYSCLK Ratio²

SYSCLK (MHz)²

66.67

100.00

133.33

PME Frequency (MHz)¹

27:1

Notes:

1. PME frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. Example values.

Table 145. SYSCLK and PME frequency options (clocked by CGA PLLn / 3)

Core cluster: SYSCLK Ratio²

SYSCLK (MHz)²

66.67

100.00

133.33

PME Frequency (MHz)¹

8:1

9:1

400

444

489

533

578

10:1

11:1

12:1

13:1

14:1

15:1

16:1

18:1

20:1

22:1

25:1

26:1

27:1

Notes:

400

467

500

533

600

400

444

489

556

578

600

1. PME frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. Example values.

Table 146. SYSCLK and PME frequency options (clocked by platform frequency/2)

Platform: SYSCLK Ratio²

SYSCLK (MHz)²

66.67

100.00

133.33

PME Frequency (MHz)¹

4:1

5:1

200

267

334

Table continues on the next page...

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Table 146. SYSCLK and PME frequency options (clocked by platform frequency/2)

(continued)

Platform: SYSCLK Ratio²

SYSCLK (MHz)²

100.00

66.67

133.33

PME Frequency (MHz)¹

6:1

200

300

400

7:1

350

400

8:1

267

300

334

367

400

9:1

10:1

11:1

12:1

Notes:

1. PME frequency values are shown rounded up to the nearest whole number (decimal place accuracy removed).

2. Example values.

4.1.10.6 Minimum platform frequency requirements for high-speed

interfaces

The platform clock frequency must be considered for proper operation of high-speed

interfaces as described below.

For proper PCI Express operation, the platform clock frequency must be greater than or

equal to:

527 MHz x (PCI Express link width)

16

Figure 50. Gen 1 PEX minimum platform frequency

527 MHz x (PCI Express link width)

8

Figure 51. Gen 2 PEX minimum platform frequency

527 MHz x (PCI Express link width)

4

Figure 52. Gen 3 PEX minimum platform frequency

See section "Link Width," in the chip reference manual for PCI Express interface width

details. Note that "PCI Express link width" in the above equation refers to the negotiated

link width as the result of PCI Express link training, which may or may not be the same

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as the link width POR selection. It refers to the widest port in use, not the combined

width of the number ports in use. For instance, if two x4 PCIe Gen3 ports are in use,

527MHz platform frequency is needed to support by using Gen 3 equation (527 x 4 / 4,

not 527 x 4 x 2 / 4).

4.2 Power supply design

4.2.1 Voltage ID (VID) controllable supply

To guarantee performance and power specifications, a specific method of selecting the

optimum voltage-level must be implemented when the chip is used. As part of the chip's

boot process, software must read the VID efuse values stored in the Fuse Status register

(FUSESR) and then configure the external voltage regulator based on this information.

This method requires a point of load voltage regulator for each chip.

NOTE

During the power-on reset process, the fuse values are read and

stored in the FUSESR. It is expected that the chip's boot code

reads the FUSESR value very early in the boot sequence and

updates the regulator accordingly.

The default voltage regulator setting that is safe for the system to boot is the

recommended operating V_DDat initial start-up of 1.025 V. It is highly recommended to

select a regulator with a Vout range of at least 0.9 V to 1.1 V, with a resolution of

12.5 mV or better, when implementing a VID solution. If the VID for a specific part is

already known at initial start-up, it is acceptable to program the voltage regulator to the

VID value. The device does not require an initial voltage of 1.025V at start-up.

The table below lists the valid VID efuse values that will be programmed at the factory

for this chip.

Table 147. Fuse Status Register

(DCFG_CCSR_FUSESR)

Binary value of DA_V / DA_ALT_V

V_DDvoltage

0.9875 V

0.9750 V

1.0000 V

1.0125 V

1.0250 V

00001

00010

10000

10001

10010

All other values

See the complete list in the Fuse Status Register

(DCFG_CCSR_FUSESR) section of the chip reference

manual.

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If DA_ALT_V is not all zeros, then software should read DA_ALT_V for the VID value

and not the DA_V. For additional information on VID, please see the chip reference

manual.

4.2.1.1 Options for system design

There are several widely-accepted options available to the system designer for obtaining

the benefits of a VID solution. The most common option is to use the VID solution to

drive a system's controllable voltage-regulators through a sideband interface such as a

simple parallel bus or PMBus interface. PMbus is similar to I²C but with extensions to

improve robustness and address shortcomings of I²C; the PMBus specification can be

found at www.pmbus.org. The simple parallel bus is supported by the chip through GPIO

pins and the PMBus interface is supported by an I²C interface. Other VID solutions may

be to access an FPGA/ASIC or separate power management chip through the IFC, SPI, or

other chip-specific interface, where the other device then manages the voltage regulator.

The method chosen for implementing the chip-specific voltage in the system is decided

by the user.

4.2.1.1.1 Example 1: Regulators supporting parallel bus configuration

In this example, a user builds a VID solution using controllable regulators with a parallel

bus. In this implementation, the user chooses to utilize any subset of the available GPIO

pins on the chip except those noted below.

NOTE

GPIO pins that are muxed on an interface used by the

application for loading RCW information are not available for

VID use.

It is recommended that all GPIO pins used for VID are located

in the same 32-bit GPIO IP block so that all bits can be

accessed with a single read or write.

The general procedure for setting the core voltage regulator to the desired operating

voltage is as follows:

1. The GPIO pins are released to high-impedance at POR. Because GPIO pins default

to being inputs, they do not begin automatically driving after POR, and only work as

outputs under software control.

2. The board is responsible for a default voltage regulator setting that is "safe" for the

system to boot. To achieve this, the user puts pull-up and/or pull-down resistors on

the GPIO pins as needed for that specific system. For the case where the regulator's

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interface operates at a different voltage than OV_DD, the chip's GPIO module can be

operated in an open drain configuration.

3. There is no direct connection between the Fuse Status Register (FUSESR) and the

chip's pins. As part of the chip's boot process, software must read the efuse values

stored in the FUSESR and then configure the voltage regulator based on this

information. The software determines the proper value for the parallel interface and

writes it to the GPIO block data (GPDAT) register. It then changes the GPIO

direction (GPDIR) register from input to output to drive the new value on the device

pins, thus overriding the board configuration default value. Note that some regulators

may require a series of writes so that the voltage is slowly stepped from its old to its

new value.

4. When the voltage has stabilized, software adjusts the operating frequencies as

desired.

Upon completion of configuration, some regulators may have a write-protect pin to

prevent undesired data changes after configuration is complete. A single GPIO pin on the

chip could be allocated for this task if desired.

4.2.1.1.2 Example 2: Regulators supporting PMBus configuration

In this example, a user builds a VID solution using controllable regulators with a PMBus

interface. For the case where the regulator's interface operates at a different voltage than

DV_DD, the chip's I²C module can be operated in an open-drain configuration.

In this implementation, the user chooses to utilize any I²C interface available on the chip.

These regulators have a means for setting a safe, default, operating value either through

strapping pins or through a default, non-volatile store.

NOTE

If I²C1 controller is selected, it is important that its calling

address is different than the 7-bit value of 0x50h used by the

pre-boot loader (PBL) for RCW and pre-boot initialization.

The general procedure for setting the core voltage regulator to the desired operating

voltage is as follows:

1. The board is responsible for configuring a safe default value for the controllable

regulator either through dedicated pins or its non-volatile store.

2. As part of the chip's boot process, software must read the efuse values stored in the

FUSESR register and then configure the voltage regulator based on this information.

The software decides on a new configuration and sends this value across the I²C

interface connected to the regulator's PMBus interface. Note that some regulators

may require a series of writes so that the voltage is slowly stepped from its old to its

new value.

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3. When the voltage has stabilized, software adjusts the operating frequencies as

desired.

Upon completion of configuration, some regulators may have a write-protect pin to

prevent undesired data changes after configuration is complete. A single GPIO pin on the

chip could be allocated for this task, if desired.

4.2.1.1.3 Example 3: Regulators supporting FPGA/ASIC or separate power

management device configuration

In this example, a user builds a VID solution using controllable regulators that are

managed by a FPGA/ASIC or a separate power-management device. In this

implementation, the user chooses to utilize the IFC, eSPI or any other available chip

interface to connect to the power-management device.

The general procedure for setting the core voltage regulator to the desired operating

voltage is as follows:

1. The board is responsible for configuring a safe default value for the controllable

regulator either through dedicated pins or its non-volatile store.

2. As part of the chip's boot process, software must read the efuse values stored in the

FUSESR and then configure the voltage regulator based on this information. The

software decides on a new configuration and sends this value across the IFC, eSPI, or

any other interface that is used to connect to the FPGA/ASIC or separate power-

management device that manages the regulator. Note that some regulators may

require a series of writes so that the voltage is slowly stepped from its old to its new

value.

3. When the voltage has stabilized, software adjusts the operating frequencies as

desired.

Upon completion of configuration, some regulators may have a write-protect pin to

prevent undesired data changes after configuration is complete. A single GPIO pin on the

chip could be allocated for this task, if desired.

4.2.2 Core and platform supply voltage filtering

The V_DDsupply is normally derived from a high current capacity linear or switching

power supply which can regulate its output voltage very accurately despite changes in

current demand from the chip within the regulator's relatively low bandwidth. Several

bulk decoupling capacitors must be distributed around the PCB to supply transient

current demand above the bandwidth of the voltage regulator.

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These bulk capacitors should have a low ESR (equivalent series resistance) rating to

ensure the quick response time necessary. They should also be connected to the power

and ground planes through two vias to minimize inductance. However, customers should

work directly with their power regulator vendor for best values and types of bulk

capacitors.

As a guideline for customers and their power regulator vendors, NXP recommends that

these bulk capacitors be chosen to maintain the positive transient power surges to less

than VID+50 mV (except that a positive transient of up to +100 mV can be tolerated for

less than 1 us, negative transient undershoot should comply with specification of

VID-30mV) for current steps of up to 20A for 12 cores, 15A for 8 cores and 10A for 4

cores with a slew rate of 12 A/us.

These bulk decoupling capacitors will ideally supply a stable voltage for current

transients into the megahertz range. Above that, see Decoupling recommendations for

further decoupling recommendations.

4.2.3 PLL power supply filtering

Each of the PLLs described in System clocking is provided with power through

independent power supply pins (AV_DD_PLAT, A_VDD_CGAn, A_VDD_CGBn and

AV_DD_Dn and AV_DD_SDn_PLLn). AV_DD_PLAT, A_VDD_CGAn, A_VDD_CGBn and

AV_DD_Dn voltages must be derived directly from a 1.8 V voltage source through a low

frequency filter scheme. AV_DD_SDn_PLLn voltages must be derived directly from the

XnV_DDsource through a low frequency filter scheme. The recommended solution for

PLL filtering is to provide independent filter circuits per PLL power supply, as illustrated

in Figure 53, one for each of the AV_DDpins. By providing independent filters to each

PLL, the opportunity to cause noise injection from one PLL to the other is reduced. This

circuit is intended to filter noise in the PLL's resonant frequency range from a 500 kHz to

10 MHz range.

Each circuit should be placed as close as possible to the specific AV_DDpin being

supplied to minimize noise coupled from nearby circuits. It should be possible to route

directly from the capacitors to the AV_DDpin, which is on the periphery of the footprint,

without the inductance of vias.

This figure shows the PLL power supply filter circuit.

Where:

• R = 5 Ω 5%

• C1 = 10 μF 10%, 0603, X5R, with ESL ꢀ 0.5 nH

• C2 = 1.0 μF 10%, 0402, X5R, with ESL ꢀ 0.5 nH

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NOTE

A higher capacitance value for C2 may be used to improve

the filter as long as the other C2 parameters do not change

(0402 body, X5R, ESL ꢀ 0.5 nH).

NOTE

Keep filter close to pin. Voltage and tolerance for AV_DDis

defined at the input of the PLL supply filter and not the pin

of AV_DD.

R

1.8 V source

AV_DD_PLAT, AV_DD_CGAn, AV_DD_CGBn, AV_DD_Dn

C1

C2

Low-ESL surface-mount capacitors

GND

Figure 53. PLL power supply filter circuit

The AV_DD_SDn_PLLn signals provide power for the analog portions of the SerDes PLL.

To ensure stability of the internal clock, the power supplied to the PLL is filtered using a

circuit similar to the one shown in following Figure 54. For maximum effectiveness, the

filter circuit is placed as closely as possible to the AV_DD_SDn_PLLn balls to ensure it

filters out as much noise as possible. The ground connection should be near the

AV_DD_SDn_PLLn balls. The 0.003-µF capacitors closest to the balls, followed by a 4.7-

µF and 47-µF capacitor, and finally the 0.33 Ω resistor to the board supply plane. The

capacitors are connected from AV_DD_SDn_PLLn to the ground plane. Use ceramic chip

capacitors with the highest possible self-resonant frequency. All traces should be kept

short, wide, and direct.

0.33 Ω

XnV

AV_DD_SDn_PLLn

DD

47μF

4.7 μF

0.003 μF

0 Ω

XnV

DD

board GND

AGND_SDn_PLLn

zero Ω 0603 sized default resistance

with provision to be changed to inductance

Figure 54. SerDes PLL power supply filter circuit

Note the following:

• AV_DD_SDn_PLLn should be a filtered version of XnV_DD.

• Signals on the SerDes interface are fed from the XnV_DDpower plane.

• Voltage for AV_DD_SDn_PLLn is defined at the PLL supply filter and not the pin of

AV_DD_SDn_PLLn.

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• A 47-µF 0805 XR5 or XR7, 4.7-µF 0603, and 0.003-µF 0402 capacitor are

recommended. The size and material type are important. A 0.33-Ω 1% resistor is

recommended.

• There needs to be dedicated analog ground, AGND_SDn_PLLn for each

AV_DD_SDn_PLLn pin up to the physical local of the filters themselves.

4.2.4 SnV_DDpower supply filtering

SnV_DDmust be supplied by a decicated linear regulator.

An example solution for SnV_DDfiltering, where SnV_DDis sourced from a linear

regulator, is illustrated in Figure 55. The component values in this example filter are

system dependent and are still under characterization, component values may need

adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF 10%, X5R, with ESL ꢀ 0.5 nH

• C2 and C3 = 2.2 μF 10%, X5R, with ESL ꢀ 0.5 nH

• F1 and F2 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its

maximum DC resistance is 0.05Ω, or 0.025Ω for the parallel resultant, and each has

about a 120 Ω +/- 25% of AC impedance at 100 MHz, which is half valued for the

parallel resultant, with individual maximum DC current carrying capacity of 2Amps.

• Bulk and decoupling capacitors are added, as needed, per power supply design.

F1

F2

Bulk and

decoupling

capacitors

SnV_DD

Linear regulator output

C1

C2

C3

GND

Figure 55. SV_DDpower supply filter circuit

Note the following:

• Please refer to Power-on ramp rate, for maximum SnV_DDpower-up ramp rate.

• There needs to be enough output capacitance or a soft start feature to assure ramp

rate requirement is met.

• The ferrite beads should be placed in parallel to reduce voltage droop.

• Besides a linear regulator, a low noise dedicated switching regulator can also be

used. 10 mVp-p, 50kHz - 500MHz is the noise goal.

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4.2.5 XnV_DDpower supply filtering

XnV_DDmay be supplied by a linear regulator or sourced by a filtered GnV_DD. Systems

may design in both options to allow flexibility to address system noise dependencies.

However, for initial system bring-up, the linear regulator option is highly recommended.

An example solution for XnV_DDfiltering, where XnV_DDis sourced from a linear

regulator, is illustrated in Figure 56. The component values in this example filter are

system dependent and are still under characterization, component values may need

adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF 10%, X5R, with ESL ꢀ 0.5 nH

• C2 and C3 = 2.2 μF 10%, X5R, with ESL ꢀ 0.5 nH

• F1 and F2 are 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its

maximum DC resistance is 0.05Ω, or 0.025Ω for the parallel resultant, and each has

about a 120+-25% Ω of AC impedance at 100 MHz, which is half valued for the

parallel resultant, with individual maximum DC current carrying capacity of 2Amps.

• Bulk and decoupling capacitors are added, as needed, per power supply design.

F1

Bulk and

decoupling

capacitors

XnV_DD

Linear regulator output

C1

C2

C3

F2

GND

Figure 56. XnV_DDpower supply filter circuit

Note the following:

• See Power-on ramp rate for maximum XnV_DDpower-up ramp rate.

• There needs to be enough output capacitance or a soft-start feature to assure ramp

rate requirement is met.

• The ferrite beads should be placed in parallel to reduce voltage droop.

• Besides a linear regulator, a low-noise, dedicated switching regulator can be used. 10

mVp-p, 50 kHz - 500 MHz is the noise goal.

4.2.6 USB_HV_DDand USB_OV_DDpower supply filtering

USB_HV_DDand USB_OV_DDmust be sourced by a filtered 3.3 V and 1.8 V voltage

source using a star connection. An example solution for USB_HV_DDand USB_OV_DD

filtering, where USB_HV_DDand USB_OV_DDare sourced from a 3.3 V and 1.8 V voltage

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Hardware design considerations

source, is illustrated in the following figure. The component values in this example filter

is system dependent and are still under characterization, component values may need

adjustment based on the system or environment noise.

Where:

• C1 = 0.003 μF 10%, X5R, with ESL ꢀ 0.5 nH

• C2 and C3 = 2.2 μF 10%, X5R, with ESL ꢀ 0.5 nH

• F1 is an 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its

maximum DC resistance is 0.05Ω and it has about a 120+-25% Ω of AC impedance

at 100 MHz with maximum DC current carrying capacity of 2Amps.

• Bulk and decoupling capacitors are added, as needed, per power supply design.

F1

Bulk and

decoupling

capacitors

USB_HV_DD

or USB_OV_DD

3.3 V or 1.8 V source

C1

C2

C3

GND

Figure 57. USB_HV_DDand USB_OV_DDpower supply filter circuit

4.2.7 USB_SV_DDpower supply filtering

USB_SV_DDmust be sourced by a filtered V_DDusing a star connection. An example

solution for USB_SV_DDfiltering, where USB_SV_DDis sourced from V_DD, is illustrated

in the following figure. The component values in this example filter is system dependent

and are still under characterization, component values may need adjustment based on the

system or environment noise.

Where:

• C1 = 2.2 μF 20%, X5R, with Low ESL (for example, Panasonic ECJ0EB0J225M)

• F1 is an 0603 sized Ferrite SMD, like the Murata part BLM18PG121SH1. Its

maximum DC resistance is 0.05Ω and it has about a 120+-25% Ω of AC impedance

at 100 MHz with maximum DC current carrying capacity of 2Amps.

• Bulk and decoupling capacitors are added, as needed, per power supply design.

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Hardware design considerations

F1

Bulk and

decoupling

capacitors

V_DD

USB_SV_DD

C1

GND

Figure 58. USB_SV_DDpower supply filter circuit

4.3 Decoupling recommendations

Due to large address and data buses, and high operating frequencies, the device can

generate transient power surges and high frequency noise in its power supply, especially

while driving large capacitive loads. This noise must be prevented from reaching other

components in the chip system, and the chip itself requires a clean, tightly regulated

source of power. Therefore, it is recommended that the system designer place at least one

decoupling capacitor at each V_DD, OV_DD, DV_DD, GnV_DD, and LV_DDpin of the device.

These decoupling capacitors should receive their power from separate V_DD, OV_DD,

DV_DD, GnV_DD, LV_DD, and GND power planes in the PCB, utilizing short traces to

minimize inductance. Capacitors may be placed directly under the device using a

standard escape pattern. Others may surround the part.

These capacitors should have a value of 0.1 µF. Only ceramic SMT (surface mount

technology) capacitors should be used to minimize lead inductance, preferably 0402 or

0603 sizes.

As presented in Core and platform supply voltage filtering, it is recommended that there

be several bulk storage capacitors distributed around the PCB, feeding the V_DDand other

planes (for example, OV_DD, DV_DD, GnV_DD, and LV_DD), to enable quick recharging of

the smaller chip capacitors.

4.4 SerDes block power supply decoupling recommendations

The SerDes block requires a clean, tightly regulated source of power (SnV_DDand

XnV_DD) to ensure low jitter on transmit and reliable recovery of data in the receiver. An

appropriate decoupling scheme is outlined below.

NOTE

Only SMT capacitors should be used to minimize inductance.

Connections from all capacitors to power and ground should be

done with multiple vias to further reduce inductance.

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1. The board should have at least 1 x 0.1-uF SMT ceramic chip capacitor placed as

close as possible to each supply ball of the device. Where the board has blind vias,

these capacitors should be placed directly below the chip supply and ground

connections. Where the board does not have blind vias, these capacitors should be

placed in a ring around the device as close to the supply and ground connections as

possible.

2. Between the device and any SerDes voltage regulator there should be a lower bulk

capacitor for example a 10-uF, low ESR SMT tantalum or ceramic and a higher bulk

capacitor for example a 100uF - 300-uF low ESR SMT tantalum or ceramic

capacitor.

4.5 Connection recommendations

The following is a list of connection recommendations:

• To ensure reliable operation, it is highly recommended to connect unused inputs to

an appropriate signal level. Unless otherwise noted in this document, all unused

active low and open drain I/O inputs should be pulled up to V_DD, OV_DD, DV_DD,

GnV_DD, and LV_DDas required. All unused active high inputs should be connected to

GND. All NC (no-connect) signals must remain unconnected. Power and ground

connections must be made to all external V_DD, OV_DD, DV_DD, GnV_DD, LV_DDand

GND pins of the device.

• The TEST_SEL_B pin must be pulled to OV_DDthrough a 100-ohm to 1k-ohm

resistor.

• The chip has temperature diodes that can be used to monitor its temperature by using

some external temperature monitoring devices (such as Analog Devices,

ADT7481A^™). For more information, see AN4787. The following are the

specifications of the chip temperature diodes:

• Operating range: 10-230 μA

• Non-ideality factor over temperature range 85C⁰ to 105C⁰, n = 1.006 0.003,

with approximate error +/- 1 C⁰ and error under +/- 3 C⁰ for temperature range 0

C⁰ to 85C⁰.

4.5.1 Legacy JTAG configuration signals

Correct operation of the JTAG interface requires configuration of a group of system

control pins as demonstrated in Figure 60. Care must be taken to ensure that these pins

are maintained at a valid deasserted state under normal operating conditions as most have

asynchronous behavior and spurious assertion will give unpredictable results.

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Hardware design considerations

Boundary-scan testing is enabled through the JTAG interface signals. The TRST_B

signal is optional in the IEEE Std 1149.1 specification, but it is provided on all processors

built on Power Architecture technology. The device requires TRST_B to be asserted

during power-on reset flow to ensure that the JTAG boundary logic does not interfere

with normal chip operation. While the TAP controller can be forced to the reset state

using only the TCK and TMS signals, generally systems assert TRST_B during the

power-on reset flow. Simply tying TRST_B to PORESET_B is not practical because the

JTAG interface is also used for accessing the common on-chip processor (COP), which

implements the debug interface to the chip.

The COP function of these processors allow a remote computer system (typically, a PC

with dedicated hardware and debugging software) to access and control the internal

operations of the processor. The COP interface connects primarily through the JTAG port

of the processor, with some additional status monitoring signals. The COP port requires

the ability to independently assert PORESET_B or TRST_B in order to fully control the

processor. If the target system has independent reset sources, such as voltage monitors,

watchdog timers, power supply failures, or push-button switches, then the COP reset

signals must be merged into these signals with logic.

The arrangement shown in Figure 60 allows the COP port to independently assert

PORESET_B or TRST_B, while ensuring that the target can drive PORESET_B as well.

The COP interface has a standard header, shown in Figure 59, for connection to the target

system, and is based on the 0.025" square-post, 0.100" centered header assembly (often

called a Berg header). The connector typically has pin 14 removed as a connector key.

The COP header adds many benefits such as breakpoints, watchpoints, register and

memory examination/modification, and other standard debugger features. An inexpensive

option can be to leave the COP header unpopulated until needed.

There is no standardized way to number the COP header; so emulator vendors have

issued many different pin numbering schemes. Some COP headers are numbered top-to-

bottom then left-to-right, while others use left-to-right then top-to-bottom. Still others

number the pins counter-clockwise from pin 1 (as with an IC). Regardless of the

numbering scheme, the signal placement recommended in Figure 59 is common to all

known emulators.

4.5.1.1 Termination of unused signals

If the JTAG interface and COP header will not be used, NXP recommends the following

connections:

• TRST_B should be tied to PORESET_B through a 0 kΩ isolation resistor so that it is

asserted when the system reset signal (PORESET_B) is asserted, ensuring that the

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Hardware design considerations

JTAG scan chain is initialized during the power-on reset flow. NXP recommends

that the COP header be designed into the system as shown in Figure 60. If this is not

possible, the isolation resistor will allow future access to TRST_B in case a JTAG

interface may need to be wired onto the system in future debug situations.

• No pull-up/pull-down is required for TDI, TMS or TDO.

1

3

2

4

NC

COP_TDO

COP_TDI

COP_TRST_B

COP_VDD_SENSE

COP_CHKSTP_IN_B

NC

5

6

COP_TCK

7

8

COP_TMS

9

10

12

COP_SRESET_B

COP_HRESET_B

COP_CHKSTP_OUT_B

11

13

15

NC

KEY

No pin

16

GND

Figure 59. Legacy COP Connector Physical Pinout

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Hardware design considerations

OV_DD

1 kΩ

10 kΩ

From target

board sources

(if any)

HRESET_B

7

HRESET_B⁶

PORESET_B

10 kΩ

PORESET_B¹

COP_HRESET_B

COP_SRESET_B

13

11

10 kΩ

B

A

10 kΩ

5

1

3

2

4

5

6

COP_TRST_B

TRST_B¹

4

6

5

10 Ω

7

8

COP_VDD_SENSE²

9

10

12

NC

COP_CHKSTP_OUT_B

15

11

13

15

CKSTP_OUT_B

KEY

No pin

14³

10 kΩ

16

COP_CHKSTP_IN_B

COP_TMS

8

9

System logic

COP connector

physical pinout

TMS

TDO

TDI

COP_TDO

1

COP_TDI

3

COP_TCK

TCK

7

2

NC

10 kΩ

10

4

12

16

Notes:

1. The COP port and target board should be able to independently assert PORESET_B and TRST_B to the processor in

order to fully control the processor as shown here.

2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.

3. The KEY location (pin 14) is not physically present on the COP header.

4. Although pin 12 is defined as a no-connect, some debug tools may use pin 12 as an additional GND pin for improved signal integrity.

5. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally

asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.

6. Asserting HRESET_B causes a hard reset on the device

7. This is an open-drain output gate.

Figure 60. Legacy JTAG Interface Connection

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Hardware design considerations

4.5.2 Aurora configuration signals

Correct operation of the Aurora interface requires configuration of a group of system

control pins as demonstrated in the figures below. Care must be taken to ensure that these

pins are maintained at a valid deasserted state under normal operating conditions as most

have asynchronous behavior and spurious assertion will give unpredictable results.

NXP recommends that the Aurora 34 pin duplex connector be designed into the system as

shown in Figure 63 or the 70 pin duplex connector be designed into the system as shown

in Figure 64.

If the Aurora interface will not be used, NXP recommends the legacy COP header be

designed into the system as described in Termination of unused signals .

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Hardware design considerations

1

3

2

4

VIO (VSense)

TCK

TX0_P

TX0_N

GND

5

6

TMS

TDI

TX1_P

TX1_N

GND

7

8

9

10

12

14

TDO

11

13

TRST

Vendor I/O 0

Vendor I/O 1

Vendor I/O 2

Vendor I/O 3

RESET

RX0_P

RX0_N

GND

15

17

16

18

19

21

23

25

27

29

31

33

20

22

24

26

28

30

32

34

RX1_P

RX1_N

GND

CLK_P

TX2_P

TX2_N

GND

CLK_N

GND

Vendor I/O 4

Vendor I/O 5

TX3_P

TX3_N

Figure 61. Aurora 34 pin connector duplex pinout

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Hardware design considerations

1

3

2

4

VIO (VSense)

TCK

TX0_P

TX0_N

GND

5

6

TMS

TDI

TX1_P

TX1_N

GND

7

8

9

10

12

14

TDO

11

13

TRST

Vendor I/O 0

Vendor I/O 1

Vendor I/O 2

Vendor I/O 3

RESET

RX0_P

RX0_N

GND

15

17

16

18

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

RX1_P

RX1_N

GND

CLK_P

TX2_P

TX2_N

GND

CLK_N

GND

Vendor I/O 4

Vendor I/O 5

GND

TX3_P

TX3_N

GND

RX2_P

N/C

RX2_N

GND

N/C

GND

RX3_P

RX3_N

GND

N/C

GND

N/C

GND

N/C

GND

N/C

GND

N/C

TX4_P

TX4_N

GND

49

51

50

52

53

55

57

59

61

63

65

67

69

54

56

58

60

62

64

66

68

70

TX5_P

TX5_N

GND

TX6_P

TX6_N

GND

TX7_P

TX7_N

Figure 62. Aurora 70 pin connector duplex pinout

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Hardware design considerations

OV_DD

1 kΩ

10 kΩ

HRESET_B

From target

board sources

(if any)

5

HRESET_B⁴

PORESET_B

10 kΩ

PORESET_B¹

RESET

22

20, 25

27, 31

32, 33

NC

B

A

1

2

4

3

10 kΩ

3

5

6

7

8

9

10

12

14

11

13

15

17

19

21

23

25

27

29

31

33

AURORA_TRST_B

TRST_B¹

16

18

20

22

24

26

28

30

32

34

12

2

VIO VSense²

1 kΩ

AURORA_TMS

AURORA_TDO

AURORA_TDI

AURORA_TCK

6

TMS

TDO

TDI

10

8

4

TCK

Vendor I/O 5 (Aurora_HRESET_B)

Vendor I/O 2 (Aurora_Event_Out_B)

Vendor I/O 1 (Aurora_Event_In_B)

Vendor I/O 0 (Aurora_HALT_B)

34

18

16

10 kΩ

EVT4_B

EVT1_B

14

26

EVT0_B

Duplex 34 Connector

Physical Pinout

CLK

100 nF

SD4_REF_CLKn

SD4_REF_CLKn_B

CLK_B

TX0

28

1

SD4_TX5

TX0_B

TX1

SD4_TX5_B

3

SD4_TX4

7

TX1_B

RX0

SD4_TX4_B

9

0.01 uF

13

15

19

SD4_RX5

SD4_RX5_B

SD4_RX4

RX0_B

RX1

0.01 uF

RX1_B

0.01 uF

21

SD4_RX4_B

6

5, 11, 17

6

23, 24

29, 30

REF_CLK1

REF_CLK1_B

REF_CLK

REF_CLK_B

Notes:

1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in

order to fully control the processor as shown here.

2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.

3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally

asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.

4. Asserting HRESET_B causes a hard reset on the device

5. This is an open-drain output gate.

6. REF_CLK/REF_CLK_B and REF_CLK1/REFCLK1_B are buffered clocks from the same common source.

Figure 63. Aurora 34 pin connector duplex interface connection

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Hardware design considerations

1 kΩ

OV_DD

10 kΩ

From target

board sources

(if any)

HRESET_B

5

HRESET_B⁴

PORESET_B¹

PORESET_B

10 kΩ

1

3

2

4

Reset

22

5

6

20, 25, 27, 31,

32, 33, 37, 38,

39, 40, 43, 44,

45, 46, 49, 50,

51, 52, 55, 56,

57, 58, 61, 62,

63, 64, 67, 68,

69, 70

7

8

9

10

12

14

B

11

13

A

NC

3

15

17

16

18

10 kΩ

19

21

23

25

27

29

31

33

35

37

39

41

43

45

47

20

22

24

26

28

30

32

34

36

38

40

42

44

46

48

AURORA_TRST_B

TRST_B¹

12

VIO VSense²

2

6

AURORA_TMS

AURORA_TDO

AURORA_TDI

AURORA_TCK

1 kΩ

TMS

TDO

TDI

10

8

4

TCK

Vendor I/O 5 (Aurora_HRESET_B)

34

26

CLK

100 nF

10 kΩ

SD4_REF_CLKn

CLK_B

SD4_REF_CLKn_B

28

Vendor I/O 2 (Aurora_Event_Out_B)

Vendor I/O 1 (Aurora_Event_In_B)

Vendor I/O 0 (Aurora_HALT_B)

TX0

18

16

14

1

EVT4_B

49

51

50

52

EVT1_B

EVT0_B

53

55

57

59

61

63

65

67

69

54

56

58

60

62

64

66

68

70

SD4_TX5

SD4_TX5_B

TX0_B

TX1

3

7

9

SD4_TX4

TX1_B

RX0

SD4_TX4_B

0.01 uF

SD4_RX5

SD4_RX5_B

SD4_RX4

13

15

19

RX0_B

RX1

0.01 uF

RX1_B

0.01 uF

21

SD4_RX4_B

6

Duplex 70 Connector

Physical Pinout

6

5, 11, 17, 23, 24,

29, 30, 35, 36, 41,

42, 47, 48, 53, 54,

59, 60, 65, 66

REF_CLK1

REF_CLK1_B

REF_CLK

REF_CLK_B

Notes:

1. The Aurora port and target board should be able to independently assert PORESET_B and TRST_B to the processor in

order to fully control the processor as shown here.

2. Populate this with a 1 kΩ resistor for short-circuit/current-limiting protection.

3. This switch is included as a precaution for BSDL testing. The switch should be closed to position A during BSDL testing to avoid accidentally

asserting the TRST_B line. If BSDL testing is not being performed, this switch should be closed to position B.

4. Asserting HRESET_B causes a hard reset on the device

5. This is an open-drain output gate.

6. REF_CLK/REF_CLK_B and REF_CLK1/REFCLK1_B are buffered clocks from the same common source.

Figure 64. Aurora 70 pin connector duplex interface connection

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Hardware design considerations

4.5.3 Guidelines for high-speed interface termination

4.5.3.1 SerDes interface entirely unused

If the high-speed SerDes interface is not used at all, the unused pin should be terminated

as described in this section.

Note that SnV_DD, XnV_DDand AVDD_SDn_PLLn must remain powered.

For AVDD_SDn_PLLn, it must be connected to XnV_DDthrough a zero ohm resistor

(instead of filter circuit shown in Figure 54).

The following pins must be left unconnected:

• SDn_TX[7:0]

• SDn_TX[7:0]_B

• SDn_IMP_CAL_RX

• SDn_IMP_CAL_TX

The following pins must be connected to SnGND:

• SDn_REF_CLK1, SDn_REF_CLK2

• SDn_REF_CLK1_B, SDn_REF_CLK2_B

It is recommended for the following pins to be connected to SnGND:

• SDn_RX[7:0]

• SDn_RX[7:0]_B

It is possible to independently disable each SerDes module by disabling all PLLs

associated with it.

SerDes n = 1:4 is disabled as follows:

• SRDS_PLL_PD_Sn = 2’b11 (both PLLs configured as powered down, all data lanes

selected by the protocols defined in SRDS_PRTCL_Sn associated to the PLLs are

powered down as well)

• SRDS_PLL_REF_CLK_SEL_Sn = 2’b00

• SRDS_PRTCL_Sn = 2 (no other values permitted when both PLLs are powered

down

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Hardware design considerations

4.5.3.2 SerDes interface partly unused

If only part of the high speed SerDes interface pins are used, the remaining high-speed

serial I/O pins should be terminated as described in this section.

Note that both SnV_DDand XnV_DDmust remain powered.

If any of the PLLs are un-used, the corresponding AVDD_SDn_PLLn must be connected

to XnV_DDthrough a zero ohm resistor (instead of filter circuit shown in Figure 54).

The following unused pins must be left unconnected:

• SDn_TX[n]

• SDn_TX[n]_B

The following unused pins must be connected to SnGND:

• SD1_REF_CLK[1:2], SD1_REF_CLK[1:2]_B (If entire SerDes 1 unused)

• SD2_REF_CLK[1:2], SD2_REF_CLK[1:2]_B (If entire SerDes 2 unused)

• SD3_REF_CLK[1:2], SD3_REF_CLK[1:2]_B (If entire SerDes 3 unused)

• SD4_REF_CLK[1:2], SD4_REF_CLK[1:2]_B (If entire SerDes 4 unused)

It is recommended for the following unused pins to be connected to SnGND:

• SDn_RX[n]

• SDn_RX[n]_B

In the RCW configuration field SRDS_PLL_PD_Sn, the respective bits for each unused

PLL must be set to power it down. A module is disabled when both its PLLs are turned

off.

Unused lanes must be powered down through the SRDSx Lane m General Control

Register 0 (SRDSxLNmGCR0) as follows:

• SRDSxLNmGCR0[RRST] = 0

• SRDSxLNmGCR0[TRST] = 0

• SRDSxLNmGCR0[RX_PD] = 1

• SRDSxLNmGCR0[TX_PD] = 1

Note that in the case where the SerDes pins are connected to slots , it is acceptable to

have these pins unterminated when unused.

4.5.4 USB controller connections

This section details the hardware connections required for the USB controllers.

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Hardware design considerations

4.5.4.1 USB divider network

This figure shows the required divider network for the VBUS interface for the chip.

Additional requirements for the external components are:

• Both resistors require 1% accuracy and a current capability of up to 1 mA. They must

both have the same temperature coefficient and accuracy.

• The zener diode must have a value of 5 V−5.25 V.

• The 0.6 V diode requires an I_F= 10 mA, I_R< 500 nA and V_F(Max)= 0.8 V. If the

USB PHY does not support OTG mode, this diode can be removed from the

schematic or made a DNP component.

USBn_DRVVBUS

VBUS charge

pump

VBUS

(USB connector)

USBn_PWRFAULT

51.2 k Ω

0.6 V_F

5 V_Z

USBn_VBUSCLMP

18.1 k Ω

Chip

Figure 65. Divider network at VBUS

4.6 Thermal

This table shows the thermal characteristics for the chip. Note that these numbers are

based on design estimates and are preliminary.

Table 148. Package thermal characteristics⁶

Rating

Junction to ambient, natural convection

Junction to ambient (at 200 ft./min.)

Junction to board

Board

Symbol

Value

11

Unit

°C/W

Notes

1, 2

Single-layer board (1s) R_ΘJA

Four-layer board (2s2p) R_ΘJA

Single-layer board (1s) R_ΘJMA

Four-layer board (2s2p) R_ΘJMA

9

°C/W

1, 3

1, 2

3

8

6

-

R_ΘJB

3

Junction to case top

R_ΘJCtop

R_ΘJClid

0.3

0.11

4

Junction to lid top

5

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

225

Hardware design considerations

Table 148. Package thermal characteristics⁶(continued)

Rating

Board

Symbol

Value

Unit

Notes

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JESD51-3 and JESD51-6 with the board (JESD51-9) horizontal.

3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

4. Junction-to-case-top at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature

is used for the case temperature. Reported value includes the thermal resistance of the interface layer.

5. Junction-to-lid-top thermal resistance determined using the using MIL-STD 883 Method 1012.1. However, instead of the

cold plate, the lid top temperature is used here for the reference case temperature. Reported value does not include the

thermal resistance of the interface layer between the package and cold plate.

6. See Thermal management information, for additional details.

4.7 Recommended thermal model

Information about Flotherm models of the package or thermal data not available in this

document can be obtained from your local NXP sales office.

4.8 Thermal management information

This section provides thermal management information for the flip-chip, plastic-ball, grid

array (FC-PBGA) package for air-cooled applications. Proper thermal control design is

primarily dependent on the system-level design-the heat sink, airflow, and thermal

interface material.

The recommended attachment method to the heat sink is illustrated in Figure 66. The heat

sink should be attached to the printed-circuit board with the spring force centered over

the die. This spring force should not exceed 60 pounds force (270 Newtons).

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

226

NXP Semiconductors

Hardware design considerations

FC-PBGA package (with lid)

Heat sink

Heat sink clip

Adhesive or

thermal interface material

Die lid

Die

Lid adhesive

Printed circuit-board

Figure 66. Package exploded, cross-sectional view-FC-PBGA (with lid)

The system board designer can choose between several types of heat sinks to place on the

device. There are several commercially-available thermal interfaces to choose from in the

industry. Ultimately, the final selection of an appropriate heat sink depends on many

factors, such as thermal performance at a given air velocity, spatial volume, mass,

attachment method, assembly, and cost.

4.8.1 Internal package conduction resistance

For the package, the intrinsic internal conduction thermal resistance paths are as follows:

• The die junction-to-case thermal resistance

• The die junction-to-lid-top thermal resistance

• The die junction-to-board thermal resistance

This figure depicts the primary heat transfer path for a package with an attached heat sink

mounted to a printed-circuit board.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

227

Hardware design considerations

External resistance

Radiation Convection

Junction to case top

Heat sink

Thermal interface material

Junction to lid top

Die/Package

Die junction

Internal resistance

Package/Solder balls

Printed-circuit board

External resistance

(Note the internal versus external package resistance)

Radiation Convection

Figure 67. Package with heat sink mounted to a printed-circuit board

The heat sink removes most of the heat from the device. Heat generated on the active side

of the chip is conducted through the silicon and through the heat sink attach material (or

thermal interface material), and finally to the heat sink. The junction-to-case thermal

resistance is low enough that the heat sink attach material and heat sink thermal

resistance are the dominant terms.

4.8.2 Thermal interface materials

A thermal interface material is required at the package-to-heat sink interface to minimize

the thermal contact resistance. The performance of thermal interface materials improves

with increasing contact pressure; this performance characteristic chart is generally

provided by the thermal interface vendor. The recommended method of mounting heat

sinks on the package is by means of a spring clip attachment to the printed-circuit board

(see Figure 66).

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

228

NXP Semiconductors

Package information

The system board designer can choose among several types of commercially-available

thermal interface materials.

5 Package information

5.1 Package parameters for the FC-PBGA

The package parameters are as provided in the following list. The package type is 45 mm

x 45 mm, 1932 flip-chip, plastic-ball, grid array (FC-PBGA).

• Package outline - 45 mm x 45 mm

• Interconnects - 1932

• Ball Pitch - 1.0 mm

• Ball Diameter (typical) - 0.60 mm

• Solder Balls - 96.5% Sn, 3% Ag, 0.5% Cu

• Module height (typical) - 3.03 mm to 3.33 mm (maximum)

5.2 Mechanical dimensions of the FC-PBGA

This figure shows the mechanical dimensions and bottom surface nomenclature of the

chip.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

229

Package information

Figure 68. Mechanical dimensions of the FC-PBGA with full lid

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

230

NXP Semiconductors

Security fuse processor

NOTES:

1. All dimensions are in millimeters.

2. Dimensions and tolerances per ASME Y14.5M-1994.

3. Maximum solder ball diameter measured parallel to datum A.

4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.

5. Parallelism measurement shall exclude any effect of mark on top surface of package.

6 Security fuse processor

This chip implements the QorIQ platform's Trust Architecture, supporting capabilities

such as secure boot. Use of the Trust Architecture features is dependent on programming

fuses in the Security Fuse Processor (SFP). The details of the Trust Architecture and SFP

can be found in the chip reference manual.

To program SFP fuses, the user is required to supply 1.8 V to the PROG_SFP pin per

Power sequencing. PROG_SFP should only be powered for the duration of the fuse

programming cycle, with a per device limit of two fuse programming cycles. All other

times PROG_SFP should be connected to GND. The sequencing requirements for raising

and lowering PROG_SFP are shown in Figure 8. To ensure device reliability, fuse

programming must be performed within the recommended fuse programming

temperature range per Table 3.

NOTE

Users not implementing the QorIQ platform's Trust

Architecture features should connect PROG_SFP to GND.

7 Ordering information

Contact your local NXP sales office or regional marketing team for order information.

7.1 Part numbering nomenclature

This table provides the NXP QorIQ platform part numbering nomenclature.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

231

Ordering information

Table 149. Part numbering nomenclature

pt or t

n

nn

n

x

t

e

n

c

d

r

PT = 28 nm

(Prototype)

4

24 = 24 0 =

P =

S =

E = SEC

present

7 = FC- P =

PBGA 1500 MHz

Q =

A =

virtual

cores

Standard Prototype Standard

power temp

1600 MT/s Rev

C4/C5

Pb-free

1667 MHz

1.0

T = 28 nm

(Production)

N =

N = SEC

not

Q =

T= 1866

MT/s

16 = 16 1 = Low Qualified X =

B =

virtual

cores

power

to

Extended

present

Rev 2.0

T =

1800 MHz

Z= TBD

industrial temp

tier

08 = 8

virtual

cores

7.2 Orderable part numbers addressed by this document

This table provides the NXP orderable part numbers addressed by this document for the

chip.

Table 150. Orderable part numbers addressed by this document

Part number

pt or t

n

nn

n

x

t

e

n

c

d

r

(Freq-Core/Freq-

Platform/Freq-DDR

(MT/s))

T4240NSE7PQB

T4240NSE7QTB

T4240NSN7PQB

T4240NSN7QTB

T=28

nm

4

24=24

virtual

cores

0

N=Qualifie S=Std

temp

E=SEC

present

7

P=1500 M Q=1600 M B =

d

Hz CPU

T/s DDR Rev

2.0

T=28

nm

4

24=24

virtual

cores

0

N=Qualifie S=Std

temp

E=SEC

present

Q=1667 M T=1866 M B =

d

Hz CPU

T/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie S=Std

temp

N=No

SEC

present

P=1500 M Q=1600 M B =

d

Hz CPU

T/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie S=Std

temp

N=No

SEC

present

Q=1667 M T=1866 M B =

d

Hz CPU

T/s DDR Rev

2.0

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

232

NXP Semiconductors

Ordering information

Table 150. Orderable part numbers addressed by this document (continued)

Part number

pt or t

n

nn

n

x

t

e

n

c

d

r

(Freq-Core/Freq-

Platform/Freq-DDR

(MT/s))

T4240NSE7TTB

T4240NSN7TTB

T4240NXE7PQB

T4240NXN7PQB

T4241NSE7PQB

T4241NSE7QTB

T4241NSE7TTB

T4241NSN7PQB

T4241NSN7QTB

T4241NSN7TTB

T4241NXE7PQB

T4241NXE7QTB

T4241NXE7TTB

T4241NXN7PQB

T4241NXN7QTB

T = 28

nm

4

24=24

virtual

cores

0

N=Qualifie S=Std

temp

E= SEC

present

7

T=1800

MHz CPU MT/S

DDR

T=1866

B =

Rev

2.0

d

T = 28

nm

4

24=24

virtual

cores

0

1

N=Qualifie S=Std

temp

N = No

SEC

present

T=1800

MHz CPU MT/S

DDR

T=1866

B =

Rev

2.0

d

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende E=SEC

d temp present

P=1500 M Q=1600 M B =

Hz CPU

d

T/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende N=No

P=1500 M Q=1600 M B =

Hz CPU

d

d temp

SEC

present

T/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie S= Std

temp

E=SEC

present

P=1500

MHz CPU T/s DDR Rev

2.0

Q=1600 M B =

d

T=28

nm

24=24

virtual

cores

N=Qualifie S= Std

temp

E=SEC

present

Q=1667 M T=1866

Hz CPU

B =

d

MT/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie S= Std

temp

E=SEC

present

T=1800

MHz CPU MT/s DDR Rev

2.0

T=1866

B =

d

T=28

nm

24=24

virtual

cores

N=Qualifie S= Std

temp

N = SEC

not

present

P=1500

MHz CPU T/s DDR Rev

2.0

Q=1600 M B =

d

T=28

nm

24=24

virtual

cores

N=Qualifie S= Std

temp

N = SEC

not

present

Q=1667 M T=1866

Hz CPU

B =

d

MT/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie S= Std

temp

N = SEC

not

present

T=1800

MHz CPU MT/s DDR Rev

2.0

T=1866

B =

d

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende E=SEC

d temp present

P=1500

MHz CPU T/s DDR Rev

2.0

Q=1600 M B =

d

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende E=SEC

d temp present

Q=1667 M T=1866

Hz CPU

B =

d

MT/s DDR Rev

2.0

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende E=SEC

d temp present

T=1800

MHz CPU MT/s DDR Rev

2.0

T=1866

B =

d

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende N = SEC

P=

Q=1600 M B =

d

d temp

not

present

1500MHz T/s DDR Rev

CPU

2.0

B =

T=28

nm

24=24

virtual

cores

N=Qualifie X=extende N = SEC

Q=1667 M T=1866

Hz CPU

d

d temp

not

present

MT/s DDR Rev

2.0

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

233

Revision history

Table 150. Orderable part numbers addressed by this document (continued)

Part number

pt or t

n

nn

n

x

t

e

n

c

d

r

(Freq-Core/Freq-

Platform/Freq-DDR

(MT/s))

T4241NXN7TTB

T=28

nm

4

24=24

virtual

cores

1

N=Qualifie X=extende N = SEC

7

T=1800

MHz CPU MT/s DDR Rev

2.0

T=1866

B =

d

d temp

not

present

Notes:

1. The 1866 MT/s DDR rate is associated with 733 MHz platform frequency in high speed parts while the 1600 MT/s DDR

rate is associated with 667 MHz platform clock frequency in lower speed parts in the part number encoding.

2. The T4241/T4161/T4081 are identical to T4240/T4160/T4080 except they consume less power. See the power

requirements in Power characteristics.

7.2.1 Part marking

Parts are marked as in the example shown in this figure.

T424nxtencdr

ATWLYYWW

MMMMMM

CCCCC

YWWLAZ

FC-PBGA

Legend:

T424nxtencdr is the orderable part number.

ATWLYYWW is the test traceability code.

MMMMMM is the mask number.

CCCCC is the country code.

YWWLAZ is the assembly traceability code.

Figure 69. Part marking for T424n FC-PBGA chip

8 Revision history

This table summarizes revisions to this document.

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

234

NXP Semiconductors

Revision history

Table 151. Revision history

Revision

Date

Description

1

05/2016

• Updated the document title to conform with new naming requirements.

• Rebranded to NXP company name.

• Removed all references to and sections for 10.3215G Interlaken.

• Updated the speed units throughout the document.

• In the pinout list table:

• Modified notes 6, 8, 23, and 24.

• Added note 29.

• Added note 28 to the D3_MDMn pins.

• Changed the note reference on IFC_AD16 to 29.

• Updated note 29 so the pull down resistance is 4.7 K instead of 10 to 50 kΩ.

• In Table 2 :

• Changed format to group "Supply Voltage Levels," "Storage Temperature Conditions,"

and "Signal Voltage Levels."

• Reduced Maximum VDD, SnVDD supply voltage level from 1.1 V to 1.08 V.

• Reduced the max GnVDD I/O voltage levels from 1.65 to 1.58 (DDR3) and from 1.45 to

1.42 (DDR3L).

• Increased the storage temperature range max value from 150 to 155.

• Added "Min_DCV V_input," "Max_DCV V_input," and "Max Overshoot Voltage"

columns for Signal Voltage level signals.

• In the SerDes signals, added additional rows for "No internal termination selected" and

"50 ohm internal termination selected".

• Added the LP Trust signal LP_TMP_DETECT_B.

• Renamed "USBn_V_IN_3P3" and "USBn_V_IN_1P8" in note 5 and stressed the max slew

rate of Dn_MVREF to 25 kv/s.

• Updated note 9 to include "See also note 6 in Table 3".

• Updated note 10 to include required biasing.

• Added notes 11, 12, and 13.

• In Table 3, added table note 11 and added the LP Trust signal.

• Updated Figure 7.

• In Power sequencing, added a paragraph for V_DD_LP special power sequencing. Also relaxed

power lines stability time from 75 ms to 400 ms.

• In Table 6 :

• Added 1.8 GHz power numbers.

• Updated note 9.

• In Table 8 :

• Added 1.8 GHz power numbers.

• Changed the 1667 MHz freq DDR data rate from 1867 to 1866.

• Updated note 9.

• Added Table 7 and Table 9 for the T4241 low-power device.

• In Table 10 :

• Added the 1.8 GHz frequency.

• Added the T4240/T4160 and T4080 LPM20 data.

• Updated power numbers so they are relevant to 65°C.

• Added a note saying that these numbers are good for the T4241 device.

• In Table 11 :

• Reduced the 1600 MT/s GV_DDtypical and max values from 3150 to 3100 and 4920 to

4900, respectively.

• Improved the PLL_SerDes typical value from 40 to 60.

• Added a formula for XV_DDand SV_DDtypical power estimation rather than have multiple

rows showing different SerDes configuration power.

• Removed the note: "Maximum DDR power numbers are based on one 2-rank DIMM

with 100% utilization," (previously note 5) and renumbered the notes.

• Updated note 6 and added example.

• Added low power devices to the table title.

Table continues on the next page...

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

NXP Semiconductors

235

Revision history

Table 151. Revision history (continued)

Revision

Date

Description

• In Table 13, included RTC clock DC specifications and updated the input capacitance data for

both SYSCLK and RTC clock pins.

• In Table 14, changed the maximum SYSCLK AC swing value from "TBD" to "1 x OV_DD" and

updated note 6.

• In "SYSCLK and RTC AC timing specifications," added Table 15, "RTC AC timing

specification."

• In Real-time clock (RTC) timing, removed the 50% duty cycle requirement from the RTC

period minimum.

• In Table 19, changed the DDRCLK input pin capacitance typical value from 7 to 11 and

removed the max value.

• In Table 20 :

• Changed the minimum DDRCLK cycle time from 5 ns to 7.5 ns.

• Changed the maximum DDRCLK AC swing value from "TBD" to "1 x OV_DD".

• Updated note 6.

• In Table 21, relaxed HRESET_B signal rise/fall time to 4 SYSCLK cycles.

• In Table 29, updated the SPI_MOSI hold time min and SPI_MOSI delay max formulas.

• Updated the t_MDKHDXdelay equation presentation in Table 38 and Table 39. (When

MDIO_CFG[NEG] = 0 then Y = 0.5 and t_MDKHDXis Y x T_{MDC_ClK}3 ns.)

• In Table 42 :

• Updated the TSEC_1588_CLK_IN clock period min value and removed the max value.

• Updated the TSEC_1588_CLK_OUT clock period min value.

• Added "hold time" to TSEC_1588_ALARM_OUT1/2.

• Changed the TSEC_1588_TRIG_IN1/2 pulse width min value.

• Removed notes 4 and 5 and updated notes 1 and 2.

• Updated all note references.

• In Table 46, changed VOH/VOL min and max from (0.8 x OVDD, 0.4) to (1.6 V, 0.32 V).

• In Table 55, changed IOL at 1.8 V from 1 mA to 3 mA.

• In "GPIO DC electrical characteristics," added Table 59, "LP_TMP_DETECT_B pin DC

electrical characteristics."

• In Table 76, Table 84, and Table 111, removed the absolute output voltage limits (min -0.4 V,

max 2.30 V).

• In Table 105, changed the figure reference in note 2 from Figure 43 to Figure 42.

• In Table 122, added note 2 and 3 and updated all note references.

• In Table 127, added the 1800 MHz data columns and added note 8 to describe why FMAN

might have two different minimum frequencies.

• In Table 133, changed the 133.333 MHz DDRCLK frequency example value to 1866.667.

• In Table 137, added the 1800 MHz Core cluster: SYSCLK Ratio options.

• In Minimum platform frequency requirements for high-speed interfaces, removed the SRIO

equation that shows minimum platform frequency.

• In Table 147, changed the VDD voltage note for "All other values". After the table, added

paragraph for if DA_ALT_V is not all zeroes.

• In PLL power supply filtering, updated the second NOTE.

• Updated Figure 53 and Figure 54.

• In Connection recommendations, added the expected temperature error to the non-ideality

factor temperature range.

• Updated Mechanical dimensions of the FC-PBGA to include package parameters.

• In Table 149 :

• Added 16 and 08 cores to column nn.

• Changed column n to "0 = Standard power; 1 = Low power".

• Added symbol "T = 1800 MHz" to column C.

• In Orderable part numbers addressed by this document, added two new orderable 1.8 G parts

and added T4241 part numbers.

• Updated Part marking to include low power numbers.

0

07/2014

Initial release

QorIQ T4240 Data Sheet, Rev. 1, 05/2016

236

NXP Semiconductors

Information in this document is provided solely to enable system and software

implementers to use NXP products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits based

on the information in this document. NXP reserves the right to make changes

without further notice to any products herein.

How to Reach Us:

Home Page:

nxp.com

Web Support:

nxp.com/support

NXP makes no warranty, representation, or guarantee regarding the suitability of

its products for any particular purpose, nor does NXP assume any liability arising

out of the application or use of any product or circuit, and specifically disclaims

any and all liability, including without limitation consequential or incidental

damages. “Typical” parameters that may be provided in NXP data sheets and/or

specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be

validated for each customer application by customer's technical experts. NXP

does not convey any license under its patent rights nor the rights of others. NXP

sells products pursuant to standard terms and conditions of sale, which can be

found at the following address: nxp.com/SalesTermsandConditions.

NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER

WORLD, COOLFLUX, EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE,

JCOP, LIFE VIBES, MIFARE, MIFARE CLASSIC, MIFARE DESFire, MIFARE

PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT, MIFARE4MOBILE,

MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,

TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, QorIQ, and

CoreNet are trademarks of NXP B.V. All other product or service names are the

property of their respective owners. The Power Architecture and Power.org word

marks and the Power and Power.org logos and related marks are trademarks

and service marks licensed by Power.org.

Document Number T4240

Revision 1, 05/2016


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