NLV74HCT04ADR2G [ONSEMI]
Hex Inverter;
| 型号： | NLV74HCT04ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | Hex Inverter |
| 文件： | 总5页 (文件大小：80K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT04A
Hex Inverter
With LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT04A may be used as a level converter for interfacing
TTL or NMOS outputs to High−Speed CMOS inputs. The HCT04A is
identical in pinout to the LS04.
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Features
• Output Drive Capability: 10 LSTTL Loads
• TTL/NMOS−Compatible Input Levels
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5 V
PIN ASSIGNMENT
• Low Input Current: 1 mA
• In Compliance With the JEDEC Standard No. 7 A Requirements
• Chip Complexity: 48 FETs or 12 Equivalent Gates
V
CC
A6 Y6 A5 Y5 A4 Y4
14 13 12 11 10
9
8
• NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
1
2
3
4
5
6
7
Compliant
A1 Y1 A2 Y2 A3 Y3 GND
14−Lead (Top View)
LOGIC DIAGRAM
MARKING DIAGRAMS
1
3
5
2
4
6
A1
A2
A3
Y1
Y2
Y3
14
14
HCT
HCT04AG
04A
AWLYWW
ALYWG
G
1
1
SOIC−14 NB
TSSOP−14
9
8
10
12
A4
A5
Y4
Y5
Y6
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
11
13
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
A6
FUNCTION TABLE
Y = A
Pin 14 = V
CC
Pin 7 = GND
Inputs
A
Outputs
Y
L
H
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
August, 2015 − Rev. 12
MC74HCT04A/D
MC74HCT04A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
–0.5 to +7.0
CC
V
–0.5 to V + 0.5
V
in
CC
V
out
–0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
DC Output Current, per Pin
out
CC
V
out
should be constrained to the
range GND v (V or V ) v V
.
I
DC Supply Current, V and GND Pins
in
out
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
SOIC Package†
TSSOP Package†
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature Range
–65 to +150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
L
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Min
4.5
0
Max
Unit
V
V
CC
5.5
V , V
in out
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
V
CC
V
T
A
–55
0
+125
500
_C
ns
t , t
r
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
Symbol
Parameter
Condition
= 0.1V
out
|I | ≤ 20mA
out
−55 to 25°C ≤85°C ≤125°C Unit
V
V
IH
Minimum High−Level Input Voltage
V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
V
V
V
IL
Maximum Low−Level Input Voltage
V
out
= V − 0.1V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
CC
|I | ≤ 20mA
out
V
OH
Minimum High−Level Output
Voltage
V
in
= V
IL
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
|I | ≤ 20mA
out
V
in
= V
|I | ≤ 4.0mA
out
4.5
3.98
3.84
3.70
IL
V
I
Maximum Low−Level Output
Voltage
V
= V
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IH
|I | ≤ 20mA
out
V
V
V
= V
|I | ≤ 4.0mA
out
4.5
5.5
5.5
0.26
0.1
1
0.33
1.0
10
0.40
1.0
40
in
IH
Maximum Input Leakage Current
= V or GND
mA
mA
in
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
CC
in
CC
I
= 0mA
out
DI
CC
Additional Quiescent Supply
Current
V
V
I
= 2.4V, Any One Input
in
in
≥ −55°C
25 to 125°C
2.4
= V or GND, Other Inputs
CC
2.9
= 0mA
mA
5.5
out
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Total Supply Current = I + ΣDI
.
CC
CC
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2
MC74HCT04A
AC CHARACTERISTICS (V = 5.0V 10%, C = 50pF, Input t = t = 6ns)
CC
L
r
f
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
15
17
19
21
22
26
ns
PLH
PHL
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
15
19
22
ns
TLH
THL
C
Maximum Input Capacitance
10
10
10
pF
in
Typical @ 25°C, V = 5.0 V
CC
22
C
Power Dissipation Capacitance (Per Inverter)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
t
f
t
r
3.0V
TEST
POINT
2.7V
1.3V
0.3V
INPUT A
GND
OUTPUT
DEVICE
UNDER
TEST
t
t
PLH
PHL
C *
L
90%
1.3V
10%
OUTPUT Y
t
t
THL
*Includes all probe and jig capacitance
TLH
Figure 1. Switching Waveforms
Figure 2. Test Circuit
A
Y
Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT04ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
55 Units / Rail
MC74HCT04ADR2G
MC74HCT04ADTR2G
NLV74HCT04ADG*
SOIC−14 NB
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14 NB
(Pb−Free)
NLV74HCT04ADR2G*
NLV74HCT04ADTR2G*
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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3
MC74HCT04A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
14X K REF
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
0.10 (0.004)
L
M
6.40 BSC
0.252 BSC
SEATING
−T−
H
G
0
8
0
8
DETAIL E
_
_
_
_
D
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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4
MC74HCT04A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
14
8
7
A3
E
H
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
L
DETAIL A
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
13X b
M
M
B
0.25
A
A1
A3
b
D
E
1.35
0.10
0.19
0.35
8.55
3.80
1.75 0.054 0.068
0.25 0.004 0.010
0.25 0.008 0.010
0.49 0.014 0.019
8.75 0.337 0.344
4.00 0.150 0.157
M
S
S
0.25
C
A
B
DETAIL A
h
A
X 45
_
e
H
h
L
1.27 BSC
0.050 BSC
6.20 0.228 0.244
0.50 0.010 0.019
1.25 0.016 0.049
5.80
0.25
0.40
0
M
A1
e
M
7
0
7
_
_
_
_
SEATING
PLANE
C
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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MC74HCT04A/D
相关型号：
NLV74HCT4851ADR2G
Analog Multiplexers/ Demultiplexers with Injection Current Effect Control with LSTTL Compatible Inputs
ONSEMI
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