NLV74HCT125ADR2G [ONSEMI]
四路非反相缓冲器，带 LSTTL 兼容输入，3 态;
| 型号： | NLV74HCT125ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 四路非反相缓冲器，带 LSTTL 兼容输入，3 态 驱动 解码器 驱动器 |
| 文件： | 总8页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT125A
Quad 3-State Noninverting
Buffer with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
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MARKING
The MC74HCT125A is identical in pinout to the LS125. The device
inputs are compatible with standard CMOS and LSTTL outputs.
The MC74HCT125A noninverting buffer is designed to be used
with 3−state memory address drivers, clock drivers, and other
bus−oriented systems. The devices have four separate output enables
that are active−low.
DIAGRAMS
14
1
PDIP−14
N SUFFIX
CASE 646
MC74HCT125AN
AWLYYWWG
14
Features
1
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
14
• Low Input Current: 1.0 mA
SOIC−14
D SUFFIX
CASE 751A
HCT125AG
AWLYWW
14
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the JEDEC Standard No. 7A Requirements
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These are Pb−Free Devices
1
1
14
HCT
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
LOGIC DIAGRAM
14
125A
ALYWG
OE1
A1
1
2
14
13 OE4
12
V
Active−Low Output Enables
1
CC
G
1
2
3
A1
Y1
Y2
Y3
Y1
3
4
A4
14
1
OE2
11 Y4
1
5
OE1
A2
A2
Y2
5
6
7
10 OE3
SOEIAJ−14
F SUFFIX
CASE 965
6
74HCT125A
ALYWG
14
9
8
A3
Y3
1
GND
4
9
OE2
A3
8
A
=
=
=
=
Assembly Location
Wafer Lot
Year
FUNCTION TABLE
L, WL
Y, YY
W, WW
G
10
12
OE3
A4
HCT125A
Work Week
11
Inputs Output
Y4
= Pb−Free Package
= Pb−Free Package
A
OE
Y
G
13
H
L
L
L
H
L
(Note: Microdot may be in either location)
OE4
X
H
Z
PIN 14 = V
CC
PIN 7 = GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
November, 2009 − Rev. 1
MC74HCT125A/D
MC74HCT125A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
35
75
mA
mA
mA
mW
in
I
DC Output Current, per Pin
out
CC
cuit. For proper operation, V and
in
V
out
should be constrained to the
I
DC Supply Current, V and GND Pins
CC
range GND v (V or V ) v V
.
in
out
CC
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
_C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
6.0
V , V
in out
DC Input Voltage, Output Voltage
(Referenced to GND)
V
CC
V
T
Operating Temperature, All Package Types
– 55
+ 125
_C
A
t , t
r
Input Rise and Fall Time
(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
ns
f
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2
MC74HCT125A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25_C
Symbol
Parameter
Test Conditions
= V – 0.1 V
v 85_C v 125_C
Unit
V
IH
Minimum High−Level Input Voltage
V
4.5 to
5.5
2.0
2.0
2.0
V
out
CC
|I | v 20 mA
out
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1 V
4.5 to
5.5
0.8
0.8
0.8
V
V
|I | v 20 mA
out
V
OH
Minimum High−Level Output
V
in
= V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
Voltage
|I | v 20 mA
out
V
V
= V
= V
|I | v 6.0 mA
out
4.5
3.98
3.84
3.7
in
IH
V
I
Maximum Low−Level Output
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
in
IL
Voltage
|I | v 20 mA
out
V
V
= V
|I | v 6.0 mA
out
4.5
5.5
5.5
0.26
0.1
0.33
1.0
0.4
in
IL
Maximum Input Leakage Current
= V or GND
1.0
mA
mA
in
in
CC
I
Maximum Three−State Leakage
Output in High−Impedance State
V = V or V
in
0.5
5.0
10
OZ
Current
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply Current
(per Package)
V
= V or GND
= 0 mA
5.5
4.0
40
160
mA
CC
in
CC
I
out
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns, V = 5.0 V 10%)
L
r
f
CC
Guaranteed Limit
– 55 to
V
CC
25_C
v 85_C
v 125_C
V
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
5.0
18
23
27
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
5.0
5.0
5.0
24
18
12
30
23
15
36
27
18
ns
ns
ns
PLZ
t
PHZ
,
Maximum Propagation Delay, Output Enable to Y
(Figures 2 and 4)
PZL
t
PZH
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
TLH
t
THL
C
Maximum Input Capacitance
−
−
10
15
10
15
10
15
pF
pF
in
C
Maximum 3−State Output Capacitance (Output in High−Impedance State)
out
Typical @ 25°C, V = 5.0 V
CC
30
C
Power Dissipation Capacitance (Per Buffer)*
pF
PD
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT125ANG
PDIP−14
(Pb−Free)
25 Units / Rail
MC74HCT125ADG
MC74HCT125ADR2G
MC74HCT125ADTG
MC74HCT125ADTR2G
MC74HCT125AFG
SOIC−14
(Pb−Free)
55 Units / Rail
2500 / Tape & Reel
96 Units / Rail
TSSOP−14*
TSSOP−14*
2500 / Tape & Reel
50 Units / Rail
SOEIAJ−14
(Pb−Free)
2000 / Tape & Reel
MC74HCT125AFELG
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
3
MC74HCT125A
SWITCHING WAVEFORMS
V
CC
OE (V )
I
V
M
t
r
t
f
GND
V
CC
90%
INPUT A (V )
I
V
M
10%
GND
HIGH
t
PHL
t
IMPEDANCE
PLH
V
V
OUTPUT Y
OUTPUT Y
M
90%
M
10%
OUTPUT Y
10%
90%
V
OL
V
t
t
PHZ
PZH
V
OH
t
t
THL
TLH
M
HIGH
V = GND to 3.0 V
I
IMPEDANCE
V
M
= 1.3 V
Figure 1.
Figure 2.
TEST POINT
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t and t
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
V
CC
OE
A
Y
(1/4 OF THE DEVICE)
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4
MC74HCT125A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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5
MC74HCT125A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6
MC74HCT125A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
J1
K
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MC74HCT125A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
H
E
_
E
M
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
A
e
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
MAX
0.081
0.008
0.020
0.008
0.413
0.215
c
A
---
0.05
0.35
0.10
9.90
5.10
---
0.002
0.014
0.004
0.390
0.201
A
1
b
c
A
b
D
E
e
1
M
0.13 (0.005)
0.10 (0.004)
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
0
10
0
10
_
0.035
0.056
_
_
_
Q
0.70
---
0.90
1.42
0.028
---
1
Z
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74HCT125A/D
相关型号：
NLV74HCT4851ADR2G
Analog Multiplexers/ Demultiplexers with Injection Current Effect Control with LSTTL Compatible Inputs
ONSEMI
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