NLV74HCT4051ADTR2G [ONSEMI]
模拟多工器/信号分离器，带 LSTTL 兼容输入;
| 型号： | NLV74HCT4051ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 模拟多工器/信号分离器，带 LSTTL 兼容输入 开关 信号电路 复用器 复用器或开关 |
| 文件： | 总18页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT4051A,
MC74HCT4052A,
MC74HCT4053A
Analog Multiplexers /
Demultiplexers with LSTTL
Compatible Inputs
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MARKING
High−Performance Silicon−Gate CMOS
DIAGRAMS
16
The MC74HCT4051A, MC74HCT4052A and MC74HCT4053A
utilize silicon−gate CMOS technology to achieve fast propagation
delays, low ON resistances, and low OFF leakage currents. These
analog multiplexers/demultiplexers control analog voltages that may
SOIC−16 WIDE
DW SUFFIX
CASE 751G
HCT405xA
AWLYWWG
16
16
vary across the complete power supply range (from V to V ).
CC
EE
1
1
The HCT4051A, HCT4052A and HCT4053A are identical in
pinout to the metal−gate MC14051AB, MC14052AB and
MC14053AB. The Channel−Select inputs determine which one of the
Analog Inputs/Outputs is to be connected, by means of an analog
switch, to the Common Output/Input. When the Enable pin is HIGH,
all analog switches are turned off.
16
SOIC−16
D SUFFIX
CASE 751B
HCT405xAG
AWLYWW
1
1
The Channel−Select and Enable inputs are compatible with standard
CMOS and LSTTL outputs.
16
TSSOP−16
DT SUFFIX
CASE 948F
HCT40
5xA
These devices have been designed so that the ON resistance (R ) is
on
16
more linear over input voltage than R of metal−gate CMOS analog
on
ALYWG
1
x
G
switches.
1
For a multiplexer/demultiplexer with injection current protection,
see HC4851A and HCT4851A.
= Specific Device Code
= Assembly Location
Features
A
• Fast Switching and Propagation Speeds
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Analog Power Supply Range (V − V ) = 2.0 to 12.0 V
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G
G
= Pb−Free Package
= Pb−Free Package
CC
EE
(Note: Microdot may be in either location)
• Digital (Control) Power Supply Range (V − GND) = 2.0 to 6.0 V
CC
• Improved Linearity and Lower ON Resistance Than Metal−Gate
Counterparts
• Low Noise
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
• In Compliance with the Requirements of JEDEC Standard No. 7A
• Chip Complexity: HCT4051A − 184 FETs or 46 Equivalent Gates
HCT4052A − 168 FETs or 42 Equivalent Gates
HCT4053A − 156 FETs or 39 Equivalent Gates
• These are Pb−Free Devices
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
January, 2010 − Rev. 0
MC74HCT4051A/D
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
FUNCTION TABLE − MC74HCT4051A
Control Inputs
13
14
15
12
1
Select
B
X0
X1
X2
X3
X4
X5
X6
X7
A
Enable
C
A
ON Channels
3
COMMON
OUTPUT/
INPUT
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X
ANALOG
INPUTS/
OUTPUTS
MULTIPLEXER/
DEMULTIPLEXER
L
5
H
H
H
H
X
2
L
4
H
H
X
11
10
9
CHANNEL
SELECT
INPUTS
B
X = Don’t Care
C
6
V
X2
15
X1
14
X0
13
X3
12
A
B
C
9
CC
ENABLE
PIN 16 = V
CC
PIN 7 = V
16
11
10
EE
PIN 8 = GND
Figure 1. Logic Diagram − MC74HCT4051A
Single−Pole, 8−Position Plus Common Off
1
2
3
4
5
6
7
8
X4
X6
X
X7
X5 Enable
V
GND
EE
Figure 2. Pinout: MC74HCT4051A
(Top View)
FUNCTION TABLE − MC74HCT4052A
Control Inputs
Select
Enable
B
A
ON Channels
12
X0
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
X0
14
X1
13
X1
X2
X3
X SWITCH
Y SWITCH
X
Y
15
11
X2
X3
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
NONE
1
5
Y0
Y1
Y2
Y3
A
X = Don’t Care
3
2
V
X2
15
X1
14
X
X0
12
X3
11
A
B
CC
4
16
13
10
9
10
9
CHANNEL‐SELECT
INPUTS
PIN 16 = V
CC
PIN 7 = V
B
EE
PIN 8 = GND
6
ENABLE
Figure 3. Logic Diagram − MC74HCT4052A
Double−Pole, 4−Position Plus Common Off
1
2
3
4
5
6
7
8
Y0
Y2
Y
Y3
Y1 Enable
V
GND
EE
Figure 4. Pinout: MC74HCT4052A (Top View)
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2
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
FUNCTION TABLE − MC74HCT4053A
Control Inputs
Select
B
Enable
C
A
ON Channels
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
H
L
H
L
H
X
Z0
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
12
13
Z0
Z0
Z0
Z1
Z1
Z1
Z1
X1
X0
X1
X0
X1
X0
X1
X0
X1
14
X
X SWITCH
L
H
H
H
H
X
2
1
L
Y0
Y1
15
4
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y
Z
H
H
X
Y SWITCH
Z SWITCH
5
3
Z0
Z1
X = Don’t Care
11
10
9
A
B
C
PIN 16 = V
CC
PIN 7 = V
PIN 8 = GND
CHANNEL‐SELECT
INPUTS
V
Y
X
X1
X0
12
A
B
C
9
CC
EE
16
15
14
13
11
10
6
ENABLE
NOTE: This device allows independent control of each switch.
Channel−Select Input A controls the X−Switch, Input B controls
the Y−Switch and Input C controls the Z−Switch
Figure 5. Logic Diagram − MC74HCT4053A
Triple Single−Pole, Double−Position Plus Common Off
1
2
3
4
Z
5
6
7
8
Y1
Y0
Z1
Z0 Enable
V
GND
EE
Figure 6. Pinout: MC74HCT4053A (Top View)
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
CC
Positive DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
−0.5 to +14.0
V
(Referenced to V
)
EE
V
EE
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
−7.0 to +5.0
V
V
V
IS
V
V
− 0.5 to
EE
+ 0.5
CC
cuit. For proper operation, V and
in
V
should be constrained to the
V
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
−0.5 to V + 0.5
V
out
in
CC
range GND v (V or V ) v V
.
in
out
CC
I
25
mA
mW
Unused inputs must always be
tied to an appropriate logic voltage
P
Power Dissipation in Still Air,
SOIC Package†
500
450
D
level (e.g., either GND or V ).
Unused outputs must be left open.
TSSOP Package†
CC
T
stg
Storage Temperature Range
−65 to +150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
†Derating
−
SOIC Package: − 7 mW/°C from 65°C to 125°C
TSSOP Package: − 6.1 mW/°C from 65°C to 125°C
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MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Positive DC Supply Voltage (Referenced to GND)
2.0
2.0
6.0
12.0
V
(Referenced to V
)
EE
V
EE
Negative DC Supply Voltage, Output (Referenced to
GND)
−6.0
GND
V
V
Analog Input Voltage
V
V
V
V
V
IS
EE
CC
V
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature Range, All Package Types
GND
in
CC
V
IO
*
1.2
V
T
−55
+125
°C
ns
A
t , t
r
Input Rise/Fall Time
(Channel Select or Enable Inputs)
V
CC
= 2.0 V
= 3.0 V
= 4.5 V
= 6.0 V
0
0
0
0
1000
600
500
400
f
V
CC
V
V
CC
CC
*For voltage drops across switch greater than 1.2 V (switch on), excessive V current may be
CC
drawn; i.e., the current out of the switch may contain both V and switch input components. The
CC
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS − Digital Section (Voltages Referenced to GND) V = GND, Except Where Noted
EE
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
V
V
CC
Symbol
Parameter
Condition
= Per Spec
Unit
V
IH
Minimum High−Level Input Voltage,
Channel−Select or Enable Inputs
R
R
4.5 to
5.5
2.0
0.8
0.1
2.0
0.8
1.0
2.0
0.8
1.0
V
on
on
V
IL
Maximum Low−Level Input Voltage,
Channel−Select or Enable Inputs
= Per Spec
4.5 to
5.5
V
I
in
Maximum Input Leakage Current,
Channel−Select or Enable Inputs
V
V
= V or GND,
6.0
mA
mA
in
CC
= − 6.0 V
EE
I
Maximum Quiescent Supply
Current (per Package)
Channel Select, Enable and
CC
V
V
= V or GND;
V
EE
V
EE
= GND
= − 6.0
6.0
6.0
1
4
10
40
20
80
IS
CC
= 0 V
IO
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MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
DC CHARACTERISTICS − Analog Section
Guaranteed Limit
−55 to 25°C ≤85°C ≤125°C
Symbol
Parameter
Condition
= V or V ; V = V to
V
V
Unit
CC
EE
R
Maximum “ON” Resistance
V
in
V
4.5
4.5
6.0
0.0
−4.5
−6.0
190
120
100
240
150
125
280
170
140
W
on
IL
IH
IS
CC
; I ≤ 2.0 mA
S
EE
(Figures 7, 8)
V
V
= V or V ; V = V or
4.5
4.5
6.0
0.0
−4.5
−6.0
150
100
80
190
125
100
230
140
115
in
IL
IH
IS
CC
(Endpoints); I ≤ 2.0 mA
EE
S
(Figures 7, 8)
DR
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
V
V
= V or V ;
IH
4.5
4.5
6.0
0.0
−4.5
−6.0
30
12
10
35
15
12
40
18
14
W
on
in
IL
= 1/2 (V − V );
IS
CC
EE
I
S
≤ 2.0 mA
I
off
Maximum Off−Channel Leakage
Current, Any One Channel
V
V
= V or V
IH
;
mA
in
IL
= V − V
;
6.0
−6.0
0.1
0.5
1.0
IO
CC
EE
Switch Off (Figure 3)
Maximum Off−Channel HCT4051A
V
V
= V or V
IH
;
6.0
6.0
6.0
−6.0
−6.0
−6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
in
IL
Leakage Current,
Common Channel
HCT4052A
HCT4053A Switch Off (Figure 10)
= V − V
;
IO
CC
EE
I
on
Maximum On−Channel HCT4051A
Leakage Current, HCT4052A Switch−to−Switch =
Channel−to−Channel HCT4053A
V
= V or V
;
6.0
6.0
6.0
−6.0
−6.0
−6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
mA
in
IL
IH
V
CC
− V ; (Figure 11)
EE
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MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
V
CC
V
−55 to 25°C ≤85°C ≤125°C
Symbol
Parameter
Unit
t
t
t
t
,
Maximum Propagation Delay, Channel−Select to Analog Output
(Figure 15)
2.0
3.0
4.5
6.0
270
90
59
320
110
79
350
125
85
ns
PLH
t
PHL
45
65
75
,
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 16)
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 17)
2.0
3.0
4.5
6.0
160
70
48
200
95
63
220
110
76
PLZ
t
PHZ
39
55
63
,
Maximum Propagation Delay, Enable to Analog Output
(Figure 17)
2.0
3.0
4.5
6.0
245
115
49
315
145
69
345
155
83
PZL
t
PZH
39
58
67
C
Maximum Input Capacitance, Channel−Select or Enable Inputs
10
35
10
35
10
35
pF
pF
in
C
Maximum Capacitance
(All Switches Off)
Analog I/O
I/O
Common O/I: HCT4051A
HCT4052A
130
80
130
80
130
80
HCT4053A
50
50
50
Feed−through
1.0
1.0
1.0
Typical @ 25°C, V = 5.0 V, V = 0 V
CC
EE
45
80
45
C
Power Dissipation Capacitance (Figure 19)*
HCT4051A
HCT4052A
HCT4053A
pF
PD
2
*Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V)
Limit*
25°C
‘52
V
V
V
EE
V
CC
Symbol
Parameter
Condition
= 1 MHz Sine Wave; Adjust f Voltage
Unit
BW
Maximum On−Channel Bandwidth
or Minimum Frequency Response
(Figure 12)
f
‘51
‘53
MHz
in
in
to Obtain 0 dBm at V ; Increase f
OS
in
80
80
80
95
95
95
120
120
120
2.25
4.50
6.00
−2.25
−4.50
−6.00
Frequency Until dB Meter Reads −3 dB;
R = 50 W, C = 10 pF
L
L
−
−
Off−Channel Feed−through
Isolation (Figure 13)
f
= Sine Wave; Adjust f Voltage to
2.25
4.50
−2.25
−4.50
−6.00
−50
−50
−50
dB
in
in
Obtain 0 dBm at V
IS
f
in
= 10 kHz, R = 600 W, C = 50 pF 6.00
L L
2.25
4.50
−2.25
−4.50
−6.00
−40
−40
−40
f
in
= 1.0 MHz, R = 50 W, C = 10 pF 6.00
L L
Feedthrough Noise.
Channel−Select Input to Common
I/O (Figure 14)
V
≤ 1 MHz Square Wave (t = t = 6 ns);
2.25
4.50
−2.25
−4.50
−6.00
25
105
135
mV
PP
in
r
f
Adjust R at Setup so that I = 0 A;
Enable = GND R = 600 W, C = 50 pF 6.00
L
S
L
L
2.25
4.50
−2.25
−4.50
−6.00
35
145
190
R = 10 kW, C = 10 pF 6.00
L
L
−
Crosstalk Between Any Two
Switches (Figure 18)
(Test does not apply to HCT4051A)
f
= Sine Wave; Adjust f Voltage to
2.25
4.50
−2.25
−4.50
−6.00
−50
−50
−50
dB
in
in
Obtain 0 dBm at V
IS
f
in
= 10 kHz, R = 600 W, C = 50 pF 6.00
L
L
2.25
4.50
−2.25
−4.50
−6.00
−60
−60
−60
f
in
= 1.0 MHz, R = 50 W, C = 10 pF 6.00
L L
THD
Total Harmonic Distortion
(Figure 20)
f
= 1 kHz, R = 10 kW, C = 50 pF
%
in
L
L
THD = THD
− THD
measured
source
V
V
= 4.0 V sine wave 2.25
−2.25
−4.50
−6.00
0.10
0.08
0.05
IS
IS
PP
= 8.0 V sine wave 4.50
PP
V
IS
= 11.0 V sine wave 6.00
PP
*Limits not tested. Determined by design and verified by qualification.
180
160
140
300
250
200
120
100
80
125°C
125°C
150
25°C
25°C
-ꢀ55°C
100
60
-ꢀ55°C
40
50
0
20
0
0
0.25 0.5
0.75
1.0
1.25
1.5 1.75
2.0 2.25
0
0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
IS
EE
Figu
Figure 7a. Typical On Resistance, VCC − VEE = 2.0 V
Figure 7b. Typical On Resistance, VCC − VEE = 3.0 V
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MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
105
90
120
100
80
75
125°C
125°C
60
25°C
60
45
25°C
-ꢀ55°C
40
20
0
30
-ꢀ55°C
15
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
IS
EE
Figure 7c. Typical On Resistance, VCC − VEE = 4.5 V
Figure 7d. Typical On Resistance, VCC − VEE = 6.0 V
80
70
60
60
50
125°C
40
50
25°C
125°C
40
30
-ꢀ55°C
25°C
30
20
-ꢀ55°C
20
10
0
10
0
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
10 11 12
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
V , INPUT VOLTAGE (VOLTS), REFERENCED TO V
IS
EE
EE
Figure 7e. Typical On Resistance, VCC − VEE = 9.0 V
Figure 7f. Typical On Resistance, VCC − VEE = 12.0 V
PLOTTER
PROGRAMMABLE
MINI COMPUTER
DC ANALYZER
POWER
SUPPLY
-
+
V
CC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
V
EE
GND
Figure 8. On Resistance Test Set−Up
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MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
V
CC
V
CC
V
V
CC
CC
16
16
V
V
V
V
EE
EE
ANALOG I/O
OFF
OFF
OFF
OFF
A
V
CC
CC
COMMON O/I
NC
COMMON O/I
V
IH
6
7
8
6
7
8
IH
V
EE
V
EE
Figure 9. Maximum Off Channel Leakage Current,
Figure 10. Maximum Off Channel Leakage Current,
Any One Channel, Test Set−Up
Common Channel, Test Set−Up
V
CC
V
OS
V
V
CC
V
CC
16
16
0.1mF
A
dB
METER
f
in
ON
ON
N/C
R
L
C *
L
EE
CC
COMMON O/I
OFF
V
ANALOG I/O
V
IL
6
7
8
6
7
8
V
EE
V
EE
*Includes all probe and jig capacitance
Figure 11. Maximum On Channel Leakage Current,
Figure 12. Maximum On Channel Bandwidth,
Channel to Channel, Test Set−Up
Test Set−Up
V
CC
V
CC
V
IS
V
OS
16
16
0.1mF
dB
METER
R
L
f
in
OFF
ON/OFF
OFF/ON
COMMON O/I
TEST
POINT
ANALOG I/O
R
R
L
L
C *
L
R
L
C *
L
R
L
6
7
8
6
7
8
V
CC
V
≤ 1 MHz
f
11
in
t = t = 6 ns
r
V
EE
V
EE
3.0 V
GND
CHANNEL SELECT
*Includes all probe and jig capacitance
CHANNEL SELECT
*Includes all probe and jig capacitance
V
IL
or V
IH
Figure 13. Off Channel Feedthrough Isolation,
Figure 14. Feedthrough Noise, Channel Select to
Test Set−Up
Common Out, Test Set−Up
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9
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
V
CC
V
CC
16
V
CC
ON/OFF
OFF/ON
COMMON O/I
C *
CHANNEL
SELECT
TEST
POINT
V
m
ANALOG I/O
GND
(V )
I
L
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
V = GND to 3.0 V
I
CHANNEL SELECT
*Includes all probe and jig capacitance
V
m
= 1.3 V
Figure 15a. Propagation Delays, Channel Select
to Analog Out
Figure 15b. Propagation Delay, Test Set−Up Channel
Select to Analog Out
Figur
V
CC
16
COMMON O/I
C *
ANALOG I/O
TEST
POINT
V
CC
ON
ANALOG
IN
50%
L
GND
t
t
PHL
PLH
6
7
8
ANALOG
OUT
50%
*Includes all probe and jig capacitance
Figure 16a. Propagation Delays, Analog In
to Analog Out
Figure 16b. Propagation Delay, Test Set−Up
Analog In to Analog Out
Figur
t
t
POSITION 1 WHEN TESTING t
AND t
PZH
POSITION 2 WHEN TESTING t AND t
f
r
PHZ
1
2
PLZ
PZL
V
CC
90%
ENABLE
V
M
V
M
V
CC
(V )
I
10%
GND
1kW
V
CC
16
t
t
PLZ
PZL
HIGH
IMPEDANCE
1
2
ANALOG I/O
ENABLE
TEST
POINT
ON/OFF
ANALOG
OUT
50%
C *
L
10%
90%
V
OL
t
t
PHZ
PZH
6
7
8
V
OH
ANALOG
OUT
50%
HIGH
IMPEDANCE
V = GND to 3.0 V
I
V
m
= 1.3 V
Figur
Figure 17a. Propagation Delays, Enable to
Analog Out
Figure 17b. Propagation Delay, Test Set−Up
Enable to Analog Out
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10
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
V
CC
V
IS
A
V
CC
16
16
R
V
OS
L
ON/OFF
OFF/ON
COMMON O/I
f
in
ON
NC
ANALOG I/O
0.1mF
OFF
V
EE
R
L
R
L
C *
L
C *
L
V
CC
R
6
7
8
L
6
7
8
11
V
EE
CHANNEL SELECT
*Includes all probe and jig capacitance
Figure 18. Crosstalk Between Any Two
Figure 19. Power Dissipation Capacitance,
Switches, Test Set−Up
Test Set−Up
0
-ꢀ10
-ꢀ20
-ꢀ30
-ꢀ40
V
IS
FUNDAMENTAL FREQUENCY
V
CC
V
OS
16
0.1mF
TO
DISTORTION
METER
f
in
ON
R
L
C *
L
-ꢀ50
-ꢀ60
DEVICE
SOURCE
6
7
8
-ꢀ70
-ꢀ80
V
EE
-ꢀ90
*Includes all probe and jig capacitance
-100
1.0
2.0
3.125
Figure 20.
Figure 20a. Total Harmonic Distortion, Test Set−Up
FREQUENCY (kHz)
Figure 20b. Plot, Harmonic Distortion
APPLICATIONS INFORMATION
The maximum analog voltage swings are determined by
the supply voltages V and V . The positive peak analog
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
CC
EE
voltage should not exceed V . Similarly, the negative peak
CC
analog voltage should not go below V . In this example,
V
CC
− GND = 2 to 6 V
EE
the difference between V and V is ten volts. Therefore,
V
EE
− GND = 0 to −6 V
CC
EE
using the configuration of Figure 21, a maximum analog
signal of ten volts peak−to−peak can be controlled. Unused
analog inputs/outputs may be left floating (i.e., not
connected). However, tying unused analog inputs and
V
− V = 2 to 12 V
CC EE
and V ≤ GND
EE
When voltage transients above V and/or below V are
anticipated on the analog channels, external Germanium or
Schottky diodes (D ) are recommended as shown in
Figure 22. These diodes should be able to absorb the
maximum anticipated current surges during clipping.
CC
EE
outputs to V or GND through a low value resistor helps
CC
x
minimize crosstalk and feed−through noise that may be
picked up by an unused switch.
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11
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
V
CC
V
CC
+5V
V
CC
D
D
16
x
16
ON/OFF
x
+5V
-5V
+5V
-5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ON
D
D
x
x
V
EE
V
EE
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
6
7
8
11
10
9
7
8
-5V
V
EE
Figure 21. Application Example
Figure 22. External Germanium or
Schottky Clipping Diodes
+5V
+5V
16
16
+5V
+5V
+5V
+5V
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ANALOG
SIGNAL
ON/OFF
ON/OFF
V
EE
V
EE
V
EE
V
EE
+5V
HC405x
HCT405x
*
R
R
R
+5V
6
7
8
11
10
9
6
7
8
11
10
9
LSTTL/NMOS
CIRCUITRY
LSTTL/NMOS
CIRCUITRY
V
EE
V
EE
* 2K ≤ R ≤ 10K
a. Using Pull−Up Resistors with a HC Device
b. Using HCT Interface
Figure 23. Interfacing LSTTL/NMOS to CMOS Inputs
11
10
9
13
X0
LEVEL
SHIFTER
A
14
X1
15
X2
LEVEL
SHIFTER
B
12
X3
1
LEVEL
SHIFTER
C
X4
5
X5
6
2
LEVEL
SHIFTER
ENABLE
X6
4
X7
3
X
Figure 24. Function Diagram, HCT4051A
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12
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
10
12
14
15
LEVEL
SHIFTER
A
B
X0
X1
X2
9
LEVEL
SHIFTER
11
13
1
X3
X
6
LEVEL
SHIFTER
ENABLE
Y0
5
2
4
3
Y1
Y2
Y3
Y
Figure 26. Function Diagram, HCT4052A
11
10
9
13
LEVEL
SHIFTER
A
X1
12
14
1
X0
X
LEVEL
SHIFTER
B
Y1
2
15
3
Y0
Y
LEVEL
SHIFTER
C
Z1
5
4
Z0
Z
6
LEVEL
SHIFTER
ENABLE
Figure 25. Function Diagram, HCT4053A
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13
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
ORDERING INFORMATION
†
Device
MC74HCT4051ADG
Package
Shipping
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HCT4051ADR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HCT4051ADTG
MC74HCT4051ADTR2G
MC74HCT4051ADWG
TSSOP−16*
TSSOP−16*
96 Units / Rail
2500 / Tape & Reel
48 Units / Rail
SOIC−16 WIDE
(Pb−Free)
MC74HCT4051ADWR2G
MC74HCT4052ADG
SOIC−16 WIDE
(Pb−Free)
1000 / Tape & Reel
48 Units / Rail
SOIC−16
(Pb−Free)
MC74HCT4052ADR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HCT4052ADTG
MC74HCT4052ADTR2G
MC74HCT4052ADWG
TSSOP−16*
TSSOP−16*
96 Units / Rail
2500 / Tape & Reel
48 Units / Rail
SOIC−16 WIDE
(Pb−Free)
MC74HCT4052ADWR2G
MC74HCT4053ADG
SOIC−16 WIDE
(Pb−Free)
1000 / Tape & Reel
48 Units / Rail
SOIC−16
(Pb−Free)
MC74HCT4053ADR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
MC74HCT4053ADTG
MC74HCT4053ADTR2G
MC74HCT4053ADWG
TSSOP−16*
TSSOP−16*
96 Units / Rail
2500 / Tape & Reel
48 Units / Rail
SOIC−16 WIDE
(Pb−Free)
MC74HCT4053ADWR2G
SOIC−16 WIDE
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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14
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
PACKAGE DIMENSIONS
SOIC−16 WIDE
DW SUFFIX
CASE 751G−03
ISSUE C
NOTES:
A
D
1. DIMENSIONS ARE IN MILLIMETERS.
q
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
16
9
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
2.35
A1 0.10
MAX
2.65
0.25
0.49
0.32
1
8
A
B
C
D
E
e
H
h
L
q
0.35
0.23
10.15 10.45
7.40 7.60
1.27 BSC
10.05 10.55
B
16X B
M
S
S
B
0.25
T
A
0.25
0.50
0
0.75
0.90
7
_
_
SEATING
PLANE
14X
e
C
T
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15
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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16
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T
U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
17
MC74HCT4051A, MC74HCT4052A, MC74HCT4053A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC74HCT4051A/D
相关型号：
NLV74HCT4851ADR2G
Analog Multiplexers/ Demultiplexers with Injection Current Effect Control with LSTTL Compatible Inputs
ONSEMI
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