NLV74HCT132ADR2G [ONSEMI]
四路 2 输入 NAND 门极，带施密特触发器输入，可兼容 LSTTL 输入;
| 型号： | NLV74HCT132ADR2G |
| 厂家： | 
ONSEMI |
| 描述： | 四路 2 输入 NAND 门极，带施密特触发器输入，可兼容 LSTTL 输入 栅 光电二极管 逻辑集成电路 触发器 栅极 |
| 文件： | 总9页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
with LSTTL Compatible
Inputs
http://onsemi.com
High−Performance Silicon−Gate CMOS
MARKING
DIAGRAMS
The MC74HCT132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
The MC74HCT132A can be used to enhance noise immunity or to
square up slowly changing waveforms.
14
PDIP−14
N SUFFIX
CASE 646
MC74HCT132AN
AWLYYWWG
1
Features
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
14
SOIC−14
D SUFFIX
CASE 751A
HCT132AG
AWLYWW
• Low Input Current: 1.0 mA
1
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements as Defined by JEDEC
14
Standard No. 7A
HCT
132A
ALYWG
G
TSSOP−14
DT SUFFIX
CASE 948G
• Chip Complexity: 72 FETs or 18 Equivalent Gates
• These are Pb−Free Devices
1
A1
B1
1
2
14
13 B4
12
V
CC
14
74HCT132A
ALYWG
SOEIAJ−14
F SUFFIX
CASE 965
Y1
A2
3
4
A4
11 Y4
10 B3
1
B2
Y2
5
6
9
8
A3
Y3
A
= Assembly Location
L, WL = Wafer Lot
Y, YY = Year
GND
7
W, WW = Work Week
Figure 1. Pin Assignment
G or G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
Y
A
B
L
L
H
H
L
H
L
H
H
H
L
H
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
November, 2009 − Rev. 1
MC74HCT132A/D
MC74HCT132A
1
A1
3
6
8
Y1
2
4
B1
A2
Y2
5
9
B2
A3
Y = AB
Y3
Y4
10
12
B3
A4
11
13
B4
PIN 14 = V
CC
PIN 7 = GND
Figure 2. Logic Diagram
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT132ANG
PDIP−14
25 / Tape & Ammo Box
55 Units / Rail
(Pb−Free)
MC74HCT132ADG
SOIC−14
(Pb−Free)
MC74HCT132ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
2000 / Tape & Reel
MC74HCT132ADTR2G
MC74HCT132AFELG
TSSOP−14*
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HCT132A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
Positive DC Supply Voltage
Digital Input Voltage
ꢀ0.5 to ꢁ7.0
ꢀ0.5 to ꢁ7.0
ꢀ0.5 to ꢁ7.0
CC
V
V
IN
V
OUT
DC Output Voltage
Output in 3−State
High or Low State
V
ꢀ0.5 to V
ꢁ 0.5
CC
I
Input Diode Current
ꢀ20
mA
mA
mA
mA
mA
_C
IK
I
Output Diode Current
DC Output Current, per Pin
ꢂ
2
0
OK
I
ꢂ
2
5
OUT
I
DC Supply Current, V and GND Pins
ꢂ75
CC
CC
I
DC Ground Current per Ground Pin
Storage Temperature Range
ꢂ
7
5
GND
T
ꢀ65 to ꢁ150
260
STG
T
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance
_C
L
T
ꢁ150
_C
_C/W
J
q
14−PDIP
14−SOIC
14−TSSOP
78
125
170
JA
P
D
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Level 1
F
R
Oxygen Index: 30% − 35%
UL 94 V0 @ 0.125 in
V
ESD
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
ꢃ2000
ꢃ100
ꢃ500
V
I
Latch−Up Performance
Above V and Below GND at 85_C (Note 4)
ꢂ
3
0
0
mA
Latch−Up
CC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
DC Supply Voltage (Referenced to GND)
Min
2.0
0
Max
Unit
V
V
CC
6.0
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 3)
V
CC
V
T
A
ꢀ55
−
ꢁ
1
2
5
_C
ns
t , t
No Limit
(Note 5)
r
f
5. When V ꢄ 0.5 V , I >> quiescent current.
IN
CC CC
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
MC74HCT132A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
V
CC
Guaranteed Limit
Symbol
Parameter
Test Conditions
= 0.1 V
OUT
V
*55_C to 25_C
ꢅ85_C ꢅ125_C Unit
V
T+
max Maximum Positive−Going
V
4.5
5.5
1.9
2.1
1.9
2.1
1.9
2.1
V
V
V
V
V
Input Threshold Voltage
|I
| ꢅ 20 mA
OUT
V
T+
min Minimum Positive−Going
V
OUT
= 0.1 V
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
OUT
Input Threshold Voltage
|I
| ꢅ 20 mA
V
T–
max Maximum Negative−Going
V
OUT
= V – 0.1 V
4.5
5.5
1.2
1.4
1.2
1.4
1.2
1.4
OUT
CC
Input Threshold Voltage
|I
| ꢅ 20 mA
V
T–
min Minimum Negative−Going
V
OUT
= V – 0.1 V
4.5
5.5
0.5
0.6
0.5
0.6
0.5
0.6
OUT
CC
Input Threshold Voltage
|I
| ꢅ 20 mA
V min
Minimum Hysteresis
Voltage
V
OUT
= 0.1 V or V – 0.1 V
4.5
5.5
0.4
0.4
0.4
0.4
0.4
0.4
H
OUT
CC
|I
| ꢅ 20 mA
(Note 7)
V
OH
Minimum High−Level
Output Voltage
V
OUT
ꢅ
V
min or V max
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
IN
T−
T+
|I
| ꢅ 20 mA
V
ꢅ
−V min or V max
T− T+
IN
|I
| ꢅ 4.0 mA
4.5
3.98
3.84
3.7
OUT
OUT
V
OL
Maximum Low−Level
Output Voltage
V
OUT
≥ V max
| ꢅ 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
T+
|I
V
V
≥ V max
|I
| ꢅ 4.0 mA
4.5
5.5
0.26
0.33
0.4
IN
T+
I
Maximum Input Leakage
Current
= V or GND
ꢂ
0
.
1
ꢂ
1
.
0
ꢂ
1
.
0
mA
mA
IN
IN
CC
I
Maximum Quiescent
Supply Current
(per Package)
V
OUT
= V or GND
5.5
1.0
10
40
CC
IN
CC
I
= 0 mA
7. V min ꢃ (V min) ꢀ (V max); V max = (V max) ꢁ (V min).
H
T+
T−
H
T+
T−
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns, V = 5.0 V 10%)
L
r
f
CC
V
CC
Guaranteed Limit
Symbol
Parameter
V
*55_C to 25_C
ꢅ
8
5
_
C
ꢅ
1
2
5
_
C
U
n
i
t
t
,
Maximum Propagation Delay, Input A or B to Output Y
(Figures 3 and 4)
5.0
25
31
19
10
38
22
10
ns
ns
pF
PLH
t
PHL
t
,
Maximum Output Transition Time, Any Output
(Figures 3 and 4)
5.0
—
15
10
TLH
t
THL
C
Maximum Input Capacitance
in
Typical @ 25°C, V = 5.0 V
CC
C
Power Dissipation Capacitance (per Gate) (Note 8)
24
pF
PD
2
8. Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74HCT132A
TEST POINT
OUTPUT
t
t
f
r
V
INPUT
A OR B
(V )
I
CC
90%
V
10%
M
DEVICE
UNDER
TEST
GND
t
t
PLH
C *
L
PHL
90%
Y
V
M
10%
t
t
THL
TLH
*Includes all probe and jig capacitance
V = GND to 3.0 V
I
V
M
= 1.3 V
Figure 3. Switching Waveforms
Figure 4. Test Circuit
V
CC
V
CC
V
H
V
H
V
Tꢁ+
V
Tꢁ-
V
Tꢁ+
V
Tꢁ-
V
IN
V
IN
GND
GND
V
OH
V
OH
V
OUT
V
OUT
V
OL
V
OL
V
CC
V
OUT
V
IN
(a)ꢀA SCHMITT TRIGGER SQUARES UP INPUTS
(a)ꢀWITH SLOW RISE AND FALL TIMES
(b)ꢀA SCHMITT TRIGGER OFFERS MAXIMUM
NOISE IMMUNITY
Figure 5. Typical Schmitt−Trigger Applications
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5
MC74HCT132A
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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6
MC74HCT132A
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MC74HCT132A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
K1
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
J1
K
0.10 (0.004)
K1 0.19
L
M
6.40 BSC
0.252 BSC
SEATING
PLANE
−T−
H
G
DETAIL E
D
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MC74HCT132A
PACKAGE DIMENSIONS
SOEIAJ−14
CASE 965−01
ISSUE B
NOTES:
ꢂꢀ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢂꢀ2. CONTROLLING DIMENSION: MILLIMETER.
ꢂꢀ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
14
8
E
Q
1
H
E
_
E
M
ꢂꢀ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ꢂꢀ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
VIEW P
A
e
MILLIMETERS
INCHES
MIN
---
c
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.008
0.413
0.215
A
---
0.05
0.35
0.10
9.90
5.10
2.05
A
1
b
c
0.20 0.002
0.50 0.014
0.20 0.004
A
b
1
D
E
e
10.50 0.390
5.45 0.201
M
0.13 (0.005)
0.10 (0.004)
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
0
10
0.90 0.028
10
_
0.035
0.056
0
_
_
_
Q
0.70
---
1
Z
1.42
---
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MC74HCT132A/D
相关型号：
NLV74HCT4851ADR2G
Analog Multiplexers/ Demultiplexers with Injection Current Effect Control with LSTTL Compatible Inputs
ONSEMI
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