NLV74AC74DR2G [ONSEMI]
双 D 触发器正向边触发器;
ONSEMI 
MC74AC74, MC74ACT74
Dual D−Type Positive
Edge−Triggered Flip−Flop
The MC74AC74/74ACT74 is a dual D−type flip−flop with
Asynchronous Clear and Set inputs and complementary (Q,Q)
outputs. Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at a voltage
level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold
voltage has been passed, the Data input is locked out and information
present will not be transferred to the outputs until the next rising edge
of the Clock Pulse input.
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PDIP−14
N SUFFIX
CASE 646
14
1
Asynchronous Inputs:
SOIC−14
D SUFFIX
CASE 751A
LOW input to S (Set) sets Q to HIGH level
D
14
LOW input to C (Clear) sets Q to LOW level
D
1
Clear and Set are independent of clock
Simultaneous LOW on C and S makes both Q and Q HIGH
D
D
TSSOP−14
DT SUFFIX
CASE 948G
14
Features
1
• Outputs Source/Sink 24 mA
• ′ACT74 Has TTL Compatible Inputs
SOEIAJ−14
M SUFFIX
CASE 965
• Pb−Free Packages are Available
14
1
V
C
D
CP
S
Q
Q
2
CC
D2
2
2
D2
2
14
13
12
11
10
9
8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
C
S
D1
D2
D
Q
CP
Q
1
1
2
2
CP
Q
D
Q
S
C
1
1
2
2
D1
D2
1
2
3
CP
4
5
6
7
C
D
S
Q
Q
1
GND
D1
1
1
D1
1
Figure 1. Pinout: 14−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
D , D
FUNCTION
Data Inputs
1
2
CP , CP
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
1
2
C , C
D1 D2
S
, S
D1 D2
Q , Q , Q ,
1
2
1
2
Q
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 7
MC74AC74/D
MC74AC74, MC74ACT74
TRUTH TABLE (Each Half)
Inputs
Outputs
Q
Q
1
1
S
C
D1
D1
S
C
D
CP
D
Q
Q
D
D
CP
1
1
L
H
L
H
H
H
H
L
L
H
H
H
X
X
X
X
X
X
H
L
H
L
H
H
L
L
H
H
L
H
Q
Q
Q
2
L
X
Q
2
0
0
S
CD
2
D2
NOTE: H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial;
D
CP
2
2
= LOW-to-HIGH Clock Transition
Q (Q ) = Previous Q(Q) before LOW-to-HIGH
0
0
Transition of Clock
Figure 2. Logic Symbol
S
D
D
Q
CP
Q
C
D
NOTE: This diagram is provided only for the understanding of
logic operations and should not be used to estimate
propagation delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
CC
in
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
−0.5 to V +0.5
V
CC
V
out
−0.5 to V +0.5
V
CC
I
I
I
±20
±50
mA
mA
mA
°C
in
DC Output Sink/Source Current, per Pin
out
CC
DC V or GND Current per Output Pin
±50
CC
T
stg
Storage Temperature
−65 to +150
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC74AC74, MC74ACT74
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
5.0
5.0
−
Max
6.0
Unit
′AC
2.0
4.5
0
V
Supply Voltage
V
V
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
V
V
V
V
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
−
−
CC
CC
CC
CC
CC
Input Rise and Fall Time (Note )
′AC Devices except Schmitt Inputs
−
−
−
−
−
ns/V
t , t
r
f
−
−
Input Rise and Fall Time (Note )
′ACT Devices except Schmitt Inputs
t , t
ns/V
r
f
−
T
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current − High
−
140
85
°C
°C
J
T
A
−40
−
25
−
I
I
−24
24
mA
mA
OH
OL
Output Current − Low
−
−
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
DC CHARACTERISTICS
74AC
74AC
T
=
A
V
(V)
CC
T
A
= +25°C
−40°C to
+85°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
OUT
Minimum High Level
Input Voltage
IH
V
V
V
or V − 0.1 V
CC
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
= 0.1 V
OUT
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 mA
OUT
Minimum High Level
Output Voltage
OH
*V = V or V
IH
IN
IL
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
−24 mA
−24 mA
V
V
I
I
OH
V
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
= 50 mA
OUT
Maximum Low Level
Output Voltage
OL
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
V
I
OL
I
Maximum Input
Leakage Current
IN
5.5
−
±0.1
±1.0
mA
V = V , GND
I
CC
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
V
V
= 1.65 V Max
= 3.85 V Min
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
OHD
−75
Maximum Quiescent
Supply Current
5.5
−
4.0
40
mA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
IN
CC
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3
MC74AC74, MC74ACT74
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
T
= −40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Min
Typ
Max
Min
Max
3.3
5.0
100
140
125
160
−
−
95
125
−
−
Maximum Clock
Frequency
f
t
t
t
t
MHz
ns
3−3
3−6
3−6
3−6
3−6
max
3.3
5.0
5.0
3.5
8.0
6.0
12.5
9.0
4.0
3.0
13.0
10.0
Propagation Delay
PLH
PHL
PLH
PHL
C
Dn
or S to Q or Q
Dn n
n
n
3.3
5.0
4.0
3.0
10.5
8.0
12.0
9.5
3.5
2.5
13.5
10.5
Propagation Delay
or S to Q or Q
ns
C
Dn
Dn
n
3.3
5.0
4.5
3.5
8.0
6.0
13.5
10.0
4.0
3.0
16.0
10.5
Propagation Delay
to Q or Q
ns
C
Pn
n
n
3.3
5.0
3.5
2.5
8.0
6.0
14.0
10.0
3.5
2.5
14.5
10.5
Propagation Delay
to Q or Q
ns
C
Pn
n
n
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
AC OPERATING REQUIREMENTS
74AC
74AC
T
= −40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
to +85°C
= 50 pF
Symbol
Parameter
Unit
L
C
L
Typ
Guaranteed Minimum
Set-up Time, HIGH or LOW
D to CP
3.3
5.0
1.5
1.0
4.0
3.0
4.5
3.0
t
t
t
t
ns
ns
ns
ns
3−9
3−9
3−6
3−9
s
n
n
Hold Time, HIGH or LOW
D to CP
3.3
5.0
−2.0
−1.5
0.5
0.5
0.5
0.5
h
w
n
n
C
Pn
or C or S
Dn
3.3
5.0
3.0
2.5
5.5
4.5
7.0
5.0
Dn
Pulse Width
Recovery TIme
3.3
5.0
−2.5
−2.0
0
0
0
0
rec
C
Dn
or S to CP
Dn
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
Voltage Range 5.0 V is 5.0 V ±0.5 V.
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4
MC74AC74, MC74ACT74
DC CHARACTERISTICS
Symbol
74ACT
74ACT
T
A
=
V
(V)
CC
T
= +25°C
−40°C to
+85°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
OUT
Minimum High Level
Input Voltage
IH
V
V
V
or V − 0.1 V
CC
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
= 0.1 V
OUT
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 mA
OUT
Minimum High Level
Output Voltage
OH
*V = V or V
IH
IN
IL
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
V
−24 mA
−24 mA
I
I
OH
V
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
= 50 mA
OUT
Maximum Low Level
Output Voltage
OL
*V = V or V
IN
IL
IH
4.5
5.5
−
−
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
5.5
−
±0.1
±1.0
mA
V = V , GND
I CC
DI
Additional Max. I /Input
5.5
5.5
5.5
0.6
−
−
−
−
1.5
75
mA
mA
mA
V = V − 2.1 V
CCT
CC
I
CC
I
V
V
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OLD
OHD
I
I
−
−75
= 3.85 V Min
OHD
CC
Maximum Quiescent
Supply Current
5.5
−
4.0
40
mA
V
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
T
= −40°C
A
T
C
= +25°C
= 50 pF
V
(V)
*
Fig.
No.
A
CC
to +85°C
C
Symbol
Parameter
Unit
L
= 50 pF
L
Min
Typ
Max
Min
Max
Maximum Clock
Frequency
f
t
t
t
t
5.0
5.0
5.0
5.0
5.0
145
210
−
125
−
MHz
ns
3−3
3−6
3−6
3−6
3−6
max
Propagation Delay
3.0
3.0
4.0
3.5
5.5
6.0
7.5
6.0
9.5
2.5
3.0
4.0
3.0
10.5
11.5
13.0
11.5
PLH
PHL
PLH
PHL
C
Dn
or S to Q or Q
Dn n
n
n
Propagation Delay
or S to Q or Q
10.0
11.0
10.0
ns
C
Dn
Dn
n
Propagation Delay
to Q or Q
ns
C
Pn
n
n
Propagation Delay
to Q or Q
ns
C
Pn
n
n
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
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5
MC74AC74, MC74ACT74
AC OPERATING REQUIREMENTS
74ACT
74ACT
= −40°C
T
A
T
C
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
= 50 pF
Symbol
Parameter
Unit
= 50 pF
L
C
L
Typ
Guaranteed Minimum
Set-up Time, HIGH or LOW
D to CP
t
t
t
t
5.0
5.0
5.0
5.0
1.0
3.0
1.0
5.0
0
3.5
1.0
6.0
0
ns
ns
ns
ns
3−9
3−9
3−6
3−9
s
n
n
Hold Time, HIGH or LOW
D to CP
−0.5
3.0
h
w
n
n
C
Pn
or C or S
Dn Dn
Pulse Width
Recovery TIme
−2.5
rec
C
Dn
or S to CP
Dn
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
CAPACITANCE
Symbol
Value
Typ
Parameter
Unit
Test Conditions
C
C
Input Capacitance
Power Dissipation Capacitance
4.5
35
pF
pF
V
V
= 5.0 V
= 5.0 V
IN
CC
CC
PD
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6
MC74AC74, MC74ACT74
ORDERING INFORMATION
†
Device
MC74AC74N
Package
Shipping
PDIP−14
MC74AC74NG
PDIP−14
(Pb−Free)
25 Units/Rail
MC74ACT74N
PDIP−14
MC74ACT74NG
PDIP−14
(Pb−Free)
MC74AC74D
SOIC−14
55 Units/Rail
2500/Tape & Reel
55 Units/Rail
MC74AC74DG
SOIC−14
(Pb−Free)
MC74AC74DR2
SOIC−14
MC74AC74DR2G
SOIC−14
(Pb−Free)
MC74ACT74D
SOIC−14
MC74ACT74DG
SOIC−14
(Pb−Free)
MC74ACT74DR2
MC74ACT74DR2G
SOIC−14
2500/Tape & Reel
SOIC−14
(Pb−Free)
MC74AC74DT
TSSOP−14*
TSSOP−14*
TSSOP−14*
TSSOP−14*
TSSOP−14*
TSSOP−14*
SOEIAJ−14
96 Units/Rail
2500/Tape & Reel
96 Units/Rail
MC74AC74DTR2
MC74AC74DTR2G
MC74ACT74DT
MC74ACT74DTR2
MC74ACT74DTR2G
MC74AC74MEL
MC74AC74MELG
2500/Tape & Reel
SOEIAJ−14
(Pb−Free)
2000/Tape & Reel
MC74ACT74MEL
MC74ACT74MELG
SOEIAJ−14
SOEIAJ−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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7
MC74AC74, MC74ACT74
MARKING DIAGRAMS
PDIP−14
SOIC−14
TSSOP−14
SOEIAJ−14
14
MC74AC74N
AWLYYWWG
AC
74
74AC74
ALYWG
AC74G
AWLYWW
ALYWG
G
1
MC74ACT74N
AWLYYWWG
14
74ACT74
ALYWG
ACT
74
ACT74G
AWLYWW
ALYWG
G
1
A
= Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
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8
MC74AC74, MC74ACT74
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
14
1
8
7
B
INCHES
MILLIMETERS
A
F
DIM
A
B
C
D
F
MIN
MAX
0.770
0.260
0.185
0.021
0.070
MIN
18.16
6.10
3.69
0.38
1.02
MAX
19.56
6.60
4.69
0.53
1.78
0.715
0.240
0.145
0.015
0.040
L
N
C
G
H
J
K
L
M
N
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
0.38
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
J
_
_
K
0.015
0.039
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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9
MC74AC74, MC74ACT74
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−A−
14
8
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−B−
P 7 PL
M
M
B
0.25 (0.010)
7
1
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
F
R X 45
_
C
A
B
C
D
F
G
J
K
M
P
R
8.55
3.80
1.35
0.35
0.40
8.75 0.337 0.344
4.00 0.150 0.157
1.75 0.054 0.068
0.49 0.014 0.019
1.25 0.016 0.049
0.050 BSC
0.25 0.008 0.009
0.25 0.004 0.009
−T−
SEATING
PLANE
J
M
K
1.27 BSC
D 14 PL
0.19
0.10
0
M
S
S
0.25 (0.010)
T
B
A
7
0
7
_
_
_
_
5.80
0.25
6.20 0.228 0.244
0.50 0.010 0.019
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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10
MC74AC74, MC74ACT74
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
M
S
S
V
0.10 (0.004)
T
U
S
0.15 (0.006) T
U
N
0.25 (0.010)
14
8
2X L/2
M
B
L
N
−U−
PIN 1
IDENT.
F
7
1
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T
U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
A
B
C
D
F
G
H
J
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
J1
K
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
PLANE
−T−
H
G
DETAIL E
D
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
01.34X6
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
MC74AC74, MC74ACT74
SOEIAJ−14
CASE 965−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
14
8
E
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
E
_
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN MAX
−−− 0.081
VIEW P
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
A
e
A
−−−
0.05
0.35
0.10
9.90
5.10
c
A
1
b
c
0.002
0.008
0.020
0.008
0.413
0.215
0.014
0.004
0.390
0.201
D
E
e
b
A
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
10
10
0.035
0
0.028
_
_
_
_
Q
1
0.70
−−−
0.90
1.42
Z
−−− 0.056
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