NLAS7242MUTBG [ONSEMI]
High-Speed USB 2.0 (480 Mbps) DPDT Switches; 高速USB 2.0 （ 480 Mbps）的双刀双掷开关
| 型号： | NLAS7242MUTBG |
| 厂家： | 
ONSEMI |
| 描述： | High-Speed USB 2.0 (480 Mbps) DPDT Switches |
| 文件： | 总10页 (文件大小：662K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NLAS7242
High-Speed USB 2.0
(480 Mbps) DPDT Switches
The NLAS7242 is a DPDT switch optimized for high−speed
USB 2.0 applications within portable systems. It features ultra−low on
capacitance, C = 7.5 pF (typ), and a bandwidth above 950 MHz. It
is optimized for applications that use a single USB interface connector
ON
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MARKING
to route multiple signal types. The C and R of both channels are
ON
ON
suitably low to allow the NLAS7242 to pass any speed USB data or
audio signals going to a moderately resistive terminal such as an
external headset. The device is offered in a UQFN10 1.4 mm x 1.8 mm
package.
DIAGRAM
UQFN10
CASE 488AT
AD MG
Features
G
1
• Optimized Flow−Through Pinout
• R : 5.0 ꢀ Typ @ V = 4.2 V
ON
CC
• C : 7.5 pF Typ @ V = 3.3 V
AD
M
G
=
=
=
Device Code
Date Code
Pb−Free Device
ON
CC
• V Range: 1.65 V to 4.5 V
CC
• Typical Bandwidth: 950 MHz
(Note: Microdot may be in either location)
• 1.4 mm x 1.8 mm x 0.50 mm UQFN10
• OVT on Common Signal Pins D+/D− up to 5.25 V
• 8 kV HBM ESD Protection on All Pins
• This is a Pb−Free Device
ORDERING INFORMATION
†
Device
Package
Shipping
3000/Tape & Reel
Typical Applications
NLAS7242MUTBG
UQFN0
• High Speed USB 2.0 Data
• Mobile Phones
• Portable Devices
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
NLAS7242
HS
USB
XCVR
FS USB
XCVR or
AUDIO
AMP
Figure 1. Application Diagram
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
August, 2009 − Rev. 4
NLAS7242/D
NLAS7242
HSD2+
HSD2−
7
6
8
9
5
4
3
OE
HSD1+
V
CC
HSD1−
CONTROL
S
10
GND
1
2
D+
D−
Figure 2. Pin Connections and Logic Diagram (Top View)
Table 1. PIN DESCRIPTION
Table 2. TRUTH TABLE
Function
Pin
S
HSD1+,
HSD2+,
HSD1−
HSD2−
OE
S
Control Input
Output Enable
Data Ports
1
0
0
X
0
1
OFF
ON
OFF
OFF
OFF
ON
OE
HSD1+, HSD1−, HSD2+,
HSD2−, D+, D−
MAXIMUM RATINGS
Symbol
Pins
Parameter
Value
−0.5 to +5.5
Unit
V
V
CC
V
IS
V
CC
Positive DC Supply Voltage
Analog Signal Voltage
HSDn+,
HSDn−
−0.5 to V + 0.3
V
CC
D+, D−
−0.5 to +5.25
−0.5 to +5.5
50
V
IN
S, OE
Control Input Voltage, Output Enable Voltage
Positive DC Supply Current
V
I
V
CC
mA
°C
CC
T
Storage Temperature
−65 to +150
$300
S
I
I
I
HSDn+,
HSDn−,
D+, D−
Analog Signal Continuous Current−Closed Switch
mA
IS_CON
HSDn+,
HSDn−,
D+, D−
Analog Signal Continuous Current 10% Duty Cycle
Control Input Current, Output Enable Current
$500
$20
mA
mA
IS_PK
S, OE
IN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Pins
Parameter
Positive DC Supply Voltage
Min
1.65
GND
Max
Unit
V
V
CC
V
IS
4.5
HSDn+,
HSDn−
Analog Signal Voltage
V
CC
V
D+, D−
GND
GND
−40
4.5
V
IN
S, OE
Control Input Voltage, Output Enable Voltage
Operating Temperature
V
CC
V
T
A
+85
°C
Minimum and maximum values are guaranteed through test or design across the Recommended Operating Conditions, where applicable.
Typical values are listed for guidance only and are based on the particular conditions listed for section, where applicable. These conditions
are valid for all values found in the characteristics tables unless otherwise specified in the test conditions.
ESD PROTECTION
Symbol
Parameter
Value
Unit
ESD
Human Body Model − All Pins
8.0
kV
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2
NLAS7242
DC ELECTRICAL CHARACTERISTICS
CONTROL INPUT, OUTPUT ENABLE VOLTAGE (Typical: T = 25°C)
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
V
IH
S, OE
Control Input, Output
Enable HIGH Voltage
(See Figure 11)
2.7
3.3
4.2
1.25
1.3
1.4
−
−
V
V
S, OE
S, OE
Control Input, Output
Enable LOW Voltage
(See Figure 11)
2.7
3.3
4.2
−
−
−
0.35
0.4
V
IL
0.5
I
IN
Current Input, Output
Enable Leakage Current
0 ≤ V ≤ V
CC
1.65 − 4.5
−
1.0
ꢁ
A
IS
SUPPLY CURRENT AND LEAKAGE (Typical: T = 25°C, V = 3.3 V)
CC
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
I
V
Quiescent Supply Current 0 ≤ V ≤ V ; I = 0 A
1.65 − 3.6
3.6 − 4.5
−
−
−
−
1.0
1.0
ꢁ
A
CC
CC
IS
CC
D
0 ≤ V ≤ V − 0.5 V
IS
CC
CC
CC
I
I
OFF State Leakage
0 ≤ V ≤ V
1.65 − 4.5
−
−
0.1
1.0
1.0
ꢁ A
ꢁ A
OZ
IS
D+, D− Power OFF Leakage
0 ≤ V ≤ V
0
−
OFF
IS
Current
LIMITED VIS SWING ON RESISTANCE (Typical: T = 25°C)
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
R
On−Resistance (Note 1)
I
= 8 mA
= 0 V to 0.4 V
2.7
3.3
4.2
−
6.0
5.5
5.0
8.6
7.6
7.0
ꢀ
ON
ON
IS
V
R
On−Resistance Flatness
I
= 8 mA
2.7
3.3
4.2
−
−
0.55
0.30
0.20
−
ꢀ
ꢀ
FLAT
ON
IS
(Notes 1 and 2)
V
= 0 V to 0.4 V
ꢂ
R
On−Resistance Matching
(Notes 1 and 3)
I
= 8 mA
= 0 V to 0.4 V
2.7
3.3
4.2
0.60
0.60
0.60
−
ON
ON
V
IS
1. Guaranteed by design.
2. Flatness is defined as the difference between the maximum and minimum value of On−Resistance as measured over the specified analog
signal ranges.
+
−
+
−
3. ꢂ R = R
− R
between HSD1 and HSD1 or HSD2 and HSD2 .
ON
ON(max)
ON(min)
FULL VIS SWING ON RESISTANCE (Typical: T = 25°C)
−40°C to +85°C
Min
Typ
Max
Symbol
Pins
Parameter
On−Resistance
Test Conditions
V
CC
(V)
Unit
R
I
= 8 mA
2.7
3.3
4.2
−
10
8.0
7.0
13.5
9.75
8.50
ꢀ
ON
ON
IS
V
= 0 V to V
CC
CC
CC
R
On−Resistance Flatness
(Notes 4 and 5)
I
= 8 mA
= 0 V to V
2.7
3.3
4.2
−
−
4.5
3.0
2.5
−
ꢀ
ꢀ
FLAT
ON
V
IS
ꢂ
R
On−Resistance
(Note 4 and 6)
I
= 8 mA
= 0 V to V
2.7
3.3
4.2
0.60
0.60
0.60
−
ON
ON
V
IS
4. Guaranteed by design.
5. Flatness is defined as the difference between the maximum and minimum value of On−Resistance as measured over the specified analog
signal ranges.
+
−
+
−
6. ꢂ R = R
− R between HSD1 and HSD1 or HSD2 and HSD2 .
ON(min)
ON
ON(max)
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3
NLAS7242
AC ELECTRICAL CHARACTERISTICS
TIMING/FREQUENCY (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 35 pF, f = 1 MHz)
CC
L
L
−405C to +855C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
t
Closed to Open
Turn−ON Time
1.65 − 4.5
1.65 − 4.5
1.65 − 4.5
1.65 − 4.5
−
13.0
30.0
ns
ON
(See Figures 4 and 5)
t
Open to Closed
Turn−OFF Time
(See Figures 4 and 5)
−
2.0
−
12.0
−
25.0
−
ns
ns
OFF
T
BBM
Break−Before−Make
Time (See Figure 3)
BW
−3 dB Bandwidth
(See Figure 10)
C = 5 pF
L
950
−
MHz
ISOLATION (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 5 pF)
CC
L
L
−405C to +855C
Min
Typ
Max
Symbol
Pins
Parameter
Test Conditions
V
CC
(V)
Unit
O
Open
OFF−Isolation
(See Figure 6)
f = 240 MHz
1.65 − 4.5
−
−22
−
dB
IRR
X
TALK
HSDn+ to HSDn− Non−Adjacent Channel
f = 240 MHz
1.65 − 4.5
−
−24
−
dB
Crosstalk
CAPACITANCE (Typical: T = 25°C, V = 3.3 V, R = 50 ꢀ, C = 5 pF)
CC
L
L
−405C to +855C
Min
−
Typ
1.5
1.0
7.5
Max
−
Symbol
Pins
Parameter
Test Conditions
Unit
C
S, OE
Control Pin, Output Enable
Input Capacitance
pF
V
V
V
= 0 V, f = 1 MHz
= 0 V, f = 10 MHz
IN
CC
CC
CC
−
−
C
D+ to
HSD1+ or
HSD2+
ON Capacitance
= 3.3 V; OE = 0 V, f = 1 MHz
S = 0 V or 3.3 V
−
−
ON
V
CC
= 3.3 V; OE = 0 V, f = 10 MHz
S = 0 V or 3.3 V
−
−
6.5
3.8
−
−
C
HSD1n or OFF Capacitance
HSD2n
V
CC
= V = 3.3 V;
OFF
IS
OE = 0 V, S = 3.3 V or 0 V,
f = 1 MHz
V
CC
= V = 3.3 V;
−
2.0
−
IS
OE = 0 V, S = 3.3 V or 0 V,
f = 10 MHz
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NLAS7242
V
CC
DUT
Input
V
CC
Output
GND
V
OUT
0.1 ꢁ F
50 ꢀ
35 pF
t
BMM
Output
50 % OF
DROOP
VOLTAGE
DROOP
Switch Select Pin
Figure 3. tBBM (Time Break−Before−Make)
V
CC
Input
50%
50%
90%
DUT
0 V
V
CC
Output
V
OUT
V
0.1 ꢁ F
OH
Open
90%
50 ꢀ
35 pF
Output
V
OL
Input
t
t
OFF
ON
Figure 4. tON/tOFF
V
CC
V
CC
Input
50%
50%
DUT
0 V
50 ꢀ
Output
V
OUT
V
OH
Open
35 pF
Output
V
10%
10%
OL
Input
t
t
ON
OFF
Figure 5. tON/tOFF
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5
NLAS7242
50 ꢀ
DUT
Reference
Input
50 ꢀ Generator
Transmitted
Output
50 ꢀ
Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss
is the bandwidth of an On switch. V , Bandwidth and V are independent of the input signal direction.
ISO
ONL
V
OUT
= Off Channel Isolation = 20 Logǒ Ǔfor V
V
V
at 100 kHz
IN
ISO
V
IN
OUT
V
= On Channel Loss = 20 Logǒ Ǔ for V
at 100 kHz to 50 MHz
ONL
IN
V
IN
Bandwidth (BW) = the frequency 3 dB below V
= Use V setup and test to all other switch analog input/outputs terminated with 50 ꢀ
ONL
V
CT
ISO
Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk
(On Channel to Off Channel)/VONL
DETAILED DESCRIPTION
High Speed (480Mbps) USB 2.0 Optimized
Over Voltage Tolerant
The NLAS7242 is a DPDT switch designed for USB
The NLAS7242 features over voltage tolerant I/O
protection on the common signal pins D+/D−. This allows
the switch to interface directly with a USB connector. The
applications within portable systems. The R and C of
ON
ON
both switches are maintained at industry−leading low levels
in order to ensure maximum signal integrity for USB 2.0
high speed data communication. The NLAS7242 switch can
be used to switch between high speed (480Mbps) USB
signals and a variety of audio or data signals such as full
speed USB, UART or even a moderately resistive audio
terminal.
D+/D− pins can withstand a short to V , up to 5.25 V,
BUS
continuous DC current for up to 24 hours as specified in the
USB 2.0 specification. This protection is achieved without
the need for any external resistors or protection devices.
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6
NLAS7242
NLAS7242
Figure 7. Board Schematic
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7
NLAS7242
Figure 8. Signal Quality
Figure 9. Near End Eye Diagram
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8
NLAS7242
Near End Test Data:
Consecutive jitter range
Min
Max
−54.37
−59.14
−50.79
−74.43
−61.60
−55.31
−82.55
−53.50
−62.60
73.21
59.56
34.57
81.65
58.55
48.43
80.33
71.65
47.30
ps
ps
ps
ps
ps
ps
ps
ps
ps
Paired JK jitter range
Paired KJ jitter range
Consecutive jitter range
Paired JK jitter range
Paired KJ jitter range
Consecutive jitter range
Paired JK jitter range
Paired KJ jitter range
Std.
N.C.
N.O.
−200 ps
+200 ps
−200 ps
−200 ps
+200 ps
+200 ps
0
−0.5
−1
−1.5
−2
−2.5
−3
−3.5
−4
−4.5
1.0E+6
10.0E+6
100.0E+6
1.0E+9
FREQUENCY (Hz)
Figure 10. Magnitude vs. Frequency
@ VCC = 3.3 V, All Temperatures
ICC Leakage Current as a Function of VIN Voltage (255C)
2.50E−03
4.2 V
3.3 V
2.00E−03
1.50E−03
1.00E−03
5.00E−04
0.00E+00
−5.00E−04
2.7 V
0
0.5
1
1.5
2
2.5
(V)
3
3.5
4
4.5
V
IN
Figure 11. ICC vs. VIN, Select Pin, All VCC’s, 255C
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NLAS7242
PACKAGE DIMENSIONS
UQFN10 1.4x1.8, 0.4P
CASE 488AT−01
ISSUE A
EDGE OF PACKAGE
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
D
A
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.25 AND 0.30 MM
FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED PAD
AS WELL AS THE TERMINALS.
L1
E
PIN 1 REFERENCE
DETAIL A
MILLIMETERS
Bottom View
DIM MIN
MAX
0.60
0.05
0.10
0.10
C
2X
A
A1
A3
b
0.45
0.00
(Optional)
0.127 REF
C
2X
0.15
0.25
MOLD CMPD
EXPOSED Cu
B
D
1.40 BSC
TOP VIEW
E
1.80 BSC
0.40 BSC
e
A
A3
0.05
0.05
C
L
0.30
0.50
0.15
0.60
0.00
0.40
L1
L3
A1
C
DETAIL B
Side View
(Optional)
10X
A1
SEATING
C
MOUNTING FOOTPRINT*
PLANE
SIDE VIEW
1.700
0.0669
9 X
0.563
0.0221
5
3
e/2
e
9 X L
0.663
0.0261
6
1
0.200
0.0079
1
10
10 X
0.10 C A B
2.100
L3
b
0.05 C
NOTE 3
0.0827
BOTTOM VIEW
0.400
0.0157
10 X
0.225
PITCH
0.0089
mm
inches
ǒ
Ǔ
SCALE 20:1
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operat-
ing parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor
the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associ-
ated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/
Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
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For additional information, please contact your local
Sales Representative
NLAS7242/D
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