NIS5102QP2HT1G [ONSEMI]
High Side SMART HotPlug IC/Inrush Limiter/Circuit Breaker; 高侧智能热插拔IC /浪涌限制器/断路器
| 型号： | NIS5102QP2HT1G |
| 厂家： | 
ONSEMI |
| 描述： | High Side SMART HotPlug IC/Inrush Limiter/Circuit Breaker |
| 文件： | 总14页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NIS5102
High Side
SMART HotPlugE IC/Inrush
Limiter/Circuit Breaker
The NIS5102 is a controller/FET IC that saves design time and
reduces the number of components required for a complete hot swap
application. It is designed for +12 V applications.
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MARKING
This chip includes a time delay for sequencing applications. It has a
dual function OVLO pin that allows multiple units to be ganged
together for simultaneous turn−on and shutdown, allowing units to be
operated in parallel. It allows for user selectable undervoltage and
overvoltage lockout levels. Its unique current limit circuit allows for
adjustable current limit levels with no external power resistor. An
internal temperature limiting circuit greatly increases the reliability of
this device.
DIAGRAM
1
5102QPxH
AWLYWWG
9x9 MM, 12 PIN PLLP
CASE 488AB
Features
x
= 1 or 2
• Integrated Power Device
• Power Device Thermally Protected
• No External Current Shunt Required
• Simultaneous Shutdown and Startup for Parallel Operation
• Enable/Timer Pin
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free
• Power Good
PIN CONNECTIONS
• 9.0 to 18 V Input Range
• 10 mW
• Main/Mirror MOSFET Current Ratio 1000:1
• Pb−Free Packages are Available
12
1
2
11
10
9
3
4
13
Typical Applications
5
6
8
• High Availability Systems
• Electronic Circuit Breaker
• 12 V Distributed Architecture
7
(Bottom View)
ORDERING INFORMATION
†
Device
Package
Shipping
NIS5102QP1HT1
(Latchoff)
9x9 mm 1500/Tape & Reel
12 Pin PLLP
NIS5102QP1HT1G 12 Pin PLLP 1500/Tape & Reel
(Latchoff)
(Pb−Free)
NIS5102QP2HT1
(Auto−Retry)
9x9 mm 1500/Tape & Reel
12 Pin PLLP
NIS5102QP2HT1G 12 Pin PLLP 1500/Tape & Reel
(Auto−Retry)
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
October, 2006 − Rev. 5
NIS5102/D
NIS5102
V
C
charge
CC
13
5
Voltage
Regulator
Charge
Pump
Current
Limit
Thermal
Shutdown
10, 11, 12
Source
Undervoltage
Lockout
2
6
7
Current Limit
Power Good
UVLO
Common
Shutdown
Power
Good
Enable/
Timer
1
4 GND
Overvoltage
Shutdown
OVLO
3
Enable/Timer
Figure 1. Block Diagram
PIN FUNCTION DESCRIPTION
Pin
Function
Description
1
OVLO
The overvoltage shutdown point is programmed by a resistor from this pin to the V supply. When
CC
tied together with other devices, this pin also communicates a shutdown state due to undervoltage
and overtemperature reasons. All devices connected will simultaneously shutdown. Startup for this
condition may be simultaneous or sequenced.
2
3
UVLO
A resistor from V to the UVLO pin adjusts the voltage at which the device will turn on.
CC
Enable/Timer
A high level signal on this pin allows the device to begin operation. Connection of a capacitor will
delay turn on for timing purposes. A low input signal inhibits the operation, and communicates to any
other paralleled devices (via the OVLO pin) to shutdown. This signal can also be used to reset the
thermal latch.
Ground
Negative input voltage to the device. This is used as the internal reference for the IC.
4
5
C
charge
An external capacitor is required from this pin to the source pin. This is the storage capacitor for the
internal charge pump. A small internal capacitor is included for noise filtering.
6
ILIMIT
A resistor (RLIMIT) tied from this pin to the source pin sets the current limit level.
A high impedance signal on this pin indicates that the power device is conducting.
−
7
8, 9
Power Good
No Connection
Source
10, 11, 12
13
Source of power FET, which is also the switching node for the load.
Positive input voltage to the device.
V
CC
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2
NIS5102
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Rating
Symbol
Value
−0.3 to 18
−0.3 to 25
−0.3 to 18
−0.3 to 25
20
Unit
V
Input Voltage, Operating, Steady−State (Input + to Input −)
V
in
V
in
Input Voltage, Operating, Transient (Input + to Input −), 1 second
Drain Voltage, Operating, Steady−State (Drain to Input −)
Drain Voltage, Operating, Transient (Drain to Input −), 1 second
Drain Current, Peak
V
V
V
V
DD
DD
V
I
A
Dpk
2
Continuous Current (T = 25°C, 0.5 in pad)
I
10
A
A
Davg
Voltage on Power Good Pin (Pin 7)
V
20
V
max7
Thermal Resistance, Junction−to−Air
Q
JA
2
0.5 in Copper
76.5
41.2
°C/W
°C/W
2
1 in Copper
Thermal Resistance, Junction−to−Lead
Q
3.2
1.4
°C/W
W
JL
2
Power Dissipation (T = 25°C, 0.5 in pad)
P
max
A
Operating Temperature Range (Note 1)
Non−Operating Temperature Range
Lead Temperature, Soldering (10 Sec)
T
J
T
J
T
L
−40 to 175
−55 to 175
235
°C
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Actual maximum junction temperature is limited by an internal protection circuit and will not reach the absolute maximum temperature as
specified.
ELECTRICAL CHARACTERISTICS (V = 12 V, RLIMIT = 36 W, C
= 100 pF, T = 25°C unless otherwise noted.)
J
CC
Charge
Characteristic
POWER FET
Symbol
Min
Typ
Max
Unit
Delay Time (Enable High to I = 100 mA)
T
−
−
−
−
2.0
1.0
10
−
−
−
ms
ms
mW
mA
S
dly
Charging Time (I = 100 mA to I = 5.0 A, RLIMIT = 36 W)
t
chg
S
S
ON Resistance (V = 12 V, I = 5.0 A) (Note 2)
R
13
10
CC
S
DSon
DSS1
Zero Gate Voltage Drain Current
(V = 12 V , V = 0 V
I
)
dc
DS
dc
GS
Zero Gate Voltage Drain Current
(V = 18 V , V = 0 V
I
−
−
−
−
100
−
mA
DSS2
)
dc
DS
dc
GS
Output Capacitance (V = 12 V , V = 0 V , f = 10 kHz)
−
pF
DS
dc
GS
dc
THERMAL LIMIT
Shutdown Temperature (Note 3)
Hysteresis (Note 3)
T
125
−
135
40
145
−
°C
°C
SD
T
hyst
OVER/UNDERVOLTAGE
UVLO Turn−on (Input + Increasing, Rext
= 620 k)
V
10.05
0.45
14.0
0.6
11.15
0.62
16.4
0.78
12.30
0.75
19.0
1.0
V
V
V
V
UVLO
on
UVLO Hysteresis (Input + Decreasing, Rext
= 620 k)
V
UVLO
hyst
OVLO Turn−off (Input + Increasing, Rext
= 620 k)
V
off
UVLO
OVLO Hysteresis (Input + Decreasing, Rext
= 620 k)
V
UVLO
hyst
PARALLEL SHUTDOWN (Alternate Function on OVLO Pin)
Device Fan−out (Minimum External Resistor Value = 2.0 kW (Note 3)
Shutdown Voltage Threshold (OVLO Pin)
N
V
−
0.6
−
−
4.0
−
Devices
fan
SD
low
0.8
0.3
V
V
Shutdown State Output Voltage (Isink = 2.0 mA)
V
0.4
2. Pulse Test: Pulse width 300 ms, duty cycle 2%.
3. Verified by design.
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3
NIS5102
ELECTRICAL CHARACTERISTICS (continued) (V = 12 V, RLIMIT = 36 W, C
= 100 pF, T = 25°C unless otherwise noted.)
J
CC
Charge
Characteristic
Symbol
Min
Typ
Max
Unit
CURRENT LIMIT
Current Limit (Short Circuit, R
= 36 W)
I
I
3.8
7.0
4.8
7.8
5.8
8.6
A
A
LIMIT
LIM1
LIM2
Current Limit (Overload, R
ENABLE/TIMER
= 36 W) (Note 3)
LIMIT
Enable Voltage (Turn−On)
Enable Voltage (Turn−Off)
V
V
2.2
−
−
−
−
1.6
88
−
V
V
ENon
ENoff
Charging Current (Into External Capacitor)
Turn−on Delay (Time from Enable High to I
CHARGE PUMP
I
65
−
77
2.2
mA
ms
Charge
= 100 mA)
t
delay
source
C
(Voltage on Pin 5 with Respect to Ground)
= 18 Vdc
V
−
−
18
26
−
−
V
V
Charge
Ccharge
V
CC
POWER GOOD
−
−
−
−
−
−
−
300
10
−
−
Power Good → High Z Signal when FET is Fully Enhanced
Low Z State Output Voltage (I
= 2 mA)
Vpin7
230
2.0
15
mV
mA
ms
Sink
Leakage Current (Vpin7 = 12 V, High Z State)
I
Leak
Power Good Delay
t
pwrgood
(Time from Power FET is Fully Enhanced to Power Good FET Changing State)
TOTAL DEVICE
Bias Current (Operational, V = 12 V)
I
I
−
−
−
1.3
400
8.5
2.0
700
9.0
mA
mA
V
CC
Bias
Bias
Bias Current (Non−operational, V = 7 V))
CC
Minimum Operating Voltage
Vcc
min
Output Current
Source Voltage
Enable/Timer
Threshold
Input
Figure 2. Timing Diagram for External Enabled Delay
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4
NIS5102
TYPICAL PERFORMANCE CURVES
(T = 25°C unless otherwise noted)
A
14
13
12
11
19
18
17
Turn−off
Turn−on
Turn−on
16
15
14
Turn−off
13
12
11
10
9
10
9
8
200
100 200 300 400 500 600 700 800 900 1000
300
400 500
600
700
(kW)
800 900 1000
R
R
OVLO
(kW)
UVLO
Figure 3. UVLO Adjustment
Figure 4. OVLO Adjustment
100
10
1
10
1
Vin = 12 V
Rext_ILimit = 100 W
Overload
Short Circuit
0.1
0.01
0.1
10
100
1000
10
100
1000
10000
R
ILmit
(W)
LOAD CAPACITANCE (mF)
Figure 5. Current Limit Adjustment
Figure 6. Load Capacitance vs. Output di/dt
16
14
12
10
8
105
95
85
75
65
Device Reaching
Thermal Shutdown
1/4 sq in copper area
1 sq in copper area
2 sq in copper area
6
55
45
35
4
2
0
25
1.0
3.0
5.0
7.0
9.0
11
13
−40 −25 −10
5
20 35 50 65 80 95 110 125
CONTINUOUS CURRENT, A
T , JUNCTION TEMPERATURE, (°C)
J
Figure 7. Continuous Current vs. Case Temperature
(Test performed on a double−sided copper board, 1 oz)
Figure 8. Typical RDS(on) vs. Junction
Temperature
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5
NIS5102
TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS
(T = 25°C unless otherwise noted)
A
VCC
R
OVLO
Power Good
Source
OVLO
R
UVLO
R
C
LIMIT
C
UVLO
DC−DC
Converter
Current
Limit
En/Timer
charge
C
charge
Gnd
C
delay
Figure 9. Typical Applications Circuit
Power Good
Delay
Input Voltage
Input Voltage
Output Voltage
Output Voltage
Power
Good
GND
Output Current
Device Reaching
Thermal Limit
Output Current
Turn on
Delay
Figure 10. Turn−on Waveforms for 3300 mF Load
Figure 11. Turn−on Waveforms for Shorted
Output, Latchoff Device
Capacitors
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6
NIS5102
TYPICAL APPLICATION CIRCUITS AND OPERATION WAVEFORMS (continued)
(T = 25°C unless otherwise noted)
A
Input Voltage
PowerGood
utputVoltage
utputCurrent
eviceReaching
hermal Limit
Figure 12. Turn−On Waveforms for Shorted Output,
Auto−Retry Device
Input Voltage
Overvoltage
Condition
Output Voltage
Power Good
Output Current
Figure 13. Device Response During an Overvoltage
Condition
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7
NIS5102
C
charge
C
charge
C
charge
C
charge
VCC
VCC
R
OVLO
R
OVLO
Power Good
Source
Power Good
Source
OVLO
OVLO
R
UVLO
R
LIMIT
R
LIMIT
R
UVLO
UVLO
UVLO
DC−DC
Converter
DC−DC
Converter
Current
Limit
Current
Limit
En/Timer
En/Timer
Gnd
Gnd
C
delay2
C
delay1
Figure 14. Turn−on Sequencing Using Power Good Signal
C
charge
R
UVLO
C
charge
C
charge
VCC
VCC
R
UVLO
Power Good
Source
Power Good
Source
UVLO
UVLO
R
OVLO
R
LIMIT
R
LIMIT
OVLO
OVLO
DC−DC
Converter
Current
Limit
Current
Limit
En/Timer
En/Timer
Gnd
Gnd
C
delay
Figure 15. Parallel Operation / Simultaneous Turn−on and Shutdown
Input Voltage
Output Voltage
I
I
, Device1
, Device2
out
out
Figure 16. Turn−on Waveforms for Parallel Operation
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NIS5102
OPERATING DESCRIPTION
Operation
reach the current limit threshold, or is shutdown due to an
overvoltage, undervoltage or thermal fault. Both the UVLO
and OVLO circuits incorporate hysteresis to assure clean
turn−on and turn−offs with no chatter. The thermal latching
circuit will require the input power to be recycled to resume
operation after a fault. The current limit is always active, so
any transient or overload will always be limited.
The NIS5102 has a variety of shutdown and protection
features that make this part extremely versatile as well as
rugged. For the unit to operate, the input voltage must be
within the operating range of the part which is set by the
UVLO and OVLO bias resistors. The enable must also be
high for operation. Current and thermal limit circuits
constantly monitor the operation and will protect the unit if
either of these parameters exceeds its preset limit.
Circuit Description
An additional shutdown method, is the use of the OVLO
pin, which can be tied in parallel. This allows multiple units
to be either operated in parallel, and will shutdown and turn
on simultaneously for any fault other than an overvoltage, or
it allows these hot plug devices to control independent loads,
and shutdown and turn on simultaneously.
Enable/Timer
The enable/timer pin can function either as a direct enable
pin, or as a time delay. In the enable mode, an open collector
device is connected to this pin. When the device is in its low
impedance mode, this pin is low and the operation of the chip
is disabled. If a time delay is required, a capacitor is added
to this pin. Figure 17 shows the equivalent circuit for the
enable.
Faults
Once the load capacitance is charged, the SENSEFETt
will become fully enhanced as long as the current does not
80 mA
Enable/
Timer
Enabled
+
−
2.2 V
NIS5102
Figure 17. Enable/Timer Circuit
If a capacitor is added without an open collector device,
the turn on will be delayed from the time at which the UVLO
voltage is reached. If an open collector device is also used,
the delay will start from the time that it goes into its high
impedance state. The capacitor is charged by an internal
current source.
of the internal charge pump. Once the V of the power
GS
SENSEFET reaches around 90% of the internal charge
pump output voltage, the power good will change its state
from low impedance to high impedance but only after the
power good delay has elapsed. Figure 10 shows the power
good behavior during the startup of the NIS5102 device, an
There is an inherent delay in the turn on of the hot plug
device, due to the method of gate drive used. The gate of the
power FET is charged through a high impedance resistor,
and from the time that the gate starts charging until the time
that it reaches its threshold voltage, there will be no
conduction. Once the gate reaches its threshold voltage, the
output current will begin a controlled ramp up phase.
This delay will be added to any timing delay due to the
enable/timer circuit.
external pullup resistor from power good to V was used.
CC
The power good will change its state from high impedance
to low impedance in the event of any fault condition such as
short circuit and overvoltage.
Undervoltage Lockout
The UVLO circuit holds the chip off when the input
voltage is less than the turn−on limit. It includes internal
hysteresis to assure clean on/off switching. An internal
divider sets the turn−on voltage level at 16 V. This voltage
can be reduced by adding an external resistor from the
Power Good
The power good circuit monitors the V voltage of the
UVLO pin to the V pin. The equivalent circuit is shown
GS
CC
power SENSEFET and compares it with the output voltage
in Figure 18.
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9
NIS5102
V
CC
R
UVLO
400 k
Source
UVLO
V
= 1.15 V
GS(th)
40 k
3 k
Ground
Figure 18. Equivalent Undervoltage Lockout Circuit
The theoretical equation for the UVLO turn−on voltage is:
ground. This will create a low pass filter with a cutoff
frequency of f. The required capacitance on this pin is:
400 V * 460
in
R
UVLO
(KW) +
17.5 * V
1
in
C
UVLO
+
R
· 400 K
UVLO
UVLO
ƪ
2p · f 43 K ) ǒ
Ǔƫ
The UVLO trip point voltage calculated through the
theoretical formula may show small variations with respect
to Figure 3, therefore it is recommended to use the formulas
gotten from the UVLO characterization, which are shown
below:
R
)400 K
Overvoltage Lockout and Parallel Shutdown
The overvoltage lockout (OVLO) is a dual function pin.
This pin will normally be biased somewhere between
ground and the input voltage, due to an internal voltage
divider which sets the turn−off voltage level at 22 V. This
voltage level can be reduced by adding an external resistor
[(UVLO ) 14.647)ń3.9858]
R
(kW) + e
;for T + 25°C
UVLO
J
where “UVLO” is the desired undervoltage lockout value,
and R
is the programming resistor from the UVLO pin
UVLO
from the OVLO pin to the V pin. When the input voltage
CC
to the V pin.
CC
reaches the programmed trip point, operation of the device
is inhibited.
Figure 19 shows the equivalent circuit.
To reduce nuisance tripping due to transients and noise
spikes, a capacitor may be added from the UVLO pin to
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10
NIS5102
V
CC
R
OVLO
300 k
Source
OVLO
7 V
200 k
2 M
Ground
Figure 19. Equivalent Overvoltage Lockout Circuit
Temperature Limit
The theoretical equation for the OVLO turn−on voltage is:
The temperature limit circuit senses the temperature of the
Power FET and removes the gate drive if the maximum level
is exceeded. For the auto−retry device, there is a nominal
hysteresis of 40°C for this circuit. After a thermal shutdown,
the device will automatically restart when the temperature
drops to a safe level as determined by the hysteresis. The
latching thermal circuit can be reset either by recycling the
input power, or by toggling the enable signal.
300 V * 2100
in
R
OVLO
(KW) +
21.8 * V
in
The OVLO trip point voltage calculated through the
theoretical formula may show small variations with respect
to Figure 4, therefore it is recommended to use the formulas
gotten from the OVLO characterization, which are shown
below:
[(OVLO ) 5.2)ń3.46]
R
OVLO
(kW) + e
; forT + 25°C
J
Current Limit
where “OVLO” is the desired overvoltage lockout value,
An external resistor from the current limit pin to the source
pins set the level at which the device will limit the current.
The plot of resistance vs. current limit includes two curves,
one for short circuit and one for overload.
and R is the programming resistor from the OVLO pin
OVLO
to the V pin.
CC
To reduce nuisance tripping due to transients and noise
spikes, a capacitor may be added from the OVLO pin to
ground. This will create a low pass filter with a cutoff
frequency of f. The required capacitance on this pin is:
A short circuit condition is one in which the SENSEFET
is not fully enhanced, and is therefore in a high impedance
mode of operation. In this case there are many hundreds of
millivolts across the drain to source pins of the SENSEFET.
This occurs when the output sees a very low impedance short
as well as when the capacitor is charging at turn on. In both
cases there are several volts or more across the FET.
An overload condition is one in which the SENSEFET is
still fully enhanced and the drain to source voltage is the
product of the drain current and the on resistance of the FET.
The sense voltage out of the SENSEFET has a different
relation to the drain current in these two conditions. The
difference in current limit levels for these two cases is called
DI, where:
−6
[1 ) (8.83 E · R
)]
OVLO
C
OVLO
+
2p · f · R
OVLO
This pin is also used as a common shutdown pin. In this
mode, if this pin is pulled to ground, it will shutdown the chip
and all chips connected to its OVLO pin.
The OVLO pin has an internal switch to ground that will
pull it low, whenever the device is disabled due to any fault
other than an Overvoltage condition. An enable pin
shutdown is not considered a fault and will not cause a
common shutdown. This feature allows multiple units to
turn on and off simultaneously by tying the OVLO pins
together in parallel. This can be used for operating several
hot plug devices in parallel, or for use with separate loads,
when all devices need to startup and shutdown
simultaneously.
DI + V ńR
ref DSon
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NIS5102
For this equation, V is the reference voltage of the
where “ILimit” is the desired short circuit ILimit value, and
R is the programming resistor from the ILimit pin to the
ILimit
ref
current limit circuit, and R
is the on resistance of the
DSon
SENSEFET. For more information on this, see application
note AND8140/D, “SMART HotPlugt Current Limit
Function”.
This inherent property of the SENSEFET allows for
simple dual level current limiting, in which a short circuit
condition will see a lower level of limiting than will an
overload. This operation will exist in start up as well as under
normal operation, so the device will be able to differentiate
between a short and an overload.
As with all SMART HotPlug devices, the current limit will
never shutdown the device. Only the thermal limit will stop
the flow of current to the load. Once the current is stopped due
to the thermal limit, it will remain off until input power is
recycled for the latching version, or it will continuously retry
to start again if it is the auto−retry version.
The ILimit graph shown in Figure 5 was generated from
the data of the ILimit characterization, the formula for the
short circuit curve is:
source pin.
Turn−on Surge
During the turn−on event, there is a large amount of
energy dissipated due to the linear operation of the power
device. The energy rating is the amount of energy that the
device can absorb before the thermal limit circuit will shut
the unit down. This is very important specially for the latch
off device as it determines the maximum load capacitance
that the device can charge before the thermal limit shuts the
device down. The calculation of this is not very simple as it
depends on several factors such as the input voltage (Vin),
load capacitance (CL), current limit settings (ILimit) and
device’s thermal transient response, therefore, it is
recommended to do lab evaluations for these purposes.
Figure 20 shows the device’s thermal transient response for
minimum pad.
1.02
152.86
ILimit
(W) + ǒ Ǔ
R
ILimit
for T + 25°C
J
100
10
Min Pad
1−in Pad
1
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
TIME (seconds)
Figure 20. Thermal Transient Response
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NIS5102
PACKAGE DIMENSIONS
PLLP−12, 9x9 mm
CASE 488AB−01
ISSUE C
NOTES:
0.10
C
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. COPLANARITY APPLIES TO THE LEAD,
DIMENSION B, AND EXPOSED PAD.
SEATING
PLANE
0.08
C
B
E
A
D
C
MILLIMETERS
DIM
A
A1 0.000
MIN
1.750
MAX
1.950
0.050
A3
b
0.254 REF
PIN ONE
LOCATION
0.400
0.600
D
E
e
9.000 BSC
9.000 BSC
1.270 BSC
D2 5.400
E2 7.400
5.600
7.600
(A3)
A1
4 X
K
L
0.850 REF
0.850
0.950
0.15
C
A
STYLE 1:
PIN 1. OVLO
2. UVLO
TOP VIEW
D2
SIDE VIEW
3. ENABLE/TIMER
4. GND
5. CCHARGE
6. CURRENT LIMIT
7. POWER GOOD
8. N/C
12 X K
12 X L
10 X e
9. N/C
10. SOURCE
11. SOURCE
12. SOURCE
E2
e/2
12 X
b
M
M
0.10
0.05
C
C
A B
BOTTOM VIEW
SOLDERING FOOTPRINT*
9.305
12 X
1.054
5.652
12 X
0.551
7.652
1.270 PITCH
Dimensions in mm
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
NIS5102
The product described herein (NIS5102), may be covered by one or more of the following U.S. patents: 6,781,502; 6,865,063; 7,099,135. There may be other
patents pending. SMART HotPlug and SENSEFET are trademarks of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NIS5102/D
相关型号：
NIS5132MN1T1G
1-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10, 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, DFN-10
ONSEMI
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