NIS5132MN1T1G [ONSEMI]
1-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10, 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, DFN-10;
| 型号： | NIS5132MN1T1G |
| 厂家： | 
ONSEMI |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10, 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, DFN-10 |
| 文件： | 总11页 (文件大小：263K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NIS5132 Series
+12 Volt Electronic Fuse
The NIS5132 is a cost effective, resettable fuse which can greatly
enhance the reliability of a hard drive or other circuit from both
catastrophic and shutdown failures.
It is designed to buffer the load device from excessive input voltage
which can damage sensitive circuits. It also includes an overvoltage
clamp circuit that limits the output voltage during transients but does
not shut the unit down, thereby allowing the load circuit to continue
operation. Two thermal options are available, latching and auto−retry.
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3.6 AMP, 12 VOLT
ELECTRONIC FUSE
Features
• Integrated Power Device
• Power Device Thermally Protected
• No External Current Shunt Required
• 9 V to 18 V Input Range
DFN10
CASE 485C
• 44 mW Typical
• Internal Charge Pump
MARKING DIAGRAM
• Internal Undervoltage Lockout Circuit
• Internal Overvoltage Clamp (MN1 and MN2 versions)
Pin
1
2
3
4
5
Function
GND
dv/dt
Enable/Fault
ILIMIT
NC
1
32
AYWG
G
• ESD Ratings: Human Body Model (HBM); 1500 V
Machine Model (MM); 200 V
• These Devices are Pb−Free and are RoHS Compliant
6−10
11 (flag) VCC
SOURCE
Typical Applications
• Hard Drives
• Mother Board Power Management
32 = Latching Version with V
32B = Latching Version without V
32H = Auto−Retry Version with V
Clamp
Clamp
Clamp
A
Y
W
G
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the ordering
information section on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
February, 2012 − Rev. 9
NIS5132/D
NIS5132 Series
VCC
Charge
Pump
Enable
ENABLE/
FAULT
SOURCE
Current
Limit
Thermal
Shutdown
I
LIMIT
UVLO
dv/dt
dv/dt
Control
Voltage
Clamp*
(*MN1 and MN2 versions)
Figure 1. Block Diagram
GND
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
1
Function
Ground
dv/dt
Description
Negative input voltage to the device. This is used as the internal reference for the IC.
2
The internal dv/dt circuit controls the slew rate of the output voltage at turn on. It has an internal
capacitor that allows it to ramp up over a period of 2 ms. An external capacitor can be added to
this pin to increase the ramp time. If an additional time delay is not required, this pin should be left
open.
3
4
Enable/Fault
The enable/fault pin is a tri−state, bidirectional interface. It can be used to enable or disable the
output of the device by pulling it to ground using an open drain or open collector device. If a
thermal fault occurs, the voltage on this pin will go to an intermediate state to signal a monitoring
circuit that the device is in thermal shutdown. It can also be connected to another device in this
family to cause a simultaneous shutdown during thermal events.
I
A resistor between this pin and the source pin sets the overload and short circuit current limit
levels.
Limit
6−10
Source
This pin is the source of the internal power FET and the output terminal of the fuse.
Positive input voltage to the device.
11 (belly pad)
V
CC
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage, operating, steady−state (V to GND, Note 1)
V
IN
−0.6 to 18
−0.6 to 25
V
CC
Transient (100 ms)
Thermal Resistance, Junction−to−Air
q
°C/W
JA
2
0.1 in copper (Note 2)
227
95
2
0.5 in copper (Note 2)
Thermal Resistance, Junction−to−Lead (Pin 1)
Thermal Resistance, Junction−to−Case
q
27
20
°C/W
°C/W
JL
q
JC
Total Power Dissipation @ T = 25°C
P
max
1.3
10.4
W
mW/°C
A
Derate above 25°C
Operating Temperature Range (Note 3)
Nonoperating Temperature Range
Lead Temperature, Soldering (10 Sec)
T
T
−40 to 150
−55 to 155
260
°C
°C
°C
J
J
L
T
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Negative voltage will not damage device provided that the power dissipation is limited to the rated allowable power for the package.
2. 1 oz. copper, double−sided FR4.
3. Thermal limit is set above the maximum thermal rating. It is not recommended to operate this device at temperatures greater than the
maximum ratings for extended periods of time.
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2
NIS5132 Series
ELECTRICAL CHARACTERISTICS (Unless otherwise noted: V = 12 V, C = 100 mF, dv/dt pin open, R
= 10 W, T = 25°C
j
CC
L
LIMIT
unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
POWER FET
Delay Time (enabling of chip to I = 100 mA with 1 A resistive load)
T
dly
220
ms
D
Kelvin ON Resistance (Note 4)
J
R
35
44
62
55
mW
DSon
T = 140°C (Note 5)
Off State Output Voltage
V
off
190
300
mV
(V = 18 V , V = 0 V , R = R)
CC
dc
GS
dc
L
Output Capacitance (V = 12 V , V = 0 V , f = 1 MHz)
250
pF
A
DS
dc
GS
dc
2
Continuous Current (T = 25°C, 0.5 in pad) (Note 5)
I
D
I
D
3.6
1.7
A
(T = 80°C, minimum copper)
A
THERMAL LATCH
Shutdown Temperature (Note 5)
T
150
175
45
200
°C
°C
SD
Thermal Hysteresis (Decrease in die temperature for turn on, does not apply
to latching parts)
T
Hyst
UNDER/OVERVOLTAGE PROTECTION
Output Clamping Voltage (Overvoltage Protection) (V = 18 V) (Note 6)
V
14
7.7
−
15
8.5
16.2
9.3
−
V
V
V
CC
Clamp
Undervoltage Lockout (Turn on, voltage going high)
UVLO Hysteresis
V
UVLO
V
0.80
Hyst
CURRENT LIMIT
Kelvin Short Circuit Current Limit (R
= 15.4 W, Note 7)
I
2.75
0.5
3.44
4.6
4.25
A
A
Limit
Lim−SS
I
Lim−OL
Kelvin Overload Current Limit (R
= 15.4 W, Note 7)
Limit
dv/dt CIRCUIT
Output Voltage Ramp Time (Enable to V
Maximum Capacitor Voltage
ENABLE/FAULT
= 11.7 V)
t
0.9
1.8
ms
V
OUT
slew
V
max
V
CC
Logic Level Low (Output Disabled)
V
0.35
0.82
1.96
3.40
0.58
1.4
0.81
1.95
3.30
5.2
V
V
in−low
in−mid
in−high
in−max
in−low
Logic Level Mid (Thermal Fault, Output Disabled)
Logic Level High (Output Enabled)
High State Maximum Voltage
V
V
V
2.64
4.30
−17
V
V
Logic Low Sink Current (V
= 0 V)
I
−25
1.0
mA
mA
Units
enable
Logic High Leakage Current for External Switch (V
= 3.3 V)
I
in−leak
enable
Maximum Fanout for Fault Signal (Total number of chips that can be
connected to this pin for simultaneous shutdown)
Fan
3.0
TOTAL DEVICE
Bias Current (Operational)
Bias Current (Shutdown)
I
I
1. 8
1.0
2.5
7.6
mA
mA
V
Bias
Bias
Minimum Operating Voltage (Notes 5 and 8)
V
min
4. Pulse test: Pulse width 300 us, duty cycle 2%.
5. Verified by design.
6. V
only in MN1 & MN2 versions.
Clamp
7. Refer to explanation of short circuit and overload conditions in application note AND8140.
8. Device will shut down prior to reaching this level based on actual UVLO trip point.
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3
NIS5132 Series
60
50
40
50_C
25_C
30
20
10
0
80_C
0.1
1
10
100
1000
10000 100000
TIME (ms)
Figure 2. Power Dissipation vs. Thermal Trip Time
11
10
9
V
CC
+12 V
8
7
6
SOURCE
NIS5132
R
S
4
I
LIMIT
3
ENABLE
GND
dv/dt
2
LOAD
1
ENABLE
GND
Figure 3. Application Circuit with Direct Current Sensing
11
10
9
V
CC
+12 V
8
7
6
SOURCE
NIS5132
R
S
4
I
LIMIT
3
ENABLE
GND
dv/dt
2
LOAD
1
ENABLE
GND
Figure 4. Application Circuit with Kelvin Current Sensing
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4
NIS5132 Series
V
CC
V
CC
SOURCE
SOURCE
R
S
NIS5135
NIS5132
I
LIMIT
I
LIMIT
ENABLE
ENABLE
GND
dv/dt
dv/dt
GND
LOAD
LOAD
ENABLE
Figure 5. Common Thermal Shutdown
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5
NIS5132 Series
0.86
0.84
0.82
0.8
9
8.8
8.6
8.4
8.2
8
0.78
0.76
0.74
0.72
7.8
7.6
7.4
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. UVLO Turn−On
Figure 7. UVLO Hysteresis
15.3
15.2
15.1
15
1.05
1
0.95
0.9
14.9
14.8
14.7
14.6
14.5
0.85
−50
−25
0
25
50
75
100
125
150
−50
−25
0
25
50
75
100
125 150
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. Output Clamping Voltage
(MN1 & MN2 only)
Figure 9. Output Voltage dv/dt Rate
1600
1200
800
400
0
0.5
0.6
0.7
0.8
FORWARD VOLTAGE (V)
Figure 10. Input Transient Response
Figure 11. Body Diode Forward
Characteristics
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6
NIS5132 Series
9
8
7
6
5
4
10
OL
−40°C
0°C
SC
25°C
1
50°C
85°C
0.1
0
0.5
1
1.5
2
10
100
R (W)
limit
1000
2
COPPER AREA (in )
Figure 12. Thermal Limit vs. Copper Area and
Ambient Temperature
Figure 13. Current Limit vs. Rsense for Direct
Current Sensing
4.5
4
10
OL
SC
OL
3.5
3
2.5
2
SC
1
1.5
1
0.5
0
−50
0.1
0
50
100
150
1
10
100
TEMPERATURE (°C)
R
(W)
sense
Figure 14. Direct Current Sensing Levels vs.
Figure 15. Current Limit vs. Rsense for Kelvin
Current Sensing
Temperature for 27 W Sense Resistor
6
5.5
5
4
3.5
3
OL
OL
2.5
2
4.5
4
SC
SC
1.5
1
3.5
3
−40
−20
0
20
40
60
80
100
−40
−20
0
20
40
60
80
100
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Kelvin Current Sensing Levels vs.
Figure 17. Kelvin Current Sensing Levels vs.
Temperature for 15 W Sense Resistor
Temperature for 33 W Sense Resistor
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7
NIS5132 Series
55
50
45
40
7.0
9.0
11
13
15
V
CC
(V)
Figure 18. On Resistance vs. VCC
APPLICATION INFORMATION
Basic Operation
actively limiting the current and the gate is at an intermediate
level. For a more detailed description of this circuit please
refer to application note AND8140.
This device is a self−protected, resettable, electronic fuse.
It contains circuits to monitor the input voltage, output
voltage, output current and die temperature.
On application of the input voltage, the device will apply
the input voltage to the load based on the restrictions of the
controlling circuits. The dv/dt of the output voltage will be
controlled by the internal dv/dt circuit. The output voltage
will slew from 0 V to the rated output voltage in 2 ms, unless
additional capacitance is added to the dv/dt pin.
The device will remain on as long as the temperature does
not exceed the 175°C limit that is programmed into the chip.
The current limit circuit does not shut down the part but will
reduce the conductivity of the FET to maintain a constant
current at the internally set current limit level. The input
overvoltage clamp also does not shutdown the part, but will
limit the output voltage to 15 V in the event that the input
exceeds that level.
There are two methods of biasing the current limit circuit
for this device. They are shown in the two application
figures. Direct current sensing connects the sense resistor
between the current limit pin and the load. This method
includes the bond wire resistance in the current limit circuit.
This resistance has an impact on the current limit levels for
a given resistor and may vary slightly depending on the
impedance between the sense resistor and the source pins.
The on resistance of the device will be slightly lower in this
configuration since all five source pins are connected in
parallel and therefore, the effective bond wire resistance is
one fifth of the resistance for any given pin.
The other method is Kelvin sensing. This method uses one
of the source pins as the connection for the current sense
resistor. This connection senses the voltage on the die and
therefore any bond wire resistance and external impedance
on the board have no effect on the current limit levels. In this
configuration the on resistance is slightly increased relative
to the direct sense method since only for of the source pins
are used for power.
An internal charge pump provides bias for the gate voltage
of the internal n−channel power FET and also for the current
limit circuit. The remainder of the control circuitry operates
between the input voltage (V ) and ground.
CC
Current Limit
The current limit circuit uses a SENSEFET along with a
reference and amplifier to control the peak current in the
device. The SENSEFET allows for a small fraction of the
load current to be measured, which has the advantage of
reducing the losses in the sense resistor as well as increasing
the value and decreasing the power rating of the sense
resistor. Sense resistors are typically in the tens of ohms
range with power ratings of several milliwatts making them
very inexpensive chip resistors.
The current limit circuit has two limiting values, one for
overload events which are defined as the mode of operation
in which the gate is high and the FET is fully enhanced. The
short circuit mode of operation occurs when the device is
Overvoltage Clamp (MN1 & MN2 Versions)
The overvoltage clamp consists of an amplifier and
reference. It monitors the output voltage and if the input
voltage exceeds 15 V, the gate drive of the main FET is
reduced to limit the output. This is intended to allow
operation through transients while protecting the load. If an
overvoltage condition exists for many seconds, the device
may overheat due to the voltage drop across the FET
combined with the load current. In this event, the thermal
protection circuit would shut down the device.
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8
NIS5132 Series
Undervoltage Lockout
When this pin is low, the output of the fuse will be turned off.
When this pin is high the output of the fuse will be
turned−on. If a thermal fault occurs, this pin will be pulled
low to an intermediate level by an internal circuit.
To use as a simple enable pin, an open drain or open
collector device should be connected to this pin. Due to its
tri−state operation, it should not be connected to any type of
logic with an internal pullup device.
If the chip shuts down due to the die temperature reaching
its thermal limit, this pin will be pulled down to an
intermediate level. This signal can be monitored by an
external circuit to communicate that a thermal shutdown has
occurred. If this pin is tied to another device in this family
(NIS5132 or NIS5135), a thermal shutdown of one device
will cause both devices to disable their outputs. Both devices
will turn on once the fault is removed for the auto−retry
devices.
For the latching thermal device, the outputs will be
enabled after the enable pin has been pulled to ground with
an external switch and then allowed to go high or after the
input power has been recycled. For the auto retry devices,
both devices will restart as soon as the die temperature of the
device in shutdown has been reduced to the lower thermal
limit. The thermal options are listed in the ordering table.
The undervoltage lockout circuit uses a comparator with
hysteresis to monitor the input voltage. If the input voltage
drops below the specified level, the output switch will be
switched to a high impedance state.
dv/dt Circuit
The dv/dt circuit brings the output voltage up under a
linear, controlled rate regardless of the load impedance
characteristics. An internal ramp generator creates a linear
ramp, and a control circuit forces the output voltage to
follow that ramp, scaled by a factor.
The default ramp time is approximately 2 ms. This can be
modified by adding an external capacitor at the dv/dt pin.
This pin includes an internal current source of
approximately 85 nA. Since the current level is very low, it
is important to use a ceramic cap or other low leakage
capacitor. Aluminum electrolytic capacitors are not
recommended for this circuit.
The ramp time from 0 to the nominal output voltage can
be determined by the following equation, where t is in
seconds:
ǒ
Ǔ
t0*12 + 24e6 @ 50 pF ) Cext
t0−12
Cext
+
* 50 pF
Thermal Protection
24e6
The NIS5132 includes an internal temperature sensing
circuit that senses the temperature on the die of the power
FET. If the temperature reaches 175°C, the device will shut
down, and remove power from the load. Output power can
be restored by either recycling the input power or toggling
the enable pin. Power will automatically be reapplied to the
load for auto−retry devices once the die temperature has
been reduced by 45°C.
Where:
C is in Farads
t is in seconds
Any time that the unit shuts down due to a fault, enable
shut−down, or recycling of input power, the timing capacitor
will be discharged and the output voltage will ramp from 0
at turn on.
The thermal limit has been set high intentionally, to
increase the trip time during high power transient events. It
is not recommended to operate this device above 150°C for
extended periods of time.
Enable/Fault
The Enable/Fault pin is a multi−function, bidirectional pin
that can control the output of the chip as well as send
information to other devices regarding the state of the chip.
Figure 19. Fault/Enable Signal Levels
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9
NIS5132 Series
4.3 V
Startup
Blanking*
12 mA
Enable SD
2.64 V
0.58 V
+
−
En/Fault
1.4 V
−
+
Thermal Reset
SD
Thermal
Shutdown
Thermal SD
(*MN1 and MN2 versions)
Figure 20. Enable/Fault Simplified Circuit
ORDERING INFORMATION
Device
†
Features
Thermal Latching with V
Package
Shipping
NIS5132MN1TXG
DFN10
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
Clamp
NIS5132MN2TXG
NIS5132MN3TXG
Thermal Auto−Retry with V
DFN10
(Pb−Free)
Clamp
Thermal Latching without V
DFN10
(Pb−Free)
Clamp
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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10
NIS5132 Series
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE B
EDGE OF PACKAGE
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
L1
E
DETAIL A
Bottom View
PIN 1
(Optional)
REFERENCE
EXPOSED Cu
2X
0.15
C
MOLD CMPD
TOP VIEW
MILLIMETERS
2X
0.15
C
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
A3
(A3)
A3
b
D
0.20 REF
0.18
3.00 BSC
DETAIL B
0.10
0.08
C
C
0.30
A1
A
D2 2.40
2.60
DETAIL B
Side View
(Optional)
E
3.00 BSC
SEATING
PLANE
10X
E2 1.70
1.90
e
K
L
0.50 BSC
0.19 TYP
0.35
SIDE VIEW
A1
C
0.45
0.03
L1 0.00
D2
e
DETAIL A
SOLDERING FOOTPRINT*
10X
L
1
5
2.6016
E2
10X
K
1.8508
3.3048
2.1746
10
6
10X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
Sales Representative
NIS5132/D
相关型号：
NIS5135MN1T1G
1-CHANNEL POWER SUPPLY SUPPORT CKT, DSO10, 3 X 3 MM, 0.50 MM PITCH, LEAD FREE, DFN-10
ONSEMI
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