NCV4264-2CST50T3G [ONSEMI]

Low IQ Low Dropout Linear Regulator;
NCV4264-2CST50T3G
型号: NCV4264-2CST50T3G
厂家: ONSEMI    ONSEMI
描述:

Low IQ Low Dropout Linear Regulator

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中文:  中文翻译
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NCV4264-2C  
Low IQ Low Dropout  
Linear Regulator  
The NCV4264−2C is a low quiescent current consumption LDO  
regulator. Its output stage supplies 100 mA with 2.0% output  
voltage accuracy.  
Maximum dropout voltage is 500 mV at 100 mA load current.  
It is internally protected against 45 V input transients, input supply  
reversal, output overcurrent faults, and excess die temperature. No  
external components are required to enable these features.  
www.onsemi.com  
MARKING  
DIAGRAM  
Features  
TAB  
3.3 V and 5.0 V Fixed Output  
SOT−223  
ST SUFFIX  
CASE 318E  
AYW  
642CxG  
G
"2.0% Output Accuracy, Over Full Temperature Range  
33 mA Typical Quiescent Current  
1
2
3
1
500 mV Maximum Dropout Voltage at 100 mA Load Current  
Wide Input Voltage Operating Range of 4.5 V to 45 V  
Internal Fault Protection  
−42 V Reverse Voltage  
Short Circuit/Overcurrent  
Thermal Overload  
x
= 5 (5.0 V Version)  
= 3 (3.3 V Version)  
= Assembly Location  
= Year  
= Work Week  
= Pb−Free Package  
A
Y
W
G
(Note: Microdot may be in either location)  
NCV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AEC−Q100  
Qualified and PPAP Capable  
PIN CONNECTIONS  
This is a Pb−Free Device  
TAB  
1
V
IN  
GND V  
OUT  
(Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
October, 2015 − Rev. 1  
NCV4264−2C/D  
NCV4264−2C  
IN  
OUT  
1.3 V  
Reference  
+
Error  
Amp  
-
Thermal  
Shutdown  
GND  
Figure 1. Block Diagram  
PIN FUNCTION DESCRIPTION  
Pin No.  
Symbol  
Function  
1
2
V
Unregulated input voltage; 4.5 V to 45 V.  
Ground; substrate.  
IN  
GND  
3
V
Regulated output voltage; collector of the internal PNP pass transistor.  
Ground; substrate and best thermal connection to the die.  
OUT  
TAB  
GND  
OPERATING RANGE  
Rating  
Symbol  
Min  
Max  
Unit  
V
IN  
4.5  
+45  
V
V , DC Input Operating Voltage (Note 3)  
IN  
Junction Temperature Operating Range  
T
J
−40  
+150  
°C  
Functionaloperation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the  
RecommendedOperating Ranges limits may affect device reliability.  
MAXIMUM RATINGS  
Rating  
Symbol  
Min  
Max  
Unit  
V
IN  
−42  
+45  
V
V , DC Input Voltage  
IN  
V
, DC Voltage  
V
−0.3  
−55  
+32  
V
°C  
OUT  
OUT  
Storage Temperature  
T
+150  
stg  
Moisture Sensitivity Level  
MSL  
3
ESD Capability, Human Body Model (Note 1)  
ESD Capability, Machine Model (Note 1)  
V
4000  
200  
V
ESDHB  
V
V
ESDMIM  
Lead Temperature Soldering  
Reflow (SMD Styles Only), Lead Free (Note 2)  
T
sld  
°C  
265 pk  
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality  
should not be assumed, damage may occur and reliability may be affected.  
1. This device series incorporates ESD protection and is tested by the following methods:  
ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C)  
ESD MM tested per AEC−Q100−003 (EIA/JESD22−A 115C)  
2. Lead Free, 60 sec – 150 sec above 217°C, 40 sec max at peak.  
3. See specific conditions for DC operating input voltage lower than 4.5 V in ELECTRICAL CHARACTERISTICS table at page 3  
www.onsemi.com  
2
 
NCV4264−2C  
THERMAL RESISTANCE  
Parameter  
Symbol  
Min  
Max  
109 (Note 4)  
10.9  
Unit  
Junction−to−Ambient  
SOT−223  
SOT−223  
R
q
JA  
°C/W  
Junction−to−Tab (psi−JL4)  
Y
JL4  
ELECTRICAL CHARACTERISTICS (V = 13.5 V, T = −40°C to +150°C, unless otherwise noted.)  
IN  
J
Characteristic  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Unit  
Output Voltage  
5.0 V Version  
V
V
V
4.900  
5.000  
5.100  
V
OUT  
OUT  
OUT  
5.0 mA v I v 100 mA (Note 5)  
OUT  
6.0 V v V v 28 V  
IN  
Output Voltage  
3.3 V Version  
3.234  
3.300  
3.366  
V
5.0 mA v I  
v 100 mA (Note 5)  
OUT  
4.5 V v V v 28 V  
IN  
Output Voltage  
3.3 V Version  
3.234  
−30  
3.300  
5.0  
3.366  
+30  
V
I
= 5 mA, V = 4 V (Note 7)  
IN  
OUT  
Line Regulation  
5.0 V Version  
DV  
DV  
vs. V  
vs. V  
I = 5.0 mA  
OUT  
mV  
mV  
OUT  
OUT  
OUT  
IN  
6.0 V v V v 28 V  
IN  
Line Regulation  
3.3 V Version  
I
= 5.0 mA  
−30  
5.0  
+30  
IN  
OUT  
4.5 V v V v 28 V  
IN  
Load Regulation  
DV  
vs. I  
1.0 mA v I  
v 100 mA (Note 5)  
−40  
5.0  
+40  
500  
mV  
mV  
mA  
OUT  
OUT  
Dropout Voltage − 5.0 V Version  
Quiescent Current  
V
−V  
IN OUT  
I
= 100 mA (Notes 5 & 6)  
270  
OUT  
I
q
I
= 100 mA  
OUT  
T = 25°C  
33  
33  
33  
55  
60  
70  
J
T = −40°C to +85°C  
J
J
T = −40°C to 150°C  
Active Ground Current  
Power Supply Rejection  
PROTECTION  
I
I
= 50 mA (Note 5)  
1.5  
67  
4.0  
mA  
dB  
G(ON)  
OUT  
PSRR  
V
= 0.5 V , F = 100 Hz  
RIPPLE P−P  
Current Limit  
I
V
OUT  
V
OUT  
= 4.5 V (5.0 V Version) (Note 5)  
= 3.0 V (3.3 V Version) (Note 5)  
150  
150  
500  
500  
mA  
OUT(LIM)  
Short Circuit Current Limit  
I
V
OUT  
= 0 V (Note 5)  
(Note 7)  
40  
500  
200  
mA  
OUT(SC)  
Thermal Shutdown Threshold  
T
TSD  
150  
°C  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performancemay not be indicated by the Electrical Characteristics if operated under different conditions.  
2
4. 1 oz., 100 mm copper area.  
5. Use pulse loading to limit power dissipation.  
6. Dropout voltage = (V –V  
), measured when the output voltage has dropped 100 mV relative to the nominal value obtained with  
IN OUT  
V
IN  
= 13.5 V.  
7. Not tested in production. Limits are guaranteed by design.  
4.5−45 V  
Input  
V
in  
V
out  
1
3
Output  
4264−2C  
2
C
IN  
C
10 mF  
OUT  
100 nF  
GND  
Figure 2. Applications Circuit  
www.onsemi.com  
3
 
NCV4264−2C  
TYPICAL CHARACTERISTIC CURVES − 5 V Version  
100  
Unstable Region  
10  
1
Stable Region  
0.1  
C
OUT  
10 mF  
0.01  
0
10 20 30 40 50 60 70 80 90 100  
, OUTPUT CURRENT (mA)  
I
OUT  
Figure 3. Output Stability with Output  
Capacitor ESR (5.0 V Version)  
6
5
4
3
2
5.10  
5.05  
5.00  
R = 50 W  
L
T = 25°C  
J
4.95  
4.90  
V
= 13.5 V  
IN  
1
0
R = 1 kW  
L
−40  
0
40  
80  
120  
160  
0
1
2
3
4
5
6
7
8
9
10  
T , JUNCTION TEMPERATURE (°C)  
J
V , INPUT VOLTAGE (V)  
IN  
Figure 4. Output Voltage vs. Junction  
Temperature (5.0 V Version)  
Figure 5. Output Voltage vs. Input Voltage  
(5.0 V Version)  
400  
350  
300  
250  
200  
150  
100  
350  
300  
250  
200  
T = 125°C  
J
T = 25°C  
J
T = −40°C  
J
150  
100  
V
= 0 V  
OUT  
T = 25°C  
J
50  
0
50  
0
0
25  
50  
75  
100  
125  
150  
0
5
10  
15  
20  
25  
30  
35  
40 45  
I , OUTPUT CURRENT (mA)  
OUT  
V , INPUT VOLTAGE (V)  
IN  
Figure 6. Dropout Voltage vs. Output Current  
(only 5.0 V Version)  
Figure 7. Maximum Output Current vs. Input  
Voltage (5.0 V Version)  
www.onsemi.com  
4
NCV4264−2C  
TYPICAL CHARACTERISTIC CURVES − 5 V Version  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
100  
90  
V
= 13.5 V  
IN  
80  
70  
60  
50  
40  
30  
20  
V
= 13.5 V  
IN  
T = 25°C  
J
T = 25°C  
J
0.5  
0
10  
0
0
50  
100  
150  
0
1
2
3
4
5
I , OUTPUT CURRENT (mA)  
OUT  
I , OUTPUT CURRENT (mA)  
OUT  
Figure 8. Quiescent Current vs. Output Current  
(5.0 V Version) (High Load)  
Figure 9. Quiescent Current vs. Output Current  
(5.0 V Version) (Low Load)  
4.0  
3.5  
3.0  
2.5  
T = 25°C  
J
R = 50 W  
2.0  
1.5  
1.0  
L
R = 100 W  
L
0.5  
0
0
5
10  
15  
20  
25  
30  
35  
40  
V , INPUT VOLTAGE (V)  
IN  
Figure 10. Quiescent Current vs. Input Voltage  
(5.0 V Version)  
www.onsemi.com  
5
NCV4264−2C  
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version  
100  
Unstable Region  
10  
1
Stable Region  
0.1  
C
OUT  
10 mF  
0.01  
0
10 20 30 40  
50 60 70 80 90 100  
I , OUTPUT CURRENT (mA)  
OUT  
Figure 11. Output Stability with Output  
Capacitor ESR (3.3 V Version)  
3.36  
3.34  
3.32  
3.30  
4
3
2
3.28  
R = 33 W  
T = 25°C  
J
L
1
0
V
= 13.5 V  
IN  
R = 660 W  
3.26  
3.24  
L
−40  
0
40  
80  
120  
160  
0
1
2
3
4
5
6
7
8
9
10  
T , JUNCTION TEMPERATURE (°C)  
J
V , INPUT VOLTAGE (V)  
IN  
Figure 12. Output Voltage vs. Junction  
Temperature (3.3 V Version)  
Figure 13. Output Voltage vs. Input Voltage  
(3.3 V Version)  
350  
300  
250  
200  
150  
100  
2.0  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
T = 25°C  
J
R = 50 W  
L
V
= 0 V  
OUT  
R = 100 W  
L
T = 25°C  
J
50  
0
0.2  
0
0
5
10  
15  
20  
25  
30  
35  
40  
45  
0
5
10  
15  
20  
25  
30  
35  
40  
V , INPUT VOLTAGE (V)  
IN  
V , INPUT VOLTAGE (V)  
IN  
Figure 14. Maximum Output Current vs. Input  
Voltage (3.3 V Version)  
Figure 15. Quiescent Current vs. Input Voltage  
(3.3 V Version)  
www.onsemi.com  
6
NCV4264−2C  
TYPICAL CHARACTERISTIC CURVES − 3.3 V Version  
4.0  
3.5  
100  
90  
80  
70  
60  
50  
40  
30  
20  
3.0  
2.5  
2.0  
1.5  
1.0  
V
IN  
= 13.5 V  
V
= 13.5 V  
IN  
0.5  
0
T = 25°C  
J
10  
0
T = 25°C  
J
0
50  
100  
150  
0
1
2
3
4
5
I , OUTPUT CURRENT (mA)  
OUT  
I , OUTPUT CURRENT (mA)  
OUT  
Figure 16. Quiescent Current vs. Output  
Current (3.3 V Version) (High Load)  
Figure 17. Quiescent Current vs. Output  
Current (3.3 V Version) (Low Load)  
www.onsemi.com  
7
NCV4264−2C  
Circuit Description  
Calculating Power Dissipation in a Single Output  
Linear Regulator  
The maximum power dissipation for a single output  
regulator (Figure 3) is:  
The NCV4264−2C is is a low quiescent current  
consumption LDO regulator. Its output stage supplies  
100 mA with $2.0% output voltage accuracy.  
Maximum dropout voltage is 500 mV at 100 mA load  
current. It is internally protected against 45 V input  
transients, input supply reversal, output overcurrent faults,  
and excess die temperature. No external components are  
required to enable these features.  
ƪ
ƫ
* I  
P
+ V  
−V  
) V * I  
IN(max) q  
D(max)  
IN(max) OUT(min) OUT(max)  
(eq. 1)  
Where:  
V
V
is the maximum input voltage,  
IN(max)  
is the minimum output voltage,  
OUT(min)  
Regulator  
I
is the maximum output current for the  
OUT(max)  
The error amplifier compares the reference voltage to a  
application, and I is the quiescent current the regulator  
q
sample of the output voltage (V ) and drives the base of  
OUT  
consumes at I  
. Once the value of P  
is known,  
OUT(max)  
D(max)  
a PNP series pass transistor by a buffer. The reference is a  
bandgap design to give it a temperature−stable output.  
Saturation control of the PNP is a function of the load  
current and input voltage. Oversaturation of the output  
power device is prevented, and quiescent current in the  
ground pin is minimized.  
the maximum permissible value of R  
can be calculated:  
JA  
q
(
)
150° C * T  
A
(eq. 2)  
P
qJA  
+
P
D
The value of R  
can then be compared with those in the  
JA  
q
package section of the data sheet. Those packages with  
’s less than the calculated value in Equation 2 will  
R
JA  
q
keep the die temperature below 150°C. In some cases, none  
of the packages will be sufficient to dissipate the heat  
generated by the IC, and an external heat sink will be  
required. The current flow and voltages are shown in the  
Measurement Circuit Diagram.  
Regulator Stability Considerations  
The input capacitor C in Figure 2 is necessary for  
IN  
compensating input line reactance. Possible oscillations  
caused by input inductance and input capacitance can be  
damped by using a resistor of approximately 1 W in series  
with C . The output or compensation capacitor, C  
IN  
OUT  
Heat Sinks  
helps determine three main characteristics of a linear  
regulator: startup delay, load transient response and loop  
stability. Tantalum, aluminum electrolytic, film, or  
ceramic capacitors are all acceptable solutions, however,  
attention must be paid to ESR constraints. The capacitor  
manufacturers data sheet usually provides this  
A heat sink effectively increases the surface area of the  
package to improve the flow of heat away from the IC and  
into the surrounding air. Each material in the heat flow path  
between the IC and the outside environment will have a  
thermal resistance. Like series electrical resistances, these  
resistances are summed to determine the value of R  
:
JA  
q
information. The value for the output capacitor C  
OUT  
R
qJA  
+ R  
qJC  
) R  
qCS  
) R  
qSA  
(eq. 3)  
shown in Figure 2 should work for most applications;  
however, it is not necessarily the optimized solution.  
Where:  
Stability is guaranteed at values of C  
w 10 mF, with an  
OUT  
R
R
R
= the junction−to−case thermal resistance,  
= the case−to−heat sink thermal resistance, and  
= the heat sink−to−ambient thermal resistance.  
JC  
q
q
q
ESR v 3.5 W for the 5.0 V Version with an ESR v 3.35 W  
for the 3.3 V Version within the operating temperature  
range. Actual limits are shown in a graph in the Typical  
Performance Characteristics section.  
CS  
SA  
R
appears in the package section of the data sheet.  
JC  
q
Like R , it too is a function of package type. R  
and  
CS  
JA  
q
q
R
are functions of the package type, heatsink and the  
SA  
q
interface between them. These values appear in data sheets  
of heatsink manufacturers.  
Thermal, mounting, and heat sinking are discussed in the  
ON Semiconductor application note AN1040/D, available  
on the ON Semiconductor Website.  
www.onsemi.com  
8
NCV4264−2C  
180  
160  
140  
120  
100  
80  
1 oz  
2 oz  
60  
40  
0
100  
200  
300  
400  
500  
600  
700  
2
COPPER HEAT SPREADER AREA (mm )  
Figure 18. RqJA vs. Copper Spreader Area  
1000  
100  
10  
2
Cu Area 100 mm , 1 oz  
1
0.1  
0.000001 0.00001  
0.0001  
0.001  
0.01  
0.1  
1
10  
100  
1000  
PULSE TIME (sec)  
Figure 19. Single Pulse Heating Curve  
ORDERING INFORMATION  
Device  
Package  
Shipping†  
NCV4264−2CST50T3G  
SOT−223  
(Pb−Free)  
4000 / Tape & Reel  
NCV4264−2CST33T3G  
SOT−223  
(Pb−Free)  
4000 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
www.onsemi.com  
9
NCV4264−2C  
PACKAGE DIMENSIONS  
SOT−223 (TO−261)  
CASE 318E−04  
ISSUE N  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.  
2. CONTROLLING DIMENSION: INCH.  
D
b1  
MILLIMETERS  
INCHES  
NOM  
0.064  
0.002  
0.030  
0.121  
0.012  
0.256  
0.138  
0.091  
0.037  
−−−  
DIM  
A
A1  
b
b1  
c
D
E
e
e1  
L
L1  
MIN  
1.50  
0.02  
0.60  
2.90  
0.24  
6.30  
3.30  
2.20  
0.85  
0.20  
1.50  
6.70  
NOM  
1.63  
0.06  
0.75  
3.06  
0.29  
6.50  
3.50  
2.30  
0.94  
−−−  
1.75  
7.00  
MAX  
1.75  
0.10  
0.89  
3.20  
0.35  
6.70  
3.70  
2.40  
1.05  
−−−  
MIN  
MAX  
0.068  
0.004  
0.035  
0.126  
0.014  
0.263  
0.145  
0.094  
0.041  
−−−  
0.060  
0.001  
0.024  
0.115  
0.009  
0.249  
0.130  
0.087  
0.033  
0.008  
0.060  
0.264  
4
2
H
E
E
1
3
b
e1  
e
2.00  
7.30  
0.069  
0.276  
0.078  
0.287  
H
E
q
C
q
A
0°  
10°  
0°  
10°  
0.08 (0003)  
A1  
L
L1  
SOLDERING FOOTPRINT  
3.8  
0.15  
2.0  
0.079  
6.3  
0.248  
2.3  
0.091  
2.3  
0.091  
2.0  
0.079  
mm  
inches  
1.5  
0.059  
ǒ
Ǔ
SCALE 6:1  
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NCV4264−2C/D  

相关型号:

NCV4264-2C_15

Low IQ Low Dropout Linear Regulator
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NCV4264-2D33R2G

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NCV4264-2ST33T3G

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NCV4264-2ST50T3G

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NCV4264-2_17

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NCV4264.2CST33T3G

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NCV4264.2CST50T3G

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NCV4264ST50T3G

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NCV4266

150 mA Low-Dropout Voltage Regulator with Enable
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NCV4266-2C

150 mA Low Iq, Low-Dropout Voltage Regulator with Enable
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NCV4266-2CST33T3G

150 mA Low Iq, Low-Dropout Voltage Regulator with Enable
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NCV4266-2CST50T3G

150 mA Low Iq, Low-Dropout Voltage Regulator with Enable
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