NCP360SNAIT1G [ONSEMI]
过电压保护电路，USB 正向，带内部 PMOS FET 和状态标志;
| 型号： | NCP360SNAIT1G |
| 厂家： | 
ONSEMI |
| 描述： | 过电压保护电路，USB 正向，带内部 PMOS FET 和状态标志 驱动 光电二极管 接口集成电路 外围驱动器 驱动程序和接口 |
| 文件： | 总10页 (文件大小：351K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP360
USB Positive Overvoltage
Protection Controller with
Internal PMOS FET and
Status FLAG
NCP360 is able to disconnect the systems from its output pin in
case wrong VBUS operating conditions is detected. The system is
positive over-voltage protected up to +20ꢀV.
Thanks to this device using internal PMOS FET, no external
device is necessary, reducing the system cost and the PCB area of the
application board.
NCP360 is able to instantaneously disconnect the output from the
input if the input voltage exceeds the overvoltage threshold (OVLO).
NCP360 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
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MARKING
DIAGRAMS
UDFN6
1
ZD M
G
TBD SUFFIX
CASE 517AB
M = Date Code
TSOP-5
TBD SUFFIX
CASE 483
In addition, the device has ESD-protected input (15ꢀkV Air) when
bypassed with a 1ꢀmF or larger capacitor.
SYAAYWG
5
G
1
1
Features
A
Y
= Assembly Location
= Year
•ꢁVery Fast Protection, Up to 20ꢀV, with 25 mA Current Consumption
•ꢁOn-chip PMOS Transistor
•ꢁOvervoltage Lockout (OVLO)
•ꢁUndervoltage Lockout (UVLO)
•ꢁAlert FLAG Output
W = Work Week
= Pb-Free Package
G
(Note: Microdot may be in either location)
•ꢁEN Enable Pin
•ꢁThermal Shutdown
ORDERING INFORMATION
†
Device
Package
Shipping
3000/Tape & Reel
•ꢁCompliance to IEC61000-4-2 (Level 4)
NCP360MUTBG
NCP360MUTXG
NCP360SNT1G
UDFN6
(Pb-Free)
ꢂ8ꢀkV (Contact)
ꢂ15ꢀkV (Air)
UDFN6 10000/Tape & Reel
(Pb-Free)
•ꢁESD Ratings: Machine Model = B
ESD Ratings: Human Body Model = 3
•ꢁ6 Lead UDFN 2x2 mm Package
•ꢁ5 Lead TSOP 3x3 mm Package
•ꢁThese are Pb-Free Devices
TSOP-5
(Pb-Free)
3000/Tape & Reel
NCP360SNT3G
TSOP-5 10000/Tape & Reel
(Pb-Free)
Applications
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
•ꢁUSB Devices
•ꢁMobile Phones
•ꢁPeripheral
•ꢁPersonal Digital Applications
•ꢁMP3 Players
©ꢀ Semiconductor Components Industries, LLC, 2007
May, 2007 - Rev. 1
1
Publication Order Number:
NCP360/D
NCP360
PIN CONNECTIONS
OUT
IN
GND
EN
1
2
3
5
4
1
2
3
EN
GND
IN
6
5
4
FLAG
OUT
OUT
PAD1
FLAG
TSOP-5
UDFN6
(Top Views)
PIN FUNCTION DESCRIPTION (UDFN6 Package)
Pin No.
Name
Type
Description
1
EN
INPUT
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection.
2
3
GND
IN
POWER Ground
POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
4, 5
OUT
FLAG
PAD1
OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins.
The two OUT pins must be hardwired to common supply.
6
-
OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to V must be added.
CC
POWER Exposed Pad. Can be connected to GND or isolated plane. Must be used to thermal dissipation.
PIN FUNCTION DESCRIPTION (TSOP-5 Package)
Pin No.
Name
Type
Description
1
IN
POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
2
3
GND
EN
POWER Ground
INPUT
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection.
4
5
FLAG
OUT
OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to V must be added.
CC
OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin.
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2
NCP360
INPUT
OUTPUT
3
1
4
5
OUT
OUT
IN
FLAG Power
1 mF 25 V X5R 0603
C2
1 mF 25 V X5R 0603
C1
NCP360
R1
1M
6
FLAG
EN
FLAG
GND
J2
2
1
2
FLAG_State
Figure 1. Typical Application Circuit (UDFN Pinout)
OUTPUT
INPUT
(2 out pins in
UDFN package)
Thermal Shutdown
Soft Start
FLAGV
EN
UVLO
OVLO
LDO
V
REF
Figure 2. Functional Block Diagram
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3
NCP360
MAXIMUM RATINGS
Rating
Symbol
Vmin
Value
-0.3
-0.3
21
Unit
V
MinimumVoltage (IN to GND)
in
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Vmin
Vmax
V
V
in
Maximum Voltage (All others to GND)
Maximum Current from Vin to Vout (PMOS)
Thermal Resistance, Junction-to-Air (Note 1)
Vmax
Imax
R
7.0
V
600
mA
°C/W
TSOP-5
UDFN
305
260
q
JA
Operating Ambient Temperature Range
Storage Temperature Range
T
-40 to +85
-65 to +150
150
°C
°C
°C
A
T
stg
Junction Operating Temperature
T
J
ESD Withstand Voltage (IEC 61000-4-2)
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity
MSL
Level 1
-
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. R
is highly dependent on the PCB heat sink area (connected to PAD1, UDFN). See PCB Recommendations.
q
JA
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
4. Compliant with JEDEC Latch-up Test, up to maximum voltage range.
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (-40°C < T < +85°C) and V = +5.0 V. Typical values are T = +25°C, unless otherwise noted.)
A
in
A
Characteristic
Symbol
Conditions
Min
Typ
Max
Unit
Input Voltage Range
V
1.2
2.85
50
20
3.15
90
V
V
in
Undervoltage Lockout Threshold
Uvervoltage Lockout Hysteresis
Overvoltage Lockout Threshold
Overvoltage Lockout Hysteresis
UVLO
UVLO
V
falls down UVLO threshold
3.0
70
in
mV
V
hyst
OVLO
OVLO
V
rises up OVLO threshold
= 5 V, I charge = 500 mA
5.43
50
5.675
100
105
24
5.9
125
200
35
in
mV
mV
mA
mA
mA
mV
nA
V
hyst
V
in
versus V Dopout
out
V
drop
V
in
Supply Quiescent Current
OVLO Supply Current
Output Off State Current
FLAG Output Low Voltage
FLAG Leakage Current
EN Voltage High
Idd
Idd
No Load, V = 5.25 V
in
V
in
= 7 V
50
85
uvlo
I
std
V
in
= 5.25 V, EN = 1.2 V
26
37
Vol
V
in
> OVLO, Sink 1 mA on FLAG pin
FLAG level = 5 V
400
flag
FLAG
5.0
leak
V
ih
V
in
V
in
from 3.3 V to 5.25 V
from 3.3 V to 5.25 V
1.2
EN Voltage Low
V
ol
0.4
V
EN Leakage Current
EN
EN = 5.5 V or GND
170
nA
leak
TIMINGS
Start Up Delay
t
From V > UVLO to V = 0.8xV , See Fig 3
out
4.0
3.0
0.8
15
ms
ms
ms
on
in
in
FLAG going up Delay
Output Turn Off Time
t
From V > UVLO to FLAG = 1.2 V, See Fig 3
in
start
t
off
From V > OVLO to V ≤ 0.3 V, See Fig 4
1.5
in
out
increasing from 5 V to 8 V at 1ꢀV/ms.
V
in
No output capacitor.
Alert Delay
t
From V > OVLO to FLAG ≤ 0.4 V, See Fig 4
1.0
2.0
2.0
ms
ms
stop
in
increasing from 5 V to 8 V at 3ꢀV/ms
V
in
Disable Time
t
From EN 0.4 to 1.2V to V ≤ 0.3 V, See Fig 5
out
dis
V
in
= 4.75 V. No output capacitor.
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
150
30
°C
°C
sd
T
sdhyst
NOTE: Thermal Shutdown parameter has been fully characterized and guaranteed by design.
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4
NCP360
<OVLO
UVLO
OVLO
V
V
in
V
V
in
t
on
t
off
V
in
- R
x I
DS(on)
out
0.8 V
in
V
- (R
I)
DS(on)
out
in
0.3 V
t
start
FLAG
t
stop
FLAG
1.2 V
0.4 V
Figure 3. Start Up Sequence
Figure 4. Shutdown on Over Voltage Detection
EN
1.2 V
EN
V
1.2 V
t
dis
OVLO
V
in
UVLO
out
0.3 V
V
in
- R
x I
DS(on)
3 ms
FLAG
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
CONDITIONS
IN
OUT
V
IN
> OVLO or V < UVLO
IN
Voltage Detection
Figure 7.
CONDITIONS
IN
OUT
UVLO < V < OVLO
IN
Voltage Detection
Figure 8.
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5
NCP360
TYPICAL OPERATING CHARACTERISTICS
Figure 9. Startup
Vin = Ch1, Vout = Ch3
Figure 10. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 11. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 12. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 13. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
Figure 14. Thermal Shutdown
Vin = Ch1, Vout = Ch2, FLAG = Ch3
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6
NCP360
TYPICAL OPERATING CHARACTERISTICS
450
400
350
300
250
200
150
V
= 3.6 V
= 5 V
in
V
in
100
50
0
-50
0
50
TEMPERATURE (°C)
100
150
Figure 15. Direct Output Short Circuit
Figure 16. RDS(on) vs. Temperature
(Load = 500 mA)
180
160
140
120
100
80
125°C
25°C
60
40
20
0
-40 °C
1
3
5
7
9
11 13 15
17 19 21
V , INPUT VOLTAGE (V)
in
Figure 17. Supply Quiescent Current vs. Vin
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7
NCP360
In Operation
EN Input
NCP360 provides overvoltage protection for positive
voltage, up to 20ꢀV. A PMOS FET protects the systems
(i.e.: VBUS) connected on the V pin, against positive
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
out
over-voltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Internal PMOS FET
Undervoltage Lockout (UVLO)
NCP360 includes an internal PMOS FET to protect the
systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
To ensure proper operation under any conditions, the
device has a built-in undervoltage lock out (UVLO)
circuit. During V positive going slope, the output remains
R
, during normal operation, will create low losses on
DSon
in
disconnected from input until V voltage is above 3.2ꢀV
in
V pin, characterized by V versus V dropout. (See
out in out
Figure 16).
nominal. The FLAGV output is pulled to low as long as V
in
does not reach UVLO threshold. This circuit has a 50ꢀmV
hysteresis to provide noise immunity to transient condition.
ESD Tests
NCP360 fully support the IEC61000-4-2, level 4 (Input
pin, 1 mF mounted on board).
V
in
(V)
That means, in Air condition, V has a 15ꢀkV ESD
in
protected input. In Contact condition, V has 8ꢀkV ESD
in
20 V
protected input.
Please refer to Fig 19 to see the IEC 61000-4-2
electrostatic discharge waveform.
OVLO
UVLO
0
V
out
OVLO
UVLO
0
Figure 18. Output Characteristic vs. Vin
Overvoltage Lockout (OVLO)
To protect connected systems on V
pin from
out
overvoltage, the device has a built-in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled until the input voltage exceeds OVLO -
Hysteresis.
FLAG output is tied to low until V is higher than
in
OVLO. This circuit has a 100ꢀmV hysteresis to provide
noise immunity to transient conditions.
Figure 19.
PCB Recommendations
FLAG Output
The NCP360 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
NCP360 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon the OVLO threshold is
exceeded When V level recovers normal condition,
in
FLAG is held high. The pin is an open drain output, thus a
pull up resistor (typically 1 MW- Minimum 10 kW) must
be provided to V . FLAG pin is an open drain output.
battery
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8
NCP360
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB-01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
A
B
E
MILLIMETERS
DIM
A
MIN
0.45
0.00
MAX
0.55
0.05
A1
A3
b
PIN ONE
REFERENCE
0.127 REF
0.25
1.50
0.35
D
2.00 BSC
D2
E
1.70
0.10
C
2X
2.00 BSC
E2
e
0.80
1.00
0.65 BSC
K
0.20
0.25
---
2X
0.10
C
L
0.35
A3
SOLDERING FOOTPRINT*
0.10
C
6X
A
0.47
0.95
6X
6X
0.08
C
A1
0.40
1
SEATING
C
PLANE
D2
4X
e
6X
L
1.70
1
3
E2
0.65
PITCH
2.30
6
4
6X
K
DIMENSIONS: MILLIMETERS
6X
b
0.10
0.05
C
C
A
B
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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9
NCP360
PACKAGE DIMENSIONS
TSOP-5
CASE 483-02
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
NOTE 5
5X
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
C
D
0.90
0.25
1.10
0.50
C
SEATING
PLANE
0.05
G
H
J
K
L
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
M
S
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
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NCP360/D
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