NCP367 [ONSEMI]
Battery Charge Front-End Protection, USB and AC/DC Supply Compliant; 电池充电前端保护，USB和AC / DC>供应标准
| 型号： | NCP367 |
| 厂家： | 
ONSEMI |
| 描述： | Battery Charge Front-End Protection, USB and AC/DC
Supply Compliant |
| 文件： | 总10页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP367
Battery Charge Front-End
Protection, USB and AC/DC
Supply Compliant
NCP367 is a charge path protection device which allows
disconnecting the systems from its output pin in case wrong charging
conditions are detected. The system is positive overvoltage protected
up to +30 V. Thanks to a very low current consumption, the USB
charge is compatible with this integrated component.
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This device uses internal PMOS FET, making external devices
unnecessary, which reduces the system cost and PCB area of the
application board. First, NCP367 is able to instantaneously
disconnect the output from the input if the input voltage exceeds the
overvoltage threshold. Additional overcurrent protection function
allows turning off internal PMOS FET when the charge current
exceeds current limit, which is externally selectable.
1
DFN8
MU SUFFIX
CASE 506BP
MARKING DIAGRAM
The current limit value can be modified with control logic pin to
divide it by internal gain, allowing USB 100 mA/500 mA charging or
USB/Wall adapter charging up to overcurrent threshold. At the same
time, Li ion Battery voltage is continuously monitored, providing
more safety during the charge. Thermal shutdown protection is also
available.
1
XX MG
G
XX = Specific Device Code
M
= Date Code
NCP367 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred as overvoltage (power
supply or battery voltage), overcurrent or thermal event.
G
= Pb−Free Device
(Note: Microdot may be in either location)
In addition, the device has ESD-protected input (15 kV Air) when
bypassed with a 1 mF or larger capacitor.
PIN ASSIGNMENT
GND
FLAG
GS
IN
VBAT
NC
1
2
3
4
8
7
6
5
Features
• Overvoltage Protection Up to + 30 V
• Fast Turn Off Time
• Very Low Current Consumption/USB Compliant
• Li ion Battery Voltage Monitoring
• Overvoltage Lockout (OVLO)
OUT
EN
ILIM
(Top View)
• Undervoltage Lockout (UVLO)
• Overcurrent Protection Externally Adjustable (OCP) up to 2.8 A
• Thermal Shutdown
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 9 of this data sheet.
• Shutdown EN and Gain Input Pins
• Soft−Start to Eliminate Inrush Current
• Alert FLAG Output
Typical Applications
• USB Devices
• Compliance to IEC61000-4-2 (Level 4)
• Mobile Phones
• Peripheral
8 kV (Contact), 15 kV (Air)
• ESD Ratings: Machine Model = B
ESD Ratings: Human Body Model = 2
• 8 Lead DFN 2.2x2 mm Package
• Personal Digital Applications
• MP3 Players
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
October, 2011 − Rev. 2
NCP367O/D
NCP367
NCP367
B+
1
5
6
9
7
2
4
Wall Adapter / USB
IN
OUT
Battery Charger
EN
FLAG
VBAT
ILIM
1 mF
1 mF
GS
GND
8
10 k
100 k
Li+
BATTERY
DCDC
MCU
Figure 1. Typical Application Circuit
VIN/VUSB
OUT
ILIM
GS
Soft−Start
I limit
+
GAIN
VBAT
1/2.75
4.35 V
LDO
Driver
VREF
OVLO
UVLO
Logic
+
Timer
Thermal
Shutdown
FLAG
GND
EN Pin
Figure 2. Functional Block Diagram
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NCP367
PIN FUNCTION DESCRIPTION
Pin
Name
Type
Description
1
IN
POWER Input Voltage Pin. This pin is connected to the power supply: Wall Adapter or USB. A 1 mF low ESR
ceramic capacitor, or larger, must be connected between this pin and GND.
2
V
BAT
INPUT
Li ion Battery voltage sense pin. A serial resistor must be placed between this pin and positive pin of
the battery pack.
3
4
NC
OUTPUT Not Connected
I
OUTPUT Current Limit Pin. This pin provides the reference, based on the internal band−gap voltage reference, to
limit the overcurrent, across internal PMOSFET, from IN to OUT. A 1% tolerance, or better, resistor
shall be used to get the highest accuracy of the Overcurrent Limit.
LIM
5
EN
INPUT
Enable Mode Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case
the output is disconnected from the input. The state of this pin does not have an impact on the fault
detection of the FLAG pin.
6
7
GS
INPUT
Gain Select Pin. When the GS pin is tied to 0 level, the Overcurrent threshold is defined by Ilimit set-
ting. See logic table. When GS pin is tied to high, the Overcurrent threshold is set to Ilimit/GS
FLAG
OUTPUT Fault Indication Pin. This pin allows an external system to detect fault condition. The FLAG pin goes
low when input voltage is below UVLO threshold, exceeds OVLO threshold, charge current from wall
adapter to battery exceeds programmed current limit, Li ion Battery voltage (4.3 V) is exceeded or in-
ternal temperature exceeds thermal shutdown limit. Since the FLAG pin is open drain functionality, an
external pull−up resistor to VBattery must be added (10 kW minimum value).
8
9
GND
OUT
POWER Ground.
OUTPUT Output Voltage Pin. This pin follows IN pin when “no input fault” is detected. The output is disconnected
from the Vin power supply when voltage, current or thermal fault events are detected. A 1 mF low ESR
ceramic capacitor, or larger, must be connected between this pin and GND.
NOTE: Pin out provided for concept purpose only and might change in the final product
MAXIMUM RATINGS
Rating
Symbol
Vmin
Value
−0.3
Unit
V
Minimum Voltage (IN to GND)
in
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Vmin
Vmax
−0.3
V
30
V
in
Maximum Voltage (All others to GND)
Maximum DC Current from Vin to Vout (PMOS)
Thermal Resistance, Junction−to−Air (without PCB area)
Operating Ambient Temperature Range
Storage Temperature Range
Vmax
Imax
R
7.0
V
3.4
A
190
°C/W
°C
°C
°C
q
JA
T
A
−40 to +85
−65 to +150
150
T
stg
Junction Operating Temperature
T
J
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2 (Note 1)
Machine Model (MM) Model = B (Note 2)
Vesd
15 Air, 8.0 Contact
kV
V
V
2000
200
Latchup
LU
Class 1
Level 1
−
−
Moisture Sensitivity
MSL
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
2. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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NCP367
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (−40°C < T < +85°C) and V = +5.0 V. Typical values are T = +25°C, unless otherwise noted.)
A
in
A
Characteristic
Symbol
Conditions
Min
1.2
Typ
Max
28
Unit
V
Input Voltage Range
V
in
Undervoltage Lockout Threshold
UVLO
UVLO
V
in
falls down UVLO threshold
1.75
1.85
80
1.9
100
V
Undervoltage Lockout
Hysteresis
mV
hyst
Overvoltage Lockout Threshold
NCP367DPMUEC
OVLO
V
in
rises up OVLO threshold
V
5.64
5.85
6.60
6.90
5.85
6.07
6.84
7.20
6.05
6.28
7.08
7.50
NCP367DPMUEE
NCP367DPMUEL
NCP367OPMUEO
Overvoltage Lockout Hysteresis
Vin versus Vout Resistance
Supply Quiescent Current
Disable Mode
OVLO
100
50
150
100
130
110
mV
mW
mA
mA
A
hyst
R
DS(on)
V
= 5 V, Enable Mode, Load Connected to V
in
out
Idd
No Load
42
Idd
EN = 1.2 V
40
dis
Overcurrent Threshold
NCP367Dx
I
V
= 5 V, EN = low, Load Connected to V ,,
OCP
in out
R
ilim
= 0 ohms, 1 A/ms, GS = 0.4 V
1.25
2.30
1.51
2.85
1.80
3.40
NCP367Ox
Overcurrent Response
I
1 A/ms, GS = low, I = 1.51 A
5.0
%
reg
lim
Current Limit Gain
NCP367Dx
NCP367Ox
GS
GS = 1.2 V
1.51
2.85
value
Battery Overvoltage Threshold
Battery Overvoltage Hysteresis
OV
OV
0°C to 85°C
0°C to 85°C
4.3
4.35
150
4.4
200
20
V
BAT
100
mV
nA
ms
mV
HYS
V
BAT
V
BAT
Pin Leakage
VBAT
LEAK
Deglitch Time
VBAT
V
BAT
> OV
BAT
0.2
2.0
10
4.0
400
DEG
FLAG Output Low Voltage
Vol
V > OVLO
in
Sink 1 mA on FLAG pin
flag
FLAG Leakage Current
EN Voltage High
FLAG
FLAG level = 5 V
nA
V
leak
V
V
V
from 3.3 V to 5.25 V
from 3.3 V to 5.25 V
1.2
1.2
ih
in
EN Voltage Low
V
0.4
0.4
V
il
in
EN Leakage Current
GS Voltage High
EN
V
EN = 5.5 V or GND
200
200
nA
V
leak
ih
V
in
V
in
from 3.3 V to 5.25 V
from 3.3 V to 5.25 V
GS Voltage Low
V
V
il
GS Leakage Current
GS
EN = 5.5 V or GND
nA
leak
TIMINGS
Start Up Delay
t
From V > UVLO to V = 0.8xV
in
15
15
15
1.2
30
30
45
45
ms
ms
ms
ms
ms
on
in
out
FLAG going up Delay
Rearming Delay
t
From V > 0.2xV to FLAG = 1.2 V
start
out
in
t
OCP Active
30
45
REARM
Overcurrent Regulation Time
Output Turn Off Time
t
OCP Active
1.8
1.5
3.0
5.0
REG
t
off
From V > OVLO to V ≤ 0.3 V, V increasing
in out in
from 5 V to 8 V at 3 V/ms.
Alert Delay
t
From V > OVLO to FLAG ≤ 0.4 V, (see Figure 14)
1.5
ms
stop
in
V
increasing from 5 V to 8 V at 3 V/ms
in
Disable Time
t
From EN 0.4 to 1.2 V to V ≤ 0.3 V
3.0
150
30
ms
°C
°C
dis
out
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
sd
Tsd
hyst
NOTE: Electrical parameters are guaranteed by correlation across the full range of temperature.
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NCP367
TYPICAL OPERATING CHARACTERISTICS
V
in
t
off
V
out
V
in
V
in
t
stop
t
on
/FL
A
G
t
start
/FLAG
Figure 3. Hot Plug−in from 0 to 5 V,
Figure 4. Overvoltage from 5 to 8 V,
toff and tstop
ton and tstart
V
in
t
on
V
out
V
in
t
start
/Flag
V
/Flag
out
Figure 5. Retrieve Normal Operation,
ton and tstart
Figure 6. Overvoltage from 0 to 10 V
VBat
DEG
V
in
V
bat
V
out
/Flag
Figure 7. Battery Overvoltage, Deglitch Time
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NCP367
TYPICAL OPERATING CHARACTERISTICS
2.00
1.98
1.96
1.94
1.92
1.90
1.88
5.66
5.64
5.62
OVLO
UVLO + hysteresis
5.60
5.58
5.56
OVLO − Hysteresis
UVLO
1.86
1.84
1.82
1.80
5.54
5.52
5.50
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. UVLO and Hysteresis
Figure 9. OVLO and Hysteresis vs. Temperature
(5.6 V version)
20
15
4.40
4.35
4.30
4.25
10
5
4.20
4.15
4.10
0
−50
−50
−25
0
25
50
75
100
125
−25
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. VBAT Pin Leakage vs. Temperature
Figure 10. VBAT Threshold and Hysteresis vs.
Temperature
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NCP367
APPLICATION INFORMATION
EN Input
Operation
The NCP367 is an integrated IC which offers a complete
protection of the portable devices during the Li ion battery
charge.
First, the input pin is protected up to +30 V, protecting
the down stream system (charger, transceiver, system...)
against the power supply transients such as inrush current
or defective functionality. Additional protection level is
offered with the overcurrent block which eliminates
current peak or opens the charge path if an overcurrent
default appears.
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin,
disconnects OUT pin from IN pin. EN does not overdrive
a UVLO or OVLO fault.
Overcurrent Protection (OCP)
This device integrates the overcurrent protection
function, from wall adapter to battery. That means the
current across the internal PMOS is regulated and cut when
the value, set by external RSEL resistor, exceeds I
LIM
longer than t
.
REG
More of that, the battery voltage is monitored all along
the input power supply is connected, allowing to open
charge path if Li ion battery voltage exceeds 4.3 V, caused
by CCCV charger or battery pack fault.
The integrated pass element (PMOS FET) is sized to
support very high charge DC current up to 2.3 A. The
overcurrent threshold can be externally adjusted with a
pull-down resistor and gain select pin is available to divide
current limit threshold with internal fixed gain. Allowing
to adjust with logic pin the overcurrent threshold if
USB/500 mA or WA/1.5 A is detected, without changing
An internal resistor is placed in series with the pin
allowing to have a maximum OCP value when I
directly connected to GND.
pin is
LIM
By adding external resistors in series with I
the OCP value is decreased.
and GND,
LIM
An additional logic pin, GS (gain select), is very useful
in case of different charge rate is necessary (Wall adapter
and USB, for example).
By setting GS to 0.4 V, overcurrent thresholds are
depending on R select resistor, which is connect between
pin 4 and GND. When the GS pin is tied to 1.2 V (high logic
level) the preselected current limit is divided by 2.75.
Thanks to this option, both fast charge or USB charge are
authorized with the same device.
R
resistor, in example.
ILIM
Undervoltage, Overvoltage, Overcurrent and thermal
faults are signalized thanks to the open drain FLAG pin, by
pulling its down.
Undervoltage Lockout (UVLO)
1500
To ensure proper operation under any conditions, the
device has a built−in undervoltage lock out (UVLO)
circuit. During Vin positive going slope, the output remains
disconnected from input until Vin voltage is above 1.85 V
plus hysteresis nominal. This circuit has a 80 mV
hysteresis to provide noise immunity to transient condition.
1000
GS = Low
Overvoltage Lockout (OVLO)
500
To protect connected systems on Vout pin from
overvoltage, the device has a built-in overvoltage lock out
(OVLO) circuit. During overvoltage condition, the output
remains disabled as long as the input voltage exceeds this
threshold.
GS = High
0
0
100 200 300 400 500 600 700
800
Rilim(kW)
FLAG output is tied to low as long as Vin is higher than
OVLO. This circuit has a 100 mV hysteresis to provide
noise immunity to transient conditions.
Figure 12. IOCP versus RLIM, GS = low and high,
1.5 A version
FLAG Output
Typical R
calculation is following:
LIM
NCP367 provides a FLAG output, which alerts external
systems that a fault has occurred.
NCP367DxMUxxTBG
(kW) = 249 / I
R
− 165
− 180
LIM
OCP
This pin is tied to low as soon as the OVLO, OV , I
NCP367OxMUxxTBG
(kW) = 532 / I
BAT OCP
or internal temperature thresholds are exceeded and
remains low until between minimum driving voltage and
UVLO threshold. When Vin level recovers normal
condition, FLAG is held high. The pin is an open drain
output, thus a pull up resistor (typically 1 MW − Minimum
10 kW) must be provided to Vcc. FLAG pin is an open drain
output, which is able to support 1 mA maximum.
R
LIM
OCP
During overcurrent event, charge area is opened and
FLAG output is tied to low, allowing the mController to take
into account the fault event and then open the charge path.
At power up (accessory is plugged on input pins), the
current is limited up to I
during 1.8 ms (typical), to
LIM
allow capacitor charge and limit inrush current. If the I
LIM
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NCP367
threshold is exceeded over 1.8 ms, the device enter in OCP
At wall adapter insertion, and if the battery is fully
burst mode until the overcurrent event disappears.
charged, V comparator stays locked until battery needs
bat
to be recharged (4.2 V typ − 4.1 V min).
A serial resistor has to be placed in series with Vbat pin
and battery connection, with a 200 kW recommended
value.
VBAT Sense
The connection of the V
pin to the positive
BAT
connection of the Li ion battery pack allows preventing
overvoltage transient, greater than 4.35 V. In case of wrong
charger conditions, the PMOS is then opened, eliminating
Battery pack over voltage which could create safety issues
and temperature increasing.
The 4.35 V comparator has a 150 mV built-in hysteresis.
More of that, deglitch function of 2 ms is integrated to
prevent voltage transients on the Battery voltage. If the
battery over voltage condition exceeds deglitch time, the
charge path is opened and FLAG pin is tied to low level
PCB Recommendations
The NCP367 integrates low R
PMOS FET,
DS(on)
nevertheless PCB layout rules must be respected to
properly evacuate the heat out of the silicon. The DFN
PAD1 corresponds to the PMOS drain so must be connected
to OUT plane to increase the heat transfer. Of course, in any
case, this pad shall be not connected to any other potential.
Following figure shows package thermal resistance of a
until the V
is greater than 4.35 V – hysteresis.
DFN 2.2x2 mm.
BAT
240
1.2
Theta JA curve with PCB cu thk 1.0 oz
Theta JA curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 2.0 oz
Power curve with PCB cu thk 1.0 oz
220
200
180
160
140
120
100
80
1.1
1
0.9
0.8
0.7
0.6
0.5
T_ambient
25°C
0
100
200
300
400
500
600
700
COPPER HEAT SPREADER AREA
2
(mm )
Internal PMOS FET
ESD Tests
NCP367 includes an internal PMOS FET to protect the
systems, connected on OUT pin, from positive
over-voltage. Regarding electrical characteristics, the
NCP367 fully support the IEC61000-4-2, level 4 (Input pin,
1 mF mounted on board). That means, in Air condition, Vin
has a 15kV ESD protected input. In Contact condition, Vin
has 8kV ESD protected input. Please refer to Figure 14 to see
the IEC 61000-4-2 electrostatic discharge waveform.
R
, during normal operation, will create low losses on
DSon
V
out
pin versus V , thanks to very low R
.
in
DSon
100
90
80
70
60
50
40
30
20
−50
−25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 14. IEC 61000-4-2 Electrostatic Discharge
Figure 13. Typical RDS(on) versus Temperature
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NCP367
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCP367DPMUECTBG
DC
DFN8
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
3000 / Tape & Reel
(*available in January 2011)
(Pb−Free)
NCP367DPMUEETBG
DE
DL
P3
DFN8
(Pb−Free)
NCP367DPMUELTBG
(*available in January 2011)
DFN8
(Pb−Free)
NCP367OPMUEOTBG
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP367 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP367xxMUxxTBG
a b
c d
Code
Contents
a
Overcurrent threshold
a = D: 1.51 A
a = O: 2.85 A
b
V
BAT
Voltage
b: P = 4.36 V
(additional thresholds available for a wide
Lithium ion material range)
c
UVLO Typical Threshold
c: E = 1.85 V
d
OVLO Typical Threshold
(Additional thresholds available)
d: C = 5.85 V
d: E = 6.07 V
d: L = 6.85 V
d: O = 7.20 V
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NCP367
PACKAGE DIMENSIONS
DFN8, 2.0x2.2, 0.5P
CASE 506BP−01
ISSUE A
NOTES:
D
A
B
E
L
L
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
PIN ONE
REFERENCE
DETAIL A
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
2X
0.10
C
DIM
A
MIN
0.80
0.00
TYP
---
MAX
1.00
0.05
EXPOSED Cu
MOLD CMPD
2X
0.10
C
A1
A3
b
---
TOP VIEW
0.20 REF
---
0.20
1.43
1.05
0.30
1.53
1.25
A
D
2.00 BSC
---
DETAIL B
(A3)
0.05
0.05
C
C
D2
E
2.20 BSC
---
DETAIL B
E2
e
ALTERNATE
9X
0.50 BSC
0.22
CONSTRUCTIONS
K
0.20
0.25
---
0.30
0.35
0.15
NOTE 4
L
---
L1
---
SEATING
PLANE
A1
C
SIDE VIEW
D2
SOLDERING FOOTPRINT*
0.10 C A B
1.63
DETAIL A
8X
0.45
8X L
1
4
E2
0.10 C A B
1.15
2.50
8
5
8X K
8X b
e
0.10 C A B
e/2
BOTTOM VIEW
NOTE 3
C
0.05
1
8X
0.28
0.50
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
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PUBLICATION ORDERING INFORMATION
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Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your loca
Sales Representative
NCP367/D
相关型号：
NCP370
Positive and Negative Overvoltage Protection with Internal Low RON N-MOSFETs and Reverse Charge Control Pin
ONSEMI
NCP370MUAITXG
Positive and Negative Overvoltage Protection with Internal Low RON N-MOSFETs and Reverse Charge Control Pin
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