NCP361MUTBG [ONSEMI]
USB Positive Overvoltage Protection Controller with Internal PMOS FET and Overcurrent Protection; USB正过压保护控制器，内置PMOS FET和过流保护
| 型号： | NCP361MUTBG |
| 厂家： | 
ONSEMI |
| 描述： | USB Positive Overvoltage Protection Controller with Internal PMOS FET and Overcurrent Protection |
| 文件： | 总12页 (文件大小：710K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP361
USB Positive Overvoltage
Protection Controller with
Internal PMOS FET and
Overcurrent Protection
The NCP361 disconnects systems at its output when wrong VBUS
operating conditions are detected at its input. The system is positive
over−voltage protected up to +20 V.
Thanks to an integrated PMOS FET, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
The NCP361 is able to instantaneously disconnect the output from
the input if the input voltage exceeds the overvoltage threshold
(5.675 V). Thanks to an overcurrent protection, the integrated PMOS
is turning off when the charge current exceeds current limit (see
options in ordering information).
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MARKING
DIAGRAMS
6 PIN UDFN
CASE 517AB
1
xx M
G
5
1
xxx AYWG
G
TSOP−5
The NCP361 provides a negative going flag (FLAG) output, which
alerts the system that voltage, current or overtemperature faults have
occurred.
CASE 483
1
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1 mF or larger capacitor.
xxx
M
A
= Specific Device Code
= Date Code
= Assembly Location
Features
Y
= Year
• Overvoltage Protection up to 20 V
• On−chip PMOS Transistor
• Overvoltage Lockout (OVLO)
• Undervoltage Lockout (UVLO)
• Overcurrent Protection
• Alert FLAG Output
W
G
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
2
3
EN
GND
IN
6
5
4
FLAG
OUT
OUT
• EN Enable Pin
• Thermal Shutdown
• Compliance to IEC61000−4−2 (Level 4)
8 kV (Contact)
15 kV (Air)
UDFN
• ESD Ratings: Machine Model = B
ESD Ratings: Human Body Model = 2
• 6 Leads UDFN 2x2 mm Package
• 5 Leads TSOP−5 3x3 mm Package
• This is a Pb−Free Device
OUT
IN
GND
EN
1
2
3
5
4
FLAG
Applications
• USB Devices
• Mobile Phones
• Peripheral
• Personal Digital Applications
• MP3 Players
• Set Top Boxes
TSOP−5
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
June, 2010 − Rev. 3
NCP361/D
NCP361
INPUT
OUTPUT
3
1
4
5
OUT
OUT
IN
FLAG Power
1 mF 25 V X5R 0603
C2
1 mF 25 V X5R 0603
C1
NCP361
R1
1M
J2
2
6
FLAG
EN
FLAG
GND
1
2
FLAG_State
Figure 1. Typical Application Circuit (UDFN Pinout)
OUTPUT
INPUT
EN
(2 out pins in
UDFN package)
Thermal Shutdown
Soft Start
FLAGV
UVLO
OVLO
LDO
V
REF
Figure 2. Functional Block Diagram
PIN FUNCTION DESCRIPTION (UDFN Package)
Pin No.
Name
Type
Description
1
EN
INPUT
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
2
3
GND
IN
POWER Ground
POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
4, 5
6
OUT
OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins.
The two OUT pins must be hardwired to common supply.
FLAG
OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to V must be added.
CC
PIN FUNCTION DESCRIPTION (TSOP−5 Package)
Pin No.
Name
Type
Description
1
IN
POWER Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
2
3
GND
EN
POWER Ground
INPUT
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
4
5
FLAG
OUT
OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to V must be added.
CC
OUTPUT Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin.
NOTE: Pin out provided for concept purpose only and might change in the final product
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2
NCP361
MAXIMUM RATINGS
Rating
Symbol
Vmin
Value
−0.3
−0.3
21
Unit
V
MinimumVoltage (IN to GND)
in
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Vmin
Vmax
V
V
in
Maximum Voltage (All others to GND)
Maximum DC Current from Vin to Vout (PMOS) (Note 1)
Thermal Resistance, Junction−to−Air
Vmax
Imax
R
7.0
V
600
mA
°C/W
TSOP−5
UDFN
305
240
q
JA
Operating Ambient Temperature Range
Storage Temperature Range
T
−40 to +85
−65 to +150
150
°C
°C
°C
A
T
stg
Junction Operating Temperature
T
J
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
kV
V
V
2000
200
Moisture Sensitivity
MSL
Level 1
−
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
RecommendedOperating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. With minimum PCB area. By decreasing R , the current capability increases. See PCB recommendation page 9.
q
JA
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP361
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (−40°C < T < +85°C) and V = +5.0 V. Typical values are T = +25°C, unless otherwise noted.)
A
in
A
Characteristic
Symbol
Conditions
Min
1.2
Typ
Max
20
Unit
V
Input Voltage Range
V
in
Undervoltage Lockout Threshold
Uvervoltage Lockout Hysteresis
Overvoltage Lockout Threshold
Overvoltage Lockout Hysteresis
UVLO
UVLO
V
falls down UVLO threshold
2.85
50
3.0
70
3.15
90
V
in
mV
V
hyst
OVLO
OVLO
V
rises up OVLO threshold
5.43
50
5.675
100
150
750
20
5.9
125
200
950
35
in
mV
mV
mA
mA
mA
mA
mV
hyst
V
in
versus V Dopout
V
drop
V
= 5 V, I charge = 500 mA
out
in
Overcurrent Limit
I
lim
V
in
= 5 V
550
Supply Quiescent Current
Standby Current
Idd
No Load, V = 5.25 V
in
I
V
in
= 5 V, EN = 1.2 V
26
37
std
Zero Gate Voltage Drain Current
FLAG Output Low Voltage
I
V
DS
= 20 V, V = 0 V
0.08
DSS
GS
Vol
V
in
> OVLO
400
flag
Sink 1 mA on FLAG pin
FLAG Leakage Current
EN Voltage High
FLAG
FLAG level = 5 V
5.0
nA
V
leak
V
ih
V
V
from 3.3 V to 5.5 V
from 3.3 V to 5.5 V
1.2
in
EN Voltage Low
V
il
0.55
V
in
EN Leakage Current
EN
EN = 5.5 V or GND
170
nA
leak
TIMINGS
Start Up Delay
t
From V > UVLO to V = 0.8xV , See Fig 3 & 9
4.0
3.0
0.7
15
ms
ms
ms
on
in
out
in
FLAG going up Delay
Output Turn Off Time
t
From V > UVLO to FLAG = 1.2 V, See Fig 3 & 10
in
start
t
off
From V > OVLO to V ≤ 0.3 V, See Fig 4 & 11
1.5
in
out
V
in
increasing from 5 V to 8 V at 3 V/ms.
No output capacitor.
Alert Delay
t
From V > OVLO to FLAG ≤ 0.4 V, See Fig 4 & 12
1.0
3.0
ms
ms
stop
in
V
increasing from 5 V to 8 V at 3 V/ms
in
Disable Time
t
From EN 0.4 to 1.2V to V ≤ 0.3 V, See Fig 5 & 13
out
dis
V
in
= 4.75 V.
No output capacitor.
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
T
150
30
°C
°C
sd
T
sdhyst
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4
NCP361
<OVLO
OVLO
UVLO
V
in
V
in
t
off
t
on
V
− R
x I
in
DSon
V
in
− R
x I
DS(on)
0.8 V
in
V
out
V
out
0.3 V
t
stop
t
start
FLAG
FLAG
1.2 V
0.4 V
Figure 3. Start Up Sequence
Figure 4. Shutdown on Over Voltage Detection
EN
1.2 V
EN
V
1.2 V
t
dis
OVLO
V
out
UVLO
out
0.3 V
V
in
− R
x I
DS(on)
t
start
FLAG
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
CONDITIONS
IN
OUT
V
IN
> OVLO or V < UVLO
IN
Voltage, Current and Thermal Detection
Figure 7.
CONDITIONS
IN
OUT
UVLO < V < OVLO
IN
Voltage, Current and Thermal Detection
Figure 8.
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5
NCP361
TYPICAL OPERATING CHARACTERISTICS
Figure 9. Start Up. Vin=Ch1, Vout=Ch2
Figure 10. FLAG Going Up Delay. Vin=Ch1,
FL:AG=Ch3
Figure 12. Alert Delay. Vout=Ch1, FLAG=Ch3
Figure 11. Output Turn Off time. Vin=Ch1,
Vout=Ch2
Figure 13. Disable Time. EN=Ch4, Vin=Ch1,
Vout=Ch2
Figure 14. Thermal Shutdown. Vin=Ch1,
Vout=Ch2, FLAG=Ch3
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6
NCP361
TYPICAL OPERATING CHARACTERISTICS
450
400
350
300
250
200
V
in
= 3.6 V
150
100
50
V
in
= 5 V
0
−50
0
50
100
150
TEMPERATURE (°C)
Figure 15. RDS(on) vs. Temperature
(Load = 500 mA)
Figure 16. Output Short Circuit
900
880
860
840
820
800
780
760
740
720
180
160
140
120
100
80
V
V
V
= 3.25 V
in
in
in
= 3.6 V
= 4.2 V
125°C
25°C
V
= 5 V
in
60
40
−40°C
V
in
= 5.25 V
20
0
−50
0
50
TEMPERATURE (°C)
100
150
1
3
5
7
9
11
13 15 17
19 21
V , INPUT VOLTAGE (V)
in
Figure 18. Overcurrent Protection Threshold
vs. Temperature
Figure 17. Quiescent Current vs. Input Voltage
900
25°C
880
860
840
820
800
780
760
740
720
125°C
85°C
0°C
−25°C
−40°C
3
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
Figure 19. Overcurrent Protection Threshold
vs. Input Voltage
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7
NCP361
Operation
V
out
NCP361 provides overvoltage protection for positive
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the V pin, against positive
out
overvoltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
To ensure proper operation under any conditions, the
device has a built−in undervoltage lock out (UVLO)
Overload
Retrieve
normal
operation
I
load
circuit. During V positive going slope, the output remains
in
I
lim
disconnected from input until V voltage is above 3.0 V
in
nominal. The FLAGV output is pulled to low as long as V
in
does not reach UVLO threshold. This circuit has a 70 mV
hysteresis to provide noise immunity to transient condition.
t
on
V
in
(V)
Figure 21. Overcurrent Event Example
FLAG Output
NCP361 provides a FLAG output, which alerts external
systems that a fault has occurred.
20 V
OVLO
UVLO
0
This pin is tied to low as soon as: 1.2 V < V < UVLO,
in
V
> OVLO, I
> I , T > 150°C. When NCP361
in
charge limit J
recovers normal condition, FLAG is held high. The pin is
V
out
an open drain output, thus a pull up resistor (typically 1 MW
− Minimum 10 kW) must be provided to V . FLAG pin is
CC
OVLO
an open drain output.
UVLO
0
EN Input
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Figure 20. Output Characteristic vs. Vin
Overvoltage Lockout (OVLO)
To protect connected systems on V
pin from
out
Internal PMOS FET
overvoltage, the device has a built−in overvoltage lock out
(OVLO) circuit. During overvoltage condition (OVLO
exceeds), the output remains disabled and FLAG is tied
low, as long as the input voltage is higher than OVLO −
hysteresis. This circuit has a 100 mV hysteresis to provide
noise immunity to transient conditions.
The NCP361 includes an internal PMOS FET to protect
the systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
R
, during normal operation, will create low losses on
DS(on)
V
out
pin, characterized by V versus V dropout.
in out
ESD Tests
Overcurrent Protection (OCP)
The NCP361 fully supports the IEC61000−4−2, level 4
(Input pin, 1 mF mounted on board). That means, in Air
The NCP361 integrates overcurrent protection to
prevent system/battery overload or defect. The current
limit threshold is internally set at 750 mA. This value can
be changed from 150 mA to 750 mA by a metal tweak,
please contact your ON Semiconductor representative for
availability. During current fault, the internal PMOS FET
is automatically turned off (5 ms) if the charge current
condition, V has a 15 kV ESD protected input. In
in
Contact condition, V has 8 kV ESD protected input.
in
Please refer to Figure 22 to see the IEC61000−4−2
electrostatic discharge waveform.
exceeds I . NCP361 goes into turn on and turn off mode
lim
as long as defect is present. The internal ton delay (4 ms
typical) allows limiting thermal dissipation. The Flag pin
goes to low level when an overcurrent fault appears. That
allows the microcontroller to count defect events and turns
off the PMOS with EN pin.
Figure 22.
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8
NCP361
PCB Recommendations
two different example of current capability, depending on
PCB area:
• With 305°C/W (without PCB area), allowing DC
The NCP361 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
current is 500 mA
2
• With 260°C/W (200 mm ), the charge DC current
allows with a 85°C ambient temperature is:
I = √(T -T )/(R
x R
)
DSON
J
A
JA
q
By increasing PCB area, the R
of the package can be
JA
q
I = 625 mA
decreased, allowing higher charge current to fill the battery.
Taking into account that internal bondings (wires
between package and silicon) can handle up to 1 A (higher
than thermal capability), the following calculation shows
In every case, we recommend to make thermal
measurement on final application board to make sure of the
final Thermal Resistance.
380
330
280
230
180
130
80
50%
45%
40%
TSOP−5 1.0 oz
TSOP−5 2.0 oz
35%
DFN 2x2.2 1.0 oz
DFN 2x2.2 2.0 oz
% Delta DFN vs TSOP−5
30%
25%
20%
15%
10%
5%
0%
700
0
100
200
300
400
500
600
Copper heat spreader area (mm^2)
Figure 23. Thermal Resistance of UDFN 2x2 and TSOP Packages as a Function of PCB Area and Thickness
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9
NCP361
ORDERING INFORMATION
Device
†
Marking
Package
Shipping
NCP361MUTBG
AD
UDFN6
3000 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NCP361SNT1G
ACD
TSOP−5
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
SELECTION GUIDE
The NCP361 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP361xxxxxTxG
a b c d
e
Code
Contents
a
Overcurrent Threshold
−: 750 mA
b
Package
MU: UDFN
SN: TSOP−5
c
d
e
UVLO Typical Threshold
−: 3.00 V
OVLO Typical Threshold
−: 5.675 V
Tape & Reel Type
B: = 3000
1: = 3000
NOTE: Additional current limit, UVLO and OVLO can be available.
Please contact your ON Semiconductor representative for
availability.
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10
NCP361
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
A
B
E
MILLIMETERS
DIM
A
MIN
0.45
0.00
MAX
0.55
0.05
A1
A3
b
PIN ONE
REFERENCE
0.127 REF
0.25
1.50
0.35
D
2.00 BSC
D2
E
1.70
0.10
C
2X
2.00 BSC
E2
e
0.80
1.00
0.65 BSC
K
0.20
0.25
---
2X
0.10
C
L
0.35
A3
SOLDERING FOOTPRINT*
0.10
C
6X
0.47
A
0.95
6X
0.40
6X
0.08
C
A1
1
SEATING
C
PLANE
D2
4X
e
6X
L
1.70
1
6
3
E2
0.65
PITCH
2.30
4
6X
K
DIMENSIONS: MILLIMETERS
6X
b
0.10
0.05
C
C
A
B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
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11
NCP361
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
ǒinches
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
MountingTechniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your loca
Sales Representative
NCP361/D
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