NB6HQ14MMNG [ONSEMI]
2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer; 2.5V的5GHz / 6.5Gbps的差分输入至1.8V / 2.5V 1 ： 4 CML时钟/数据扇出缓冲器
| 型号： | NB6HQ14MMNG |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer |
| 文件： | 总11页 (文件大小：1258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB6HQ14M
2.5V 5GHz / 6.5Gbps
Differential Input to 1.8V /
2.5V 1:4 CML Clock / Data
Fanout Buffer w/ Selectable
Input Equalizer
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MARKING
DIAGRAM*
Multi−Level Inputs w/ Internal Termination
16
Description
1
The NB6HQ14M is a high performance differential 1:4 CML fanout
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 5 GHz or 6.5 Gb/s, respectively, the
NB6HQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal. Therefore, the serial data rate
is increased by reducing Inter−Symbol Interference (ISI) caused by
losses in copper interconnect or long cables. The EQualizer ENable
pin (EQEN) allows the IN/IN inputs to either flow through or bypass
the Equalizer section. Control of the Equalizer function is realized by
setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the
Equalizer. When EQEN is set High, the IN/IN inputs flow through the
Equalizer. The default state at start−up is LOW. As such, NB6HQ14M
is ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
1
NB6H
Q14M
ALYWG
G
QFN−16
MN SUFFIX
CASE 485G
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
The differential inputs incorporate internal 50 W termination
resistors that are accessed through the VT pin. This feature allows the
NB6HQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The outputs have the flexibility of being powered by
either a 2.5 V or 1.8 V supply. The 1:4 fanout design was optimized
for low output skew applications.
SIMPLIFIED BLOCK DIAGRAM
The NB6HQ14M is a member of the ECLinPS MAX™ family of
high performance clock products.
EQ
Features
• Input Data Rate > 6.5 Gb/s
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
• Input Clock Frequency > 5 GHz
• 170 ps Typical Propagation Delay
• 35 ps Typical Rise and Fall Times
• < 15 ps Output Skew
• < 0.8 ps RMS Clock Jitter
• < 10 ps pp of Data Dependent Jitter
• Differential CML Outputs, 400 mV Peak−to−Peak, Typical
• Selectable Input Equalization
• Operating Range: V = 2.375 V to 2.625 V, V
= 1.71 V to
CC
CCO
2.625 V
• Internal Input Termination Resistors, 50 W
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
©
Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
June, 2009 − Rev. 0
NB6HQ14M/D
NB6HQ14M
CML Outputs
Multi−Level Inputs
LVPECL, LVDS, CML
V
CC0
Q0
Q0
Q1
Q1
IN
50 W
VT
0
50 W
IN
2:1
MUX
Q2
Q2
VREFAC
EQ
1
V
CC
GND
Q3
Q3
EQEN
(Equalizer Enable)
56 kW
Figure 1. Detailed Block Diagram of NB6HQ14M
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2
NB6HQ14M
GND Q0
16 15
Q0
14
V
Exposed Pad (EP)
CC
Table 1. EQUALIZER ENABLE FUNCTION
13
EQEN
Function
0
1
IN / IN Inputs By−pass the Equalizer section
Inputs flow through the Equalizer
IN
1
2
3
4
12
11
10
9
Q1
Q1
Q2
Q2
VT
NB6HQ14M
VREFAC
IN
5
6
7
8
EQEN Q3 Q3
V
CCO
Figure 2. QFN−16 Pinout (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
Description
1
IN
LVPECL, CML,
LVDS Input
Non−inverted Differential Input. Note 1.
2
3
4
VT
VREFAC
IN
Internal 100 W Center−tapped Termination Pin for IN / IN
Output Voltage Reference for Capacitor−Coupled Inputs, only
Inverted Differential Input. Note 1.
LVPECL, CML,
LVDS Input
5
6
EQEN
Q3
LVCMOS Input
CML Output
CML Output
−
Equalizer Enable Input; pin will default LOW when left open (has internal pull−down resistor)
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
7
Q3
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
8
VCCO
Q2
1.8 V or 2.5 V Positive Supply Voltage for the Qn / Qn CML Outputs
9
CML Output
CML Output
CML Output
CML Output
−
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
10
11
12
13
14
15
16
−
Q2
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
.
CC
Q1
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
Q1
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
VCC
Q0
2.5 V Positive Supply Voltage for the core
CML Output
CML Output
−
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
Q0
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
GND
EP
Negative Supply Voltage
−
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is electrically connected to the die, and must be electrically and thermally con-
nected to GND on the PC board.
1. In the differential configuration when the input termination pin (VT) is connected to a common termination voltage or left open, and if no signal
is applied on IN / IN input, then, the device will be susceptible to self−oscillation.
2. All VCC, VCCO and GND pins must be externally connected to a power supply for proper operation.
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3
NB6HQ14M
Table 3. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
> 2 kV
> 200V
Machine Model
R
PD
− EQEN Input Pulldown Resistor
56 kW
Moisture Sensitivity (Note 3)
Flammability Rating
Transistor Count
16−QFN
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
277
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply − Core
Condition 1
GND = 0 V
GND = 0 V
GND = 0 V
Condition 2
Rating
3.0
Unit
V
V
CC
CCO
IO
V
V
Positive Power Supply − Outputs
3.0
V
Positive Input/Output Voltage
−0.5 to V
+
V
CC
0.5
V
INPP
Differential Input Voltage |IN − IN|
1.89
V
I
I
I
Input Current Through R (50 W Resistor)
$40
$40
mA
mA
mA
°C
IN
T
Output Current Through R (50 W Resistor)
OUT
T
VREFAC Sink/Source Current
$1.5
VFREFAC
T
Operating Temperature Range
16 QFN
−40 to +85
A
T
stg
Storage Temperature Range
−65 to +150
°C
θ
JA
Thermal Resistance (Junction−to−Ambient) (Note 4)
0 lfpm
500 lfpm
16 QFN
16 QFN
42
35
°C/W
°C/W
θ
Thermal Resistance (Junction−to−Case) (Note 4)
16 QFN
4
°C/W
°C
JC
T
Wave Solder
Pb−Free
265
sol
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NB6HQ14M
Table 5. DC CHARACTERISTICS, MULTI−LEVEL INPUTS V = 2.375 V to 2.625 V; V
= 1.71 V to 2.625 V; GND = 0 V;
CC
CCO
T = −40°C to 85°C (Note 5)
A
Symbol
Characteristic
Min
Typ
Max
Unit
POWER SUPPLY / CURRENT
V
V
Power Supply Voltage
V
= 2.5 V
= 2.5 V
= 1.8 V
2.375
2.375
1.71
2.5
2.5
1.8
2.625
2.625
1.89
V
CC
CCO
CC
V
CCO
CCO
V
I
I
Power Supply Current for VCC (Inputs and Outputs Open)
Power Supply Current for VCCO (Inputs and Outputs Open)
75
65
110
90
mA
CC
CCO
CML OUTPUTS (Note 6)
V
Output HIGH Voltage
Output LOW Voltage
V
– 30
2470
1770
V
– 10
2490
1790
V
CCO
2500
1800
mV
mV
OH
OL
CCO
CCO
V
CCO
V
CCO
= 2.5 V
= 1.8 V
V
V
CCO
– 550
V
CCO
– 450
V
– 300
CCO
V
CCO
V
CCO
= 2.5 V
= 1.8 V
1950
1250
2050
1350
2200
1500
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figure 5 & 7) (Note 7)
V
V
V
V
Single−ended Input HIGH Voltage
Vth + 100
GND
V
mV
mV
mV
mV
IH
IL
CC
Single−ended Input LOW Voltage
Vth −100
Input Threshold Reference Voltage Range (Note 8)
1100
V
− 100
th
CC
Single−ended Input Voltage Amplitude (V − V )
200
2800
ISE
IH
IL
VREFAC
V
Output Reference Voltage @100 mA for capacitor− coupled inputs, only
V
CC
– 1325
V – 1125
CC
V
CC
– 925
mV
REFAC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figure 6 & 8) (Note 9)
V
V
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
V
mV
mV
mV
mV
IHD
ILD
ID
CC
0
V
− 100
IHD
Differential Input Voltage (V
− V )
ILD
100
1200
V − 50
CC
IHD
Input Common Mode Range (Differential Configuration) (Note 10)
(Figure 9)
1050
CMR
I
I
Input HIGH Current IN / IN, (VT Open)
Input LOW Current IN / IN, (VT Open)
−150
−150
150
150
uA
uA
IH
IL
CONTROL INPUTS (EQEN)
V
V
Input HIGH Voltage for Control Pins
Input LOW Voltage for Control Pins
Input HIGH Current
V
CC
x 0.65
V
CC
V
V
IH
IL
GND
−150
−150
V
x 0.35
CC
I
IH
I
IL
150
mA
mA
Input LOW Current
150
TERMINATION RESISTORS
R
R
Internal Input Termination Resistor
Internal Output Termination Resistor
45
45
50
50
55
55
W
W
TIN
TOUT
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input parameters vary 1:1 with V . Output parameters vary 1:1 with V
.
CC
CCO
6. CML outputs loaded with 50 W to V
for proper operation.
CCO
7. Vth, V , V and V
parameters must be complied with simultaneously.
IH IL,,
ISE
8. Vth is applied to the complementary input when operating in single−ended mode.
9. V , V and V parameters must be complied with simultaneously.
V
IHD ILD, ID
CMR
signal.
CMR
10.V
min varies 1:1 with GND, V
max varies 1:1 with V . The V
range is referenced to the crosspoint side of the differential input
CMR
CC
CMR
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5
NB6HQ14M
Table 6. AC CHARACTERISTICS V = 2.375 V to 2.625 V; V
= 1.71 V to 2.625 V; GND = 0 V; T = −40°C to 85°C (Note 11)
CC
CCO
A
Symbol
Characteristic
Min
5
Typ
Max
Unit
GHz
Gbps
mV
f
Maximum Input Clock Frequency;
V
OUT
w 200 mV
7
MAX
f
Maximum Operating Data Rate (PRBS23)
6.5
200
10
DATAMAX
V
Output Voltage Amplitude, EQEN = 0 or 1 (Note 15)
(See Figures 3 and 10)
f
in
≤ 5 GHz
400
OUTPP
t
t
,
Propagation Delay, EQEN = 0 or 1
IN to Q
150
45
220
275
ps
ps
PLH
PHL
t
Duty Cycle Skew (Note 12)
Output – Output Within Device Skew
Device to Device Skew
15
15
50
SKEW
3
10
t
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
Phase Noise, fin = 1 GHz
f
in
= 1 GHz
50
55
%
DC
F
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
−132
−135
−145
−146
−147
−148
dBc
N
t
t
Integrated Phase Jitter f = 1 GHz, 12 kHz − 20 MHz
50
fs
ŐF
in
N
Offset (RMS)
RMS Random Clock Jitter (Note 13)
f
in
v 5 GHz
0.2
0.8
ps rms
JITTER
Peak−to−Peak Data Dependent Jitter (Note 14)
f v 3.0 Gb/s
in
EQEN = 0 (v 3” FR4)
15
10
ps pk−pk
ps pk−pk
EQEN = 1 (12” FR4)
V
Input Voltage Swing/Sensitivity
100
15
1200
mV
INPP
(Differential Configuration) (Note 15)
t
r
t
f
Output Rise/Fall Times @ 1.0 GHz
(20% − 80%)
Qx, Qx
30
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured by forcing V
min from a 50% duty cycle clock source. All loading with an external R = 50 W to V
. Input edge rates 40
CCO
INPP
L
ps (20% − 80%).
12.Skew is measured between outputs under identical transitions and conditions @ 0.5 GHz. Duty cycle skew is measured between differential
outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23. For applications requiring equalization, the vertical eye height
is also a critical figure of merit. See Figure 4 for equalized eye height versus data rate.
15.Input and output voltage swings are single−ended measurements operating in a differential mode.
400
350
300
250
200
150
100
50
600
500
Q AMP (mV)
400
300
200
100
0
0
0
1
2
3
4
5
6
7
8
0
1
2
3
4
4
6
5
8
7
f , CLOCK INPUT FREQUENCY (GHz)
in
DATE RATE (Gbps)
Figure 3. CLOCK Output Voltage Amplitude (VOUTPP) vs.
Input Frequency (fin) at Ambient Temperature (Typical)
Figure 4. NB6HQ14M Eye Height vs. Data
Rate
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6
NB6HQ14M
V
CC
IN
50 W
50 W
V
T
IN
Figure 5. Input Structure
IN
V
IH
IN
IN
V
th
IL
V
IN
V
th
Figure 6. Differential Input Driven
Figure 7. Differential Inputs
Driven Differentially
Single−Ended
V
CC
thmax
V
V
IHmax
V
ILmax
V
IHD
= |V
− V
ID
IHD(IN) ILD(IN)|
V
IH
V
th
V
IL
IN
IN
V
V
th
IN
V
ILD
V
thmin
V
V
IHmin
ILmin
GND
Figure 8. Vth Diagram
Figure 9. Differential Inputs Driven Differentially
V
CC
V
V
V
IHD(MAX)
INx
V
CMRmax
ILD(MAX)
V
V
= V (IN) − V (IN)
IH IL
INPP
INx
Q
IHD
V
CMR
V
= V
− V
IHD ILD
ID
V
ILD
= V (Q) − V (Q)
OUTPP
OH
OL
Q
V
V
IHD(MIN)
t
PHL
V
CMRmin
t
PLH
ILD(MIN)
GND
Figure 10. VCMR Diagram
Figure 11. AC Reference Measurement
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7
NB6HQ14M
V
CC
NB6HQ14M
EQualizer
EQEN = 1
VT
FR4 − 12 Inch Backplane
IN
IN
Driver
Q
Q
DJ1
DJ2
DJ3
Figure 12. Typical NB6HQ14M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1
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8
NB6HQ14M
V
CC
V
CC
V
CC
V
CC
NB6HQ14M
IN
NB6HQ14M
IN
Z
= 50 W
Z
Z
= 50 W
O
O
50 W
50 W
50 W
50 W
LVPECL
Driver
LVDS
Driver
V = V − 2 V
O
V = Open
T
= 50 W
O
T
CC
= 50 W
Z
IN
IN
GND/V
GND
EE
GND
GND
Figure 13. LVPECL Interface
Figure 14. LVDS Interface
V
CC
V
CC
V
CC
V
CC
NB6HQ14M
IN
NB6HQ14M
IN
Z
= 50 W
O
Z
= 50 W
O
50 W
50 W
CML
Driver
50 W
50 W
Differential
Driver
V = V
T
CC
VT = V
*
REFAC
Z
= 50 W
O
Z
= 50 W
O
IN
IN
GND
GND
GND
GND
Figure 15. Standard 50 W Load CML Interface
Figure 16. Capacitor−Coupled
Differential Interface
(VT Connected to VREFAC
)
*V
REFAC
bypassed to ground with a 0.01 mF capacitor
V
CC
V
CC
NB6HQ14M
IN
Z
= 50 W
O
50 W
50 W
Differential
Driver
VT = V
*
REFAC
IN
GND
GND
Figure 17. Capacitor−Coupled
Single−Ended Interface
(VT Connected to VREFAC
)
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NB6HQ14M
NB6HQ14M
Receiver
V (Receiver)
CC
V
CCO
V
CCO
=
V
CC
(Receiver)
50 W
50 W
50 W
50 W
16 mA
GND
Figure 18. Typical CML Output Structure
and Termination
ORDERING INFORMATION
Device
†
Package
Shipping
NB6HQ14MMNG
QFN−16
123 Units / Rail
100 / Tape & Reel
3000 / Tape & Reel
(Pb−Free)
NB6HQ14MMNHTBG
NB6HQ14MMNTXG
QFN−16
(Pb−Free)
QFN−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB6HQ14M
PACKAGE DIMENSIONS
16 PIN QFN
CASE 485G−01
ISSUE D
NOTES:
L
L
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L1
DETAIL A
PIN 1
LOCATION
ALTERNATE TERMINAL
CONSTRUCTIONS
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
MILLIMETERS
A3
EXPOSED Cu
MOLD CMPD
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
0.15
C
TOP VIEW
A3
b
D
D2 1.65
E
0.20 REF
0.18
0.30
0.15
C
A1
3.00 BSC
1.85
3.00 BSC
1.85
0.50 BSC
0.18 TYP
DETAIL B
DETAIL B
ALTERNATE
(A3)
0.10
0.08
C
C
E2 1.65
CONSTRUCTIONS
e
K
L
A
0.30
0.50
0.15
L1 0.00
SEATING
PLANE
16 X
SIDE VIEW
A1
C
SOLDERING FOOTPRINT*
D2
3.25
0.128
0.30
DETAIL A
e
L
16X
0.575
0.022
5
8
EXPOSED PAD
NOTE 5
EXPOSED PAD
0.012
4
1
9
E2
K
16X
e
12
1.50
0.059
3.25
0.128
16
13
16X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
0.30
0.012
NOTE 3
0.50
0.02
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NB6HQ14M/D
相关型号：
NB6HQ14MMNHTBG
2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
ONSEMI
NB6HQ14MMNTXG
2.5V 5GHz / 6.5Gbps Differential Input to 1.8V / 2.5V 1:4 CML Clock / Data Fanout Buffer
ONSEMI
NB6L11
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
ONSEMI
NB6L11D
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
ONSEMI
NB6L11DG
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
NB6L11DR2
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
ONSEMI
NB6L11DR2G
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
NB6L11DT
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
ONSEMI
NB6L11DTG
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
NB6L11DTR2
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
ONSEMI
NB6L11DTR2G
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
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