NB6L11M [ONSEMI]
2.5V / 3.3V 1:2 Differential CML Fanout Buffer; 2.5V / 3.3V 1 ： 2差分CML扇出缓冲器
| 型号： | NB6L11M |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V / 3.3V 1:2 Differential CML Fanout Buffer |
| 文件： | 总9页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB6L11M
2.5V / 3.3V 1:2 Differential
CML Fanout Buffer
Multi−Level Inputs w/ Internal Termination
http://onsemi.com
MARKING
Description
The NB6L11M is a differential 1:2 CML fanout buffer. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the V pins and will accept LVPECL, LVCMOS,
DIAGRAM*
T
16
LVTTL, CML, or LVDS logic levels.
1
The V
pin is an internally generated voltage supply available
REFAC
NB6L
11M
QFN−16
MN SUFFIX
CASE 485G
to this device only. V
single−ended PECL or NECL inputs. For all single−ended input
conditions, the unused complementary differential input is connected
is used as a reference voltage for
REFAC
ALYWG
G
to V
as a switching reference voltage. V
may also rebias
REFAC
REFAC
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
capacitor−coupled inputs. When used, decouple V
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L11M is a member of the ECLinPS MAXt family of
high performance clock products.
with a
REFAC
REFAC
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Features
• Maximum Input Clock Frequency > 4 GHz, Typical
• 225 ps Typical Propagation Delay
Q0
• 70 ps Typical Rise and Fall Times
VTD
Q0
• 0.5 ps maximum RMS Clock Jitter
D
D
• Differential CML Outputs, 380 mV peak−to−peak, typical
Q1
Q1
• LVPECL Operating Range: V = 2.375 V to 3.63 V with V = 0 V
CC
EE
VTD
• NECL Operating Range: V = 0 V with V = −2.375 V to −3.63 V
CC
EE
V
REFAC
• Internal Input Termination Resistors, 50 W
• VREFAC Reference Output
Figure 1. Simplified Logic Diagram
• Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP,
EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page NO TAG of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 0
NB6L11M/D
NB6L11M
Exposed Pad (EP)
V
V
V
V
CC
CC
EE
EE
16
15
14
13
VTD
D
Q0
11 Q0
1
2
3
4
12
NB6L11M
D
Q1
Q1
10
9
VTD
5
6
7
8
V
V
V
V
CC
CC
REFAC EE
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin
1
Name
VTD
D
I/O
Description
−
Internal 50 W Termination Pin for D input.
2
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
3
D
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
4
5
VTD
−
−
Internal 50 W Termination Pin for D input.
Positive Supply Voltage
V
CC
6
V
Output Reference Voltage for direct or capacitor coupled inputs
Negative Supply Voltage
REFAC
7
V
−
EE
8
V
−
Positive Supply Voltage
CC
9
Q1
Q1
Q0
Q0
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
10
11
12
13
14
15
16
−
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
.
.
CC
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
.
CC
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
Positive Supply Voltage
CC
V
−
−
−
−
−
CC
V
Negative Supply Voltage
EE
EE
CC
V
Negative Supply Voltage
V
Positive Supply Voltage
EP
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and
if no signal is applied on D/D input, then, the device will be susceptible to self−oscillation.
2. All V and V pins must be externally connected to a power supply for proper operation.
CC
EE
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2
NB6L11M
Table 2. ATTRIBUTES
Characteristics
Value
> 2 kV
ESD Protection
Human Body Model
Machine Model
> 200V
Moisture Sensitivity
Flammability Rating
Transistor Count
16−QFN
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Positive Power Supply
Condition 1
= 0 V
Condition 2
Rating
4.0
Unit
V
V
V
V
CC
EE
IO
EE
CC
V
V
Negative Power Supply
= 0 V
−4.0
V
Positive Input/Output Voltage
Negative Input/Output Voltage
V
V
= 0 V
= 0 V
−0.5 v V v V + 0.5
4.0
−4.0
V
V
EE
CC
Io
CC
+0.5 v V v V − 0.5
Io
EE
V
Differential Input Voltage |D − D|
V
− V
EE
V
INPP
CC
I
Input Current Through R (50 W Resistor)
Static
Surge
45
80
mA
mA
IN
T
I
Output Current (CML Output)
Continuous
Surge
25
50
mA
mA
OUT
I
VREFAC Sink/Source Current
Operating Temperature Range
Storage Temperature Range
$0.5
mA
_C
_C
VREFAC
T
16 QFN
−40 to +85
A
T
−65 to +150
stg
q
Thermal Resistance (Junction−to−Ambient)
(Note 3)
0 lfmp
500 lfmp
QFN−16
QFN−16
42
35
_C/W
JA
_C/W
_C/W
_C
q
Thermal Resistance (Junction−to−Case)
Wave Solder Pb−Free
(Note 3)
QFN−16
4
JC
T
265
sol
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB6L11M
Table 4. DC CHARACTERISTICS, Multi−Level Inputs V = 2.375 V to 3.63 V, V = 0 V, or V = 0 V, V = −2.375 V to
CC
EE
CC
EE
−3.63 V, T = −40°C to +85°C
A
Symbol
Characteristic
Min
Typ
Max
Unit
mA
mV
POWER SUPPLY CURRENT
I
Power Supply Current (Inputs and Outputs Open)
45
60
75
CC
CML OUTPUTS (Notes 4 and 5)
V
V
Output HIGH Voltage
Output LOW Voltage
V
− 40
V
− 10
V
CC
3300
2500
OH
OL
CC
CC
V
V
= 3.3 V
= 2.5 V
3260
2460
3290
2490
CC
CC
V
− 500
V
− 400
V − 300
CC
3000
2200
mV
CC
CC
V
V
= 3.3V
= 2.5V
2800
2000
2900
2100
CC
CC
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 4 and 5) (Note 6)
V
V
V
V
Input Threshold Reference Voltage Range (Note 7)
Single−ended Input HIGH Voltage
1125
V
− 75
CC
mV
mV
mV
mV
th
V
+ 75
V
CC
IH
IL
th
Single−ended Input LOW Voltage
V
V
− 75
th
EE
Single−ended Input Voltage Amplitude (V − V )
150
2800
ISE
IH
IL
VREFAC
V
Output Reference Voltage
V
– 1.525
+ 1200
V
– 1.425
V – 1.325
CC
mV
REFAC
CC
CC
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6, 7 and 8) (Note 8)
V
V
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
V
V
mV
mV
mV
mV
uA
IHD
ILD
ID
EE
CC
V
V
− 100
EE
CC
CC
Differential Input Voltage (V
− V )
ILD
V
+ 100
V
− V
EE
IHD
EE
EE
Input Common Mode Range (Differential Configuration) (Note9)
Input HIGH Current D / D, (VTD/VTD Open)
V
+ 1150
V
− 50
CC
CMR
I
I
−10
−50
50
IH
IL
Input LOW Current D / D, (VTD/VTD Open)
10
uA
TERMINATION RESISTORS
R
R
Internal Input Termination Resistor
Internal Output Termination Resistor
40
40
50
50
60
60
W
W
TIN
TOUT
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs loaded with 50 W to V for proper operation.
CC
5. Input and output parameters vary 1:1 with V
.
CC
6. V , V , V and V parameters must be complied with simultaneously.
th
IH
IL,,
ISE
7. V is applied to the complementary input when operating in single−ended mode.
th
IHD
CMR
input signal.
8. V , V
V
and V
parameters must be complied with simultaneously.
ILD, ID
CMR
9. V
min varies 1:1 with V , V
maximum varies 1:1 with V . The V
range is referenced to the most positive side of the differential
EE CMR
CC
CMR
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NB6L11M
Table 5. AC CHARACTERISTICS V = 2.375 V to 3.63 V, V = 0 V, or V = 0 V, V = −2.375 V to −3.63 V, T = −40°C to
CC
EE
CC
EE
A
+85°C; (Note 10)
Symbol
Characteristic
Min
Typ
Max
Unit
V
Output Voltage Amplitude (@ V
(Note 15) (See Figure 9)
f
in
in
≤ 3.0GHz
in
230
190
150
380
320
270
mV
OUTPP
INPP(MIN)
f
≤ 3.5 GHz
≤ 4.0 GHz
f
t
t
Propagation Delay
D to Q
175
40
225
325
ps
ps
PD
SKEW
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
5.0
3.0
15
15
80
t
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
RMS Random Clock Jitter (Note 13)
f
≤ 4.0GHz
in
50
60
%
DC
t
ps
JITTER
f
in
≤ 4GHz
f ≤ 4Gb/s
in
0.2
40
0.5
Peak−to−Peak Data Dependent Jitter
(Note 14)
V
Input Voltage Swing/Sensitivity
150
2800
120
mV
ps
INPP
(Differential Configuration) (Note 15)
t
t
Output Rise/Fall Times @ 0.5 GHz
(20% − 80%)
Q, Q
70
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
(MIN) from a 50% duty cycle clock source. All loading with an external R = 50 W to V . Input edge rates 40 ps
INPP
L CC
(20% − 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz.
12.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swing is a single−ended measurement operating in differential mode.
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NB6L11M
VTD
50 W
V
CC
R
C
R
C
D
I
D
50 W
VTD
Figure 3. Input Structure
V
CC
V
V
D
IHmax
ILmax
V
thmax
V
IH
V
th
IL
V
V
V
IH
th
IL
V
th
V
V
D
V
V
thmin
IHmin
ILmin
V
V
th
EE
Figure 5. Vth Diagram
Figure 4. Differential Input Driven
Single−Ended
D
D
V
= |V
− V
ID
IHD(D) ILD(D)|
D
V
IHD
D
V
ILD
Figure 6. Differential Inputs
Driven Differentially
Figure 7. Differential Inputs Driven Differentially
V
CC
V
V
V
IHD(MAX)
ILD(MAX)
D
V
V
= V (D) − V (D)
IH IL
INPP
D
Q
IHD
V
V
= V
− V
IHD ILD
CMR
ID
V
ILD
= V (Q) − V (Q)
OUTPP
OH
OL
Q
V
V
IHD(MIN)
IL(MIN)
t
PD
t
PD
GND
Figure 8. VCMR Diagram
Figure 9. AC Reference Measurement
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NB6L11M
V
V
V
V
CC
CC
CC
CC
NB6L11M
NB6L11M
Z
= 50 W
Z
Z
= 50 W
O
O
D
D
D
D
50 W
50 W
50 W
50 W
LVPECL
Driver
LVDS
Driver
VT = V − 2 V
O
V = Open
T
= 50 W
O
CC
= 50 W
Z
V
V
EE
EE
V
V
EE
EE
Figure 10. LVPECL Interface
Figure 11. LVDS Interface
V
V
CC
CC
NB6L11M
Z
= 50 W
O
D
50 W
50 W
CML
Driver
V
= V
CC
T
Z
= 50 W
O
D
V
EE
V
EE
Figure 12. Standard 50 W Load CML Interface
V
V
V
V
CC
CC
CC
CC
NB6L11M
NB6L11M
Z
= 50 W
Z = 50 W
O
O
D
D
D
D
50 W
50 W
50 W
Differential
Driver
Single−Ended
VT = V
= 50 W
*
VT = V
*
REFAC
REFAC
Driver
Z
50 W
O
(Open)
V
V
V
V
EE
EE
EE
EE
Figure 13. Capacitor−Coupled
Figure 14. Capacitor−Coupled
Single−Ended Interface
Differential Interface
(VT Connected to VREFAC
)
(VT Connected to VREFAC)
*V
bypassed to ground with a 0.01 mF capacitor
REFAC
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NB6L11M
V
CC
800
700
600
500
400
300
50 W
50 W
Q
Q
200
100
0
0
1
2
3
4
f
, CLOCK OUTPUT FREQUENCY (GHz)
out
16 mA
Figure 15. Output Voltage Amplitude (VOUTPP) versus Output
Frequency at Ambient Temperature (Typical)
V
EE
Figure 16. CML Output Structure
V
CC
50 W
Z = 50 W
50 W
Q
Q
D
DUT
Driver
Device
Receiver
Device
Z = 50 W
D
Figure 17. Typical CML Termination for Output Driver and Device Evaluation
ORDERING INFORMATION
†
Device
Package
Shipping
NB6L11MMNG
QFN−16 (Pb−free)
QFN−16 (Pb−free)
123 Units / Rail
NB6L11MMNR2G
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB6L11M
PACKAGE DIMENSIONS
16 PIN QFN
MN SUFFIX
CASE 485G−01
ISSUE C
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
PIN 1
LOCATION
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
5.
L
CONDITION CAN NOT VIOLATE 0.2 MM
max
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
0.15
C
TOP VIEW
MILLIMETERS
0.15
C
DIM MIN
0.80
A1 0.00
MAX
1.00
0.05
A
(A3)
0.10
0.08
C
C
A3
b
D
0.20 REF
0.18
3.00 BSC
0.30
A
D2 1.65
1.85
E
3.00 BSC
SEATING
PLANE
16 X
E2 1.65
1.85
SIDE VIEW
D2
A1
e
K
L
0.50 BSC
0.18 TYP
0.30 0.50
C
SOLDERING FOOTPRINT*
e
L
16X
EXPOSED PAD
5
8
3.25
0.128
0.30
NOTE 5
0.575
0.022
4
9
EXPOSED PAD
0.012
E2
e
K
16X
12
1
16
13
1.50
0.059
3.25
0.128
16X b
0.10
0.05
C
C
A
B
BOTTOM VIEW
NOTE 3
0.30
0.012
0.50
0.02
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Email: orderlit@onsemi.com
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2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NB6L11M/D
相关型号：
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