NB6L11DT [ONSEMI]
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR; 2.5V / 3.3V多级输入至差分LVPECL / LVNECL 1 ： 2时钟或数据扇出缓冲器/翻译
| 型号： | NB6L11DT |
| 厂家： | 
ONSEMI |
| 描述： | 2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR |
| 文件： | 总12页 (文件大小：115K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢄ
ꢅꢆ ꢇ ꢈꢉ ꢊ ꢆ ꢊꢈ ꢋ ꢌꢍ ꢎꢏ ꢍꢐ ꢑ ꢐꢍ ꢒꢓꢔꢌ ꢎ ꢎꢕ
ꢖ ꢏꢗꢗ ꢐꢘꢐꢓ ꢎꢏ ꢙꢍ ꢃꢈꢚ ꢛꢜ ꢃ ꢉ ꢃꢈꢀ ꢛꢜ ꢃ
ꢄ
ꢡ
ꢝ ꢅꢞꢜ ꢍꢕ ꢟꢠ ꢕꢘ ꢖꢙꢎ ꢙ
ꢙ ꢓꢕ ꢌꢎ ꢁ ꢌꢗꢗ ꢐꢘ ꢉꢢꢘ ꢙꢓꢣ ꢍ ꢙꢎ ꢕꢘ
http://onsemi.com
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
MARKING DIAGRAMS*
8
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complimentary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
8
6L11
ALYW
1
SO−8
D SUFFIX
CASE 751
1
• Maximum Input Clock Frequency w 6 GHz Typical
• Maximum Input Data Rate w 6 Gb/s Typical
• Low 14 mA Typical Power Supply Current
• 150 ps Typical Propagation Delay
8
1
8
6L11
ALYW
1
TSSOP−8
DT SUFFIX
CASE 948R
• 5 ps Typical Within Device Skew
• 75 ps Typical Rise/Fall Times
• PECL Mode Operating Range: V
= 2.375 V to 3.465 V
CC
A = Assembly Location
L = Wafer Lot
with V = 0 V
EE
Y = Year
W = Work Week
• NECL Mode Operating Range: V = 0 V
CC
with V = −2.375 V to −3.465 V
EE
• Open Input Default State
• Q Outputs Will Default LOW with Inputs Open or at V
*For additional marking information, refer to
Application Note AND8002/D.
EE
• LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
ORDERING INFORMATION
†
Device
NB6L11D
Package
Shipping
SO−8
98 Units/Rail
NB6L11DR2
SO−8
2500/
Tape & Reel
NB6L11DT**
TSSOP−8 100 Units/Rail
NB6L11DTR2**
TSSOP−8
2500/
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
**Future Product − Contact factory for availability.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
April, 2004 − Rev. 2
NB6L11/D
NB6L11
Q0
Q0
1
2
8
7
V
CC
R
R
2
D
D
R
R
1
1
6
5
Q1
Q1
3
4
2
V
EE
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
Non−inverted differential clock/data output 0. Typically
1
Q0
ECL Output
−
terminated with 50 W Resistor to V = V − 2 V.
TT
CC
2
3
4
Q0
Q1
Q1
ECL Output
ECL Output
ECL Output
−
−
−
−
Inverted differential clock/data output 0. Typically termi-
nated with 50 W resistor to V = V − 2 V.
TT
CC
Non−inverted differential clock/data output 1. Typically
terminated with 50 W resistor to V = V − 2 V.
TT
CC
Inverted differential clock/data output 1. Typically termi-
nated with 50 W resistor to V = V − 2 V.
TT
CC
5
6
V
EE
−
Negative power supply voltage
D
LVDS, CML, LVPECL,
LVNECL, LVCMOS,
LVTTL Input
HIGH
Inverted differential clock/data input. Internal 37.5 kW to
and 75 kW to V
V
CC
.
EE
7
8
D
LVDS, CML, LVPECL,
LVNECL, LVCMOS,
LVTTL Input
LOW
−
Non−inverted differential clock/data input. Internal
75 kW to V and 37.5 kW to V
.
CC
EE
V
CC
−
Positive power supply voltage
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Default State Resistor
Internal Input Default State Resistor
ESD Protection
(R )
37.5 kW
75 kW
1
(R )
2
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 1 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
http://onsemi.com
2
NB6L11
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
3.6
Unit
V
V
CC
V
EE
V
I
Positive Power Supply
Negative Power Supply
V
V
= 0 V
= 0 V
EE
−3.6
V
CC
Positive Input Voltage
Negative Input Voltage
V
V
= 0 V
= 0 V
V v V
3.6
V
V
EE
I
CC
V w V
−3.6
CC
I
EE
V
INPP
Differential Input Voltage
|D − D|
V
CC
V
CC
− V w 2.8 V
2.8
|V − V
CC
V
EE
− V t 2.8 V
|
EE
EE
I
Output Current
Continuous
Surge
25
50
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
500 lfpm
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
0 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
500 lfpm
q
Thermal Resistance (Junction−to−Case)
Wave Solder
Standard Board
TSSOP−8
41 to 44
265
°C/W
°C
JC
T
sol
< 2 to 3 sec @ 248°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not im-
plied, damage may occur and reliability may be affected.
http://onsemi.com
3
NB6L11
Table 4. DC CHARACTERISTICS, PECL V = 2.5 V, V = 0 V (Note 4)
CC
EE
−40°C
Typ
14
25°C
Typ
14
85°C
Typ
14
Min
5
Max
Min
5
Max
Min
5
Max
Symbol
Characteristic
Unit
mA
mV
mV
I
EE
Negative Power Supply Current (Note 5)
Output HIGH Voltage (Note 6)
20
20
20
V
V
1350
630
1450 1550
750 870
1400
680
1500 1600
1450
730
1550 1650
OH
Output LOW Voltage (Note 6)
800
920
850
970
OL
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
V
th
V
IH
V
IL
Input Threshold Reference Voltage Range
(Note 2)
1125
V
−75
1125
V
−75
1125
V
CC
−75
mV
mV
mV
CC
CC
Single−Ended Input HIGH Voltage
V
th
V
CC
V
th
V
CC
V
th
V
CC
+75
+75
+75
Single−Ended Input LOW Voltage
V
EE
V
−75
V
EE
V
−75
V
EE
V
th
−75
th
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
V
IHD
V
ILD
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
V
V
1200
V
V
1200
V
V
mV
mV
CC
CC
CC
V
EE
V
EE
V
EE
CC
CC
CC
−75
−75
−75
V
V
Input Common Mode Range
(Differential Cross−Point Voltage) (Note 3)
1163
75
V
−38
1163
75
V
−38
1163
75
V
CC
−38
mV
CMR
CC
CC
Differential Input Voltage (V
Input HIGH Current
− V
)
2500
2500
2500
mV
ID
IHD
ILD
I
IH
D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
I
IL
Input LOW Current
D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. V is applied to the complementary input when operating in single−ended mode.
th
3. V
minimum varies 1:1 with V , V
maximum varies 1:1 with V
.
CMR
EE
CMR
CC
4. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −1.3 V.
CC
EE
5. All input and output pins left open.
6. All loading with 50 W to V − 2.0 V.
CC
http://onsemi.com
4
NB6L11
Table 5. DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 9)
CC
EE
−40°C
Typ
14
25°C
Typ
14
85°C
Typ
14
Min
5
Max
Min
5
Max
Min
5
Max
Symbol
Characteristic
Unit
mA
mV
mV
I
EE
Negative Power Supply Current (Note 10)
Output HIGH Voltage (Note 11)
20
20
20
V
V
2150
1430
2250 2350
1550 1670
2200
1480
2300 2400
1600 1720
2250
1530
2350 2450
1650 1770
OH
Output LOW Voltage (Note 11)
OL
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
V
th
V
IH
V
IL
Input Threshold Reference Voltage Range
(Note 7)
1125
V
−75
1125
V
−75
1125
V
CC
−75
mV
mV
mV
CC
CC
Single−Ended Input HIGH Voltage
V
th
V
CC
V
th
V
CC
V
th
V
CC
+75
+75
+75
Single−Ended Input LOW Voltage
V
EE
V
−75
V
EE
V
−75
V
EE
V
th
−75
th
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
V
IHD
V
ILD
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
V
V
1200
V
V
1200
V
V
mV
mV
CC
CC
CC
V
EE
V
EE
V
EE
CC
CC
CC
−75
−75
−75
V
V
Input Common Mode Range
(Differential Cross−Point Voltage) (Note 8)
1163
75
V
−38
1163
75
V
−38
1163
75
V
CC
−38
mV
CMR
CC
CC
Differential Input Voltage (V
Input HIGH Current
− V
)
2500
2500
2500
mV
ID
IHD
ILD
I
IH
D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
I
IL
Input LOW Current
D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. V is applied to the complementary input when operating in single−ended mode.
th
8. V
minimum varies 1:1 with V , V
maximum varies 1:1 with V
.
CMR
EE
CMR
CC
9. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
10.All input and output pins left open.
11. All loading with 50 W to V − 2.0 V.
CC
http://onsemi.com
5
NB6L11
Table 6. DC CHARACTERISTICS, NECL V = 0 V; V = −3.465 V to −2.375 V (Note 14)
CC
EE
−40°C
25°C
Typ
14
85°C
Typ
14
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
I
EE
Negative Power Supply Current
(Note 15)
5
14
20
5
20
5
20
mA
V
V
Output HIGH Voltage (Note 16)
Output LOW Voltage (Note 16)
−1150 −1050 −950 −1100 −1000 −900 −1050 −950
−850
mV
OH
−1870 −1750 −1630 −1820 −1700 −1580 −1770 −1650 −1530 mV
OL
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
V
th
V
IH
V
IL
Input Threshold Reference Voltage
Range (Note 12)
V
V
−75
V
V
−75
V
V
CC
−75
mV
mV
mV
EE
CC
EE
CC
EE
+1125
+1125
+1125
Single−Ended Input HIGH Voltage
V
+75
V
CC
V
+75
V
CC
V
+75
V
CC
th
th
th
Single−Ended Input LOW Voltage
V
EE
V
−75
V
EE
V
−75
V
EE
V
th
−75
th
th
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
V
V
V
Differential Input HIGH Voltage
V
V
V
V
V
V
V
V
V
mV
mV
mV
IHD
EE
CC
EE
CC
EE
CC
+1200
+1200
+1200
Differential Input LOW Voltage
V
EE
V
EE
V
EE
ILD
CC
CC
CC
−75
−75
−75
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 13)
V
EE
V
CC
V
EE
V
CC
V
EE
V
CC
−38
CMR
+1163
75
−38
+1163
75
−38
+1163
75
V
ID
Differential Input Voltage (V
−
2500
2500
2500
mV
mA
mA
IHD
V
ILD
)
I
IH
Input HIGH Current
Input LOW Current
D
D
50
10
150
150
50
10
150
150
50
10
150
150
I
IL
D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
12.V is applied to the complementary input when operating in single−ended mode.
th
13.V
minimum varies 1:1 with V , V
maximum varies 1:1 with V
CMR CC
CMR
EE
14.Input and output parameters vary 1:1 with V
15.Input and output pins left open.
.
CC
16.All loading with 50 W to V − 2.0 V.
CC
http://onsemi.com
6
NB6L11
Table 7. AC CHARACTERISTICS V = 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V (Note 17)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figures 2 & 3)
f
in
f
in
v 3 GHz 480
v 6 GHz 270
700
300
480
270
700
300
480
270
700
300
mV
OUTPP
t
t
,
Propagation Delay to
Output Differential @ 1 GHz
ps
ps
PLH
PHL
D to Q, Q 110
(Note 18)
150
190
110
150
200
120
160
220
t
Duty Cycle Skew
Within Device Skew
Device−to−Device Skew
2
5
15
10
15
60
2
5
15
10
15
60
2
5
15
10
15
60
SKEW
t
RMS Random Clock Jitter
(Note 19)
Peak−to−Peak Data Dependent Jitter
(Note 20)
ps
JITTER
f
v 6 GHz
0.2
2
1
0.2
2
1
0.2
2
1
in
f
in
v 6 Gb/s
12
12
12
V
Input Voltage Swing / Sensitivity
(Differential Configuration) (Note 21)
75
700 2500
75
30
700 2500
75
30
700 2500 mV
INPP
t
r
t
f
Output Rise/Fall Times @ 1 GHz
(20% − 80%)
Q, Q
30
75
120
75
120
75
120
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
17.Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V. Input edge rates 40 ps (20% − 80%).
CC
18.See Figure 9 t
= |t
− t
PHL
| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
skew
PLH
transitions and conditions @ 1 GHz.
19.Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
20.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2 −1 data rate at 6 Gb/s.
23
21.V
cannot exceed V − V (applicable only when V − V < 2500 mV). Input voltage swing is a single−ended measurement
INPP(max)
CC EE CC EE
operating in differential mode
0.8
0.7
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.6
0.5
−40°C
−40°C
0.4
25°C
25°C
0.3
0.2
0.1
0.0
85°C
85°C
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 3.3 V
)
Figure 3. Output Voltage Amplitude (VOUTPP
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 2.5 V
)
http://onsemi.com
7
NB6L11
TIME (64 ps/div)
TIME (32 ps/div)
Figure 4. Typical Output Waveform at
2.488 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 17 ps. Device Pk−Pk Jitter
Contribution is 4 ps)
Figure 5. Typical Output Waveform at
6.125 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 20 ps. Device Pk−Pk Jitter
Contribution is 5 ps)
NOTE:
V − V = 3.3 V; V = 700 mV; T = 25°C.
CC EE IN A
210
190
170
150
130
110
120
110
100
90
80
70
60
50
40
30
85°C
85°C
25°C
−40°C
−40°C
25°C
2.375
2.5
3.3
3.465
2.375
2.5
3.3
3.465
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY VOLTAGE (V)
Figure 6. Propagation Delay versus Power
Supply Voltage and Temperature
Figure 7. Rise/Fall Time versus Power Supply
Voltage and Temperature
20
17
V
CC
− V = −3.465 V
EE
14
11
8
V
CC
− V = −2.375 V
EE
5
−40
25
85
TEMPERATURE (°C)
Figure 8. IEE Current versus Temperature and
Power Supply Voltage
http://onsemi.com
8
NB6L11
D
V
INPP
V
INPP
(D) = V (D) − V (D)
IH IL
(D) = V (D) − V (D)
IH
IL
D
Q
V
V
(Q) = V (Q) − V (Q)
OH OL
OUTPP
OUTPP
(Q) = V (Q) − V (Q)
OH
OL
Q
t
PHL
t
PLH
Figure 9. AC Reference Measurement
D
D
V
th
D
D
V
th
Figure 10. Differential Input Driven
Single−Ended
Figure 11. Differential Inputs Driven
Differentially
V
CC
thmax
V
CC
V
V
IHmax
V
V
IHDmax
V
V
CMmax
ILDmax
ILmax
V
= V − V
IHD ILD
ID
V
IH
V
th
V
IL
V
CMR
V
IHDtyp
ILDtyp
V
th
V
V
V
IHmin
V
IHDmin
V
V
thmin
CMmax
V
ILmin
ILDmin
GND
GND
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
Z = 50 W
o
Q
D
Receiver
Device
Driver
Device
Q
Z = 50 W
o
D
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 14. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
http://onsemi.com
9
NB6L11
Resource Reference of Application Notes
AN1405
AN1568
AN1650
−
−
−
ECL Clock Distribution Techniques
Interfacing Between LVDS and ECL
Using Wire−OR Ties in ECLinPS De-
signs
AN1672
−
−
−
−
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
AND8001
AND8002
AND8003
Storage and Handling of Drypack Sur-
face Mount Device
AND8020
AND8072
−
−
Termination of ECL Logic Devices
Thermal Analysis and Reliability of
Wire Bonded ECL
AND8066
AND8090
−
−
Interfacing with ECLinPS
AC Characteristics of ECL Devices
For an updated list of Application Notes, please
see our website at http://onsemi.com.
http://onsemi.com
10
NB6L11
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
ISSUE AB
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
ꢇ
ꢇ
B
ꢀꢁ ꢉꢊ ꢃꢄ ꢀ ꢁꢀ ꢂꢀꢆ
ꢈ
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
ꢀ
ꢁ
ꢂ
ꢀ
ꢃ
ꢄ
ꢀ
ꢁ
ꢀ
ꢀ
ꢅ
ꢆ
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
ꢇ
ꢌ
ꢌ
ꢍ
ꢀ
ꢁ
ꢉ
ꢊ
ꢃ
ꢄ
ꢀ
ꢁ
ꢀ
ꢂ
ꢀ
ꢆ
ꢋ
ꢈ
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
SO−8
http://onsemi.com
11
NB6L11
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
ꢘ ꢙ ꢖꢚ ꢌ ꢛ
ꢂꢁ ꢜ ꢝ ꢇꢚꢘ ꢌ ꢝꢙ ꢘ ꢝ ꢘ ꢞ ꢟ ꢘꢜ ꢖꢙ ꢠꢚ ꢡ ꢟꢘ ꢔ ꢝ ꢘ ꢞ ꢢ ꢚꢡ ꢟꢘ ꢌ ꢝ
ꢈ ꢂꢅꢁ ꢊꢇꢣ ꢂꢎꢐ ꢉꢁ
ꢇ
ꢌ
ꢌ
ꢗ
ꢀꢁ ꢂꢀ ꢃꢄ ꢀ ꢁꢀ ꢀꢅ ꢆ
ꢖ ꢕ
ꢌ
ꢀ ꢁꢂ ꢊꢃ ꢄꢀ ꢁꢀ ꢀ ꢑꢆ ꢖ ꢕ
ꢉꢁ ꢔ ꢙ ꢘ ꢖꢡ ꢙ ꢠꢠ ꢝꢘ ꢞ ꢜ ꢝ ꢇꢚꢘ ꢌ ꢝꢙ ꢘ ꢛ ꢇꢝ ꢠꢠꢝ ꢇꢚ ꢖꢚ ꢡ ꢁ
ꢏꢁ ꢜ ꢝ ꢇꢚꢘ ꢌ ꢝꢙ ꢘ ꢟ ꢜ ꢙ ꢚꢌ ꢘ ꢙ ꢖ ꢝ ꢘ ꢔꢠ ꢕ ꢜ ꢚ ꢇꢙ ꢠꢜ ꢤꢠ ꢟꢌꢥ ꢁ
ꢢ ꢡ ꢙꢖ ꢡ ꢕ ꢌꢝ ꢙ ꢘ ꢌ ꢙ ꢡ ꢞ ꢟꢖ ꢚ ꢓ ꢕꢡ ꢡ ꢌ ꢁ ꢇꢙ ꢠ ꢜ ꢤꢠ ꢟꢌꢥ
ꢙ ꢡ ꢞ ꢟꢖ ꢚ ꢓ ꢕꢡ ꢡ ꢌ ꢌ ꢥꢟ ꢠꢠ ꢘ ꢙ ꢖ ꢚ ꢍꢔ ꢚ ꢚꢜ ꢀ ꢁꢂ ꢊ
ꢄꢀ ꢁꢀꢀ ꢑꢆ ꢢ ꢚꢡ ꢌ ꢝꢜ ꢚ ꢁ
ꢅꢁ ꢜ ꢝ ꢇꢚꢘ ꢌ ꢝꢙ ꢘ ꢓ ꢜ ꢙ ꢚꢌ ꢘ ꢙ ꢖ ꢝ ꢘ ꢔꢠ ꢕ ꢜ ꢚ ꢝ ꢘ ꢖ ꢚꢡ ꢠꢚ ꢟꢜ
ꢤ ꢠꢟꢌ ꢥ ꢙ ꢡ ꢢ ꢡꢙ ꢖ ꢡ ꢕ ꢌꢝ ꢙ ꢘ ꢁ ꢝ ꢘ ꢖꢚ ꢡ ꢠꢚ ꢟꢜ ꢤꢠ ꢟꢌꢥ ꢙ ꢡ
ꢢ ꢡ ꢙꢖ ꢡ ꢕ ꢌꢝ ꢙ ꢘ ꢌ ꢥ ꢟꢠꢠ ꢘ ꢙ ꢖ ꢚ ꢍꢔ ꢚ ꢚꢜ ꢀꢁ ꢉꢊ ꢄꢀ ꢁꢀ ꢂꢀ ꢆ
ꢢ ꢚꢡ ꢌ ꢝꢜ ꢚ ꢁ
2X L/2
8
5
4
ꢀ ꢁ ꢉꢊ ꢃ ꢄꢀ ꢁ ꢀꢂ ꢀ ꢆ
B
−U−
L
1
M
PIN 1
IDENT
ꢊꢁ ꢖ ꢚꢡ ꢇꢝ ꢘ ꢟꢠ ꢘ ꢕ ꢇꢓ ꢚꢡ ꢌ ꢟ ꢡꢚ ꢌ ꢥ ꢙꢦ ꢘ ꢤ ꢙꢡ
ꢡ ꢚꢤ ꢚ ꢡ ꢚꢘ ꢔ ꢚ ꢙ ꢘ ꢠꢈꢁ
ꢑꢁ ꢜ ꢝ ꢇꢚꢘ ꢌ ꢝ ꢙꢘ ꢟ ꢟ ꢘꢜ ꢓ ꢟ ꢡ ꢚ ꢖꢙ ꢓ ꢚ ꢜ ꢚꢖ ꢚ ꢡ ꢇꢝ ꢘ ꢚꢜ
ꢟ ꢖ ꢜ ꢟꢖ ꢕ ꢇ ꢢ ꢠꢟꢘ ꢚ ꢧꢦꢧ ꢁ
ꢌ
ꢀ ꢁꢂ ꢊꢃ ꢄꢀ ꢁꢀ ꢀ ꢑꢆ ꢖ ꢕ
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
ꢏꢁ ꢂꢀ
ꢏꢁ ꢂꢀ
MAX
ꢀꢁ ꢂꢉꢉ
ꢀꢁ ꢂꢉ ꢉ
ꢀꢁ ꢀꢅ ꢏ
ꢀꢁ ꢀꢀ ꢑ
ꢀꢁ ꢀꢉ ꢐ
A
B
C
D
F
ꢉꢁ ꢎꢀ
ꢉꢁ ꢎꢀ
ꢀꢁ ꢐꢀ
ꢀꢁ ꢀꢊ
ꢀꢁ ꢅꢀ
ꢀꢁ ꢂꢂꢅ
ꢀꢁ ꢂꢂꢅ
C
ꢂꢁ ꢂꢀ ꢀꢁ ꢀꢏꢂ
ꢀꢁ ꢂꢊ ꢀꢁ ꢀꢀꢉ
ꢀꢁ ꢒꢀ ꢀꢁ ꢀꢂꢑ
ꢀ ꢁꢂ ꢀꢃ ꢄꢀ ꢁꢀ ꢀꢅꢆ
−W−
SEATING
PLANE
D
−T−
G
G
K
L
ꢀꢁ ꢑꢊꢃ ꢓ ꢌꢔ
ꢀꢁ ꢀꢉꢑ ꢃꢓ ꢌꢔ
ꢀꢁ ꢉꢊ
ꢀꢁ ꢅꢀ ꢀꢁ ꢀꢂꢀ
ꢀ
ꢁ
ꢀ
ꢂ
ꢑ
ꢅꢁ ꢎꢀꢃ ꢓ ꢌꢔ
ꢀꢃ ꢃꢃ
ꢀꢁ ꢂꢎꢏ ꢃꢓ ꢌꢔ
ꢀꢃ ꢃꢃ
DETAIL E
M
ꢑꢃ ꢃꢃ ꢃ
_
ꢑ ꢃꢃꢃ
_
_
_
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NB6L11/D
相关型号：
NB6L11DTG
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
NB6L11DTR2
2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR
ONSEMI
NB6L11DTR2G
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
NB6L11M_07
2.5V / 3.3V 1:2 Differential CML Fanout Buffer Multi−Level Inputs w/ Internal Termination
ONSEMI
NB6L11_06
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator
ONSEMI
©2020 ICPDF网 联系我们和版权申明