NB6L11DR2G [ONSEMI]
2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator; 2.5 V / 3.3 V的多级输入至差分LVPECL / LVNECL 1 ： 2时钟或数据扇出缓冲器/翻译
| 型号： | NB6L11DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2 Clock or Data Fanout Buffer/Translator |
| 文件： | 总12页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB6L11
2.5 V/3.3 V Multilevel Input to
Differential LVPECL/LVNECL
1:2 Clock or Data
Fanout Buffer/Translator
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MARKING
The NB6L11 is an enhanced differential 1:2 clock or data fanout
buffer/translator. The device has the same pinout and is functionally
equivalent to the LVEL11, EP11, LVEP11 devices. Moreover, the
device is optimized for the systems that require LOW skew, LOW
jitter and LOW power consumption.
DIAGRAMS*
8
Differential input can be configured to accept single−ended signal
by applying an external reference voltage to unused complementary
input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS,
CML, or LVDS. The outputs are 800 mV ECL signals.
8
6L11
ALYW G
1
G
SO−8
1
D SUFFIX
CASE 751
Features
8
• Maximum Input Clock Frequency w 6 GHz Typical
• Maximum Input Data Rate w 6 Gb/s Typical
• Low 14 mA Typical Power Supply Current
• 150 ps Typical Propagation Delay
8
6L11
1
ALYW G
TSSOP−8
DT SUFFIX
CASE 948R
G
1
• 5 ps Typical Within Device Skew
• 75 ps Typical Rise/Fall Times
• PECL Mode Operating Range:
A
L
Y
W
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
V
CC
= 2.375 V to 3.465 V with V = 0 V
EE
• NECL Mode Op rating Range:
= 0 V with V = −2.375 V to −3.465 V
(Note: Microdot may be in either location)
V
CC
EE
• Open Input Default State
• Q Outputs Will Default LOW with Inputs Open or at V
*For additional marking information, refer to
Application Note AND8002/D.
EE
• LVDS, LVPECL, LVNECL, LCMOS, LVTTL and CML Input
Compatible
• Pb−Free Packages are Available
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 6
NB6L11/D
NB6L11
Q0
Q0
1
2
8
7
V
CC
R
R
2
D
D
R
R
1
1
6
5
Q1
Q1
3
4
2
V
EE
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
Pin
Name
I/O
Default State
Description
1
Q0
ECL Output
ECL Output
ECL Output
ECL Output
−
−
−
−
−
Non−inverted differential clock/data output 0. Typically termi-
nated with 50 W Resistor to V = V − 2 V.
TT
CC
2
3
4
Q0
Q1
Q1
Inverted differential clock/data output 0. Typically terminated with
50 W resistor to V = V − 2 V.
TT
CC
Non−inverted differential clock/data output 1. Typically termi-
nated with 50 W resistor to V = V − 2 V.
TT
CC
Inverted differential clock/data output 1. Typically terminated with
50 W resistor to V = V − 2 V.
TT
CC
5
6
V
−
Negative power supply voltage
Inverted differential clock/data input. Internal 37.5 kW to V and
EE
D
LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
HIGH
CC
75 kW to V .
EE
7
8
D
LVDS, CML, LVPECL, LVNECL,
LVCMOS, LVTTL Input
LOW
Non−inverted differential clock/data input. Internal 75 kW to V
CC
and 37.5 kW to V
.
EE
V
−
−
Positive power supply voltage
CC
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
37.5 kW
75 kW
Human Body Model
> 2 kV
> 100 V
> 1 kV
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
TSSOP−8
Level 1
Level 1
Level 1
Level 3
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
167 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
NB6L11
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
3.6
Unit
V
V
V
V
Positive Power Supply
Negative Power Supply
V
V
= 0 V
= 0 V
CC
EE
I
EE
CC
−3.6
V
Positive Input Voltage
Negative Input Voltage
V
V
= 0 V
= 0 V
V v V
3.6
−3.6
V
V
EE
CC
I
CC
V w V
I
EE
V
Differential Input Voltage
|D − D|
V
V
− V w 2.8 V
2.8
CC
V
INPP
CC
CC
EE
− V t 2.8 V
|V − V
|
EE
EE
I
Output Current
Continuous
Surge
25
50
mA
mA
out
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
°C
°C
A
T
−65 to +150
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−8
SOIC−8
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
SOIC−8
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
Standard Board
TSSOP−8
41 to 44
°C/W
°C
JC
T
sol
Wave Solder
Standard v 3 sec @ 248°C
Pb−Free v 3 sec @ 260°C
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
NB6L11
Table 4. DC CHARACTERISTICS, PECL V = 2.5 V, V = 0 V (Note 4)
CC
EE
−40°C
25°C
Typ
14
85°C
Typ
14
Min
5
Typ
Max
Min
5
Max
Min
5
Max
Symbol
Characteristic
Unit
mA
mV
mV
I
Negative Power Supply Current (Note 5)
Output HIGH Voltage (Note 6)
14
20
20
20
EE
V
V
1350
565
1450 1550
725 870
1400
630
1500 1600
1450
690
1550 1650
OH
OL
Output LOW Voltage (Note 6)
765
920
825
970
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
V
V
V
Input Threshold Reference Voltage Range
(Note 2)
1125
V
1125
V
1125
V
CC
mV
mV
mV
th
IH
IL
CC
CC
−75
−75
−75
Single−Ended Input HIGH Voltage
V
V
V
V
V
V
CC
th
CC
th
CC
th
+75
+75
+75
Single−Ended Input LOW Voltage
V
V
−75
V
V
−75
V
V
th
−75
EE
th
EE
th
EE
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
V
V
1200
V
V
1200
V
V
mV
mV
IHD
ILD
CC
CC
CC
CC
CC
CC
V
V
V
EE
EE
EE
−75
−75
−75
V
V
Input Common Mode Range
1163
75
V
1163
75
V
1163
75
V
CC
mV
CMR
ID
CC
CC
(Differential Cross−Point Voltage) (Note 3)
−38
−38
−38
Differential Input Voltage (V
Input HIGH Current
− V )
ILD
2500
2500
2500
mV
IHD
I
D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
IH
I
Input LOW Current
D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
2. V is applied to the complementary input when operating in single−ended mode.
th
CMR
3. V
minimum varies 1:1 with V , V
maximum varies 1:1 with V
.
EE
CMR
CC
4. Input and output parameters vary 1:1 with V . V can vary +0.125 V to −1.3 V.
CC
EE
5. All input and output pins left open.
6. All loading with 50 W to V − 2.0 V.
CC
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4
NB6L11
Table 5. DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 9)
CC
EE
−40°C
25°C
Typ
14
85°C
Typ
14
Min
5
Typ
Max
Min
5
Max
Min
5
Max
Symbol
Characteristic
Unit
mA
mV
mV
I
Negative Power Supply Current (Note 10)
Output HIGH Voltage (Note 11)
14
20
20
20
EE
V
V
2150
1365
2250 2350
1525 1670
2200
1430
2300 2400
1565 1720
2250
1490
2350 2450
1625 1770
OH
OL
Output LOW Voltage (Note 11)
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
V
V
V
Input Threshold Reference Voltage Range
(Note 7)
1125
V
1125
V
1125
V
CC
mV
mV
mV
th
IH
IL
CC
CC
−75
−75
−75
Single−Ended Input HIGH Voltage
V
V
V
V
V
V
CC
th
CC
th
CC
th
+75
+75
+75
Single−Ended Input LOW Voltage
V
V
−75
V
V
−75
V
V
th
−75
EE
th
EE
th
EE
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
1200
V
V
1200
V
V
1200
V
V
mV
mV
IHD
ILD
CC
CC
CC
CC
CC
CC
V
V
V
EE
EE
EE
−75
−75
−75
V
V
Input Common Mode Range
1163
75
V
1163
75
V
1163
75
V
CC
mV
CMR
ID
CC
CC
(Differential Cross−Point Voltage) (Note 8)
−38
−38
−38
Differential Input Voltage (V
Input HIGH Current
− V )
ILD
2500
2500
2500
mV
IHD
I
D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
IH
I
Input LOW Current
D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
7. V is applied to the complementary input when operating in single−ended mode.
th
CMR
8. V
minimum varies 1:1 with V , V
maximum varies 1:1 with V
.
EE
CMR
CC
9. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
10.All input and output pins left open.
11. All loading with 50 W to V − 2.0 V.
CC
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5
NB6L11
Table 6. DC CHARACTERISTICS, NECL V = 0 V; V = −3.465 V to −2.375 V (Note 14)
CC
EE
−40°C
25°C
Typ
14
85°C
Typ
14
Min
Typ
Max
Min
Max
Min
Max
Symbol
Characteristic
Unit
I
Negative Power Supply Current
(Note 15)
5
14
20
5
20
5
20
mA
EE
V
V
Output HIGH Voltage (Note 16)
Output LOW Voltage (Note 16)
−1150 −1050 −950 −1100 −1000 −900 −1050 −950
−850
mV
OH
OL
−1935 −1775 −1630 −1870 −1735 −1580 −1810 −1675 −1530 mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 10, 12)
V
V
V
Input Threshold Reference Voltage
Range (Note 12)
V
V
V
V
V
V
CC
mV
mV
mV
th
IH
IL
EE
CC
EE
CC
EE
+1125
−75
+1125
−75
+1125
−75
Single−Ended Input HIGH Voltage
V
+75
V
V
+75
V
V
+75
V
CC
th
CC
th
CC
th
Single−Ended Input LOW Voltage
V
V
−75
V
V
−75
V
V
th
−75
EE
th
EE
th
EE
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 11, 13)
V
V
V
Differential Input HIGH Voltage
Differential Input LOW Voltage
V
V
V
V
V
V
V
V
V
mV
mV
mV
IHD
ILD
EE
CC
CC
EE
CC
CC
EE
CC
CC
+1200
+1200
+1200
V
V
V
EE
EE
EE
−75
−75
−75
Input Common Mode Range
(Differential Cross−Point Voltage)
(Note 13)
V
V
−38
V
V
−38
V
V
CC
−38
CMR
EE
CC
EE
CC
EE
+1163
75
+1163
75
+1163
75
V
Differential Input Voltage (V
Input HIGH Current
− V )
ILD
2500
2500
2500
mV
ID
IHD
I
D
D
50
10
150
150
50
10
150
150
50
10
150
150
mA
IH
I
Input LOW Current
D
D
−150
−150
−5
−30
−150
−150
−5
−30
−150
−150
−5
−30
mA
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
12.V is applied to the complementary input when operating in single−ended mode.
th
CMR
13.V
minimum varies 1:1 with V , V
maximum varies 1:1 with V
CC
EE
CMR CC
14.Input and output parameters vary 1:1 with V
15.Input and output pins left open.
16.All loading with 50 W to V − 2.0 V.
.
CC
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6
NB6L11
Table 7. AC CHARACTERISTICS V = 0 V; V = −3.465 V to −2.375 V or V = 2.375 V to 3.465 V; V = 0 V (Note 17)
CC
EE
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
V
Output Voltage Amplitude
(See Figures 2 & 3)
f
f
v 3 GHz 480
v 6 GHz 270
700
300
480
270
700
300
480
270
700
300
mV
OUTPP
in
in
t
t
,
Propagation Delay to
ps
ps
PLH
PHL
Output Differential @ 1 GHz
D to Q, Q 110
(Note 18)
150
190
110
150
200
120
160
220
t
Duty Cycle Skew
Within Device Skew
Device−to−Device Skew
2
5
15
10
15
60
2
5
15
10
15
60
2
5
15
10
15
60
SKEW
t
RMS Random Clock Jitter
(Note 19)
Peak−to−Peak Data Dependent Jitter
(Note 20)
ps
JITTER
f
v 6 GHz
0.2
2
1
0.2
2
1
0.2
2
1
in
f
v 6 Gb/s
12
12
12
in
V
Input Voltage Swing / Sensitivity
75
700 2500
75
30
700 2500
75
30
700 2500 mV
INPP
(Differential Configuration) (Note 21)
t
t
Output Rise/Fall Times @ 1 GHz
Q, Q
30
75 120
75 120
75 120 ps
r
f
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
17.Measured using a 800 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V. Input edge rates 40 ps (20% − 80%).
CC
18.See Figure 9 t
= |t
− t
| for a nominal 50% differential clock input waveform. Skew is measured between outputs under identical
skew
PLH
PHL
transitions and conditions @ 1 GHz.
19.Additive RMS jitter with 50% duty cycle clock signal at 6 GHz.
23
20.Additive Peak−to−Peak data dependent jitter with NRZ PRBS 2 −1 data rate at 6 Gb/s.
21.V
cannot exceed V − V (applicable only when V − V < 2500 mV). Input voltage swing is a single−ended measurement
INPP(max)
CC EE CC EE
operating in differential mode
0.8
0.7
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.6
0.5
−40°C
85°C
−40°C
0.4
25°C
25°C
0.3
0.2
0.1
0.0
85°C
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (VOUTPP
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 3.3 V
)
Figure 3. Output Voltage Amplitude (VOUTPP
versus Input Clock Frequency (fIN) and
Temperature at VCC − VEE = 2.5 V
)
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7
NB6L11
TIME (64 ps/div)
TIME (32 ps/div)
Figure 4. Typical Output Waveform at
2.488 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 17 ps. Device Pk−Pk Jitter
Contribution is 4 ps)
Figure 5. Typical Output Waveform at
6.125 Gb/s with PRBS 223−1 (Total System
Pk−Pk Jitter is 20 ps. Device Pk−Pk Jitter
Contribution is 5 ps)
NOTE:
V
− V = 3.3 V; V = 700 mV; T = 25°C.
CC EE IN A
210
190
170
150
130
110
120
110
100
90
80
70
60
50
40
30
85°C
85°C
25°C
−40°C
−40°C
25°C
2.375
2.5
3.3
3.465
2.375
2.5
3.3
3.465
POWER SUPPLY VOLTAGE (V)
POWER SUPPLY VOLTAGE (V)
Figure 6. Propagation Delay versus Power
Supply Voltage and Temperature
Figure 7. Rise/Fall Time versus Power Supply
Voltage and Temperature
20
17
V
− V = −3.465 V
EE
CC
14
11
8
V
− V = −2.375 V
CC
EE
5
−40
25
85
TEMPERATURE (°C)
Figure 8. IEE Current versus Temperature and
Power Supply Voltage
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8
NB6L11
D
V
V
(D) = V (D) − V (D)
IH IL
INPP
INPP
(D) = V (D) − V (D)
IH
IL
D
Q
V
V
(Q) = V (Q) − V (Q)
OH OL
OUTPP
OUTPP
(Q) = V (Q) − V (Q)
OH
OL
Q
t
PHL
t
PLH
Figure 9. AC Reference Measurement
D
D
V
D
D
th
V
th
Figure 10. Differential Input Driven
Figure 11. Differential Inputs Driven
Differentially
Single−Ended
V
CC
thmax
V
CC
V
V
IHmax
ILmax
V
V
V
V
IHDmax
ILDmax
CMmax
V
= V − V
IHD ILD
ID
V
V
V
IH
th
IL
V
V
IHDtyp
ILDtyp
CMR
V
th
V
V
V
IHmin
ILmin
V
V
IHDmin
V
V
thmin
CMmax
ILDmin
GND
GND
Figure 12. Vth Diagram
Figure 13. VCMR Diagram
Z = 50 W
o
Q
D
Receiver
Device
Driver
Device
Q
Z = 50 W
o
D
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 14. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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9
NB6L11
ORDERING INFORMATION
†
Device
NB6L11D
Package
Shipping
SOIC−8
98 Units / Rail
98 Units / Rail
NB6L11DG
SOIC−8
(Pb−Free)
NB6L11DR2
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
NB6L11DR2G
SOIC−8
(Pb−Free)
NB6L11DT
TSSOP−8
100 Units / Rail
100 Units / Rail
NB6L11DTG*
TSSOP−8
(Pb−Free)
NB6L11DTR2
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
NB6L11DTR2G*
TSSOP−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*Future Product − Contact factory for availability.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
10
NB6L11
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
NB6L11
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
PLANE
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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