NB3V60113GV3 [ONSEMI]
1.8 V 12.288 MHz OmniClock Generator;
| 型号： | NB3V60113GV3 |
| 厂家： | 
ONSEMI |
| 描述： | 1.8 V 12.288 MHz OmniClock Generator |
| 文件： | 总7页 (文件大小：91K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3V60113GV3
1.8 V 12.288 MHz OmniClock
Generator with Single Ended
(LVCMOS) Output
The NB3V60113GV3, which is a member of the OmniClock family,
is a low power PLL−based clock generator. The device accepts a
6.144 MHz single ended (LVCMOS) reference clock as input. It
generates one single ended (LVCMOS) output of 12.288 MHz. The
device can be powered down using the Power Down pin (PD#).
www.onsemi.com
Features
• Member of the OmniClock Family of Programmable Clock
Generators
WDFN8
CASE 511AT
• Operating Power Supply: 1.8 V 0.1 V
MARKING DIAGRAM
• I/O Standards
1
♦ Input: 6.144 MHz Reference Clock (LVCMOS)
♦ Output: 12.288 MHz (LVCMOS)
V3MG
G
• Output Drive Current for Single Ended Output: 8 mA
• Power Saving Mode through Power Down Pin
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
V3 = Specific Device Code
M
G
= Date Code
= Pb−Free Device
(Note: Microdot may be in either location)
• These are Pb−Free Devices
Typical Application
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
• Audio Systems (Lightning Audio Module)
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
October, 2016 − Rev. 0
NB3V60113GV3/D
NB3V60113GV3
BLOCK DIAGRAM
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
Output
CMOS
Buffer
12.288 MHz
Divider
PLL Block
XIN/CLKIN
6.144 MHz
Clock Buffer/
Phase
Crystal
Oscillator and
AGC
Charge
VCO
Pump
Detector
NC
XOUT
Feedback
Divider
NC
GND
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
XIN/CLKIN
6.144 MHz
1
2
3
4
8
7
6
5
NC
XOUT
VDD
NC
NB3V60113GV3
PD#
CLK0
12.288 MHz
GND
Figure 2. Pin Connections (Top View) – WDFN8
www.onsemi.com
2
NB3V60113GV3
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
XIN/CLKIN
XOUT
Pin Type
Input
Description
1
2
3
6.144 MHz single−ended external reference input clock (LVCMOS)
Output
Input
Crystal output. Float this pin when external reference clock is connected at XIN
PD#
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set
outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal op-
eration of the chip.
4
5
6
7
8
GND
CLK0
NC
Ground
Output
−
Power supply ground
12.288 MHz Single−ended (LVCMOS) output
No Connection. Not to be connected to any circuit
1.8 V Power Supply
VDD
NC
Power
−
No Connection. Not to be connected to any circuit
Table 2. POWER DOWN FUNCTION TABLE
PD#
0
Function
Device Powered Down
Device Powered Up
1
NOTE: PD# has internal pull down resistor.
Table 3. ATTRIBUTES
Characteristic
Value
ESD Protection Human Body Model
2 kV
50 kW
Internal Input Default State Pull up/ down Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating Oxygen Index: 28 to 34
Transistor Count
MSL1
UL 94 V−0 @ 0.125 in
130 k
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
Parameter
Positive power supply with respect to Ground
Input Voltage with respect to chip ground
Operating Ambient Temperature Range (Industrial Grade)
Storage temperature
Rating
−0.5 to +4.6
−0.5 to VDD + 0.5
−40 to +85
−65 to +150
265
Unit
V
VDD
V
T
V
I
°C
°C
°C
A
T
STG
SOL
T
Max. Soldering Temperature (10 sec)
q
Thermal Resistance (Junction−to−ambient)
(Note 3)
0 lfpm
500 lfpm
129
84
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−case)
Junction temperature
35 to 40
125
°C/W
°C
JC
T
J
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 sq mm, 2 oz
(0.070 mm) copper thickness.
www.onsemi.com
3
NB3V60113GV3
Table 5. RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Condition
Min
Typ
Max
1.9
15
Unit
V
V
DD
Core Power Supply Voltage
1.8 V operation
1.7
1.8
CL
Clock output load capacitance for
LVCMOS clock
pF
fclkin
Reference Clock Frequency
Single ended Clock input (LVCMOS)
6.144
4.5
MHz
pF
C
XIN / XOUT pin stray Capacitance
X
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. DC ELECTRICAL CHARACTERISTICS (V = 1.8 V 0.1 V; GND = 0 V, T = −40°C to +85°C)
DD
A
Symbol
Parameter
Power Supply current
Condition
fout = 12.288 MHz
Min
Typ
Max
Unit
mA
mA
I
13
DD_1.8 V
I
Power Down Supply Current
Input HIGH Voltage
PD# is Low to make all outputs OFF
20
PD
V
IH
Pin XIN/CLKIN
Pin PD#
0.65 V
V
V
DD
DD
DD
0.85 V
V
DD
V
Input LOW Voltage
Input Capacitance
Pin XIN/CLKIN
Pin PD#
0
0
0.35 V
0.15 V
6
V
IL
DD
DD
Cin
LVCMOS OUTPUT
Pin PD#
4
pF
V
Output HIGH Voltage
Output LOW Voltage
V
V
= 1.8 V
= 1.8 V
I
= 8 mA 0.75*V
= 8 mA
V
V
OH
DD
OH
DD
V
I
0.25*V
DD
OL
DD
OL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 7. AC ELECTRICAL CHARACTERISTICS (V = 1.8 V 0.1 V, GND = 0 V, T = −40°C to +85°C)
DD
A
Symbol
Parameter
Conditions
Min
Typ
12.288
3.0
Max
Unit
MHz
ms
fout
Single Ended Output Frequency
Stabilization time from Power−up
Stabilization time from Power Down
t
V
DD
= 1.8 V
PU
PD
t
Time from falling edge on PD# pin to
tri−stated outputs (Asynchronous)
3.0
ms
Eppm
Synthesis Error
0
ppm
ps
SINGLE ENDED OUTPUT (V = 1.8 V 0.1 V; T = −40°C to 85°C)
DD
A
t
Period Jitter Peak−to−Peak
Configuration Dependent
200
200
1
JITTER−1.8 V
Cycle−Cycle Peak Jitter
Rise/Fall Time
Configuration Dependent
t / t
Measured between 20% to 80% with
ns
r
f 1.8 V
15 pF load, f = 12.288 MHz,
out
V
DD
= 1.8 V
t
Output Clock Duty Cycle
V
= 1.8 V;
%
DC
DD
Duty Cycle of Ref clock is 50%
PLL Clock
45
50
55
www.onsemi.com
4
NB3V60113GV3
PARAMETER MEASUREMENT TEST CIRCUIT
Measurement
Equipment
Hi−Z Probe
LVCMOS Clock
CL
Figure 3. LVCMOS Clock Parameter Measurement
TIMING MEASUREMENT DEFINITIONS
t
2
t
= 100 * t / t
1 2
DC
t
1
80% of VDD
50% of VDD
20% of VDD
GND
LVCMOS
Clock Output
t
t
r
f
Figure 4. LVCMOS Measurement for AC Parameters
t
period−jitter
50% of CLK Swing
Clock
Output
t
t
(N+1)cycle
Ncycle
50% of CLK Swing
Clock
Output
t
= t
− t
CTC−jitter
(N+1)cycle Ncycle (over 1000 cycles)
Figure 5. Period and Cycle−Cycle Jitter Measurement
www.onsemi.com
5
NB3V60113GV3
1.8 V
0.1 mF
0.01 mF
VDD
Reference
Clock Input
12.288 MHz single
ended clock output
XIN / CLKIN
XOUT
6.144 MHz
CLK0
NB3V60113GV3
VDD
PD#
GND
Figure 6. Typical Application Setup
ORDERING INFORMATION
Device
†
Case
Package
Shipping
NB3V60113GV3MTR2G
511AT
DFN−8
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Please contact your ON Semiconductor sales representative for information on un−programmed versions of this device.
www.onsemi.com
6
NB3V60113GV3
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT
ISSUE O
L
L
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
0.20 REF
2X
0.10
C
0.20
0.30
EXPOSED Cu
MOLD CMPD
TOP VIEW
2.00 BSC
2.00 BSC
0.50 BSC
D
E
e
DETAIL B
L
0.40
---
0.50
0.60
0.15
0.70
0.05
C
L1
L2
DETAIL B
ALTERNATE
CONSTRUCTIONS
A
8X
0.05
C
A1
A3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
C
SIDE VIEW
7X
0.78
PACKAGE
OUTLINE
e/2
e
DETAIL A
7X
L
4
1
L2
2.30
0.88
1
8
5
8X
b
0.50
PITCH
8X
0.30
0.10
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
◊
NB3V60113GV3/D
相关型号：
©2020 ICPDF网 联系我们和版权申明