NB3V8312C [ONSEMI]
Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer; 超低抖动，低偏移1:12 LVCMOS / LVTTL扇出缓冲器
| 型号： | NB3V8312C |
| 厂家： | 
ONSEMI |
| 描述： | Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer |
| 文件： | 总11页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3V8312C
Ultra-Low Jitter, Low Skew
1:12 LVCMOS/LVTTL Fanout
Buffer
The NB3V8312C is a high performance, low skew LVCMOS
fanout buffer which can distribute 12 ultra−low jitter clocks from an
LVCMOS/LVTTL input up to 250 MHz.
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The 12 LVCMOS output pins drive 50 W series or parallel
terminated transmission lines. The outputs can also be disabled to a
high impedance (tri−stated) via the OE input, or enabled when High.
The NB3V8312C provides an enable input, CLK_EN pin, which
synchronously enables or disables the clock outputs while in the LOW
state. Since this input is internally synchronized to the input clock,
changing only when the input is LOW, potential output glitching or
runt pulse generation is eliminated.
32
1
QFN32
MN SUFFIX
CASE 488AM
LQFP−32
FA SUFFIX
CASE 873A
Separate V
core and V
output supplies allow the output
V
DD
DDO
DDO
buffers to operate at the same supply as the V (V = V ) or
V
DD
DD
DDO
DD
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
GND
from a lower supply voltage. Compared to single−supply operation,
dual supply operation enables lower power consumption and
output−level compatibility.
R
PU
CLK_EN
D
The V core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V,
Q
DD
while the V
output supply voltage can be set to 3.3 V, 2.5 V, or
DDO
1.8 V, with the constraint that V ≥ V
.
DD
DDO
This buffer is ideally suited for various networking, telecom, server
and storage area networking, RRU LO reference distribution, medical
and test equipment applications.
CLK
R
PD
Features
• Power Supply Modes:
V
DD
(Core) / V
(Outputs)
DDO
3.3 V
3.3 V
3.3 V
2.5 V
2.5 V
1.8 V
/ 3.3 V
/ 2.5 V
/ 1.8 V
/ 2.5 V
/ 1.8 V
/ 1.8 V
R
PU
OE
Figure 1. Simplified Logic Diagram
• 250 MHz Maximum Clock Frequency
• Accepts LVCMOS, LVTTL Clock Inputs
• LVCMOS Compatible Control Inputs
• 12 LVCMOS Clock Outputs
ORDERING AND MARKING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
• Synchronous Clock Enable
Applications
• Output Enable to High Z State Control
• 150 ps Max. Skew Between Outputs
• Temp. Range −40°C to +85°C
• 32−pin LQFP and QFN Packages
• These are Pb−Free Devices
• Networking
• Telecom
• Storage Area Network
End Products
• Servers
• Routers
• Switches
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2013 − Rev. 0
NB3V8312C/D
NB3V8312C
Exposed
Pad (EP)
32 31 30 29 28 27 26
25
24
GND
1
2
3
4
5
6
7
8
Q4
23
22
21
20
19
18
17
V
DD
V
DDO
24
1
2
3
4
5
6
7
8
GND
Q4
CLK_EN
CLK
Q5
V
23
DD
V
DDO
GND
22
21
20
19
18
17
Q5
CLK_EN
CLK
NB3V8312C
GND
Q6
Q6
GND
OE
NB3V8312C
GND
OE
V
DDO
V
DDO
Q7
V
DD
V
Q7
DD
GND
GND
GND
GND
9
10 11 12 13 14 15
16
Figure 2. LQFP−32 Pinout Configuration
Figure 3. QFN32 Pinout Configuration
(Top View)
(Top View)
Table 1. PIN DESCRIPTION
Open
Default
Pin
Name
I/O
Description
1, 5, 8, 12, 16, 17,
21, 25, 29
GND
Power
Ground, Negative Power Supply
2, 7
3
VDD
Power
Input
Positive Supply for Core and Inputs
CLK_EN
High
Synchronous Clock Enable Input. When High, outputs
are enabled. When Low, outputs are disabled Low.
Internal Pullup Resistor.
4
6
CLK
OE
Input
Low
Single−ended Clock input; LVCMOS/LVTTL. Internal
Pull−down Resistor.
Input
High
Output Enable. Internal Pullup Resistor.
9, 11, 13, 15, 18,
20, 22, 24, 26, 28,
30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4,
Q3, Q2, Q1, Q0
Output
Single−ended LVCMOS/LVTTL outputs
10, 14, 19, 23, 27,
31
VDDO
Power
Positive Supply for Outputs
−
EP
−
−
The Exposed Pad (EP) on the package bottom is ther-
mally connected to the die for improved heat transfer
out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is connected to the die
and must only be connected electrically to GND on the
PC board.
1. All VDD, VDDO and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each supply pin with
0.01 mF to GND.
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2
NB3V8312C
CLK
CLK_EN
Q
Figure 4. CLK_EN Control Timing Diagram
Table 2. OE, CLK_EN FUNCTION TABLES
Inputs
Outputs
Q[0:11]
Hi−Z
OE
0
CLK_EN (Note 2)
CLK
X
X
0
1
1
1
X
Low
1
0
Low
1
1
High
2. The CLK_EN control input synchronously enables or disables the outputs as shown in Figure 4.
This control latches on the falling edge of the selected input CLK. When CLK_EN is LOW, the
outputs are disabled in a LOW state. When CLK_EN is HIGH, the outputs are enabled as
shown. CLK_EN to CLK Set up and Hold times must be satisfied.
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3
NB3V8312C
Table 3. ATTRIBUTES (Note 3)
Characteristics
Internal Input Pullup (R ) and Pulldown (R ) Resistor
Value
50 kW
4 pF
PU
PD
Input Capacitance, C
IN
Power Dissipation Capacitance, C (per Output)
20 pF
8 W
PD
R
OUT
ESD Protection
Human Body Model
Machine Model
> 1.5 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 3)
Level 1
Flammability Rating
Oxygen Index
UL−94 code V−0 A 1/8”
28 to 34
Transistor Count
464 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS (Note 4)
Symbol Parameter
Positive Power Supply
Condition
GND = 0 V
Rating
4.6
Unit
V
/
V
DD
V
DDO
V
I
Input Voltage
−0.5 v V v V + 0.5
V
I
DD
T
stg
Storage Temperature Range
−65 to +150
°C
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
LQFP−32
LQFP−32
80
55
°C/W
°C/W
JA
JC
JA
JC
(Note 5)
500 lfpm
q
Thermal Resistance (Junction−to−Case)
(Note 5)
Standard Board
LQFP−32
LQFP−32
12−17
°C/W
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Ambient)
(Note 5)
0 lfpm
500 lfpm
QFN*32
QFN*32
31
27
Thermal Resistance (Junction−to−Case)
(Note 5)
Standard
Board
QFN*32
12
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
5. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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4
NB3V8312C
Table 5. LVCMOS/LVTTL DC CHARACTERISTICS (T = −40°C to +85°C)
A
Symbol
Characteristics
Conditions
Min
Typ
Max
Unit
2.0
V
+
DD
V
V
= 3.465 V
= 2.625 V
V
DD
0.3
1.7
V
DD
0.3
+
+
V
V
V
IH
Input High Voltage
DD
0.65 x
V
DD
0.3
V
= 2.0 V
DD
V
DD
V
= 3.465 V
= 2.625 V
−0.3
−0.3
−0.3
1.3
0.7
V
V
DD
V
DD
V
IL
Input Low Voltage
0.35 x
V
= 2.0 V
V
DD
V
DD
CLK
150
5
Input High
Current
I
V
= V = 3.465 V or 2.625 V or 2.0 V
mA
IH
DD
IN
OE, CLK_EN
CLK
−5
−150
2.6
Input Low
Current
I
V
= 3.465 V or 2.625 V or 2.0 V, V = 0 V
mA
IL
DD
IN
OE, CLK_EN
V
V
= 3.3 V 5%
= 2.5 V 5%
DDO
1.8
DDO
V
DDO
= 2.5 V 5%; I = −1 mA
2.0
OH
V
OH
Output High Voltage (Note 6)
V
V
DD
0.4
–
V
DDO
= 1.8 V 0.2 V
V
DD
0.2
–
V
DDO
= 1.8 V 0.2 V; I = −100 mA
OH
V
V
= 3. 3V 5%
= 2.5 V 5%
0.5
0.45
0.4
DDO
DDO
V
DDO
= 2.5 V 5%; I = 1 mA
OL
V
OL
Output Low Voltage (Note 6)
V
V
= 1.8 V 0.2 V
0.35
0.2
DDO
V
DDO
= 1.8 V 0.2 V; I = 100 mA
OL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
6. Outputs terminated 50 W to V /2 unless otherwise specified. See Figure 7.
DDO
Table 6. POWER SUPPLY DC CHARACTERISTICS, (T = −40°C to +85°C)
A
V
(Core)
V
DDO
(Outputs)
Min
Typ
Max
10
Unit
mA
mA
mA
mA
mA
mA
DD
3.3 V 5%
3.3 V 5%
3.3 V 5%
2.5 V 5%
2.5 V 5%
1.8 V 0.2 V
3.3 V 5%
2.5 V 5%
1.8 V 0.2V
2.5 V 5%
10
10
10
1.8 V 0.2V
1.8 V 0.2V
10
10
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5
NB3V8312C
Table 7. AC CHARACTERISTICS (T = −40°C to +85°C) (Note 7)
A
Symbol
Characteristic
Min
Typ
Max
Unit
f
Maximum Operating Frequency
V
/ V
DD DDO
MAX
3.3 V 5% / 3.3 V 5%
3.3 V 5% / 2.5 V 5%
250
250
200
250
200
200
3.3 V 5% / 1.8 V 0.2 V
2.5 V 5% / 2.5 V 5%
2.5 V 5% / 1.8 V 0.2 V
1.8 V 0.2 V / 1.8 V 0.2 V
MHz
t
Propagation Delay, Low to High; (Note 8)
V
/ V
pLH
DD DDO
3.3 V 5% / 3.3 V 5%
3.3 V 5% / 2.5 V 5%
0.9
1.0
1.0
1.3
1.3
2.4
2.2
2.3
3.0
3.1
3.5
4.2
3.3 V 5% / 1.8 V 0.2 V
2.5 V 5% / 2.5 V 5%
2.5 V 5% / 1.8 V 0.2 V
1.8 V 0.2 V / 1.8 V 0.2 V
ns
fs
t
jit
Additive Phase Jitter, RMS;
V
/ V
DD DDO
f
= 100 MHz
3.3 V 5% / 3.3 V 5%
3.3 V 5% / 2.5 V 5%
30
40
C
Integration Range: 12 kHz − 20 MHz
See Figure 5
3.3 V 5% / 1.8 V 0.2 V
2.5 V 5% / 2.5 V 5%
50
20
2.5 V 5% / 1.8 V 0.2 V
1.8 V 0.2 V / 1.8 V 0.2 V
100
130
t
Output−to−output skew; (Note 9); Figure 6
Part−to−Part Skew; (Note 10)
Output rise and fall times
V
/ V
sk(o)
DD DDO
3.3 V 5% / 3.3 V 5%
3.3 V 5% / 2.5 V 5%
125
135
145
150
150
140
3.3 V 5% / 1.8 V 0.2 V
2.5 V 5% / 2.5 V 5%
2.5 V 5% / 1.8 V 0.2 V
1.8 V 0.2 V / 1.8 V 0.2 V
ps
ps
ps
%
t
V
/ V
DD DDO
sk(pp)
3.3 V 5% / 3.3 V 5%
3.3 V 5% / 2.5 V 5%
250
250
250
250
250
250
3.3 V 5% / 1.8 V 0.2 V
2.5 V 5% / 2.5 V 5%
2.5 V 5% / 1.8 V 0.2 V
1.8 V 0.2 V / 1.8 V 0.2 V
t /t
f
V
/ V
r
DD DDO
3.3 V 5% / 3.3 V 5%
3.3 V 5% / 2.5 V 5%
3.3 V 5% / 1.8 V 0.2 V
2.5 V 5% / 2.5 V 5%
2.5 V 5% / 1.8 V 0.2 V
1.8 V 0.2 V / 1.8 V 0.2 V
200
200
200
200
200
200
700
700
700
700
700
800
ODC
Output Duty Cycle (Note 11)
V / V
DD DDO
f ≤ 200 MHz, 3.3 V 5% / 3.3 V 5%
f ≤ 150 MHz, 3.3 V 5% / 2.5 V 5%
f ≤ 100 MHz, 3.3 V 5% / 1.8 V 0.2 V
f ≤ 150 MHz, 2.5 V 5% / 2.5 V 5%
f ≤ 100 MHz, 2.5 V 5% / 1.8 V 0.2 V
f ≤ 100 MHz, 1.8 V 0.2 V / 1.8 V 0.2 V
45
45
45
45
45
45
55
55
55
55
55
55
All parameters measured at f
unless noted otherwise.
MAX
7. Outputs loaded with 50 W to V
/2; see Figure 7. CLOCK input with 50% duty cycle; minimum input amplitude = 1.2 V at V = 3.3 V,
DDO
DD
1.0 V at V = 2.5 V, V /2 at V = 1.8 V.
DD
DD
DD
8. Measured from the V /2 of the input to V
/2 of the output.
DDO
DD
9. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
/2.
DDO
10.Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of input on each device, the output is measured at V /2.
DDO
11. Clock input with 50% duty cycles, rail−to−rail amplitude and t /t = 500 ps.
r
f
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NB3V8312C
NB3V8312C
Additive Phase Jitter @ 100 MHz
VDD = VDDO = 3.3 V
Filter = 12 kHz − 20 MHz
Source RMS Jitter = 200.53 fs
Output RMS Jitter = 202.73 fs
12 kHz to 20 MHz = 29.8 fs (typical)
2
2
RMS addititive jitter + ǸRMS phase jitter of output
* RMS phase jitter of input
2
2
29.8 + Ǹ202.73 fs
* 200.53 fs
Output (DUT + Source)
Input Source
Figure 5. Typical Phase Noise Plot at fcarrier = 100 MHz at an Operating Voltage of 3.3 V, Room Temperature
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The RMS Phase Jitter
contributed by the device (integrated between 12 kHz and
20 MHz) is 29.8 fs.
notably lower than that of the DUT. If the phase noise of the
source is greater than the device under test output, the source
noise will dominate the additive phase jitter calculation and
lead to an artificially low result for the additive phase noise
measurement within the integration range. The Figure above
is a good example of the NB3V8312C source generator
phase noise having a significantly higher floor such that the
DUT output results in an additive phase jitter of 29.8 fs.
The additive phase jitter performance of the fanout buffer
is highly dependent on the phase noise of the input source.
To obtain the most accurate additive phase noise
measurement, it is vital that the source phase noise be
2
2
RMS addititive jitter + ǸRMS phase jitter of output * RMS phase jitter of input
2
2
29.8 + Ǹ202.73 fs * 200.53 fs
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7
NB3V8312C
V
PP
= V − V
IH
IL
CLK
CLK
V
V
DD
2
DD
V
IHCMR
2
GND
V
DD
V
DD
2
LVCMOS_CLK
2
V
DDO
2
V
DDO
2
Qx
t
LH
t
PHL
V
V
V
DDO
2
DDO
2
DDO
2
t
PW
Qx
t
P
% + ǒt
Ǔ
t
ńt 100
SKEWDC
PW
P
Figure 6. AC Reference Measurement
V
DD
V
DDO
Z
O
= 50 W
NB3V8312C
GND
Q
Scope
IN
x
50 W
V
÷ 2 = 0 V = Ground
DDO
Figure 7. Typical Device Evaluation and Termination Setup − See Table 8
Table 8. TEST SUPPLY SETUP. VDDO SUPPLY MAY BE CENTERED ON 0.0 V (SCOPE GND) TO PERMIT DIRECT
CONNECTION INTO “50 W TO GND” SCOPE MODULE. VDD SUPPLY TRACKS DUT GND PIN
Spec Condition:
V
Test Setup
VDDO Test Setup
+1.65 V 5%
+1.25 V 5%
+0.9 V 0.1 V
+1.25 V 5%
+0.9 V 0.1 V
+0.9 V 0.1 V
GND Pin Test Setup
−1.65 V 5%
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3.3 V 5%, V
= 3.3 V 5%, V
= 3.3 V 5%, V
= 2.5 V 5%, V
= 2.5 V 5%, V
= 3.3 V 5%
= 2.5 V 5%
= 1.8 V 5%
O = 2.5 V 5%
= 1.8 V 0.2 V
+1.65 5%
+2.05 V 5%
+2.4 V 5%
+1.25 V 5%
+1.6 V 5%
DDO
DDO
DDO
DDO
DDO
−1.25 V 5%
−0.9 V 0.1 V
−1.25 V 5%
−0.9 V 0.1 V
−0.9 V 0.1 V
= 1.8 V 0.2 V, V
= 1.8 V 0.2 V
+0.9 V 0.1 V
DDO
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8
NB3V8312C
MARKING DIAGRAMS*
32
1
NB3V
NB3V
8312C
AWLYYWWG
8312C
AWLYYWWG
LQFP−32
QFN32
A
= Assembly Location
WL
YY
WW
G
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(*Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device
†
Package
Shipping
NB3V8312CFAG
LQFP−32
(Pb−Free)
250 Units / Tray
2000 / Tape & Reel
74 Units / Rail
NB3V8312CFAR2G
NB3V8312CMNG
NB3V8312CMNR4G
LQFP−32
(Pb−Free)
QFN32
(Pb−Free)
QFN32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NB3V8312C
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
A
A1
0.20 (0.008) AB T-U
Z
32
25
BASE
METAL
1
−U−
−T−
N
AE
AE
B
V
P
F
D
B1
DETAIL Y
V1
17
8
DETAIL Y
J
9
4X
−Z−
0.20 (0.008) AC T-U
Z
9
SECTION AE−AE
S1
_
8X M
S
R
DETAIL AD
E
G
C
−AB−
−AC−
SEATING
PLANE
W
0.10 (0.004) AC
_
Q
H
K
NOTES:
X
MILLIMETERS
DIM MIN MAX
7.000 BSC
3.500 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
A
A1
B
DETAIL AD
2. CONTROLLING DIMENSION:
MILLIMETER.
0.138 BSC
0.276 BSC
0.138 BSC
7.000 BSC
3.500 BSC
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
D
0.300
1.350
0.300
0.012
0.053
0.012
0.018
0.057
0.016
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.450
0.150
0.200
0.750
0.002
0.004
0.018
0.006
0.008
0.030
J
K
_
12 REF
_
12 REF
M
N
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5 _
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
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10
NB3V8312C
PACKAGE DIMENSIONS
QFN32 5x5, 0.5P
CASE 488AM
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
SOLDERING FOOTPRINT*
L
5.30
EXPOSED PAD
32 X
K
16
9
32 X
3.20
17
8
32 X
0.63
E2
1
24
3.20 5.30
25
32
32 X
b
e
0.10
0.05
C
A
B
32 X
0.28
C
28 X
0.50 PITCH
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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