NB3W1200LMNG [ONSEMI]
Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle; 差分HCSL 1:12或推挽式时钟ZDB /扇出缓冲器，用于PCle
| 型号： | NB3W1200LMNG |
| 厂家： | 
ONSEMI |
| 描述： | Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle |
| 文件： | 总26页 (文件大小：230K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3N1200K, NB3W1200L
3.3 V 100/133 MHz
Differential 1:12 HCSL or
Push-Pull Clock ZDB/Fanout
Buffer for PCle
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Description
The NB3N1200K and NB3W1200L differential clock buffers are
DB1200Z and DB1200ZL compliant and are designed to work in
conjunction with a PCIe compliant source clock synthesizer to provide
point−to−point clocks to multiple agents. The device is capable of
®
distributing the reference clocks for Intel QuickPath Interconnect
64
1
(Intel QPI), PCIe Gen1/Gen2/Gen3, SAS, SATA, and Intel Scalable
Memory Interconnect (Intel SMI) applications. The VCO of the
device is optimized to support 100 MHz and 133 MHz frequency
operation. The NB3N1200K and NB3W1200L utilize
pseudo−external feedback topology to achieve low input−to output
delay variation. The NB3N1200K is configured with the HCSL buffer
type, while the NB3W1200L is configured with the low−power
NMOS Push−Pull buffer type.
QFN64
MN SUFFIX
CASE 485DH
MARKING DIAGRAMS
1
1
Features
NB3N
1200K
AWLYYWWG
NB3W
1200L
AWLYYWWG
• 12 Differential Clock Output Pairs @ 0.7 V
• HCSL Compatible Outputs for NB3N1200K
• Low−Power NMOS Push−Pull Compatible Outputs for NB3W1200L
• Optimized 100 MHz and 133 MHz Operating Frequencies to Meet
The Next Generation PCIe Gen 2/Gen 3 and Intel QPI Phase Jitter
• DB1200Z and DB1200ZL Compliant
NB3x1200x= Specific Device Code
A
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
WL
YY
WW
G
• 3.3 V 5% Supply Voltage Operation
• Fixed−Feedback for Lowest Input−To−Output Delay Variation
• SMBus Programmable Configurations to Allow Multiple Buffers in a
Single Control Network
ORDERING INFORMATION
• PLL Bypass Configurable for PLL or Fanout Operation
• Programmable PLL Bandwidth
†
Device
Package
Shipping
NB3N1200KMNG
NB3N1200KMNTXG
NB3W1200LMNG
NB3W1200LMNTXG
QFN−64
(Pb−Free)
260 Units /
Tray
• 2 Tri−level Addresses Selection (9 SMBUS Addresses)
• Individual OE Control Pin for Each of 12 Outputs
• Low Phase Jitter (Intel QPI, PCIe Gen 2/Gen 3 Phase Jitter Compliant)
• 50 ps Max Output−to−Output Skew Performance
• 50 ps Max Cycle−to−Cycle Jitter (PLL mode)
• 100 ps Input to Output Delay Variation Performance
• QFN 64−pin Package, 9 mm x 9 mm
QFN−64
(Pb−Free)
1000 / Tape &
Reel
QFN−64
(Pb−Free)
260 Units /
Tray
QFN−64
(Pb−Free)
1000 / Tape &
Reel
• Spread Spectrum Compatible: Tracks Input Clock Spreading for Low
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
EMI
• 0°C to +70°C Ambient Operating Temperature
• These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
August, 2013 − Rev. 0
NB3N1200K/D
NB3N1200K, NB3W1200L
12
OE_[11:0]#
FB_OUT*
FB_OUT#*
DIF_[11:0]
SSC Compatible
PLL
MUX
DIF_[11:0]#
CLK_IN
CLK_IN#
100M_133M#
HBW_BYPASS_LBW#
SA_0
Control
Logic
SA_1
PWRGD/PWRDN#
SDA
SCL
IREF**
* FB_OUT pins are for NB3N1200K only; they are NC for NB3W1200L
** IREF pin is for NB3N1200K only; it is NC for NB3W1200L
R
REF
Figure 1. Simplified Block Diagram
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2
NB3N1200K, NB3W1200L
PIN CONNECTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
Exposed Pad (EP)
GND
VDDA
GNDA
IREF
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DIF_7#
DIF_7
OE_7#
OE_6#
DIF_6#
DIF_6
GND
2
3
100M_133M#
HBW_BYPASS_LBW#
PWRGD/PWRDN#
GND
4
5
6
7
VDDR
CLK_IN
CLK_IN#
SA_0
SDA
SCL
SA_1
FB_OUT#
FB_OUT
8
NB3N1200K
VDD
9
DIF_5#
DIF_5
OE_5#
OE_4#
DIF_4#
DIF_4
GND
10
11
12
13
14
15
16
(Top View)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 2. NB3N1200K Pinout: QFN−64 (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
VDDA
GNDA
2
DIF_7#
DIF_7
OE_7#
OE_6#
DIF_6#
DIF_6
GND
Exposed Pad (EP)
3
NC
4
100M_133M#
HBW_BYPASS_LBW#
5
6
PWRGD/PWRDN#
GND
7
8
VDDR
CLK_IN
CLK_IN#
SA_0
NB3W1200L
9
VDD
10
11
12
13
14
15
16
DIF_5#
DIF_5
OE_5#
OE_4#
DIF_4#
DIF_4
GND
SDA
SCL
SA_1
NC
(Top View)
NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 3. NB3W1200L Pinout: QFN−64 (Top View)
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3
NB3N1200K, NB3W1200L
Table 1. NB3N1200K PIN DESCRIPTIONS
Pin Number
Pin Name
VDDA
Type
Description
1
2
3
3.3 V
GND
I
3.3 V Power Supply for PLL.
Ground for PLL.
GNDA
IREF
A precision resistor is attached to this pin to set the differential output current.
Use R
Use R
= 475 W, 1% for 100 Ohms trace.
= 412 W, 1% for 85 Ohms trace.
REF
REF
4
5
100M_133M#
I, SE
I, SE
Input/output Frequency Selection (FS). An external pull−up
or pull−down resistor is attached to this pin to select the input/output frequency.
High = 100 MHz Output
Low = 133 MHz Output
HBW_BYPASS_LBW#
Tri−Level input for selecting the PLL bandwidth or bypass mode
(refer to tri− level threshold in Table 4).
High = High BW mode Med = Bypass mode Low = Low BW mode
6
7
PWRGD / PWRDN#
GND
I, SE
GND
VDD
I, DIF
I, DIF
I, SE
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
8
VDDR
3.3 V power supply for receiver.
9
CLK_IN
0.7 V Differential True input
10
11
CLK_IN#
SA_0
0.7 V Differential Complementary input
3.3 V LVTTL input selecting the address.
Tri−level input (refer to tri−level threshold in Table 4.)
12
13
14
SDA
SCL
I/O
I/O
Open collector SMBus data.
SMBus slave clock input.
SA_1
I, SE
3.3 V LVTTL input selecting the address.
Tri−level input (refer to tri−level threshold in Table 4.)
15
16
FB_OUT#
FB_OUT
O, DIF
O, DIF
Complementary Feedback out pin, termination required.
See External Feedback Termination section.
True Feedback out pin, termination required.
See External Feedback Termination section.
17
18
19
DIF_0
DIF_0#
OE_0#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 0.
0 enables outputs, 1 disables outputs. Internal pull down.
20
OE_1#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 1.
0 enables outputs, 1 disables outputs. Internal pull down.
21
22
23
24
25
26
27
28
DIF_1
DIF_1#
GND
O, DIF
O, DIF
GND
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
VDD
3.3 V
3.3 V power supply for outputs.
VDD
3.3 V
3.3 V power supply for outputs.
DIF_2
DIF_2#
OE_2#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 2.
0 enables outputs, 1 disables outputs. Internal pull down.
29
OE_3#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 3.
0 enables outputs, 1 disables outputs. Internal pull down.
30
31
32
33
DIF_3
DIF_3#
VDD
O, DIF
O, DIF
3.3 V
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
Ground for outputs.
GND
GND
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4
NB3N1200K, NB3W1200L
Table 1. NB3N1200K PIN DESCRIPTIONS
Pin Number
Pin Name
DIF_4
Type
Description
34
35
36
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
DIF_4#
OE_4#
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 4.
0 enables outputs, 1 disables outputs. Internal pull down.
37
OE_5#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 5.
0 enables outputs, 1 disables outputs. Internal pull down.
38
39
40
41
42
43
44
DIF_5
DIF_5#
VDD
O, DIF
O, DIF
3.3 V
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
GND
GND
Ground for outputs.
DIF_6
DIF_6#
OE_6#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 6.
0 enables outputs, 1 disables outputs. Internal pull down.
45
OE_7#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 7.
0 enables outputs, 1 disables outputs. Internal pull down.
46
47
48
49
50
51
52
DIF_7
DIF_7#
GND
O, DIF
O, DIF
GND
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
VDD
3.3 V
3.3 V power supply for outputs.
DIF_8
DIF_8#
OE_8#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 8.
0 enables outputs, 1 disables outputs. Internal pull down.
53
OE_9#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 9.
0 enables outputs, 1 disables outputs. Internal pull down.
54
55
56
57
58
59
60
61
DIF_9
DIF_9#
VDD
O, DIF
O, DIF
3.3 V
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for outputs.
VDD
3.3 V
3.3 V power supply for outputs.
GND
GND
Ground for outputs.
DIF_10
DIF_10#
OE_10#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 10.
0 enables outputs, 1 disables outputs. Internal pull down.
62
OE_11#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 11.
0 enables outputs, 1 disables outputs. Internal pull down.
63
64
DIF_11
DIF_11#
O, DIF
O, DIF
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
EP
Exposed Pad
Thermal
The Exposed Pad (EP) on the QFN−64 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die,
and must be electrically and thermally connected to GND on the PC board.
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NB3N1200K, NB3W1200L
Table 2. NB3W1200L PIN DESCRIPTIONS
Pin Number
Pin Name
VDDA
Type
Description
1
2
3
4
3.3 V
GND
I/O
3.3 V Power Supply for PLL.
Ground for PLL.
GNDA
NC
No Connect
100M_133M#
I, SE
3.3 V tolerant inputs for input/output Frequency Selection (FS). An external pull−
up or
pull−down resistor is attached to this pin to select the input/output frequency.
High = 100 MHz Output
Low = 133 MHz Output
5
HBW_BYPASS_LBW#
I, SE
Tri−Level input for selecting the PLL bandwidth or bypass mode
(refer to tri− level threshold in Table 4).
High = High BW mode, Med = Bypass mode,
Low = Low BW mode
6
7
PWRGD / PWRDN#
GND
I
3.3 V LVTTL input to power up or power down the device.
Ground for outputs.
GND
VDD
I, DIF
I, DIF
I
8
VDDR
3.3 V power supply for receiver.
9
CLK_IN
0.7 V Differential True input
10
11
CLK_IN#
SA_0
0.7 V Differential Complementary input
3.3 V LVTTL input selecting the address.
Tri−level input (refer to tri−level threshold in Table 4.)
12
13
14
SDA
SCL
I/O
I/O
I
Open collector SMBus data.
SMBus slave clock input.
SA_1
3.3 V LVTTL input selecting the address. Tri−level input
(refer to tri−level threshold in Table 4.)
15
16
NC
NC
I/O
I/O
No Connect. There are active signals on pin 15;
do not connect anything to this pin.
No Connect. There are active signals on pin 16;
do not connect anything to this pin.
17
18
19
DIF_0
DIF_0#
OE_0#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 0.
0 enables outputs, 1 disables outputs. Internal pull down.
20
OE_1#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 1.
0 enables outputs, 1 disables outputs. Internal pull down.
21
22
23
24
25
26
27
28
DIF_1
DIF_1#
GND
O, DIF
O, DIF
GND
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
VDD
3.3 V
3.3 V power supply for core.
VDD_IO
DIF_2
DIF_2#
OE_2#
VDD
Power supply for differential outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
O, DIF
O, DIF
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 2.
0 enables outputs, 1 disables outputs. Internal pull down.
29
OE_3#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 3.
0 enables outputs, 1 disables outputs. Internal pull down.
30
31
32
33
DIF_3
DIF_3#
VDD_IO
GND
O, DIF
O, DIF
VDD
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Power supply for differential outputs.
Ground for outputs.
GND
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6
NB3N1200K, NB3W1200L
Table 2. NB3W1200L PIN DESCRIPTIONS
Pin Number
Pin Name
DIF_4
Type
Description
34
35
36
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
DIF_4#
OE_4#
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 4.
0 enables outputs, 1 disables outputs. Internal pull down.
37
OE_5#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 5.
0 enables outputs, 1 disables outputs. Internal pull down.
38
39
40
41
42
43
44
DIF_5
DIF_5#
VDD
O, DIF
O, DIF
3.3 V
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V power supply for core.
GND
GND
Ground for outputs.
DIF_6
DIF_6#
OE_6#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 6.
0 enables outputs, 1 disables outputs. Internal pull down.
45
OE_7#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 7.
0 enables outputs, 1 disables outputs. Internal pull down.
46
47
48
49
50
51
52
DIF_7
DIF_7#
GND
O, DIF
O, DIF
GND
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Ground for outputs.
VDD_IO
DIF_8
VDD
Power supply for differential outputs.
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
O, DIF
O, DIF
I, SE
DIF_8#
OE_8#
3.3 V LVTTL active low input for enabling DIF output pair 8.
0 enables outputs, 1 disables outputs. Internal pull down.
53
OE_9#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 9.
0 enables outputs, 1 disables outputs. Internal pull down.
54
55
56
57
58
59
60
61
DIF_9
DIF_9#
VDD_IO
VDD
O, DIF
O, DIF
VDD
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
Power supply for differential outputs.
3.3 V power supply for core.
3.3 V
GND
GND
Ground for outputs.
DIF_10
DIF_10#
OE_10#
O, DIF
O, DIF
I, SE
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
3.3 V LVTTL active low input for enabling DIF output pair 10.
0 enables outputs, 1 disables outputs. Internal pull down.
62
OE_11#
I, SE
3.3 V LVTTL active low input for enabling DIF output pair 11.
0 enables outputs, 1 disables outputs. Internal pull down.
63
64
DIF_11
DIF_11#
O, DIF
O, DIF
0.7 V Differential True clock output
0.7 V Differential Complementary clock output
EP
Exposed Pad
Thermal
The Exposed Pad (EP) on the QFN−64 package bottom is thermally connected
to the die for improved heat transfer out of package. The exposed pad must be
attached to a heat−sinking conduit. The pad is electrically connected to the die,
and must be electrically and thermally connected to GND on the PC board.
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7
NB3N1200K, NB3W1200L
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition
Min
Max
4.6
4.6
4.6
5.5
Units
V
V
/V
/V
Core Supply Voltage
I/O Supply Voltage
DD DDA DDR
V
DD_IO
V
V
IH
(Note 1)
Input High Voltage
V
V
SMB Input High Voltage
3.3 V Input Low Voltage
Storage Temperature
Input ESD protection
Maximum Output Current
SDA, SCL Pins
V
IHSMB
V
IL
−0.5
−65
V
ts
ESD prot.
150
°C
V
Human Body Model
2000
I
Powerdown Mode
(PWRGD/PWRDN# = 0)
OUTmax
NB3N1200K All Pairs Tri−stated
NB3W1200L All Pairs Tri−state Low/Low
24
12
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Maximum VIH is not to exceed maximum VDD.
Table 4. DC OPERATING CHARACTERISTICS (V = V
= V
= 3.3 V 5%, T = 0°C − 70°C)
DD
DDA
DDR
A
Symbol
/V /V
Parameter
Condition
Min
Max
3.465
3.465
Units
V
3.3 V Core Supply Voltage
I/O Supply Voltage
3.3 V 5%
1.05 V to 3.3 V 5%
At 133 MHz, C = 2 pF
3.135
0.975
V
V
DD DDA DDR
V
(Note 2)
DD_IO
I
Power Supply Current
DD
L
NB3N1200K
NB3W1200L
330
180
mA
mA
I
Power Down Current
DDPD
NB3N1200K
NB3W1200L
6
6
V
(Note 3)
(Note 3)
Input High Voltage, Single−Ended Inputs
Input Low Voltage, Single−Ended Inputs
CLK_IN/CLK_IN# High
2.0
GND−0.3
600
5.5
0.8
V
V
IH
V
IL
V
1150
300
+5
mV
mV
mA
V
IHCLK_IN
V
CLK_IN/CLK_IN# Low
−300
−5
ILCLK_IN
I
IL
(Note 4)
Input Leakage Current
0 < V < V
IN DD
VIH_FS (Note 5)
VIL_FS (Note 5)
Input High Voltage
0.7
V
+0.3
DD
Input Low Voltage
GND−0.3
0
0.35
V
V
IL_Tri
(Note 6)
(Note 6)
(Note 6)
Tri−Level Input Low Voltage
Tri−Level Input Med Voltage
Tri−Level Input High Voltage
Output High Voltage SCL, SDA
Output Low Voltage SCL, SDA
Input Capacitance
0.8
1.8
V
V
1.2
V
IM_Tri
V
2.2
V
DD
V
IH_Tri
V
OH
(Note 7)
(Note 7)
(Note 8)
(Note 8)
I
= −1 mA
2.4
V
OH
V
OL
I
OL
= 1 mA
0.4
4.5
4.5
7
V
C
2.5
2.5
pF
pF
nH
°C
in
C
Output Capacitance
out
L
pin
Pin Inductance
ta
Ambient Temperature
No Airflow
0
70
2. V
applies to the low power NMOS push−pull NB3W1200L only.
DD_IO
3. SDA, SCL, OEn#, PWRGD/PWRDN#.
4. Input Leakage Current does not include inputs with pull−up or pull−down resistors.
5. 100M_133M# Frequency Select (FS).
6. SA_0, SA_1, HBW_BYPASS_LBW#.
7. Signal edge is required to be monotonic when transitioning through this region.
8. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including package pin capacitance.
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8
NB3N1200K, NB3W1200L
NB3N1200K / NB3W1200L Output Relational Timing Parameters
Table 5. ELECTRICAL CHARACTERISTICS − Skew and Differential Jitter Parameters
(V = V
= V = 3.3 V 5%, T = 0 − 70°C)
DDR A
DD
DDA
Group
Description
Min
Typ
Max
Units
CLK_IN, DIF[x:0]
(Notes 9, 10, 12, 13)
Input−to−Output Delay in PLL mode, nominal value
−100
100
ps
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay in Bypass mode, nominal value
2.5
4.5
|100|
|250|
50
ns
ps
ps
ps
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay variation in PLL mode
(over voltage and temperature), nominal value
CLK_IN, DIF[x:0]
(Notes 10, 11, 13)
Input−to−Output Delay variation in Bypass mode
(over voltage and temperature), nominal value
DIF[11:0]
(Notes 9, 10, 11, 13)
Output−to−Output Skew across all 12 outputs
(Common to Bypass and PLL mode)
0
9. Measured into fixed 2 pF load capacitance. Input to output skew is measured at the first output edge following the corresponding input.
10.Measured from differential cross−point to differential cross−point.
11. All Bypass Mode Input−to−Output specs refer to the timing between an input edge and the specific output edge created by it.
12.This parameter is deterministic for a given device.
13.Measured with scope averaging on to find mean value.
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NB3N1200K, NB3W1200L
Table 6. LOW BAND PHASE JITTER − PLL MODE
Group
Parameter
Min
Typ
Max
Units
DIF
Output PCIe Gen1
13
86
ps
(p−p)
(Notes 14, 16, 17)
DIF
Output PCIe Gen2 Low Band, 10 kHz < f < 1.5 MHz
Output PCIe Gen2 High Band, 1.5 MHz < f < 50 MHz
0.1
0.8
3.0
3.1
ps
(Notes 14, 15, 17, 19)
RMS
DIF
ps
RMS
(Notes 14, 15, 17, 19)
HIGH BAND, 1.5 MHz < F < Nyquist
DIF
Output phase jitter impact – PCIe* Gen3
0.18
0.14
0.07
0.06
1.0
0.5
0.3
0.2
ps
(Notes 14, 15, 17, 19) (including PLL BW 2 – 4 MHz, CDR = 10 MHz)
RMS
DIF
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(4.8 Gb/s or 6.4 Gb/s, 100 MHz or 133 MHz, 12 UI)
ps
RMS
(Notes 14, 18, 20)
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(8 Gb/s, 100 MHz, 12 UI)
ps
RMS
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(9.6 Gb/s, 100 MHz, 12 UI)
ps
RMS
Table 7. ADDITIVE PHASE JITTER − BYPASS MODE
Group
Parameter
Min
Typ
Max
Units
DIF
Output PCIe Gen1
0.04
10
ps
(p−p)
(Notes 14, 16, 17)
DIF
Output PCIe Gen2 Low Band, 10 kHz < f < 1.5 MHz
Output PCIe Gen2 High Band, 1.5 MHz < f < 50 MHz
Output phase jitter impact – PCIe* Gen3
0.001
0.002
0.001
0.001
0.001
0.001
0.3
0.7
0.3
0.3
0.1
0.1
ps
(Notes 14, 15, 17, 19)
RMS
DIF
ps
RMS
(Notes 14, 15, 17, 19)
DIF
ps
RMS
(Notes 14, 15, 17, 19)
DIF
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(4.8 Gb/s or 6.4 Gb/s, 100 MHz or 133 MHz, 12 UI)
ps
RMS
(Notes 14, 18, 20)
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(8 Gb/s, 100 MHz, 12 UI)
ps
RMS
DIF
(Notes 14, 18)
Output Intel QPI & Intel SMI REFCLK accumulated jitter
(9.6 Gb/s, 100 MHz, 12 UI)
ps
RMS
14.Post processed evaluation through Intel supplied Matlab scripts. Tested with NB3N1200K/NB3W1200L driven by a CK420BQ or equivalent.
15.PCIe Gen3 filter characteristics are subject to final ratification by PCISIG. Please check the PCI SIG for the latest specification.
16.These jitter numbers are defined for a BER of 1E−12. Measured numbers at a smaller sample size have to be extrapolated to this BER target.
17.⎛ = 0.54 is implying a jitter peaking of 3 dB.
18.Measuring on 100 MHz output using Intel supplied clock template jitter tool.
19.Measuring on 100 MHz PCIe SRC output using Intel supplied clock jitter tool.
20.Measuring on 100 MHz, 133 MHz output using Intel supplied clock jitter tool.
Table 8. PLL BANDWIDTH AND PEAKING
Group
Parameter
Min
−
Typ
0.7
0.4
2.7
0.9
Max
2.0
2.5
4.0
1.4
Units
dB
DIF (Note 21)
DIF (Note 21)
DIF (Note 22)
DIF (Note 22)
PLL Jitter Peaking (HBW_BYPASS_LBW# = 0)
PLL Jitter Peaking (HBW_BYPASS_LBW# = 1)
PLL Bandwidth (HBW_BYPASS_LBW# = 1)
PLL Bandwidth (HBW_BYPASS_LBW# = 0)
−
dB
2.0
0.7
MHz
MHz
21.Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
22.Measured at 3 db down or half power point.
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NB3N1200K, NB3W1200L
Table 9. DIF 0.7 V AC TIMING CHARACTERISTICS (Non−Spread or −0.5% Spread Spectrum Mode)
(V = V
= V
= 3.3 V 5%)
DD
DDA
DDR
CLK = 100 MHz, 133.33 MHz
Min
Max
1.8
Symbol
Tstab (Note 44)
Parameter
Clock Stabilization Time
Long Accuracy
Unit
ms
Laccuracy (Notes 26, 30, 38, 45)
Tabs (Notes 26, 27, 30)
100
ppm
ns
9.94900 for 100 MHz 10.05100 for 100 MHz
7.44925 for 133 MHz 7.55075 for 133 MHz
9.49900 for 100 MHz 10.10126 for 100 MHz
Absolute
Min/Max
Host CLK
Period
No Spread
−0.5% Spread
7.44925 for 133 MHz
1.0
7.58845 for 133 MHz
Slew_rate (Notes 24, 26, 30)
DTrise / DTfall (Notes 26, 29, 40)
Rise/Fall Matching (Notes 26, 30, 41, 43)
VHigh (Notes 26, 29, 32)
DIFF OUT Slew_rate (see Figure 4)
Rise and Fall Time Variation
4.0
125
20
V/ns
ps
%
Voltage High (typ 0.70 Volts)
Voltage Low (typ 0.0 Volts)
Maximum Voltage
660
850
150
1150
550
Calc
140
mV
mV
mV
mV
VLow (Notes 26, 29, 33)
−150
Vmax (Note 29)
Vcross absolute (Notes 23, 25, 26, 29, 36) Absolute Crossing Point Voltages
250
Vcross relative (Notes 26, 28, 29, 36)
Relative Crossing Point Voltages
Calc
Total D Vcross (Notes 26, 29, 37)
Total Variation of Vcross
Over All Edges
mV
Tccjitter (Notes 26, 30, 42)
Duty Cycle (Notes 26, 30)
tOE# Latency
Cycle−to−Cycle Jitter
50
55
12
ps
%
PLL and Bypass Modes
45
4
OE# Latency − DIFF start after OE#
Assertion
− DIFF stop after OE# Deassertion
Clocks
Vovs (Notes 26, 29, 34)
Vuds (Notes 26, 29, 35)
Vrb (Notes 26, 29)
Maximum Voltage (Overshoot)
Maximum Voltage (Undershoot)
Ringback Voltage
Vhigh + 0.3
Vlow − 0.3
N/A
V
V
V
0.2
23.Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of CLK#.
24.Measurment taken from differential waveform on a component test board. The slew rate is measured from −150 mV to +150 mV on the
differential waveform. Scope is set to average because the scope sample clock is making most of the dynamic wiggles along the clock edge
Only valid for Rising CLK_IN and Falling CLK_IN#. Signal must be monotonic through the Vol to Voh region for Trise and Tfall.
25.This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
26.Test configuration is Rs = 33.2 W, Rp = 49.9, 2 pF for 100 W transmission line; Rs = 27 W, Rp = 42.2, 2 pF for 85 W transmission line.
27.The average period over any 1 ms period of time must be greater than the minimum and less than the maximum specified period.
28.Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg − 0.700), Vcross(rel) Max = 0.550 − 0.5 (0.700
– Vhavg), (see Figure 7).
29.Measurement taken from Single Ended waveform.
30.Measurement taken from differential waveform. Bypass mode, input duty cycle = 50%.
31.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
32.VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
33.VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
34.Overshoot is defined as the absolute value of the maximum voltage.
35.Undershoot is defined as the absolute value of the minimum voltage.
36.The crossing point must meet the absolute and relative crossing point specifications simultaneously.
37.DVcross is defined as the total variation of all crossing voltages of Rising DIFF and Falling DIFF#. This is the maximum allowed variance
in Vcross for any particular system.
38.Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 100,000,000 Hz, 133,333,333 Hz.
39.Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are 99,750,00 Hz, 133,000,000 Hz.
40.Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
41.Measured with oscilloscope, averaging on, The difference between the rising edge rate (average) of DIFF versus the falling edge rate
(average) of DIFF#. Measured in a 75 mV window around the crosspoint of DIFF and DIFF#.
42.Measured with device in PLL mode, in BYPASS mode jitter is additive.
43.Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
44.This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8 V – 2.0 V to the time that stable clocks
are output from the buffer chip (PLL locked).
45.All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+/CK420BQ accuracy
requirements. The NB3N1200K and NB3W1200L itself do not contribute to ppm error.
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NB3N1200K, NB3W1200L
Table 10. CLOCK PERIOD SSC DISABLED
SSC OFF
Measurement Window
1 Clock
1 ms
0.1 s
0.1 s
0.1 s
1 ms
1 Clock
Center
Freq.
MHz
− Jitter c−c
Abs Per Min
− SSC Short
Avg Min
− ppm Long
Avg Min
0 ppm
Period
+ ppm Long
Avg Max
+ SSC Short
Avg Max
+ Jitter c−c
Abs Per Max
Units
ns
100.00
133.33
9.94900
7.44925
9.99900
7.49925
10.00000
7.50000
10.00100
7.50075
10.05100
7.55075
ns
Table 11. CLOCK PERIOD SSC ENABLED
SSC ON
Measurement Window
0.1 s
1 Clock
1 ms
0.1 s
0.1 s
1 ms
1 Clock
Center
Freq.
MHz
− Jitter c−c
Abs Per Min
− SSC Short
Avg Min
− ppm Long
Avg Min
0 ppm
Period
+ ppm Long
Avg Max
+ SSC Short
Avg Max
+ Jitter c−c
Abs Per Max
Units
ns
99.75
9.94900
7.44925
9.99900
7.49925
10.02406
7.51805
10.02506
7.51880
10.02607
7.51955
10.05126
7.53845
10.10126
7.58845
133.00
ns
Table 12. INPUT EDGE RATE (Note 46)
Frequency Select (FS)
100 MHz
Min
0.35
0.35
Max
N/A
N/A
Unit
V/ns
V/ns
133 MHz
46.Input edge rate is based on single ended measurement. This is the minimum input edge rate at which the NB3N1200K / NB3W1200L devices
are guaranteed to meet all performance specifications.
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NB3N1200K, NB3W1200L
Measurement Points for Differential
DIFF #
X
Trise (DIFF )
X
VOH = 0.525 V
VCross
VOL = 0.175 V
Tfall (DIFF #)
X
DIFF
X
Figure 4. Single−Ended Measurement Points for Trise, Tfall
Vovs
VHigh
Vrb
Vrb
VLow
Vuds
Figure 5. Single−Ended Measurement Points for Vovs, Vuds, Vrb
TPeriod
High Duty Cycle%
Low Duty Cycle%
Skew measurement point
0.0 V
Figure 6. Differential (DIFFX – DIFFX#) Measurement Points (Tperiod, Duty Cycle, Jitter)
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NB3N1200K, NB3W1200L
600
550
500
450
400
350
300
CLK_IN, CLK_IN#
The differential input clock is expected to be sourced from
a clock synthesizer.
Vcross(rel) Max
OE# and Output Enables (Control Registers)
For
For
Each output can be individually enabled or disabled by
SMBus control register bits. Additionally, each output of the
DIF[11:0] has a dedicated OE# pin. The OE# pins are
asynchronous asserted−low signals. The Output Enable bits
in the SMBus registers are active high and are set to enable
by default.
The disabled state for the NB3N1200K HCSL outputs is
Hi−Z, with the termination network pulling the outputs
Low/Low. The disabled state for the NB3W1200L low
power NMOS Push−Pull outputs is Low/Low. In the
following text, if the NB3N1200K HCSL output is referred
to as Hi−Z or Tri− state, the equivalent state of the
NB3W1200L NMOS Push−pull output is Low/Low.
Please note that the logic level for assertion or deassertion
is different in software than it is on hardware. This follows
hardware default nomenclature for communication
channels (e.g., output is enabled if OE# pin is pulled low)
and still maintains software programming logic (e.g., output
is enabled if OE register is true).
Vhigh < 700 mV
Use Equ. 1
Vhigh > 700 mV
Use Equ. 2
Vcross(rel) Min
250
200
625 650 675 700 725 750 775 800 825 850
VHigh AVERAGE (mV)
Equ 1: Vcross(rel) Max = 0.550 − 0.5(0.7 − Vhavg)
Equ 2: Vcross(rel) Min = 0.250 + 0.5(Vhavg − 0.7)
Figure 7. Vcross Range Clarification
The picture above illustrates the effect of Vhigh above and
below 700 mV on the Vcross range. The purpose of this is
to prevent a 250 mV Vcross with an 850 mV Vhigh. In
addition, this prevents the case of a 550 mV Vcross with a
660 mV Vhigh. The actual specification for Vcross is
dependent upon the measured amplitude of Vhigh.
Please refer to Table 13 for the truth table for enabling and
disabling outputs via hardware and software. Note that both
the control register bit must be a ‘1’ AND the OE# pin must
be a ‘0’ for the output to be active.
NOTE: The assertion and de−assertion of this signal is
absolutely asynchronous.
Table 13. NB3N1200K OE AND POWER MANAGEMENT
Inputs
OE# Hardware Pins & Control Register Bits
Outputs
PWRGD/
PWRDN#
CLK_IN/
CLK_IN#
SMBUS
Enable Bit
FB_OUT/
FB_OUT#
OE# Pin
DIF/DIF# [11:0]
Hi−Z
PLL State
OFF
0
1
X
X
0
1
1
X
X
0
1
Hi−Z
Running
Hi−Z
Running
Running
Running
ON
Running
Hi−Z
ON
ON
Table 14. NB3W1200L POWER MANAGEMENT
Inputs
OE# Hardware Pins & Control Register Bits
Outputs
PWRGD/
PWRDN#
CLK_IN/
CLK_IN#
SMBUS
Enable Bit
NC pins
(Pins 15, 16)
OE# Pin
DIF/DIF# [11:0]
Low/Low
PLL State
OFF
0
1
X
X
0
1
1
X
X
0
1
Low/Low
Running
Running
Running
Running
Low/Low
ON
Running
ON
Low/Low
ON
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NB3N1200K, NB3W1200L
OE# Assertion (Transition from ‘1’ to ‘0’)
Table 16. SMBUS ADDRESS TABLE
All differential outputs that were tri−stated are to resume
normal operation in a glitch free manner. The latency from
the assertion to active outputs is 4 − 12 DIF clock periods.
SA_1
L
SA_0
L
SMBUS Address
D8
DA
DE
C2
C4
C6
CA
CC
CE
L
M
H
OE# De-Assertion (Transition from ‘0’ to ‘1’)
The impact of de−asserting OE# is each corresponding
output will transition from normal operation to tri−state in
a glitch free manner. A minimum of 4 valid clocks will be
provided after the de−assertion of OE#. The maximum
latency from the de−assertion to tri−stated outputs is 12 DIF
clock periods.
L
M
M
M
H
L
M
H
L
H
M
H
100M_133M# − Frequency Selection (FS)
H
The NB3N1200K / NB3W1200L is optimized for lowest
phase jitter performance at 100 MHz and 133 MHz
operating frequencies. The 100M_133M# is a hardware pin,
which programs the appropriate output frequency of the DIF
pairs. Note that the CLK_IN frequency is equal to
CLK_OUT frequency; this means that the NB3N1200K /
NB3W1200L is operated in the 1:1 mode only. The
Frequency Selection can be enabled by the 100M_133M#
hardware pin. An external pull−up or pull−down resistor is
attached to this pin to select the input/output frequency. The
functionality is summarized in Table 15.
PWRGD/PWRDN#
PWRGD is asserted high and de−asserted low.
De−assertion of PWRGD (pulling the signal low) is
equivalent to indicating a powerdown condition. PWRGD
(assertion) is used by the NB3N1200K / NB3W1200L to
sample initial configurations such as frequency select
condition and SA selections.
After PWRGD has been asserted high for the first time,
the pin becomes a PWRDN# (Power Down) pin that can be
used to shut off all clocks cleanly and instruct the device to
invoke power savings mode. PWRDN# is a completely
asynchronous active low input. When entering power
savings mode, PWRDN# should be asserted low prior to
shutting off the input clock or power to ensure all clocks
shut down in a glitch free manner. When PWRDN# is
asserted low, all clocks will be tri-stated prior to turning off
the VCO. When PWRDN# is de-asserted high, all clocks
will start and stop without any abnormal behavior and will
meet all AC and DC parameters.
Table 15. FREQUENCY SELECT (FS) PROGRAM
Optimized Frequency
(CLK_IN = CLK_OUT)
100M_133M#
0
1
133.33 MHz
100.00 MHz
NOTE: All differential outputs transition from 100 MHz
to 133 MHz or from 133 MHz to 100 MHz in a
glitch free manner.
NOTE: The assertion and de-assertion of PWRDN# is
SA_0, SA_1 – Address Selection
absolutely asynchronous.
SA_0 and SA_1 are tri−level hardware pins, which
program the appropriate address for the NB3N1200K /
NB3W1200L. The two tri-level input pins that can
configure the NB3N1200K / NB3W1200L to nine different
addresses (refer to Table 4 for VIL_Tri, VIM_Tri, VIH_Tri
signal level).
WARNING: Disabling of the CLK_IN input clock prior
to assertion of PWRDN# is an undefined
mode and not recommended. Operation in
this mode may result in glitches, excessive
frequency shifting, etc.
Table 17. PWRGD/PWRDN# FUNCTIONALITY
PWRGD/PWRDN#
DIF
DIF#
0
1
Tri−state
Normal
Tri−state
Normal
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NB3N1200K, NB3W1200L
PWRDN# Assertion
When PWRDN# is sampled low by two consecutive rising edges of DIF#, all differential outputs must held tri-stated on the
next DIF# high to low transition.
PWRDN#
DIF
DIF#
Figure 8. PWRDN#—Assertion
PWRGD Assertion
The power−up latency is to be less than 1.8 ms. This is the
time from the valid CLK_IN input clocks and the assertion
of the PWRGD signal to the time that stable clocks are
output from the buffer chip (PLL locked). All differential
outputs stopped in a tri−state condition resulting from power
down must be driven high in less than 300 ms of PWRDN#
de−assertion to a voltage greater than 200 mV.
Tstable
<1.8 mS
PWRGD
DIF
DIF#
Tdrive_PWRDN#
<300 ms; >200 mV
Figure 9. PWRGD Assertion (Pwrdown − De−assertion)
HBW_BYPASS_LBW#
cycle−to−cyclejitter (50 ps + input jitter) on DIF outputs. In
the case of PLL mode, the input clock is passed through a
PLL to reduce high frequency jitter. The PLL HBW,
BYPASS, and PLL LBW mode may be selected by asserting
the HBW_BYPASS_LBW# input pin to the appropriate
level per the following table:
The HBW_BYPASS_LBW# is a tri level function input
pin (refer to Table 13 for VIL_Tri, VIM_Tri,
VIH_Tri−signal level). It is used to select between PLL high
bandwidth, bypass mode and PLL low bandwidth mode. In
the bypass mode, the input clock is passed directly to the
output stage which may result in up to 50 ps of additive
Table 18. PLL BANDWIDTH AND READBACK TABLE
HBW_BYPASS_LBW#
Pin
Byte 0,
Bit 7
Byte 0,
Bit 6
Mode
LBW
L
M
H
0
0
1
0
1
1
BYPASS
HBW
Additionally, the NB3N1200K/NB3W1200L has the
ability to override the Latch value of the PLL operating
mode from hardware strap pin 5 via use of Byte 0, bits 2 and
1. Byte 0 Bit 3 must be set to 1 to allow user to change Bits
2 and 1 to affect the PLL. Bits 7 and 6 will always read back
the original latched value. A warm reset of the system will
have to be accomplished if the user changes these bits.
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NB3N1200K, NB3W1200L
External Feedback Termination
NB3N1200K External Feedback Termination
For 100 W trace impedance line:
Rs = 33 W; Rp = 49.9 W
The NB3N1200K utilizes fixed external feedback
topology to achieve low input−to−output delay variation. A
normal HCSL termination will be needed on the
FB_OUT/FB_OUT# pin 15 and pin 16. A combined shunt
and series resistors value can be used to form a single
termination resistor for the RFB_term.
Therefore,
R
= 82.9 W
FB_term
NOTE: Use the standard 82.5 W, 1% resistor value.
For 85 W trace impedance line:
Rs = 27 W; Rp = 43.2 W
The termination resistor value is the sum of the Rs and Rp
values.
Therefore,
R
= 70.2 W
FB_term
NOTE: Use the standard 69.8 W, 1% resistor value.
R
R
FB_term
FB_term
FB_OUT
FB_OUT#
NB3N1200K
Figure 10. External Feedback Example Schematic
NB3W1200L Feedback Termination
Table 19. FEEDBACK TERMINATION RESISTORS
There is no termination resistor needed at pin 15 and pin
16 of the NB3W1200L NMOS push−pull low power buffer.
Pin 15 and pin 16 of the NB3W1200L are no connect (NC)
pins. These pins have an active signal on them, so they
MUST be left unconnected.
Board Trace Impedance
R
Units
FB_term
100
82.5
1%
W
85
69.8
1%
W
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NB3N1200K, NB3W1200L
Byte Read/Write
Reading or writing a register in a SMBus slave device in
byte mode always involves specifying the register number.
data and the master acknowledges it until the last byte is sent.
The master terminates the transfer with a NAK, then a stop
th
condition. For byte operation, the 2*7 bit of the command
th
byte must be set. For block operations, the 2*7 bit must be
Read. The standard byte read is as shown in the following
figure. It is an extension of the byte write. The write start
condition is repeated then the slave device starts sending
reset. If the bit is not set, the next byte must be the byte
transfer count.
1
T
7
1
1
8
1
1
r
7
1
1
8
1
1
Slave
Wr A Command
A
Slave
Rd A
Data Byte 0
N
P
Repeat starT
Not ack
stoP
Register # to read
2*7 bit = 1
starT
Acknowledge
Condition
Command
Condition
Byte Read Protocol
Figure 11. Byte Read Protocol
Write. The following figure illustrates a simple typical byte
write. For byte operation the 2*7th bit of the command byte
must be set. For block operations, the 2*7th bit must be reset.
If the bit is not set, the next byte must be the byte transfer
count. The count can be between 1 and 32. It is not allowed
to be zero or exceed 32.
1
T
7
1
1
8
1
8
1
1
M to Master to
S to Slave to
Slave
Wr A Command
A
Data Byte 0
A
P
Register # to write
2*7 bit = 1
starT
stoP
Acknowledge
Condition
Command
Condition
Byte Write Protocol
Figure 12. Byte Write Protocol
Block Read/Write
Read. After the slave address is sent with the r/w condition
bitset, the command byte is sent with the MSB = 0. The slave
Ack’s the register index in the command byte. The master
sends a repeat start function. After the slave Ack’s this, the
slave sends the number of bytes it wants to transfer (>0 and
<33). The master Ack’s each byte except the last and sends
a stop function.
1
T
7
1
1
8
1
1
7
1
1
Slave
Wr A Command Code
A
r
Slave
Rd A
repeat starT Condition
Register # to write
2*7 bit = 0
starT
Acknowledge
Condition
Command
8
1
8
1
8
1
1
Data Byte
A
Data Byte 0
A
Data Byte 1
N
P
Not acknowledge
stoP
Condition
Block Read Protocol
Figure 13. Block Read Protocol
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NB3N1200K, NB3W1200L
Write. After the slave address is sent with the r/w condition
will transfer to the slave device. The byte count must be
greater than zero and less than 33. Following this byte are the
data bytes to be transferred to the slave device. The slave
device always acknowledges each byte received. The
transfer is terminated after the slave sends the Ack and the
master sends a stop function.
bit not set, the command byte is sent with the MSB = 0. The
lower seven bits indicate what register to start the transfer at.
If the command byte is 00h, the slave device will be
compatible with existing block mode slave devices. The
next byte of a write must be the count of bytes that the master
1
T
7
1
1
8
1
M to Master to
S to Slave to
Slave Address Wr A Command
A
Register # to write
2*7 bit = 0
starT
Acknowledge
Condition
Command bit
1
8
8
1
8
1
1
Byte Count = 2
A
Data Byte 0
A
Data Byte 1
A
P
stoP
Condition
Block Write Protocol
Figure 14. Block Write Protocol
NB3N1200K/NB3W1200L Control Register
Table 20. BYTE 0: FREQUENCY SELECT, OUTPUT ENABLE, PLL MODE CONTROL REGISTER
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
100M_133M# Frequency Select (FS)
133 MHz
100 MHz
R
Latched at
power up
DIF[11:0]
1
2
3
4
5
6
PLL Mode 0
PLL Mode 1
See PLL Operating Mode
Readback Table
RW
RW
RW
1
1
0
0
0
PLL Software Enable
Reserved
HW Latch
SMBUS Control
Reserved
PLL Mode 0
See PLL Operating Mode
Readback Table
R
R
Latched at
power up
7
PLL Mode 1
See PLL Operating Mode
Readback Table
Latched at
power up
NOTE: Byte 0, bit_[3:1] are BW PLL SW enable for the NB3W1200L and NB3N1200K. Setting bit 3 to ‘1’ allows the
user to override the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating Mode
Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the
system will have to be accomplished if the user changes these bits.
http://onsemi.com
19
NB3N1200K, NB3W1200L
Table 21. BYTE 1: OUTPUT ENABLE CONTROL REGISTER
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
Output Enable DIF 0
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Enabled
RW
1
DIF_0,
DIF_0#
1
2
3
4
5
6
7
Output Enable DIF 1
Output Enable DIF 2
Output Enable DIF 3
Output Enable DIF 4
Output Enable DIF 5
Output Enable DIF 6
Output Enable DIF 7
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
RW
RW
RW
RW
RW
RW
RW
1
1
1
1
1
1
1
DIF_1,
DIF_1#
DIF_2,
DIF_2#
DIF_3,
DIF_3#
DIF_4,
DIF_4#
DIF_5,
DIF_5#
DIF_6,
DIF_6#
DIF_7,
DIF_7#
Table 22. BYTE 2: OUTPUT ENABLE CONTROL REGISTER
Output(s)
Affected
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
Output Enable DIF 8
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Hi−Z for NB3N1200K
Low/Low for NB3W1200L
Enabled
RW
1
DIF_8,
DIF_8#
1
2
3
Output Enable DIF 9
Output Enable DIF 10
Output Enable DIF 11
Enabled
Enabled
Enabled
RW
RW
RW
1
1
1
DIF_9,
DIF_9#
DIF_10,
DIF_10#
DIF_11,
DIF_11#
4
5
6
7
Reserved
Reserved
Reserved
Reserved
http://onsemi.com
20
NB3N1200K, NB3W1200L
Table 23. BYTE 3: OE_[7:0]# PINS REALTIME READBACK CONTROL REGISTER
Output(s)
Affected
Bit
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
If Bit = 0
If Bit = 1
Type
Default
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Table 24. BYTE 4: OE_[11:8]# PINS REALTIME READBACK CONTROL REGISTER
Output(s)
Affected
Bit
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
If Bit = 0
If Bit = 1
Type
Default
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
Table 25. BYTE 5: VENDOR/REVISION IDENTIFICATION CONTROL REGISTER
Bit
0
Description
Vendor ID Bit 0
If Bit = 0
If Bit = 1
Type
R
Default
1
1
1
Vendor ID Bit 1
R
1111 = ON Semiconductor
Vendor ID
2
Vendor ID Bit 2
R
1
3
Vendor ID Bit 3
R
1
4
Revision Code Bit 0
Revision Code Bit 1
Revision Code Bit 2
Revision Code Bit 3
R
X
X
X
X
5
R
0011
Revision Code
6
R
7
R
http://onsemi.com
21
NB3N1200K, NB3W1200L
Table 26. BYTE 6: DEVICE ID CONTROL REGISTER
Bit
0
Description
Device ID 0
If Bit = 0
If Bit = 1
Type
R
1200K
1200L
0
0
0
1
1
1
1
0
0
1
0
0
0
0
0
1
1
Device ID 1
R
2
Device ID 2
R
3
Device ID 3
R
1200K = 120d = 78hex
1200L = 130d = 82hex
4
Device ID 4
R
5
Device ID 5
R
6
Device ID 6
R
7
Device ID 7 (MSB)
R
Table 27. BYTE 7: BYTE COUNT REGISTER
Bit
Description
If Bit = 0
If Bit = 1
Type
Default
0
BC0 − Writing to this register configures
RW
0
0
0
1
0
how many bytes will be read back
1
2
3
4
BC1 − Writing to this register configures
RW
RW
RW
RW
how many bytes will be read back
BC2 − Writing to this register configures
how many bytes will be read back
BC3 − Writing to this register configures
how many bytes will be read back
BC4 − Writing to this register configures
how many bytes will be read back
5
6
7
Reserved
Reserved
Reserved
0
0
0
Table 28. BYTE 8 AND BEYOND: VENDOR SPECIFIC
Bit
0
Description
If Bit = 0
If Bit = 1
Type
Default
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
http://onsemi.com
22
NB3N1200K, NB3W1200L
Buffer Power−Up State Machine
Table 29. BUFFER POWER−UP STATE MACHINE
State
Description
0
1
2
3
3.3 V Buffer power off
After 3.3 V supply is detected to rise above 1.8 V–2.0 V, the buffer enters State 1 and initiates a 0.1 ms–0.3 ms delay.
Buffer waits for a valid clock on the CLK input and PWRDN# de−assertion
Once the PLL is locked to the CLK_IN input clock, the buffer enters state 3 and enables outputs for normal operation.
(Notes 47, 48)
47.The total power up latency from power on to all outputs active must be less than 1.8 ms (assuming a valid clock is present on CLK_IN input).
48.If power is valid and powerdown is de−asserted but no input clocks are present on the CLK_IN input, DIF clocks must remain disabled. Only
after valid input clocks are detected, valid power, PWRDN# de−asserted with the PLL locked/stable and the DIF outputs enabled.
No input clock
State 1
State 2
Wait for input
clock and
powerdown
de−assertion
Delay
0.1 ms − 0.3 ms
Powerdown Asserted
State 3
State 0
Normal
Operation
Power Off
Figure 15. Buffer Power−Up State Diagram
http://onsemi.com
23
NB3N1200K, NB3W1200L
Table 30. DIF CLOCK OUTPUT CURRENT
Board Target Trace/Term Z
Reference R, I = V /(3*R )
Output Current
V
OH
@ Z
ref
DD
r
100 W
85 W
R
= 475 W 1%, I = 2.32 mA
I
I
= 6*I
= 6*I
0.7 V @ 50 W
REF
REF
ref
OH
OH
ref
ref
R
= 412 W, 1%, I = 2.67 mA
0.7 V @ 43.2 W
ref
NMOS Push−Pull Buffer Specifications for NB3W1200L
Low Power NMOS Push−Pull Differential Buffer
The NB3W1200L utilizes the low−power output buffer
for all differential clocks. This buffer uses efficient NMOS
push−pull drivers powered off a low voltage rail, offering a
reduction in power consumption, improved edge rate
performance, and cross point voltage control.
3.3 V
0.8 V Nominal
Receiver
Rs
Rs
Clock
T−Line 10″ Typical
Zo = 20
ohms
2 pF
3.3 V
Core
Source Terminated
2 pF
Clock#
T−Line 10″ Typical
Figure 16. NMOS Push−Pull Buffer Diagram
Power Filtering Example
Ferrite Bead Power Filtering
Recommended ferrite bead filtering equivalent to the following:
600 W impedance at 100 MHz, ≤ 0.1 W DCR max., ≥ 400 mA current rating.
V3P3
Place at pin
VDD for PLL
FB1
R1
2.2
VDDA
C7
FERRITE
C9
1 mF
0.1 mF
R2
2.2
VDDR
C8
VDD for Input Receiver
VDD_DIFF
C10
1 mF
0.1 mF
C5
C5
0.1 mF
0.1 mF
VDD_DIFF
C1
10 mF
C2
0.1 mF
C4
0.1 mF
C3
0.1 mF
C5
0.1 mF
C5
0.1 mF
Figure 17. Schematic Example of the NB3N1200K / NB3W1200L Power Filtering
http://onsemi.com
24
NB3N1200K, NB3W1200L
Termination of Differential Outputs
Table 31. NB3N1200K RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS
Clock
Board Trace Impedance
R
R
RI
ref
Units
s
p
DIFF Clocks –
33
49.9
475
1%
W
50 W configuration
100
85
5%
1%
DIFF Clocks –
43 W configuration
27
5%
42.2
1%
412
1%
W
Table 32. NB3W1200L RESISTIVE LUMPED TEST LOADS FOR DIFFERENTIAL CLOCKS
Clock
Board Trace Impedance
R
R
RI
ref
Units
s
p
DIFF Clocks –
33
W
50 W configuration
100
85
5%
N/A
N/A
N/A
N/A
DIFF Clocks –
43 W configuration
27
5%
W
Termination of Differential HCSL Type Outputs (NB3N1200K)
CLOCK
Rs
TLA = 10 in.
CLOCK#
Rs
TLA = 10 in.
2 pF
5%
2 pF
5%
Rp
Rp
475 W
1%
Figure 18. 0.7 V Configuration Test Load Board Termination for HCSL NB3N1200K
Termination of Differential NMOS Push− Pull Type Outputs (NB3W1200L)
Receiver
Rs
Rs
Clock
T−Line 10″ Typical
Source Terminated
T−Line 10″ Typical
2 pF
2 pF
Clock#
Figure 19. 0.7 V Configuration Test Load Board Termination for NMOS Push−Pull NB3W1200L
http://onsemi.com
25
NB3N1200K, NB3W1200L
PACKAGE DIMENSIONS
QFN64 9x9, 0.5P (PUNCH & SAWN)
CASE 485DH
ISSUE O
2X
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
0.15
C
PIN ONE
INDICATOR
A
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.25mm FROM THE TERMINAL TIP
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. ALL DIMENSIONS APPLY TO BOTH THE
SAWN AND PUNCH PACKAGES.
D
A B
B
PIN ONE
INDICATOR
MILLIMETERS
E
DIM MIN
MAX
1.00
0.05
A
A1
A3
b
0.80
0.00
0.20 REF
2X
0.18
0.30
D
D2
E
9.00 BSC
0.15
C
5.90
6.25
TOP VIEW
TOP VIEW
ALTERNATE CONSTRUCTION
9.00 BSC
E2
e
L
5.90
0.50 BSC
0.30
0.00
6.25
0.50
0.15
DETAIL B
A
A3
A1
0.10
0.08
C
L1
A3
C
SEATING
PLANE
SIDE VIEW
C
NOTE 4
SIDE VIEW
D2
ALTERNATE CONSTRUCTION
64X
L
M
0.10
C A B
DETAIL A
17
17
M
33
33
0.10
C A B
DETAIL C
RECOMMENDED
SOLDERING FOOTPRINT
E2
64X
0.62
9.30
6.40
PACKAGE
OUTLINE
1
1
64
64
49
49
e
e/2
64X b
BOTTOM VIEW
ALTERNATE CONSTRUCTION
M
M
0.10
C A B
NOTE 3
0.05
C
BOTTOM VIEW
9.30
6.40
L1
EXPOSED Cu
MOLD CMPD
L
L
L
64X
0.32
DETAIL A
DETAIL C
DETAIL B
0.50
PITCH
ALTERNATE
ALTERNATE
ALTERNATE
DIMENSIONS: MILLIMETERS
CONSTRUCTIONS
CONSTRUCTION
CONSTRUCTION
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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NB3N1200K/D
相关型号：
NB3W1900L_16
3.3 V 100/133 MHz Differential 1:19 HCSL-Compatible PushâPull Clock ZDB/Fanout Buffer
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