NB3V60113GxxMTR2G [ONSEMI]
1.8 V Programmable OmniClock Generator;
| 型号： | NB3V60113GxxMTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 1.8 V Programmable OmniClock Generator |
| 文件： | 总20页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3V60113G
1.8 V Programmable
OmniClock Generator
with Single Ended (LVCMOS) and Differential
(LVDS/HCSL) Outputs
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The NB3V60113G, which is a member of the OmniClock family, is
a one−time programmable (OTP), low power PLL−based clock
generator that supports any output frequency from 8 kHz to 200 MHz.
The device accepts fundamental mode parallel resonant crystal or a
single ended (LVCMOS) reference clock as input. It generates either
three single ended (LVCMOS) outputs, or one single ended output and
one differential (LVDS/HCSL) output. The output signals can be
modulated using the spread spectrum feature of the PLL
(programmable spread spectrum type, deviation and rate) for
applications demanding low electromagnetic interference (EMI).
Using the PLL bypass mode, it is possible to get a copy of the input
clock on any or all of the outputs. The device can be powered down
using the Power Down pin (PD#). It is possible to program the internal
input crystal load capacitance and the output drive current provided by
the device. The device also has automatic gain control (crystal power
limiting) circuitry which avoids the device overdriving the external
crystal.
WDFN8
CASE 511AT
MARKING DIAGRAM
1
V0MG
G
V0 = Specific Device Code
M
G
= Date Code
= Pb−Free Device
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
Features
• Member of the OmniClock Family of Programmable Clock
Generators
this data sheet.
• Operating Power Supply: 1.8 V 0.1 V
• I/O Standards
♦ Inputs: LVCMOS, Fundamental Mode Crystal
• Power Saving mode through Power Down Pin
• Programmable PLL Bypass Mode
• Programmable Output Inversion
♦ Outputs: LVCMOS
♦ Outputs: LVDS and HCSL
• 3 Programmable Single Ended (LVCMOS) Outputs
from 8 kHz to 200 MHz
• Programming and Evaluation Kit for Field
Programming and Quick Evaluation
• Temperature Range −40°C to 85°C
• Packaged in 8−Pin WDFN
• 1 Programmable Differential Clock Output up to
200 MHz
• Input Frequency Range
• These are Pb−Free Devices
♦ Crystal: 3 MHz to 50 MHz
♦ Reference Clock: 3 MHz to 200 MHz
Typical Applications
• Configurable Spread Spectrum Frequency Modulation
Parameters (Type, Deviation, Rate)
• eBooks and Media Players
• Smart Wearables, Portable Medical and Industrial
• Programmable Internal Crystal Load Capacitors
• Programmable Output Drive Current for Single Ended
Outputs
Equipment
• Set Top Boxes, Printers, Digital Cameras and
Camcorders
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
January, 2016 − Rev. 2
NB3V60113G/D
NB3V60113G
BLOCK DIAGRAM
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
CMOS/
Diff
buffer
Output
Divider
CLK0
PLL Block
XIN/CLKIN
Clock Buffer/
Phase
Crystal
Oscillator and
AGC
Charge
VCO
Pump
CMOS /
Diff
buffer
Crystal
Output
Divider
Detector
CLK1
CLK2
XOUT
Feedback
Divider
Output
Divider
CMOS
buffer
PLL Bypass Mode
GND
Notes:
1. CLK0 and CLK1 can be configured to be one of LVDS or HCSL output, or two single−ended LVCMOS outputs.
2. Dotted lines are the programmable control signals to internal IC blocks.
3. PD# has internal pull down resistor.
Figure 1. Simplified Block Diagram
PIN FUNCTION DESCRIPTION
1
2
3
4
8
7
6
5
XIN/CLKIN
CLK2
XOUT
PD#
VDD
CLK1
CLK0
NB3V60113G
GND
Figure 2. Pin Connections (Top View) – WDFN8
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2
NB3V60113G
Table 1. PIN DESCRIPTION
Pin No.
Pin Name
Pin Type
Description
1
XIN/CLKIN
Input
3 MHz to 50 MHz crystal input connection or an external single−ended reference input
clock between 3 MHz and 200 MHz
2
3
XOUT
PD#
Output
Input
Crystal output. Float this pin when external reference clock is connected at XIN
Asynchronous LVCMOS input. Active Low Master Reset to disable the device and set
outputs Low. Internal pull−down resistor. This pin needs to be pulled High for normal op-
eration of the chip.
4
5
GND
Ground
Power supply ground
CLK0
SE/DIFF
output
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS) signals or Differential (LVDS/
HCSL) signals. Using PLL Bypass mode, the output can also be a copy of the input clock.
The single ended output will be LOW and differential outputs will be complementary LOW/
HIGH until the PLL has locked and the frequency has stabilized.
6
CLK1
SE/DIFF
output
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS) signals or Differential (LVDS/
HCSL) signals. Using PLL Bypass mode, the output can also be a copy of the input clock.
The single ended output will be LOW and differential outputs will be complementary LOW/
HIGH until the PLL has locked and the frequency has stabilized.
7
8
VDD
Power
1.8 V power supply
CLK2
SE
output
Supports 8 kHz to 200 MHz Single−Ended (LVCMOS) signals. Using PLL Bypass mode,
the output can also be a copy of the input clock. The output will be LOW until the PLL has
locked and the frequency has stabilized.
TYPICAL CRYSTAL PARAMETERS
Table 2. POWER DOWN FUNCTION TABLE
Crystal: Fundamental Mode Parallel Resonant
Frequency: 3 MHz to 50 MHz
PD#
0
Function
Device Powered Down
Device Powered Up
1
Table 3. MAX CRYSTAL LOAD CAPACITORS
RECOMMENDATION
Crystal Frequency Range
3 MHz – 30 MHz
Max Cap Value
20 pF
10 pF
30 MHz – 50 MHz
Shunt Capacitance (C0): 7 pF (Max)
Equivalent Series Resistance (ESR): 150 W (Max)
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3
NB3V60113G
FUNCTIONAL DESCRIPTION
The NB3V60113G is a 1.8 V programmable, single ended
ability to configure a number of parameters as detailed in the
following section. The One−Time Programmable memory
allows programming and storing of one configuration in the
memory space.
/ differential clock generator, designed to meet the clock
requirements for consumer and portable markets. It has a
small package size and it requires low power during
operation and while in standby. This device provides the
1.8 V
R (optional)
0.1 mF
0.01 mF
VDD
Crystal or
Reference
Clock input
XIN/CLKIN
XOUT
NB3V60113G
Single Ended Clock
CLK2
PD#
CLK1
CLK0
Single Ended Clocks
OR
GND
Differential Clock
LVDS/HCSL
Figure 3. Power Supply Noise Suppression
Power Supply
20.39 pF with a step size of 0.05 pF. Refer to Table 3 for
recommended maximum load capacitor values for stable
operation. There are three modes of loading the crystal –
with internal chip capacitors only, with external capacitors
only or with the both internal and external capacitors. Check
with the crystal vendor’s load capacitance specification for
setting of the internal load capacitors. The minimum value
of 4.36 pF internal load capacitor need to be considered
while selecting external capacitor value. These will be
bypassed when using an external reference clock.
Device Supply
The NB3V60113G is designed to work with a 1.8 V VDD
power supply. For VDD operation of 3.3 V/2.5 V, refer to
NB3H60113G datasheet. In order to suppress power supply
noise it is recommended to connect decoupling capacitors of
0.1 mF and 0.01 mF close to the VDD pin as shown in
Figure 3.
Clock Input
Input Frequency
Automatic Gain Control (AGC)
The clock input block can be programmed to use a
fundamental mode crystal from 3 MHz to 50 MHz or a
single ended reference clock source from 3 MHz to
200 MHz. When using output frequency modulation for
EMI reduction, for optimal performance, it is recommended
to use crystals with frequency more than 6.75 MHz as input.
Crystals with ESR values of up to 150 W are supported.
When using a crystal input, it is important to set crystal load
capacitor values correctly to achieve good performance.
The Automatic Gain Control (AGC) feature adjusts the
gain to the input clock based on its signal strength to
maintain a good quality input clock signal level. This feature
takes care of low clock swings fed from external reference
clocks and ensures proper device operation. It also enables
maximum compatibility with crystals from different
manufacturers, processes, quality and performance. AGC
also takes care of the power dissipation in the crystal; avoids
over driving the crystal and thus extending the crystal life.
In order to calculate the AGC gain accurately and avoid
increasing the jitter on the output clocks, the user needs to
provide crystal load capacitance as well as other crystal
parameters like ESR and shunt capacitance (C0).
Programmable Crystal Load Capacitors
The provision of internal programmable crystal load
capacitors eliminates the necessity of external load
capacitors for standard crystals. The internal load capacitor
can be programmed to any value between 4.36 pF and
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4
NB3V60113G
Programmable Clock Outputs
frequency modulation. It should be noted that certain
combinations of output frequencies and spread spectrum
configurations may not be recommended for optimal and
stable operation.
For differential clocking, CLK0 and CLK1 can be
configured as LVDS or HCSL. Refer to the Application
Schematic in Figure 4.
Output Type and Frequency
The NB3V60113G provides three independent single
ended LVCMOS outputs, or one single ended LVCMOS
output and one LVDS/HCSL differential output. The device
supports any single ended output or differential output
frequency from 8 kHz up to 200 MHz with or without
1.8 V
0.1 mF
0.01 mF
VDD
Crystal or
Reference
XIN / CLKIN
Clock Input
CLK2
Single Ended Clock
CLK1
CLK0
Differential Clock
LVDS/HCSL
XOUT
NB3V60113G
VDD
PD#
GND
Figure 4. Application Setup for Differential Output Configuration
Programmable Output Drive
Spread Spectrum Frequency Modulation
The drive strength or output current of each of the
Spread spectrum is a technique using frequency
modulation to achieve lower peak electromagnetic
interference (EMI). It is an elegant solution compared to
techniques of filtering and shielding. The NB3V60113G
modulates the output of its PLL in order to “spread” the
bandwidth of the synthesized clock, decreasing the peak
amplitude at the center frequency and at the frequency’s
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most clock generators. Lowering EMI by
increasing a signal’s bandwidth is called ‘spread spectrum
modulation’.
LVCMOS clock outputs is programmable. For V of 1.8 V
DD
four distinct levels of LVCMOS output drive strengths can
be selected as mentioned in the DC Electrical
Characteristics. This feature provides further load drive and
signal conditioning as per the application requirement.
PLL BYPASS Mode
PLL Bypass mode can be used to buffer the input clock on
any of the outputs or all of the outputs. Any of the clock
outputs can be programmed to generate a copy of the input
clock.
Output Inversion
All output clocks of the NB3V60113G can be
phase inverted relative to each other. This feature can also be
used in conjunction with the PLL Bypass mode.
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5
NB3V60113G
Figure 5. Frequency Modulation or Spread Spectrum Clock for EMI Reduction
The outputs of the NB3V60113G can be programmed to
For any input frequency selected, above limits must be
have either center spread from 0.125% to 3% or down
spread from −0.25% to −4%. The programmable step size
for spread spectrum deviation is 0.125% for center spread
and 0.25% for down spread respectively. Additionally, the
frequency modulation rate is also programmable.
Frequency modulation from 30 kHz to 130 kHz can be
selected. Spread spectrum, when on, applies to all the
outputs of the device but not to output clocks that use the
PLL bypass feature. There exists a tradeoff between the
input clock frequency and the desired spread spectrum
profile. For certain combinations of input frequency and
modulation rate, the device operation could be unstable and
should be avoided. For spread spectrum applications, the
following limits are recommended:
observed for a good spread spectrum profile.
For example, the minimum recommended reference
frequency for a modulation rate of 30 kHz would be 30 kHz
* 225 = 6.75 MHz. For 27 MHz, the maximum recommended
modulation rate would be 27 MHz / 225 = 120 kHz.
Control Inputs
Power Down
Power saving mode can be activated through the power
down PD# input pin. This input is an LVCMOS active Low
Master Reset that disables the device and sets outputs Low.
By default it has an internal pull−down resistor. The chip
functions are disabled by default and when PD# pin is pulled
high the chip functions are activated.
Fin (Min) = 6.75 MHz
Configuration Space
Fmod (range) = 30 kHz to 130 kHz
Fmod (Max) = Fin / 225
NB3V60113G has one Configuration. Table 4 shows an
example of device configuration.
Table 4. EXAMPLE CONFIGURATION
Input
Frequency
SS Mod
Rate
Output
Inversion
Output
Enable
Output Frequency
VDD
SS%
Output Drive
PLL Bypass
Notes
24 MHz
CLK0 = 33 MHz
CLK1 = 12 MHz
CLK2 = 24 MHz
1.8 V
−0.5%
100 kHz
CLK0 = 8 mA
CLK1 = 4 mA
CLK2 = 2 mA
CLK0 = N
CLK1 = N
CLK2 = Y
CLK0 = Y
CLK1 = Y
CLK2 = Y
CLK0 = N
CLK1 = N
CLK2 = Y
CLK2 Ref clk
Default Device State
The NB3V60113G parts shipped from ON Semiconductor
are blank, with no inputs/outputs programmed. These need
to be programmed by the field sales or distribution or by the
user themselves before they can be used. Programmable
clock software downloadable from the ON Semiconductor
website can be used along with the programming kit to
achieve this purpose. For mass production, parts can be
programmed with a customer qualified configuration and
sourced from ON Semiconductor as a dash part number (Eg.
NB3V60113G−01).
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NB3V60113G
Table 5. ATTRIBUTES
Characteristic
ESD Protection Human Body Model
Value
2 kV
Internal Input Default State Pull up/ down Resistor
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Flammability Rating Oxygen Index: 28 to 34
50 kW
MSL1
UL 94 V−0 @ 0.125 in
130 k
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 6. ABSOLUTE MAXIMUM RATING (Note 2)
Symbol
Parameter
Positive power supply with respect to Ground
Input Voltage with respect to chip ground
Operating Ambient Temperature Range (Industrial Grade)
Storage temperature
Rating
−0.5 to +4.6
−0.5 to VDD + 0.5
−40 to +85
−65 to +150
265
Unit
V
VDD
V
T
V
I
°C
°C
°C
A
T
STG
T
SOL
Max. Soldering Temperature (10 sec)
q
Thermal Resistance (Junction−to−ambient)
(Note 3)
0 lfpm
500 lfpm
129
84
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−case)
Junction temperature
35 to 40
125
°C/W
°C
JC
T
J
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and not valid simultaneously. If
stress limits are exceeded device functional operation is not implied, damage may occur and reliability may be affected.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). ESD51.7 type board. Back side Copper heat spreader area 100 sq mm, 2 oz
(0.070 mm) copper thickness.
Table 7. RECOMMENDED OPERATION CONDITIONS
Symbol
Parameter
Condition
Min
Typ
Max
Unit
V
DD
Core Power Supply Voltage
1.8 V operation
1.7
1.8
1.9
V
CL
Clock output load capacitance for
LVCMOS clock
f
f
< 100 MHz
≥ 100 MHz
15
5
pF
pF
out
out
fclkin
Crystal Input Frequency
Reference Clock Frequency
Fundamental Crystal
Single ended clock Input
3
3
50
200
MHz
C
XIN / XOUT pin stray Capacitance
Crystal Load Capacitance
Crystal ESR
Note 4
4.5
10
pF
pF
W
X
C
XL
ESR
150
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. The XIN / XOUT pin stray capacitance needs to be subtracted from crystal load capacitance (along with PCB and trace capacitance) while
selecting appropriate load for the crystal in order to get minimum ppm error.
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NB3V60113G
Table 8. DC ELECTRICAL CHARACTERISTICS (V = 1.8 V 0.1 V; GND = 0 V, T = −40°C to 85°C, Notes 5, 14)
DD
A
Symbol
Parameter
Condition
Min
Typ
Max
Unit
I
Power Supply current for core
Configuration Dependent.
13
mA
DD_1.8 V
V
DD
= 1.8 V, T = 25°C,
A
XIN/CLKIN = 25 MHz
(XTAL), CLK[0:2] = 100 MHz, 8 mA
output drive
I
Power Down Supply Current
Input HIGH Voltage
PD# is Low to make all outputs OFF
20
mA
PD
V
V
Pin XIN
0.65 V
V
DD
IH
DD
Pin PD#
0.85 V
V
DD
DD
V
IL
Input LOW Voltage
V
Pin XIN
0
0
0.35 V
0.15 V
DD
DD
Pin PD#
Zo
Nominal Output Impedance
Configuration Dependent. 8 mA drive
22
W
R
Internal Pull up/ Pull down resistor
V
= 1.8 V
150
kW
pF
PUP/PD
DD
Cprog
Programmable Internal Crystal Load Configuration Dependent
Capacitance
4.36
20.39
Programmable Internal Crystal Load
Capacitance Resolution
0.05
4
pF
pF
Cin
Input Capacitance
Pin PD#
6
LVCMOS OUTPUTS
V
Output HIGH Voltage
0.75*V
V
V
OH
DD
V
V
= 1.8 V
= 1.8 V
I
I
I
= 8 mA
= 4 mA
= 2 mA
= 1 mA
DD
OH
OH
OH
I
OH
V
Output LOW Voltage
0.25*V
OL
DD
I
I
I
= 8 mA
= 4 mA
= 2 mA
= 1 mA
DD
OL
OL
OL
I
OL
I
LVCMOS Output Supply Current
Configuration Dependent. T = 25°C,
mA
DD_LVCMOS
A
CLK[0:2] = fout in PLL bypass mode
Measured on V = 1.8 V
DD
f
= 33.33 MHz, C = 5 pF
3
out
L
f
f
= 100 MHz, C = 5 pF
6.5
12
out
out
L
= 200 MHz, C = 5 pF
L
HCSL OUTPUTS (Note 6)
V
Output HIGH Voltage (Note 7)
Output Low Voltage (Note 7)
V
DD
V
DD
V
DD
V
DD
= 1.8 V
= 1.8 V
= 1.8 V
= 1.8 V
700
0
mV
mV
mV
mV
OH_HCSL
V
OL_HCSL
V
Crossing Point Voltage (Notes 8 and 9)
250
350
450
150
CROSS
Delta Vcross Change in Magnitude of Vcross for HCSL Output
(Notes 8 and 10)
I
Measured on V = 1.8 V with
f
f
= 100 MHz, C = 2 pF
22
mA
DD_HCSL
DD
out
out
L
= 200 MHz, C = 2 pF
L
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NB3V60113G
Table 8. DC ELECTRICAL CHARACTERISTICS (V = 1.8 V 0.1 V; GND = 0 V, T = −40°C to 85°C, Notes 5, 14)
DD
A
Symbol
LVDS OUTPUTS (Notes 8 and 11)
Differential Output Voltage
Parameter
Condition
Min
Typ
Max
Unit
V
250
0
450
25
mV
mV
mV
mV
mV
mV
mA
OD_LVDS
DeltaV
Change in Magnitude of VOD for Complementary Output States
Offset Voltage
OD_LVDS
OS_LVDS
V
1200
Delta V
Change in Magnitude of VOS for Complementary Output States
0
25
OS_LVDS
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 13)
V
DD
V
DD
= 1.8 V
= 1.8 V
1425
1075
14
1600
OH_LVDS
V
900
OL_LVDS
I
f
f
= 100 MHz
= 200 MHz
DD_LVDS
out
out
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Measurement taken with single ended clock outputs terminated with test load capacitance of 5 pF and 15 pF and differential clock terminated
with test load of 2 pF. See Figures 7, 8 and 11.
6. Measurement taken with outputs terminated with RS = 0 W, RL = 50 W, with test load capacitance of 2 pF. See Figure 8. Guaranteed by
characterization.
7. Measurement taken from single−ended waveform.
8. Measured at crossing point where the instantaneous voltage value of the rising edge of CLKx+ equals the falling edge of CLKx−.
9. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points
for this measurement.
10.Defined as the total variation of all crossing voltage of rising CLKx+ and falling CLKx−. This is maximum allowed variance in the VCROSS
for any particular system.
11. LVDS outputs require 100 W receiver termination resistor between differential pair. See Figure 9.
12.VOHmax = VOSmax + 1/2 VODmax.
13.VOLmax = VOSmin − 1/2 VODmax.
14.Parameter guaranteed by design verification not tested in production.
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NB3V60113G
Table 9. AC ELECTRICAL CHARACTERISTICS
(V = 1.8 V 0.1 V, GND = 0 V, T = −40°C to 85°C, Notes 15, 16 and 19)
DD
A
Symbol
fout
Parameter
Conditions
Min
0.008
30
Typ
Max
200
130
−4
Unit
MHz
kHz
%
Single Ended Output Frequency
f
Spread Spectrum Modulation Rate
fclkin ≥ 6.75 MHz
MOD
SS
Percent Spread Spectrum
Down Spread
0
(deviation from nominal frequency)
Center Spread
0
3
%
SSstep
Percent Spread Spectrum change
step size
Down Spread step size
Center Spread step size
0.25
0.125
−10
%
%
SSC
Spectral Reduction, 3rd harmonic
@SS=−0.5%, f = 100 MHz, fclkin =
dB
RED
out
25 MHz crystal, RES BW at 30 kHz, All
Output Types
t
t
Stabilization time from Power−up
Stabilization time from Power Down
V
= 1.8 V with Frequency Modulation
3.0
3.0
ms
ms
PU
DD
Time from falling edge on PD# pin to
tri−stated outputs (Asynchronous)
PD
Eppm
Synthesis Error
Configuration Dependent
0
ppm
ps
SINGLE ENDED OUTPUTS (V = 1.8 V 0.1 V; T = −40°C to 85°C, Notes 15, 16 and 19)
DD
A
t
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
100
JITTER−1.8 V
input , f = 100 MHz, SS off
out
(Notes 17, 19 and 21, see Figure 12)
Cycle−Cycle Peak Jitter
Rise/Fall Time
Configuration Dependent. 25 MHz xtal
100
input, f = 100 MHz, SS off
out
(Notes 17, 19 and 21, see Figure 12)
t / t
Measured between 20% to 80% with
ns
%
r
f 1.8 V
15 pF load, f = 100 MHz,
out
V
DD
= V
= 1.8 V,
Max Drive
Min Drive
1
2
DDO
t
Output Clock Duty Cycle
V
DD
= 1.8 V;
DC
Duty Cycle of Ref clock is 50%
PLL Clock
Reference Clock
45
40
50
50
55
60
DIFFERENTIAL OUTPUT (CLK1, CLK0) (V = 1.8 V 0.1 V; T = −40°C to 85°C, Notes 15, 19 and 20)
DD
A
t
Period Jitter Peak−to−Peak
Configuration Dependent. 25 MHz xtal
100
100
ps
ps
ps
JITTER−1.8 V
input, f = 100 MHz, SS off, CLK = OFF
out
(Notes 18, 19, and 21, see Figure 12)
Cycle−Cycle Peak to Peak Jitter
Rise Time
Configuration Dependent. 25 MHz xtal
input, f = 100 MHz, SS off, CLK2 = OFF
out
(Notes 18, 19, and 21, see Figure 12)
t
Measured between 20% to 80%
175
175
700
700
r 1.8 V
V
DD
= 1.8 V
HCSL
LVDS
t
Fall Time
Measured between 20% to 80%
= 1.8 V
ps
f 1.8 V
V
DD
HCSL
LVDS
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NB3V60113G
Table 9. AC ELECTRICAL CHARACTERISTICS
(V = 1.8 V 0.1 V, GND = 0 V, T = −40°C to 85°C, Notes 15, 16 and 19)
DD
A
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
DIFFERENTIAL OUTPUT (CLK1, CLK0) (V = 1.8 V 0.1 V; T = −40°C to 85°C, Notes 15, 19 and 20)
DD
A
t
Output Clock Duty Cycle
V
= 1.8 V;
%
DC
DD
Duty Cycle of Ref clock is 50%
PLL Clock
Reference Clock
45
40
50
50
55
60
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
15.Parameter guaranteed by design verification not tested in production.
16.Measurement taken from single ended clock terminated with test load capacitance of 5 pF and 15 pF and differential clock terminated
with test load of 2 pF. See Figures 6, 7 and 10.
17.Measurement taken from single−ended waveform
18.Measurement taken from differential waveform
19.AC performance parameters like jitter change based on the output frequency, spread selection, power supply and loading conditions of
the output. For application specific AC performance parameters, please contact ON Semiconductor.
20.Measured at f = 100 MHz, No Frequency Modulation, fclkin = 25 MHz fundamental mode crystal and output termination as described
out
in Parameter Measurement Test Circuits
21.Period jitter Sampled with 10000 cycles, Cycle−cycle jitter sampled with 1000 cycles. Jitter measurement may vary. Actual jitter is
dependent on Input jitter and edge rate, number of active outputs, inputs and output frequencies, supply voltage, temperature, and output
load.
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11
NB3V60113G
SCHEMATIC FOR OUTPUT TERMINATION
Figure 6. Typical Termination for Single−Ended and Differential Signaling Device Load
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12
NB3V60113G
PARAMETER MEASUREMENT TEST CIRCUITS
Measurement
Equipment
CLKx
LVCMOS
Clock
Hi−Z Probe
CL
Figure 7. LVCMOS Parameter Measurement
CLK1
Hi−Z Probe
2 pF
Measurement
Equipment
HCSL
Clock
Hi−Z Probe
CLK0
2 pF
50 W
50 W
Figure 8. HCSL Parameter Measurement
CLK1
Hi−Z Probe
Measurement
Equipment
LVDS
Clock
100 W
Hi−Z Probe
CLK0
Figure 9. LVDS Parameter Measurement
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13
NB3V60113G
TIMING MEASUREMENT DEFINITIONS
t
2
t
= 100 * t / t
1 2
DC
t
1
80% of VDD
50% of VDD
20% of VDD
GND
LVCMOS
Clock Output
t
t
r
f
Figure 10. LVCMOS Measurement for AC Parameters
t
2
t
t
= 100 * t /t
1 2
DC
t
1
= t
2
Period
80%
20%
80%
20%
Vcross = 50% of output swing
DVcross
t
r
t
f
Figure 11. Differential Measurement for AC Parameters
t
period−jitter
50% of CLK Swing
Clock
Output
t
t
(N+1)cycle
Ncycle
50% of CLK Swing
Clock
Output
t
= t
− t
CTC−jitter
(N+1)cycle Ncycle (over 1000 cycles)
Figure 12. Period and Cycle−Cycle Jitter Measurement
Tpower-up
Tpower-down
PD#
VIH
VIL
CLK Output
Figure 13. Output Enable/ Disable and Power Down Functions
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14
NB3V60113G
APPLICATION GUIDELINES
Crystal Input Interface
Output Interface and Terminations
Figure 14 shows the NB3V60113G device crystal
oscillator interface using a typical parallel resonant
fundamental mode crystal. A parallel crystal with loading
The NB3V60113G consists of a unique Multi Standard
Output Driver to support LVCMOS, LVDS and HCSL
standards. Termination techniques required for each of these
standards are different to ensure proper functionality. The
required termination changes must be considered and taken
care of by the system designer.
capacitance C = 18 pF would use C1 = 32 pF and C2 =
L
32 pF as nominal values, assuming 4 pF of stray capacitance
per line.
LVCMOS Interface
(
)
CL + C1 ) Cstray ń2; C1 + C2
LVCMOS output swings rail−to−rail up to V supply
DD
The frequency accuracy and duty cycle skew can be
fine−tuned by adjusting the C1 and C2 values. For example,
increasing the C1 and C2 values will reduce the operational
frequency. Note R1 is optional and may be 0 W.
and can drive up to 15 pF load at higher drive strengths. The
output buffer’s drive is programmable up to four steps,
though the drive current will depend on the step setting as
well as the V
supply voltage. (See Figure 15 and
DD
Table 10). Drive strength must be configured high for
driving higher loads. The slew rate of the clock signal
increases with higher output current drive for the same load.
The software lets the user choose the load drive current value
per LVCMOS output based on the V supply selected.
DD
Figure 14. Crystal Interface Loading
Table 10. LVCMOS DRIVE LEVEL SETTINGS
Load Current Setting 3
Load Current Setting 0
Max Load Current
Min Load Current
VDD Supply
Load Current Setting 2
Load Current Setting 1
1.8 V
8 mA
4 mA
2 mA
1 mA
The load current consists of the static current component
(varies with drive) and dynamic current component. For any
supply voltage, the dynamic load current range per
LVCMOS output can be approximated by formula –
the cap load posed by the receiver input pin. C
Cpin+ Cin)
An optional series resistor Rs can be connected at the
output for impedance matching, to limit the overshoots and
ringings.
= (CL +
load
IDD + fout * Cload * VDD
C
load
includes the load capacitor connected to the output,
the pin capacitor posed by the output pin (typically 5 pF) and
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15
NB3V60113G
VDD
Drive Strength
selection
CLKx
Drive Strength
selection
Figure 15. Simplified LVCMOS Output Structure
VDD
LVDS Interface
Differential signaling like LVDS has inherent advantage
of common mode noise rejection and low noise emission,
and thus a popular choice clock distribution in systems.
Iss
TIA/EIA−644 or LVDS is
a standard differential,
point−to−point bus topology that supports fast switching
speeds and has benefit of low power consumption. The
driver consists of a low swing differential with constant
current of 3.5 mA through the differential pair, and
generates switching output voltage across a 100 W
terminating resistor (externally connected or internal to the
receiver). Power dissipation in LVDS standard ((3.5 mA) x
100 W = 1.2 mW) is thus much lower than other differential
signalling standards.
CLK1
CLK0
+
RT
Vout
_
100 W
+
_
2
Vin
Iss
A fan−out LVDS buffer (like ON Semiconductor’s
NB6N1xS and NB6L1xS) can be used as an extension to
provide clock signal to multiple LVDS receivers to drive
multiple point−to−point links to receiving node.
Figure 16. Simplified LVDS Output Structure with
Termination
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16
NB3V60113G
HCSL Termination
optionally used to achieve impedance matching by limiting
overshoot and ringing due to the rapid rise of current from
the output driver. The open source driver has high internal
impedance, thus a series resistor up to 33 W does not affect
HCSL is a differential signaling standard commonly used
in PCIe systems. The HCSL driver is typical 14.5 mA
switched current open source output that needs a 50 W
termination resistor to ground near the source, and generates
725 mV of signal swing. A series resistor (10 W to 33 W) is
the signal integrity. This resistor can be avoided for low V
DD
supply of operation, unless impedance matching requires it.
14.5mA
2.6mA
CLK1
CLK0
50 W
50 W
Figure 17. Simplified HCSL Output Structure with Termination
Field Programming Kit and Software
frequency is independent of signal frequency, and only
depends on the trace length and the propagation delay. For
eg. On an FR4 PCB with approximately 150 ps/ inch of
propagation rate, on a 2 inch trace, the ripple frequency = 1
/ (150 ps * 2 inch * 5) = 666.6 MHz; [5 = number of times
the signal travels, 1 trip to receiver plus 2 additional round
trips]
PCB traces should be terminated when trace length tr/f /
(2* tprate); tr/f = rise/ fall time of signal, tprate =
propagation rate of trace.
The NB3V60113G can be programmed by the user using
the ‘Clock Cruiser Programmable Clock Kit’. This device
uses the 8L daughter card on the hardware kit. To design a
new clock, ‘Clock Cruiser Software’ is required to be
installed from the ON Semiconductor website. The user
manuals for the hardware kit Clock Cruiser Programmable
Clock Kit and Clock Cruiser Software can be found
following the link www.onsemi.com.
Recommendation for Clock Performance
Clock performance is specified in terms of Jitter in time
the domain and Phase noise in frequency domain. Details
and measurement techniques of Cycle−cycle jitter, period
jitter, TIE jitter and Phase Noise are explained in application
note AND8459/D.
Ringing
Overshoot
(Positive)
In order to have a good clock signal integrity for minimum
data errors, it is necessary to reduce the signal reflections.
Reflection coefficient can be zero only when the source
impedance equals the load impedance. Reflections are based
on signal transition time (slew rate) and due to impedance
mismatch. Impedance matching with proper termination is
required to reduce the signal reflections. The amplitude of
overshoots is due to the difference in impedance and can be
minimized by adding a series resistor (Rs) near the output
pin. Greater the difference in impedance, greater is the
amplitude of the overshoots and subsequent ripples. The
ripple frequency is dependant on the signal travel time from
the receiver to the source. Shorter traces results in higher
ripple frequency, as the trace gets longer the travel time
increases, reducing the ripple frequency. The ripple
Overshoot
(Negative)
Figure 18. Signal Reflection Components
PCB Design Recommendation
For a clean clock signal waveform it is necessary to have
a clean power supply for the device. The device must be
isolated from system power supply noise. A 0.1 mF and a
2.2 mF decoupling capacitor should be mounted on the
component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling
capacitor and VDD pin. The PCB trace to VDD pin and the
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17
NB3V60113G
Device Applications
The NB3V60113G is targeted mainly for the Consumer
market segment and can be used as per the examples below.
ground via should be kept thicker and as short as possible.
All the VDD pins should have decoupling capacitors.
Stacked power and ground planes on the PCB should be
large. Signal traces should be on the top layer with minimum
vias and discontinuities and should not cross the reference
planes. The termination components must be placed near the
source or the receiver. In an optimum layout all components
are on the same side of the board, minimizing vias through
other signal layers.
Clock Generator
Consumer applications like a Set top Box, have multiple
sub−systems and standard interfaces and require multiple
reference clock sources at various locations in the system.
This part can function as a clock generating IC for such
applications generating a reference clock for interfaces like
USB, Ethernet, Audio/Video, ADSL, PCI etc.
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
CMOS/
Output
Diff
CLK0
Divider
buffer
PLL Block
Video
USB
27MHz
XIN/CLKIN
Clock Buffer/
Phase
Crystal
Oscillator and
AGC
Charge
CMOS /
Diff
buffer
VCO
Crystal
Output
Divider
Detector
Pump
CLK1
XOUT
48MHz
25MHz
Feedback
Divider
Output
Divider
CMOS
buffer
CLK2
25MHz
Ethernet
PLL Bypass Mode
GND
Figure 19. Application as Clock Generator
Buffer and Logic/Level Translator
The device can be simultaneously used as logic translator for
converting the LVCMOS input clock to HCSL or LVDS.
For instance this device can be used in applications like an
LCD monitor, for converting the LVCMOS input clock to
LVDS output.
The NB3V60113G is useful as a simple CMOS Buffer in
PLL bypass mode. One or more outputs can use the PLL
Bypass mode to generate the buffered outputs. If the PLL is
configured to use spread spectrum, all outputs using PLL
Bypass feature will not be subjected to the spread spectrum.
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
CMOS/
Output
Diff
LVCMOS
CLK0
Divider
buffer
PLL Block
XIN/CLKIN
LVDS
Clock Buffer/
Phase
Crystal
Oscillator and
AGC
Charge
CMOS /
Diff
buffer
VCO
Crystal
Output
Divider
Detector
Pump
CLK1
CLK2
XOUT
Feedback
Divider
Output
Divider
CMOS
buffer
PLL Bypass Mode
GND
Figure 20. Application as Level Translator
NOTE: LVCMOS signal level cannot be translated to a higher level of LVCMOS voltage.
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18
NB3V60113G
EMI Attenuator
clock outputs (not bypass outputs) even if they are at
different frequencies. In Figure 21, CLK0 uses the PLL and
hence is subjected to the spread spectrum modulation while
CLK1 and CLK2 use the PLL Bypass mode and hence are
not subjected to the spread spectrum modulation.
Spread spectrum through frequency modulation
technique enables the reduction of the EMI radiated from the
high frequency clock signals by spreading the spectral
energy to the nearby frequencies. While using frequency
modulation, the same selection is applied to all the PLL
PD#
VDD
Crystal/Clock Control
Output control
Configuration
Memory
Frequency
and SS
CMOS/
Output
Diff
CLK0
Divider
buffer
PLL Block
12MHz 0.375%
CPU
XIN/CLKIN
Clock Buffer/
Phase
Crystal
Oscillator and
AGC
Charge
CMOS /
Diff
buffer
VCO
Crystal
Output
Divider
Detector
Pump
CLK1
XOUT
12MHz
USB1
12MHz
Feedback
Divider
Output
Divider
CMOS
buffer
CLK2
12MHz
USB2
PLL Bypass Mode
GND
Figure 21. Application as EMI Attenuator
ORDERING INFORMATION
Device
†
Type
Package
Shipping
NB3V60113G00MTR2G
Blank Device
DFN−8
(Pb−Free)
3000 / Tape & Reel
3000 / Tape & Reel
NB3V60113GxxMTR2G
Factory Pre−Programmed
Device
DFN−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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19
NB3V60113G
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT
ISSUE O
L
L
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
0.20 REF
2X
0.10
C
0.20
0.30
EXPOSED Cu
MOLD CMPD
TOP VIEW
2.00 BSC
2.00 BSC
0.50 BSC
D
E
e
DETAIL B
L
0.40
---
0.50
0.60
0.15
0.70
0.05
C
L1
L2
DETAIL B
ALTERNATE
CONSTRUCTIONS
A
8X
0.05
C
A1
A3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
C
SIDE VIEW
7X
0.78
PACKAGE
OUTLINE
e/2
e
DETAIL A
7X
L
4
1
L2
2.30
0.88
1
8
5
8X
b
0.50
PITCH
8X
0.30
0.10
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
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Phone: 81−3−5817−1050
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Order Literature: http://www.onsemi.com/orderlit
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For additional information, please contact your local
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NB3V60113G/D
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