NB3V1106CDTR2G [ONSEMI]
LVCMOS Low Skew Fanout Buffer Family;
| 型号： | NB3V1106CDTR2G |
| 厂家： | 
ONSEMI |
| 描述： | LVCMOS Low Skew Fanout Buffer Family |
| 文件： | 总13页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NB3V110xC Series
3.3V/2.5V/1.8V LVCMOS
Low Skew Fanout Buffer
Family
Description
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The NB3V110xC are a modular, high−performance, low−skew,
general purpose LVCMOS clock buffer family. The family of devices
is designed with a modular approach. Four different fan−out
variations, 1:2, 1:3, 1:4, 1:6 and 1:8, are available. All of the devices
are pin compatible to each other for easy handling. All family
members share the same high performing characteristics like low
additive jitter, low skew, and wide operating temperature range. The
NB3V110xC supports an asynchronous output enable control (OE)
which switches the outputs into a low state when OE is low. The
NB3V110xC devices operate in a 3.3 V, 2.5 V and 1.8 V environment
and are characterized for operation from −40°C to 105°C.
TSSOP−8
DT SUFFIX
CASE 948S
TSSOP−14
DT SUFFIX
CASE 948G
TSSOP−16
DT SUFFIX
CASE 948F
WDFN8, 2x2
MT SUFFIX
CASE 511AT
Features
• Operating Temperature Range: –40°C to 105°C
• High−Performance 1:2, 1:3, 1:4, 1:6, 1:8 LVCMOS Clock Buffer
• Available in 8−, 14−, 16−Pin TSSOP and WDFN8 Packages
• Very Low Output−to−Output Skew < 50 ps
• Very Low Additive Jitter < 200 fs
MARKING DIAGRAMS
8
16
14
1108
1106
10x
YWW
AG
V
ALYWG
G
V
ALYWG
G
• Supply Voltage: 3.3 V, 2.5 V or 1.8 V
• f
= 250 MHz for 3.3 V; f
= 133 MHz for 1.8 V
= 180 MHz for 2.5 V;
max
max
f
1
max
1
1
• These Devices are Pb−Free and are RoHS Compliant
TSSOP−8
TSSOP−14
TSSOP−16
BLOCK DIAGRAM
1
0X MG
LV
CMOS
LV
CMOS
Q0
Q1
Q2
Q3
CLKIN
G
LV
CMOS
WDFN8
A
M
L
= Assembly Location
= Date Code
= Wafer Lot
LV
CMOS
Y
= Year
LV
CMOS
W, WW = Work Week
G
= Pb−Free Package
S
S
(Note: Microdot may be in either location)
S
LV
CMOS
ORDERING INFORMATION
See detailed ordering, marking and shipping information on
page 9 of this data sheet.
Qn
OE
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
January, 2017 − Rev. 3
NB3V1102C/D
NB3V110xC Series
CLKIN
OE
1
2
3
4
5
6
7
8
16
Q1
CLKIN
OE
15
14
1
2
3
4
5
6
7
14
13
12
11
10
9
Q1
Q3
Q0
Q3
VDD
Q2
CLKIN
OE
Q1
1
2
3
4
8
7
6
5
Q0
GND
VDD
Q4
13
12
11
10
9
VDD
Q2
NB3V1108C
NB3V1102C
NB3V1103C
NB3V1104C
NC/Q3
VDD
GND
VDD
Q4
GND
Q5
NB3V1106C
Q0
GND
Q5
NC/Q2
GND
GND
Q6
VDD
Q7
TSSOP−8 and WDFN8
GND
8
VDD
TSSOP−14
TSSOP−16
Figure 1. Pin Configuration
Table 1. PIN DESCRIPTION
LVCMOS Clock
Input
LVCMOS Clock
Output Enable
Device
Supply Voltage
Device
Ground
LVCMOS Clock Output
Q0, Q1, ... Q7
3, 8
CLKIN
OE
2
VDD
GND
Devices
NB3V1102C
NB3V1103C
NB3V1104C
NB3V1106C
NB3V1108C
1
1
1
1
1
6
4
4
2
3, 8, 5
6
2
3, 8, 5, 7
6
4
2
3, 14, 11, 13, 6, 9
3, 16, 13, 15, 6, 11, 8, 9
5, 8, 12
5, 10, 14
4, 7, 10
4, 7, 12
2
NOTE: Pins not mentioned in the table are NC.
Table 2. OUTPUT LOGIC TABLE
INPUTS
OUTPUTS
CLKIN
OE
L
Qn
L
X
L
H
L
H
H
H
Table 3. ATTRIBUTES
Characteristic
Value
Unit
ESD Protection
Human Body Model (HBM) per ANSI/ESDA/JEDEC JS−001−2014
Charged Device Model (CDM) per ANSI/ESDA/JEDEC JS−002−2014
5000
1500
V
V
Moisture Sensitivity, Indefinite Time Out of Dry Pack (Note 1)
Meets or exceeds JEDEC Spec JESD78D (LU) IC Latchup Test
Level 1
−
2
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm , 2 oz.)
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2
NB3V110xC Series
Table 4. ABSOLUTE MAXIMUM RATINGS (Note 2)
Over operating free−air temperature range (unless otherwise noted)
Symbol
Condition
Value
Unit
V
V
DD
Supply Voltage Range
Input Voltage Range (Note 3)
Output Voltage Range (Note 3)
Input Current
–0.5 to 4.6
V
IN
–0.5 to V + 0.5
V
DD
V
O
–0.5 to V + 0.5
V
DD
I
IN
20
50
mA
mA
°C/W
I
O
Continuous Output Current
q
Thermal Resistance (Junction−to−Ambient)
TSSOP−8
151.2*
104*
32*
JA
TSSOP−14
TSSOP−16
110**
190**
35
WDFN8
TSSOP−8
TSSOP−14
TSSOP−16
WDFN8
q
Thermal Resistance (Junction−to−Case top)
°C/W
JC
8.6
10
10
T
Maximum Junction Temperature
Storage Temperature Range
125
°C
°C
J
T
–65 to 150
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2
2. JEDEC standard multilayer board – 2S2P (2 signal, 2 power) with a large copper heat spreader (20 mm , 2 oz.)
3. For additional information, see Application Note AND8003/D.
*JEDEC51.7 four layer PCB with 100 sqmm, 2 oz with two 80x80x1oz ground planes.
**JEDEC51.3 two layer PCB with 100 sqmm, 2 oz.
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3
NB3V110xC Series
Table 5. RECOMMENDED OPERATING CONDITIONS
Over operating free−air temperature range (unless otherwise noted)
Symbol
Condition
Min
3.0
Typ
3.3
2.5
1.8
Max
3.6
Unit
VDD
Supply voltage range
3.3 V supply
2.5 V supply
V
2.3
2.7
1.8 V supply
1.71
1.89
VIL
VIH
Vth
Low−level input voltage
VDD = 3.0 V to 3.6 V
VDD/2 –
600
mV
VDD = 2.3 V to 2.7 V
VDD/2 –
400
VDD = 1.71 V to 1.89 V
VDD = 3.0 V to 3.6 V
0.3xVDD
V
High−level input voltage
Input threshold voltage
VDD/2 +
600
mV
VDD = 2.3 V to 2.7 V
VDD/2 +
400
VDD = 1.71 V to 1.89 V
VDD = 2.3 V to 3.6 V
VDD = 1.71 V to 1.89 V
0.7xVDD
V
V
VDD/2
VDD/2
V
tr / tf
tw
Input slew rate (Note 4)
1
4
V/ns
ns
Minimum pulse width at CLKIN
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 1.71 V to 1.89 V
VDD = 3.0 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 1.71 V to 1.89 V
1.8
2.75
3.75
DC
DC
DC
–40
fCLK
LVCMOS clock Input Frequency
250
180
133
105
MHz
TA
Operating free−air temperature
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
4. Guaranteed by Design.
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4
NB3V110xC Series
Table 6. DEVICE CHARACTERISTICS Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
OVERALL PARAMETERS FOR ALL VERSIONS
I
Static device current
OE = V ; CLKIN = 0 V or V ; I = 0 mA; V
3.6 V
=
=
=
0.2
0.2
0.2
60
mA
DD
DD
DD
O
DD
DD
DD
OE = V ; CLKIN = 0 V or V ; I = 0 mA; V
DD
DD
O
2.7 V
OE = V ; CLKIN = 0 V or V ; I = 0 mA; V
DD
DD
O
1.89 V
OE = 0 V; CLKIN = 0 V or V ; I = 0 mA; V =
DD
I
Power down current
mA
PD
DD
O
3.6 V, 2.7 V or 1.89 V (For 1102C, 1103C, 1104C)
OE = 0 V; CLKIN = 0 V or V ; I = 0 mA; V
=
DD
75
DD
O
3.6 V, 2.7 V or 1.89 V (For 1106C, 1108C)
C
Power dissipation capacitance per out-
put (Note 6)
V
V
V
= 3.3 V; f = 10 MHz
= 2.5 V; f = 10 MHz
= 1.8 V; f = 10 MHz
9
9
9
pF
mA
PD
DD
DD
DD
I
Input leakage current at OE
Input leakage current at CLKIN
Input leakage current at OE, CLKIN
Output impedance
V = 0 V or V , V = 3.6 V or 2.7 V
I
8
8
8
I
DD
DD
V = 0 V or V , V = 1.89 V
I
DD
DD
R
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3.3 V
= 2.5 V
= 1.8 V
40
45
60
W
OUT
f
Output frequency
= 3.0 V to 3.6 V
= 2.3 V to 2.7 V
= 1.71 V to 1.89 V
DC
DC
DC
250
180
133
MHz
OUT
OUTPUT PARAMETERS FOR V = 3.3 V + 0.3 V
DD
V
OH
High−level output voltage
V
V
V
V
V
V
= 3 V, I = –0.1 mA
2.9
2.5
2.2
V
V
DD
DD
DD
DD
DD
DD
OH
= 3 V, I = –8 mA
OH
= 3 V, I = –12 mA
OH
V
OL
Low−level output voltage
= 3 V, I = 0.1 mA
0.1
0.5
0.8
2.0
50
OL
= 3 V, I = 8 mA
OL
= 3 V, I = 12 mA
OL
t
, t
Propagation delay (Note 7)
Output skew (Note 7)
CLKIN to Qn
0.8
ns
ps
PLH PHL
t
Equal load of each output 85°C
Equal load of each output 105°C
sk(o)
60
t /t
Rise and fall time
20%–80% (V − V )
OL
0.12
0.8
6
ns
ns
ns
ps
ns
fs
r
f
OH
t
Output disable time (Note 7)
Output enable time (Note 7)
OE to Qn
OE to Qn
DIS
t
6
EN
t
Pulse skew; tPLH(Qn) – tPHL(Qn) (Note 8) To be measured with input duty cycle of 50%
180
0.5
100
sk(p)
t
Part−to−part skew
Additive jitter rms
Under equal operating conditions for two parts
sk(pp)
12 kHz...20 MHz f
12 kHz...20 MHz f
= 100 MHz
T
jit(
f
OUT
OUT
)
= 156.25 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. All typical values are at respective nominal V . For switching characteristics, outputs are terminated to 50 W to V /2 (see Figure 2).
DD
DD
6. This is the formula for the power dissipation calculation.
Ptot = Pstat + Pdyn + PCload [W] P
= V x I [W]
stat
DD DD
P
P
= C x V 2 x ƒ x n [W]
dyn
PD DD
= C
x V 2 x ƒ x n [W]
DD
Cload
load
n = Number of switching output pins
7. With rail to rail input clock.
8. t
depends on output rise− and fall−time (t /t ). The output duty−cycle can be calculated: odc = (t
t
)/t
; t
is
sk(p)
r
f
w(OUT)
sk(p) period w(OUT)
pulse−width of ideal output waveform and tperiod is 1/f
.
OUT
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5
NB3V110xC Series
Table 7. DEVICE CHARACTERISTICS (continued)
Over recommended operating free−air temperature range (unless otherwise noted) (Note 5)
Symbol Parameter Condition
Min
Typ
Max
Unit
V
OUTPUT PARAMETERS FOR V = 2.5 V + 0.2 V
DD
V
High−level output voltage
V
V
V
V
= 2.3 V, I = –0.1 mA
2.2
1.7
OH
DD
DD
DD
DD
OH
= 2.3 V, I = –8 mA
OH
V
Low−level output voltage
= 2.3 V, I = 0.1 mA
0.1
0.5
V
OL
OL
= 2.3 V, I = 8 mA
OL
t
, t
Propagation delay (Note 10)
Output skew (Note 10)
CLKIN to Qn
1.8
ns
ps
PLH PHL
t
Equal load of each output 85°C
Equal load of each output 105°C
50
60
sk(o)
t /t
Rise and fall time
20%–80% (V − V )
OL
0.12
1.2
10
ns
ns
ns
ps
r
f
OH
t
Output disable time (Note 10)
Output enable time (Note 10)
OE to Qn
OE to Qn
DIS
t
10
EN
t
t
Pulse skew ; PLH(Qn) – tPHL(Qn)
To be measured with input duty cycle of 50%
220
sk(p)
(Note 9)
t
Part−to−part skew
Under equal operating conditions for two
parts
1.2
ns
fs
sk(pp)
tjit
Additive jitter rms
12 kHz...20 MHz f
12 kHz...20 MHz f
= 100 MHz
150
100
f
(
)
OUT
OUT
= 156.25 MHz
OUTPUT PARAMETERS FOR V = 1.8 V + 5%
DD
V
High−level output voltage
V
V
V
V
= 1.71 V, I = –0.1 mA
1.6
V
V
OH
DD
DD
DD
DD
OH
= 1.71 V, I = –4 mA
0.75xV
OH
DD
V
OL
Low−level output voltage
= 1.71 V, I = 0.1 mA
0.1
0.25xV
3.5
OL
= 1.71 V, I = 4 mA
OL
DD
t
, t
Propagation delay (Note 10)
Output skew (Note 10)
CLKIN to Qn
1.8
ns
ps
ns
ns
ns
ps
PLH PHL
t
Equal load of each output
75
sk(o)
t /t
Rise and fall time
20%–80% (V − V )
OL
0.17
1.2
r
f
OH
t
Output disable time (Note 10)
Output enable time (Note 10)
OE to Qn
OE to Qn
10
DIS
t
10
EN
t
t
Pulse skew ; PLH(Qn) – tPHL(Qn)
To be measured with input duty cycle of 50%
450
sk(p)
(Note 9)
t
Part−to−part skew
Under equal operating conditions for two
parts
1.2
ns
sk(pp)
tjit
(
Additive jitter rms
12 kHz...20 MHz, f
= 100 MHz
200
fs
f
OUT
)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. t
depends on output rise− and fall−time (t /t ). The output duty−cycle can be calculated: odc = (t
t
)/t
; t
is
sk(p)
r
f
w(OUT)
sk(p) period w(OUT)
pulse−width of ideal output waveform and tperiod is 1/f
10.With rail to rail input clock.
.
OUT
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6
NB3V110xC Series
PARAMETERS MEASUREMENT INFORMATION
V
= 3.3 V, 2.5 V or 1.8 V
DD
LVCMOS
Output
Z
= 50 Ω
O
R=50 W
C=2pF
from Measurement Equipment
parasitic capacitance
V
/2
DD
Figure 2. Test Load Circuit
V
DD
V
= 3.3 V, 2.5V or 1.8 V
DD
R=100 W
LVCMOS
Output
Z
= 50 Ω
O
parasitic input capacitance
R=100 W
Figure 3. Application Load with 50 W Line Termination
V
= 3.3 V, 2.5 V or 1.8 V
DD
RS = 10 Ohms (V = 3.3 V)
DD
RS = 5 Ohms (V = 2.5 V)
DD
RS = 0 Ohms (V = 1.8 V)
DD
LVCMOS
Output
Z
= 50 Ω
O
parasitic input capacitance
Figure 4. Application Load with Series Line Termination
VDD /2
VIN /2
Qn
OE
Qn
VIN /2
VDD /2
Qn+1
tsk(o)
Figure 6. Output Skew tSk(o)
tDIS
tEN
tsk(o)
Figure 5. tDIS and tEN for Disable Low
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7
NB3V110xC Series
V
/ 2
DD
CLKIN
CLKIN
V
OH
80% V
−V
OH OL
Q
n
V
/ 2
DD
20% V
−V
OH OL
Q
n
V
OL
t
t
f
r
t
PLH
t
PHL
Note: t
= |t
− t
PHL
|
sk(p)
PLH
Figure 7. Pulse Skew tsk(p) and Propagation Delay
PLH/tPHL
Figure 8. Rise/Fall Times tr /tf
t
F_carrier = 100 MHz
Integration Range: 12 kHz − 20 MHz
DUT + Source Phase Jitter = 66.92 fs
Input Source Phase Jitter = 36.72 fs
Output (DUT + Source)
Input Source
Output
Input Source 100 MHz
Figure 9. Typical NB3V110xC Phase Noise Plot at fCarrier = 100 MHz, VDD = 3.3 V, 255C
The above phase noise data was captured using Agilent
E5052A/B. The data displays the input phase noise and
output phase noise used to calculate the additive phase jitter
at a specified integration range. The additive RMS phase
jitter contributed by the device (integrated between 12 kHz
and 20 MHz) is 55.94 fs. The additive RMS phase jitter
performance of the fan out buffer is highly dependent on the
phase noise of the input source.
To obtain the most precise additive phase noise
measurement, it is vital that the source phase noise be
notably lower than that of the DUT. If the phase noise of the
source is greater than the noise floor of the device under test,
the source noise will dominate the additive phase jitter
calculation and lead to an incorrect negative result for the
additive phase noise within the integration range. The
Figure above is a good example of the NB3V110xC source
generator phase noise having a significantly lower floor than
the DUT and results in an additive phase jitter of 55.94 fs.
Ǹ
2
2
Additive RMS phase jitter + RMS phase jitter of output * RMS phase jitter of input
2
2
55.94 fs + Ǹ66.92 fs * 36.72 fs
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8
NB3V110xC Series
F_carrier = 156.25 MHz
Integration Range: 12 kHz − 20 MHz
DUT + Source Phase Jitter = 51.76 fs
Input Source Phase Jitter = 23.5 fs
Output (DUT + Source)
Input Source
Output
Input Source 156.25 MHz
Figure 10. Typical NB3V110xC Phase Noise Plot at fCarrier = 156.25 MHz, VCC = 3.3 V V, 255C
The additive RMS phase jitter contributed by the device (integrated between 12 kHz and 20 MHz) is 46.11 fs.
Ǹ
2
2
Additive RMS phase jitter + RMS phase jitter of output * RMS phase jitter of input
2
2
46.11 fs + Ǹ51.76 fs * 23.5 fs
Figures 9 and 10 were created with measured data from
Agilent−E5052A/B Signal Source Analyzer using ON
Semiconductor Phase Noise Explorer web tool. This free
application enables an interactive environment for advanced
phase noise and jitter analysis of timing devices and clock
tree designs. To see the performance of NB3V110xC
beyond conditions outlined in this datasheet, please visit the
ON Semiconductor Green Point Design Tools homepage.
Table 8. ORDERING INFORMATION
†
Device
NB3V1102CDTR2G
Marking
102
Package
Shipping
TSSOP−8
(Pb−Free)
NB3V1103CDTR2G
NB3V1104CDTR2G
NB3V1102CMTTBG
NB3V1104CMTTBG
NB3V1106CDTR2G
103
2500 / Tape & Reel
104
02
WDFN8
(Pb−Free)
3000 / Tape & Reel
04
1106
V
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
2500 / Tape & Reel
NB3V1108CDTR2G
1108
V
TSSOP−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NOTE: Please contact your ON Semiconductor sales representative for availability of parts in tube.
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9
NB3V110xC Series
PACKAGE DIMENSIONS
TSSOP−8
CASE 948S
ISSUE C
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.20 (0.008) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
8
5
4
2X L/2
B
−U−
J
J1
L
1
PIN 1
IDENT
K1
K
S
0.20 (0.008) T U
A
SECTION N−N
−V−
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
4.50
1.10
0.15
0.70
MAX
0.122
0.177
0.043
0.006
0.028
A
B
2.90
4.30
---
0.114
0.169
---
−W−
C
C
0.076 (0.003)
D
0.05
0.50
0.002
0.020
F
DETAIL E
SEATING
D
−T−
G
G
J
0.65 BSC
0.026 BSC
PLANE
0.09
0.09
0.19
0.19
0.20
0.16
0.30
0.25
0.004
0.004
0.007
0.007
0.008
0.006
0.012
0.010
J1
K
0.25 (0.010)
N
K1
L
6.40 BSC
0.252 BSC
0
M
M
0
8
8
_
_
_
_
N
F
DETAIL E
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10
NB3V110xC Series
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
NOTES:
14X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
S
0.15 (0.006) T U
N
0.25 (0.010)
14
8
2X L/2
M
B
−U−
L
N
PIN 1
IDENT.
F
7
1
DETAIL E
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
K
0.15 (0.006) T U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
K1
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
J J1
1.20
−−− 0.047
0.15 0.002 0.006
0.75 0.020 0.030
SECTION N−N
G
H
J
J1
K
0.65 BSC
0.026 BSC
0.60 0.020 0.024
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.50
0.09
0.09
0.19
−W−
C
K1 0.19
L
M
6.40 BSC
0.252 BSC
0.10 (0.004)
0
8
0
8
_
_
_
_
SEATING
−T−
H
G
DETAIL E
D
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
www.onsemi.com
11
NB3V110xC Series
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
N
−V−
A
B
4.90
4.30
−−−
5.10 0.193 0.200
4.50 0.169 0.177
F
C
1.20
−−− 0.047
D
F
0.05
0.50
0.15 0.002 0.006
0.75 0.020 0.030
DETAIL E
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
H
DETAIL E
SEATING
−T−
M
0
8
0
8
_
_
_
_
D
PLANE
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
www.onsemi.com
12
NB3V110xC Series
PACKAGE DIMENSIONS
WDFN8 2x2, 0.5P
CASE 511AT
ISSUE O
L
L
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
L1
PIN ONE
REFERENCE
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
MILLIMETERS
DIM
A
MIN
0.70
0.00
MAX
0.80
0.05
2X
0.10
C
A1
A3
b
0.20 REF
2X
0.10
C
0.20
0.30
EXPOSED Cu
MOLD CMPD
TOP VIEW
2.00 BSC
D
E
2.00 BSC
0.50 BSC
e
DETAIL B
L
0.40
---
0.60
0.15
0.70
0.05
C
L1
L2
DETAIL B
0.50
A
ALTERNATE
CONSTRUCTIONS
8X
0.05
C
A1
A3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
C
SIDE VIEW
7X
0.78
PACKAGE
OUTLINE
e/2
e
DETAIL A
7X
L
4
1
L2
2.30
0.88
1
8
5
8X
b
0.50
PITCH
8X
0.30
0.10
0.05
C
A
B
DIMENSIONS: MILLIMETERS
NOTE 3
C
BOTTOM VIEW
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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