MC74VHC157DTR2 [ONSEMI]
Quad 2--Channel Multiplexer; 四2 - 通道多路复用器
| 型号： | MC74VHC157DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2--Channel Multiplexer |
| 文件： | 总7页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC157
Quad 2--Channel Multiplexer
The MC74VHC157 is an advanced high--speed CMOS quad
2--channel multiplexer, fabricated with silicon gate CMOS
technology. It achieves high--speed operation similar to equivalent
Bipolar--Schottky TTL, while maintaining CMOS low--power
dissipation.
It consists of four 2--input digital multiplexers with common select
(S) and enable (E) inputs. When E is held High, selection of data is
inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
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MARKING
DIAGRAMS
16
9
8
VHC157
AWLYYWW
SOIC--16
D SUFFIX
CASE 751B
1
• High Speed: tPD = 4.1 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C
• High Noise Immunity: VNIH = VNIL = 28% VCC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
16
9
VHC
157
ALYW
TSSOP--16
DT SUFFIX
CASE 948F
1
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: VOLP = 0.8 V (Max)
8
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
16
9
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 82 FETs
74VHC157
ALYW
SOIC EIAJ--16
M SUFFIX
CASE 966
• These devices are available in Pb--free package(s). Specifications herein
apply to both standard and Pb--free devices. Please see our website at
www.onsemi.com for specific Pb--free orderable part numbers, or
contact your local ON Semiconductor sales office or representative.
1
8
A
L, WL
Y, YY
= Assembly Location
= Wafer Lot
= Year
S
1
2
16
15
V
E
CC
W, WW = Work Week
A0
B0
Y0
A3
ORDERING INFORMATION
3
4
14
13
Device
Package
Shipping
B3
Y3
A2
B2
Y2
MC74VHC157D
MC74VHC157DR2
MC74VHC157DT
SOIC--16
48 Units/Rail
5
12
11
A1
SOIC--16 2500 Units/Reel
TSSOP--16 96 Units/Rail
6
B1
MC74VHC157DTR2 TSSOP--16 2500 Units/Reel
SOIC
7
8
10
9
Y1
MC74VHC157M
50 Units/Rail
EIAJ--16
GND
SOIC
EIAJ--16
MC74VHC157MEL
2000 Units/Reel
Figure 1. Pin Assignment
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
March, 2006 -- Rev. 5
MC74VHC157/D
MC74VHC157
2
A0
B0
A1
B1
4
7
3
Y0
Y1
5
6
NIBBLE
INPUTS
DATA
OUTPUTS
11
10
14
13
A2
B2
A3
B3
9
Y2
Y3
12
15
1
E
S
Figure 2. Expanded Logic Diagram
15
1
E
S
EN
G1
2
3
5
6
MUX
A0
B0
A1
B1
1
1
4
7
Y0
Y1
Y2
Y3
11
10
14
13
A2
B2
9
A3
B3
12
Figure 3. IEC Logic Symbol
FUNCTION TABLE
Inputs
Outputs
Y0 -- Y3
E
S
H
L
L
X
L
H
L
A0--A3
B0--B3
A0 -- A3, B0 -- B3 = the levels
of the respective Data--Word
Inputs.
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2
MC74VHC157
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
V
V
I
DC Supply Voltage
−0.5 to +7.0
CC
I
DC Input Voltage
−0.5 to V +7.0
V
CC
DC Output Voltage
−0.5 to V +7.0
V
O
CC
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
V < GND
−20
mA
mA
mA
mA
_C
IK
I
I
I
I
V
< GND
O
±20
OK
±25
O
±100
CC
T
T
T
−65 to +150
STG
L
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
260
_C
+150
_C
J
θ
JA
250
250
_C/W
mW
P
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
D
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 30% -- 35%
UL--94--VO (0.125 in)
V
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
>2000
>200
N/A
V
ESD
I
Latch--Up Performance
Above V and Below GND at 85_C (Note 5)
±500
mA
Latch--Up
CC
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum--rated
conditions is not implied.
2. Tested to EIA/JESD22--A114--A.
3. Tested to EIA/JESD22--A115--A.
4. Tested to JESD22--C101--A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
T
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
(Note 6)
5.5
V
0
V
V
OUT
CC
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−55
125
_C
ns/V
A
t , t
r
V
V
= 3.3 V ± 0.3 V
= 5.0 V ± 0.5 V
0
0
100
20
f
CC
CC
6. Unused inputs may not be left open. All inputs must be tied to a high--logic voltage level or a low--logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature _C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
TIME, YEARS
17,800
2.0
8,900
1.0
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHC157
DC CHARACTERISTICS (Voltages Referenced to GND)
V
T
A
= 25_C
T
A
≤85_C
-- 5 5 _C ≤T ≤125_C
A
CC
Symbol
Parameter
Condition
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
V
V
V
High--Level
2.0
1.5
1.5
1.5
V
IH
Input Voltage
3.0 to 5.5 0.7 V
0.7 V
0.7 V
CC
CC
CC
Low--Level
Input Voltage
2.0
3.0 to 5.5
0.5
0.5
0.5
V
V
IL
0.3 V
0.3 V
0.3 V
CC
CC
CC
High--Level
Output Voltage
V
OH
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
OH
IN
IH
IL
IL
IL
IL
I
= --50 mA
V
= V or V
IN
IH
I
= --4 mA
= --8 mA
3.0
4.5
2.58
3.94
2.48
3.8
2.34
3.66
OH
I
OH
V
Low--Level
Output Voltage
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
OL
IN
IH
I
= 50 mA
V
= V or V
IN
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OH
I
OH
I
Input Leakage
Current
V
= 5.5 V or
0 to 5.5
±0.1
±1.0
±1.0
mA
mA
IN
IN
GND
I
Quiescent
Supply Current
V
IN
= V or
5.5
4.0
40.0
40.0
CC
CC
GND
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
A
= 25_C
T
A
≤85_C
-- 5 5 _C ≤T ≤125_C
A
Symbol
Characteristic
Test Conditions
Min
Typ
Max
Typ
Max
Typ
Max
Unit
t
t
,
,
,
Propagation Delay,
A to B to Y
V
V
V
V
V
V
= 3.3 ± 0.3 V
= 5.0 ± 0.5 V
= 3.3 ± 0.3 V
= 5.0 ± 0.5 V
= 3.3 ± 0.3 V
= 5.0 ± 0.5 V
C
C
= 15 pF
= 50 pF
6.2
8.7
9.7
13.2
1.0
1.0
11.5
15.0
1.0
1.0
11.5
15.0
ns
PLH
PHL
CC
CC
CC
CC
CC
CC
L
L
C
L
C
L
= 15 pF
= 50 pF
4.1
5.6
6.4
8.4
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
t
t
Propagation Delay,
S to Y
C
L
C
L
= 15 pF
= 50 pF
8.4
10.9
13.2
16.7
1.0
1.0
15.5
19.0
1.0
1.0
15.5
19.0
ns
ns
PLH
PHL
C
L
C
L
= 15 pF
= 50 pF
5.3
6.8
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
t
t
Propagation Delay,
E to Y
C
L
C
L
= 15 pF
= 50 pF
8.7
11.2
13.6
17.1
1.0
1.0
16.0
19.5
1.0
1.0
16.0
19.5
PLH
PHL
C
L
C
L
= 15 pF
= 50 pF
5.6
7.1
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
10.0
12.0
C
C
Input Capacitance
4
10
10
10
pF
pF
IN
Typical @ 25_C, V = 5.0 V
CC
Power Dissipation Capacitance (Note 7)
20
PD
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ¯ V ¯ f + I . C is used to determine the no--load dynamic
CC(OPR
PD CC in CC PD
2
power consumption: P = C ¯ V
¯ f + I ¯ V
.
D
PD
CC
in
CC
CC
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4
MC74VHC157
NOISE CHARACTERISTICS (Input t = t = 3.0 ns; C = 50 pF; V = 5.0 V)
r
f
L
CC
T
A
= 25_C
Typ
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
0.3
0.8
−0.8
3.5
OLP
OLV
IHD
ILD
OL
V
V
V
−0.3
V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
1.5
V
V
V
CC
CC
E
Y
A, B, or S
50%
50%
GND
GND
t
t
PHL
PLH
t
t
PHL
PLH
Y
50% V
50% V
CC
CC
Figure 5. Switching Waveform
Figure 6. Inverting Switching
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance.
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
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5
MC74VHC157
PACKAGE DIMENSIONS
SOIC--16
D SUFFIX
CASE 751B--05
ISSUE J
-- A --
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
1
9
8
-- B --
P 8 PL
M
S
0.25 (0.010)
B
G
MILLIMETERS
DIM MIN MAX
10.00 0.386
INCHES
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
R X 45
K
_
4.00
1.75
0.49
1.25
0.150
0.054
0.014
0.016
C
G
J
K
M
P
R
1.27 BSC
0.050 BSC
-- T --
SEATING
PLANE
0.19
0.10
0.25
0.25
0.008
0.004
0.009
0.009
7
J
M
D
16 PL
0
5.80
0.25
7
0
_
_
_
_
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
TSSOP
DT SUFFIX
CASE 948F--01
ISSUE O
16X K REF
M
S
S
0.10 (0.004)
T
U
V
S
0.15 (0.006) T
U
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
K1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
16
9
2X L/2
J1
B
-- U --
SECTION N--N
L
J
PIN 1
IDENT.
8
1
N
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE --W--.
S
0.15 (0.006) T
U
A
-- V --
M
MILLIMETERS
INCHES
N
DIM MIN
MAX
5.10
4.50
1 . 2 0
0.15
0.75
MIN
MAX
0.200
0.177
0 . 0 4 7
0.006
0.030
A
B
C
D
F
4.90
4.30
-- -- --
0.193
0.169
-- -- --
F
DETAIL E
0.05
0.50
0.002
0.020
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28
0.20
0.16
0.30
0.25
0.007
0.004
0.004
0.007
0.007
0.011
0.008
0.006
0.012
0.010
-- W --
C
0.10 (0.004)
SEATING
PLANE
H
DETAIL E
6.40 BSC
0.252 BSC
-- T --
D
M
0
8
0
8
G
_
_
_
_
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6
MC74VHC157
PACKAGE DIMENSIONS
SOIC EIAJ--16
M SUFFIX
CASE 966--01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
16
9
8
E
Q
1
H
E
E
M
_
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
A
DIM MIN
MAX
2.05
0.20 0.002
0.50 0.014
0.27 0.007
10.50 0.390
5.45 0.201
MIN
-- -- --
MAX
0 . 0 8 1
0.008
0.020
0.011
0.413
0.215
c
A
1
b
c
D
E
-- -- --
0.05
0.35
0.18
9.90
5.10
A
A
1
b
0.13 (0.005)
e
E
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
L
L
E
M
Q
Z
0
0.70
-- -- --
10
0
10
0.035
0 . 0 3 1
_
_
_
_
0.90 0.028
0 . 7 8 -- -- --
1
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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC74VHC157/D
相关型号：
MC74VHC157MR2
AHC/VHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16
MOTOROLA
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