MC74VHC157DTR2G [ONSEMI]
Quad 2-Channel Multiplexer;
| 型号： | MC74VHC157DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Channel Multiplexer |
| 文件： | 总7页 (文件大小：127K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHC157
Quad 2-Channel Multiplexer
The MC74VHC157 is an advanced high−speed CMOS quad
2−channel multiplexer, fabricated with silicon gate CMOS
technology. It achieves high−speed operation similar to equivalent
Bipolar−Schottky TTL, while maintaining CMOS low−power
dissipation.
It consists of four 2−input digital multiplexers with common select
(S) and enable (E) inputs. When E is held High, selection of data is
inhibited and all the outputs go Low.
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7 V, allowing the interface of 5 V systems
to 3 V systems.
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MARKING
DIAGRAMS
16
1
9
8
VHC157G
AWLYWW
SOIC−16
D SUFFIX
CASE 751B
16
9
• High Speed: t = 4.1 ns (Typ) at V = 5 V
PD
CC
VHC
157
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
ALYW G
TSSOP−16
DT SUFFIX
CASE 948F
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
G
1
8
• Designed for 2 V to 5.5 V Operating Range
• Low Noise: V
= 0.8 V (Max)
OLP
VHC157 = Specific Device Code
= Assembly Location
WL, L = Wafer Lot
= Year
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance: HBM > 2000 V; Machine Model > 200 V
• Chip Complexity: 82 FETs
• These Devices are Pb−Free and are RoHS Compliant
A
Y
WW, W = Work Week
G or G = Pb−Free Package
ORDERING INFORMATION
Device
MC74VHC157DR2G
Package
Shipping
S
1
2
16
15
V
E
CC
SOIC−16 2500 Units/Reel
A0
MC74VHC157DTR2G TSSOP−16 2500 Units/Reel
B0
Y0
A3
3
4
14
13
B3
Y3
A2
B2
Y2
5
12
11
A1
6
B1
7
8
10
9
Y1
GND
Figure 1. Pin Assignment
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 6
MC74VHC157/D
MC74VHC157
2
A0
B0
A1
B1
4
7
3
Y0
Y1
5
6
NIBBLE
INPUTS
DATA
OUTPUTS
11
10
14
13
A2
B2
A3
B3
9
Y2
Y3
12
15
1
E
S
Figure 2. Expanded Logic Diagram
15
1
E
S
EN
G1
2
3
5
6
MUX
A0
B0
A1
B1
1
1
4
7
Y0
Y1
Y2
Y3
11
10
14
13
A2
B2
9
A3
B3
12
Figure 3. IEC Logic Symbol
FUNCTION TABLE
Inputs
Outputs
E
S
Y0 − Y3
H
L
L
X
L
H
L
A0−A3
B0−B3
A0 − A3, B0 − B3 = the levels
of the respective Data−Word
Inputs.
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2
MC74VHC157
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
Unit
V
V
V
V
DC Supply Voltage
*0.5 to )7.0
CC
I
DC Input Voltage
*0.5 to V )7.0
V
CC
DC Output Voltage
*0.5 to V )7.0
V
O
CC
I
I
I
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
Storage Temperature Range
V t GND
*20
mA
mA
mA
mA
_C
IK
I
V
t GND
O
$20
OK
O
$25
$100
CC
T
T
T
q
*65 to )150
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
260
_C
L
J
)150
_C
_C/W
mW
250
250
JA
P
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
D
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 30% − 35%
UL−94−VO (0.125 in)
V
ESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
>2000
>200
N/A
V
I
Latch−Up Performance
Above V and Below GND at 85_C (Note 5)
$500
mA
Latch−Up
CC
1. Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Extended exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum−rated
conditions is not implied.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
5.5
Unit
V
V
V
V
T
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
(Note 6)
5.5
V
0
V
CC
V
OUT
Operating Temperature Range, all Package Types
Input Rise or Fall Time
*55
125
_C
ns/V
A
t , t
V
CC
V
CC
= 3.3 V $ 0.3 V
= 5.0 V $ 0.5 V
0
0
100
20
r
f
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Junction
Temperature _C
Time, Hours
1,032,200
419,300
178,700
79,600
Time, Years
117.8
47.9
80
90
100
110
120
130
140
20.4
1
9.4
37,000
4.2
1
10
100
1000
TIME, YEARS
17,800
2.0
8,900
1.0
Figure 4. Failure Rate vs. Time Junction Temperature
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3
MC74VHC157
DC CHARACTERISTICS (Voltages Referenced to GND)
V
T
A
= 25_C
Typ
T
v85_C
−55_C vT v125_C
CC
A
A
Symbol
Parameter
Condition
(V)
Min
Max
Min
Max
Min
Max
Unit
V
V
V
High−Level
2.0
1.5
1.5
1.5
V
IH
Input Voltage
3.0 to 5.5 0.7 V
0.7 V
0.7 V
CC
CC
CC
Low−Level
Input Voltage
2.0
3.0 to 5.5
0.5
0.5
0.5
V
V
IL
0.3 V
0.3 V
0.3 V
CC
CC
CC
High−Level
Output Voltage
V
OH
= V or V
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
1.9
2.9
4.4
OH
IN
IH
IL
IL
IL
IL
I
= −50 mA
V
= V or V
IN
IH
I
= −4 mA
= −8 mA
3.0
4.5
2.58
3.94
2.48
3.8
2.34
3.66
OH
I
OH
V
OL
Low−Level
Output Voltage
V
OL
= V or V
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
IN
IH
I
= 50 mA
V
= V or V
IN
IH
I
= 4 mA
= 8 mA
3.0
4.5
0.36
0.36
0.44
0.44
0.52
0.52
OH
I
OH
I
I
Input Leakage
Current
V
= 5.5 V or
0 to 5.5
$0.1
$1.0
$1.0
mA
mA
IN
IN
GND
Quiescent
Supply Current
V
IN
= V or
5.5
4.0
40.0
40.0
CC
CC
GND
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0 ns)
r
f
T
= 25_C
T
v85_C
−55_C vT v125_C
A
A
A
Symbol
Characteristic
Test Conditions
Min
Typ
Max
Typ
Max
Typ
Max
Unit
t
t
,
,
,
Propagation Delay,
A to B to Y
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.3 $ 0.3 V
= 5.0 $ 0.5 V
= 3.3 $ 0.3 V
= 5.0 $ 0.5 V
= 3.3 $ 0.3 V
= 5.0 $ 0.5 V
C = 15 pF
L
6.2
8.7
9.7
13.2
1.0
1.0
11.5
15.0
1.0
1.0
11.5
15.0
ns
PLH
PHL
L
C = 50 pF
C = 15 pF
4.1
5.6
6.4
8.4
1.0
1.0
7.5
9.5
1.0
1.0
7.5
9.5
L
C = 50 pF
L
t
t
Propagation Delay,
S to Y
C = 15 pF
8.4
10.9
13.2
16.7
1.0
1.0
15.5
19.0
1.0
1.0
15.5
19.0
ns
ns
PLH
PHL
L
C = 50 pF
L
C = 15 pF
5.3
6.8
8.1
10.1
1.0
1.0
9.5
11.5
1.0
1.0
9.5
11.5
L
C = 50 pF
L
t
t
Propagation Delay,
E to Y
C = 15 pF
8.7
11.2
13.6
17.1
1.0
1.0
16.0
19.5
1.0
1.0
16.0
19.5
PLH
PHL
L
C = 50 pF
L
C = 15 pF
5.6
7.1
8.6
10.6
1.0
1.0
10.0
12.0
1.0
1.0
10.0
12.0
L
C = 50 pF
L
C
C
Input Capacitance
4
10
10
10
pF
pF
IN
Typical @ 25_C, V = 5.0 V
CC
Power Dissipation Capacitance (Note 7)
20
PD
7. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption: P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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4
MC74VHC157
NOISE CHARACTERISTICS (Input t = t = 3.0 ns; C = 50 pF; V = 5.0 V)
r
f
L
CC
T
A
= 25_C
Typ
Max
Symbol
Characteristic
Unit
V
V
Quiet Output Maximum Dynamic V
0.3
0.8
*0.8
3.5
OLP
OLV
IHD
ILD
OL
V
V
V
Quiet Output Minimum Dynamic V
*0.3
V
OL
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
1.5
V
V
CC
V
CC
E
Y
A, B, or S
50%
50%
GND
GND
t
t
PHL
PLH
t
t
PHL
PLH
Y
50% V
50% V
CC
CC
Figure 5. Switching Waveform
Figure 6. Inverting Switching
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C *
L
*Includes all probe and jig capacitance.
Figure 7. Test Circuit
INPUT
Figure 8. Input Equivalent Circuit
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5
MC74VHC157
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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6
MC74VHC157
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T
U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
MILLIMETERS
MAX
INCHES
MIN MAX
A
−V−
DIM MIN
A
B
C
D
N
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
1.20
0.15 0.002 0.006
0.75 0.020 0.030
F
−−− 0.047
DETAIL E
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
−W−
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
C
0.10 (0.004)
6.40 BSC
0.252 BSC
H
DETAIL E
SEATING
PLANE
−T−
M
0
8
0
8
_
_
_
_
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC157/D
相关型号：
MC74VHC157MR2
AHC/VHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, TRUE OUTPUT, PDSO16, EIAJ, PLASTIC, SOIC-16
MOTOROLA
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