LM833DR2 [ONSEMI]
Low Noise, Audio Dual Operational Amplifier; 低噪声，音频双路运算放大器
| 型号： | LM833DR2 |
| 厂家： | 
ONSEMI |
| 描述： | Low Noise, Audio Dual Operational Amplifier |
| 文件： | 总8页 (文件大小：100K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LM833
Low Noise, Audio Dual
Operational Amplifier
The LM833 is a standard low−cost monolithic dual general−purpose
operational amplifier employing Bipolar technology with innovative
high−performance concepts for audio systems applications. With high
frequency PNP transistors, the LM833 offers low voltage noise
(4.5 nV/ Hz ), 15 MHz gain bandwidth product, 7.0 V/ms slew rate,
0.3 mV input offset voltage with 2.0 mV/°C temperature coefficient of
input offset voltage. The LM833 output stage exhibits no dead−band
crossover distortion, large output voltage swing, excellent phase and
gain margins, low open loop high frequency output impedance and
symmetrical source/sink AC frequency response.
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MARKING
DIAGRAMS
8
LM833N
AWL
YYWWG
PDIP−8
N SUFFIX
CASE 626
For an improved performance dual/quad version, see the MC33079
family.
1
1
Features
LM833N = Device Code
Ǹ
• Low Voltage Noise: 4.5 nV/ Hz
A
= Assembly Location
• High Gain Bandwidth Product: 15 MHz
• High Slew Rate: 7.0 V/ms
• Low Input Offset Voltage: 0.3 mV
• Low T.C. of Input Offset Voltage: 2.0 mV/°C
• Low Distortion: 0.002%
WL
YY
WW
G
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• Excellent Frequency Stability
• Dual Supply Operation
• Pb−Free Packages are Available
LM833
ALYW
SOIC−8
D SUFFIX
CASE 751
G
1
1
MAXIMUM RATINGS
LM833 = Device Code
Rating
Supply Voltage (V to V
Symbol
Value
Unit
A
L
= Assembly Location
= Wafer Lot
)
EE
V
S
+36
V
CC
Y
W
G
= Year
= Work Week
= Pb−Free Package
Input Differential Voltage Range (Note 1)
Input Voltage Range (Note 1)
V
30
15
V
V
IDR
V
IR
Output Short Circuit Duration (Note 2)
Operating Ambient Temperature Range
Operating Junction Temperature
Storage Temperature
t
Indefinite
−40 to +85
+150
SC
PIN CONNECTIONS
T
°C
°C
°C
V
A
T
J
1
2
8
7
V
CC
Output 1
T
−60 to +150
stg
1
ESD Protection at any Pin
− Human Body Model
− Machine Model
V
esd
Output 2
Inputs 2
600
200
Inputs 1
3
6
5
Maximum Power Dissipation (Notes 2 and 3)
P
500
mW
D
2
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
4
V
EE
(Top View)
1. Either or both input voltages must not exceed the magnitude of V or V
2. Power dissipation must be considered to ensure maximum junction
.
CC
EE
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
temperature (T ) is not exceeded (see power dissipation performance
J
characteristic).
3. Maximum value at T ≤ 85°C.
A
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
December, 2005 − Rev. 5
LM833/D
LM833
ELECTRICAL CHARACTERISTICS (V = +15 V, V = −15 V, T = 25°C, unless otherwise noted.)
CC
EE
A
Characteristic
Input Offset Voltage (R = 10 W, V = 0 V)
Symbol
Min
Typ
Max
Unit
V
IO
−
0.3
5.0
mV
S
O
Average Temperature Coefficient of Input Offset Voltage
= 10 W, V = 0 V, T = T to T
DV /DT
−
2.0
−
mV/°C
IO
R
S
O
A
low
high
Input Offset Current (V
= 0 V, V = 0 V)
I
IO
−
−
10
200
nA
nA
V
CM
O
Input Bias Current (V
= 0 V, V = 0 V)
I
IB
300
1000
CM
O
Common Mode Input Voltage Range
V
−
−12
+14
−14
+12
−
ICR
Large Signal Voltage Gain (R = 2.0 kW, V
=
10 V)
A
VOL
90
110
−
dB
V
L
O
Output Voltage Swing:
V
10
−
12
−
13.7
−14.1
13.9
−
−10
−
O+
O−
O+
O−
R = 2.0 kW V = 1.0 V
L
,
ID
V
V
V
R = 2.0 kW V = 1.0 V
L
,
ID
R = 10 kW V = 1.0 V
L
,
ID
−14.7
−12
R = 10 kW, V = 1.0 V
L
ID
Common Mode Rejection (V
=
12 V)
CMR
PSR
80
80
−
100
115
4.0
−
−
dB
dB
in
Power Supply Rejection (V = 15 V to 5.0 V, −15 V to −5.0 V)
S
Power Supply Current (V = 0 V, Both Amplifiers)
I
8.0
mA
O
D
AC ELECTRICAL CHARACTERISTICS (V = +15 V, V = −15 V, T = 25°C, unless otherwise noted.)
CC
EE
A
Characteristic
Slew Rate (V = −10 V to +10 V, R = 2.0 kW, A = +1.0)
Symbol
Min
5.0
10
−
Typ
7.0
15
Max
−
Unit
V/ms
MHz
MHz
°
S
R
in
L
V
Gain Bandwidth Product (f = 100 kHz)
Unity Gain Frequency (Open Loop)
Unity Gain Phase Margin (Open Loop)
GBW
−
f
9.0
−
U
q
−
−
60
−
−
m
e
i
4.5
Ǹ
Equivalent Input Noise Voltage (R = 100 W, f = 1.0 kHz)
S
n
nVń Hz
Equivalent Input Noise Current (f = 1.0 kHz)
−
0.5
−
Ǹ
n
pAń Hz
Power Bandwidth (V = 27 V , R = 2.0 kW, THD ≤ 1.0%)
BWP
THD
−
−
−
120
0.002
−120
−
−
−
kHz
%
O
pp
L
Distortion (R = 2.0 kW, f = 20 Hz to 20 kHz, V = 3.0 V
A = +1.0)
V
L
O
rms,
Channel Separation (f = 20 Hz to 20 kHz)
C
S
dB
1000
800
600
400
200
800
V
V
V
= +15 V
= −15 V
= 0 V
CC
EE
CM
600
400
200
0
0
−55
−25
0
25
50
75
100
125
−50
0
50
100
150
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 1. Maximum Power Dissipation
versus Temperature
Figure 2. Input Bias Current versus Temperature
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2
LM833
800
600
400
10
V
CC
R = ∞
A
I
S
L
T
A
= 25°C
8.0
6.0
T
= 25°C
V
O
+
V
EE
4.0
2.0
0
200
0
5.0
10
15
20
0
5.0
10
, |V |, SUPPLY VOLTAGE (V)
CC EE
15
20
V
, |V |, SUPPLY VOLTAGE (V)
CC EE
V
Figure 3. Input Bias Current versus
Supply Voltage
Figure 4. Supply Current versus
Supply Voltage
110
105
100
95
110
100
V
V
= +15 V
= −15 V
CC
EE
R
T
= 2.0 kW
= 25°C
L
R = 2.0 kW
A
L
90
80
90
−55
−25
0
25
50
75
100
125
5.0
10
V , |V |, SUPPLY VOLTAGE (V)
CC EE
15
20
T , AMBIENT TEMPERATURE (°C)
A
Figure 5. DC Voltage Gain
versus Temperature
Figure 6. DC Voltage Gain versus
Supply Voltage
120
0
20
15
10
100
80
45
90
Phase
60
40
V
V
= +15 V
= −15 V
V
V
= +15 V
= −15 V
CC
EE
CC
EE
5.0
0
Gain
135
180
R = 2.0 kW
T
A
f = 100 kHz
L
20
0
= 25°C
1.0
10
100
1.0 k
10 k
100 k 1.0 M
10 M
−55
−25
0
25
50
75
100
125
f, FREQUENCY (Hz)
T , AMBIENT TEMPERATURE (°C)
A
Figure 7. Open Loop Voltage Gain and
Phase versus Frequency
Figure 8. Gain Bandwidth Product
versus Temperature
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3
LM833
30
10
f = 100 kHz
= 25°C
T
A
8.0
6.0
Falling
Rising
20
10
V
V
= +15 V
= −15 V
CC
EE
−
+
V
O
V
in
4.0
2.0
R = 2.0 kW
A
V
L
R
L
= +1.0
0
5.0
10
15
20
−55
−25
0
25
50
75
100
125
V
, |V |, SUPPLY VOLTAGE (V)
CC EE
T , AMBIENT TEMPERATURE (°C)
A
Figure 9. Gain Bandwidth Product versus
Supply Voltage
Figure 10. Slew Rate versus Temperature
10
8.0
6.0
4.0
2.0
0
35
30
R = 2.0k W
L
A
V
= +1.0
T
A
= 25°C
Falling
Rising
25
20
15
10
V
V
= +15 V
= −15 V
CC
EE
+
V
O
R = 2.0 kW
THD v 1.0%
T
A
−
L
V
in
R
L
= 25°C
5.0
0
5.0
10
15
20
10
100
1.0 k
10 k
1.0 M
10 M 100 k
V
, |V |, SUPPLY VOLTAGE (V)
CC EE
f, FREQUENCY (Hz)
Figure 11. Slew Rate versus Supply Voltage
Figure 12. Output Voltage versus Frequency
15
14
13
20
15
10
5.0
V
+
R = 10 kW
O
L
+V
T
= 25°C
sat
A
−V
sat
0
−5.0
V
V
= +15 V
= −15 V
CC
EE
−10
V
−
O
R = 10 kW
L
−15
−20
5.0
10
15
20
−55
−25
0
25
50
75
100
125
V
, |V |, SUPPLY VOLTAGE (V)
CC EE
T , AMBIENT TEMPERATURE (°C)
A
Figure 13. Maximum Output Voltage
versus Supply Voltage
Figure 14. Output Saturation Voltage
versus Temperature
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4
LM833
160
140
120
V
V
T
= +15 V
= −15 V
= 25°C
DV
−
A
+
CC
EE
CC
DV
CM
DM
−
DM
+
140
120
A
DV
O
A
DV
O
100
80
DV
CM
DV
EE
A
×
DM
CMR = 20 Log
DV
0
100
80
−PSR
+PSR
60
V
V
V
= +15 V
= −15 V
= 0 V
CC
EE
CM
DV /A
O
DM
40
60
+PSR = 20 Log
(
)
)
DV
CC
DV
= 1.5 V
CM
DV /A
20
0
O
DM
T
A
= 25°C
40
20
−PSR = 20 Log
1.0 k
(
DV
EE
100
10 k
100 k
1.0 M
10 M
100
1.0 k
10 k
100 k
1.0 M
10 M
100 k
1.0 M
f, FREQUENCY (Hz)
f, FREQUENCY (Hz)
Figure 15. Power Supply Rejection
versus Frequency
Figure 16. Common Mode Rejection
versus Frequency
1.0
0.1
10
V
V
= +15 V
= −15 V
CC
EE
−
V
L
O
+
R = 2.0 kW
T
A
R
L
5.0
= 25°C
V
V
= +15 V
= −15 V
= 100 W
= 25°C
CC
EE
0.01
0.001
R
T
S
V
= 1.0 V
rms
O
2.0
1.0
A
V
= 3.0 V
rms
O
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
100 k
10
100
1.0 k
f, FREQUENCY (Hz)
10 k
Figure 17. Total Harmonic Distortion
versus Frequency
Figure 18. Input Referred Noise Voltage
versus Frequency
2.0
100
V
V
T
= +15 V
= −15 V
= 25°C
V
V
= +15 V
= −15 V
CC
EE
CC
EE
2
2
V (total) = (i R ) +e
+
Ǹ
A
n
n
S
n
4KTRS
T
A
= 25°C
1.0
0.7
10
0.5
0.4
0.3
1.0
0.2
10
100
1.0 k
10 k
100 k
1.0
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
R , SOURCE RESISTANCE (W)
S
Figure 19. Input Referred Noise Current
versus Frequency
Figure 20. Input Referred Noise Voltage
versus Source Resistance
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5
LM833
V
V
= +15 V
= −15 V
V
V
= +15 V
= −15 V
CC
EE
CC
EE
R = 2.0 kW
L
R = 2.0 kW
L
C = 0 pF
L
C = 0 pF
L
A
V
= −1.0
A
V
= +1.0
T
A
= 25°C
T
A
= 25°C
t, TIME (2.0 ms/DIV)
t, TIME (2.0 ms/DIV)
Figure 21. Inverting Amplifier
Figure 22. Noninverting Amplifier Slew Rate
V
V
= +15 V
= −15 V
CC
EE
R = 2.0 kW
L
C = 0 pF
L
A
V
= +1.0
T
A
= 25°C
t, TIME (200 ns/DIV)
Figure 23. Noninverting Amplifier Overshoot
ORDERING INFORMATION
†
Device
LM833N
Package
Shipping
PDIP−8
50 Units / Rail
98 Units / Rail
LM833NG
PDIP−8
(Pb−Free)
LM833D
SOIC−8
LM833DG
SOIC−8
(Pb−Free)
LM833DR2
SOIC−8
2500 / Tape & Reel
LM833DR2G
SOIC−8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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6
LM833
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AG
NOTES:
−X−
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
A
8
5
4
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
C
N X 45
_
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
M
S
S
0.25 (0.010)
Z
Y
X
0.25
5.80
0.50 0.010
6.20 0.228
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
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7
LM833
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
8
5
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−B−
1
4
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
10.16
6.60
4.45
0.51
1.78
MAX
0.400
0.260
0.175
0.020
0.070
A
B
C
D
F
9.40
6.10
3.94
0.38
1.02
0.370
0.240
0.155
0.015
0.040
F
−A−
NOTE 2
L
G
H
J
2.54 BSC
0.100 BSC
0.76
0.20
2.92
1.27
0.30
3.43
0.030
0.008
0.115
0.050
0.012
0.135
K
L
C
7.62 BSC
0.300 BSC
M
N
−−−
0.76
10
1.01
−−−
0.030
10
0.040
_
_
J
−T−
SEATING
PLANE
N
M
D
K
G
H
M
M
M
0.13 (0.005)
T
A
B
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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For additional information, please contact your
local Sales Representative.
LM833/D
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